<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/pinctrl/qcom, branch v5.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-09-19T21:19:33Z</updated>
<entry>
<title>Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2019-09-19T21:19:33Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-09-19T21:19:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3c2edc36a77420d8be05d656019dbc8c31535992'/>
<id>urn:sha1:3c2edc36a77420d8be05d656019dbc8c31535992</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.4 kernel cycle:

  Core changes:

   - Fix errors in example code in the documentation.

  New drivers:

   - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
     Ingenic driver.

   - Support Cirrus Logic Madera CS47L92 and CS47L15.

   - Support Allwinner Sunxi V3S.

   - Support Aspeed 2600 BMC.

   - Support Qualcomm SC7180.

   - Support Marvell MVEBU CS115.

  Driver improvements:

   - Clean up a few drivers to use the devm_platform_ioremap_resource()
     helper.

   - Pass the irqchip when registering the gpio_chip in some pin
     controllers that are also GPIO controllers.

   - Support suspend/resume in the Tegra driver.

   - Support pull-up on the Broadcom BCM2711.

   - The Intel driver can now request locked pads.

   - Fix the UFS reset pin in the Qualcomm SDM845 driver"

* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
  pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
  pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
  pinctrl: bcm: remove redundant assignment to pointer log
  pinctrl: iproc: Add 'get_direction' support
  pinctrl: iproc-gpio: Handle interrupts for multiple instances
  pinctrl: iproc-gpio: Fix incorrect pinconf configurations
  pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
  pinctrl: qcom: sdm845: Fix UFS_RESET pin
  pinctrl: mvebu: add additional variant for standalone CP115
  pinctrl: mvebu: Add CP110 missing pin functionality
  dt-bindings: cp110: document the new CP115 pinctrl compatible
  pinctrl: bcm2835: Pass irqchip when adding gpiochip
  pinctrl: meson: meson: Add of_node_put() before return
  pinctrl/gpio: Take MUX usage into account
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
  pinctrl: amd: disable spurious-firing GPIO IRQs
  pinctrl: rza2: Include the appropriate headers
  pinctrl: rza2: Drop driver use of consumer flags
  ...
</content>
</entry>
<entry>
<title>pinctrl: qcom: sdm845: Fix UFS_RESET pin</title>
<updated>2019-09-04T13:23:22Z</updated>
<author>
<name>Stephen Boyd</name>
<email>swboyd@chromium.org</email>
</author>
<published>2019-08-30T06:02:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1fdbc02ce1bdcdc53c7d16cf20b80cfaa79a5a59'/>
<id>urn:sha1:1fdbc02ce1bdcdc53c7d16cf20b80cfaa79a5a59</id>
<content type='text'>
The UFS_RESET pin is the magical pin #150 now, not 153 per the
sdm845_groups array declared in this file. Fix the order of pins so that
UFS_RESET is 150 and the SDC pins follow after.

Fixes: 53a5372ce326 ("pinctrl: qcom: sdm845: Expose ufs_reset as gpio")
Signed-off-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Link: https://lore.kernel.org/r/20190830060227.12792-1-swboyd@chromium.org
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support</title>
<updated>2019-08-23T07:59:55Z</updated>
<author>
<name>Vinod Koul</name>
<email>vkoul@kernel.org</email>
</author>
<published>2019-08-14T12:35:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2dc889a8846d16574794669bbdca7401900695b7'/>
<id>urn:sha1:2dc889a8846d16574794669bbdca7401900695b7</id>
<content type='text'>
Add support for the PM8150l GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Link: https://lore.kernel.org/r/20190814123512.6017-3-vkoul@kernel.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support</title>
<updated>2019-08-23T07:59:13Z</updated>
<author>
<name>Vinod Koul</name>
<email>vkoul@kernel.org</email>
</author>
<published>2019-08-14T12:35:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9bdacadd160687599ded0b796d089a918e4ea3f9'/>
<id>urn:sha1:9bdacadd160687599ded0b796d089a918e4ea3f9</id>
<content type='text'>
Add support for the PM8150b GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Link: https://lore.kernel.org/r/20190814123512.6017-2-vkoul@kernel.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support</title>
<updated>2019-08-23T07:57:50Z</updated>
<author>
<name>Vinod Koul</name>
<email>vkoul@kernel.org</email>
</author>
<published>2019-08-14T12:35:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d67070c372dda5d15730182d8640998601b6d3f0'/>
<id>urn:sha1:d67070c372dda5d15730182d8640998601b6d3f0</id>
<content type='text'>
Add support for the PM8150 GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Link: https://lore.kernel.org/r/20190814123512.6017-1-vkoul@kernel.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>gpio: Use callback presence to determine need of valid_mask</title>
<updated>2019-08-20T08:42:07Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2019-08-19T09:30:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=eb1e8bd6e3900e3a3b9776cd1b09ecfc05573619'/>
<id>urn:sha1:eb1e8bd6e3900e3a3b9776cd1b09ecfc05573619</id>
<content type='text'>
After we switched the two drivers that have .need_valid_mask
set to use the callback for setting up the .valid_mask,
we can just use the presence of the .init_valid_mask()
callback (or the OF reserved ranges, nota bene) to determine
whether to allocate the mask or not and we can drop the
.need_valid_mask field altogether.

Cc: Benjamin Gaignard &lt;benjamin.gaignard@st.com&gt;
Cc: Amelie Delaunay &lt;amelie.delaunay@st.com&gt;
Cc: Stephen Boyd &lt;swboyd@chromium.org&gt;
Cc: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Link: https://lore.kernel.org/r/20190819093058.10863-1-linus.walleij@linaro.org
</content>
</entry>
<entry>
<title>gpio: Pass mask and size with the init_valid_mask()</title>
<updated>2019-08-20T08:42:07Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2019-08-19T08:49:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c9fc5aff217267a9ef3a76450760534488870c69'/>
<id>urn:sha1:c9fc5aff217267a9ef3a76450760534488870c69</id>
<content type='text'>
It is more helpful for drivers to have the affected fields
directly available when we use the callback to set up the
valid mask. Change this and switch over the only user
(MSM) to use the passed parameters. If we do this we can
also move the mask out of publicly visible struct fields.

Cc: Stephen Boyd &lt;swboyd@chromium.org&gt;
Cc: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Link: https://lore.kernel.org/r/20190819084904.30027-1-linus.walleij@linaro.or
Reviewed-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>qcom: spmi-gpio: convert to hierarchical IRQ helpers in gpio core</title>
<updated>2019-08-15T07:44:19Z</updated>
<author>
<name>Brian Masney</name>
<email>masneyb@onstation.org</email>
</author>
<published>2019-08-08T12:32:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=821c76c4c374adf0c7a7608ee4661aa801f3c1c5'/>
<id>urn:sha1:821c76c4c374adf0c7a7608ee4661aa801f3c1c5</id>
<content type='text'>
Now that the GPIO core has support for hierarchical IRQ chips, convert
Qualcomm's spmi-gpio over to use these new helpers to reduce duplicated
code across drivers.

This change was tested on a LG Nexus 5 (hammerhead) phone.

Signed-off-by: Brian Masney &lt;masneyb@onstation.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Link: https://lore.kernel.org/r/20190808123242.5359-3-linus.walleij@linaro.org
</content>
</entry>
<entry>
<title>pinctrl: qcom: Add SC7180 pinctrl driver</title>
<updated>2019-08-07T12:43:51Z</updated>
<author>
<name>Jitendra Sharma</name>
<email>shajit@codeaurora.org</email>
</author>
<published>2019-08-06T06:05:36Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f2ae04c45b1a9d6c61faa8a946d515f81876e703'/>
<id>urn:sha1:f2ae04c45b1a9d6c61faa8a946d515f81876e703</id>
<content type='text'>
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7180

Signed-off-by: Jitendra Sharma &lt;shajit@codeaurora.org&gt;
Signed-off-by: Vivek Gautam &lt;vivek.gautam@codeaurora.org&gt;
[rnayak: modify to use upstream tile support
	 sort and squash some functions]
Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Reviewed-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Link: https://lore.kernel.org/r/20190806060536.18094-2-rnayak@codeaurora.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Remove dev_err() usage after platform_get_irq()</title>
<updated>2019-08-05T11:24:06Z</updated>
<author>
<name>Stephen Boyd</name>
<email>swboyd@chromium.org</email>
</author>
<published>2019-07-30T18:15:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=64c4dcbfcc4ea3ae8f898e6dac836e57acb16b6b'/>
<id>urn:sha1:64c4dcbfcc4ea3ae8f898e6dac836e57acb16b6b</id>
<content type='text'>
We don't need dev_err() messages when platform_get_irq() fails now that
platform_get_irq() prints an error message itself when something goes
wrong. Let's remove these prints with a simple semantic patch.

// &lt;smpl&gt;
@@
expression ret;
struct platform_device *E;
@@

ret =
(
platform_get_irq(E, ...)
|
platform_get_irq_byname(E, ...)
);

if ( \( ret &lt; 0 \| ret &lt;= 0 \) )
{
(
-if (ret != -EPROBE_DEFER)
-{ ...
-dev_err(...);
-... }
|
...
-dev_err(...);
)
...
}
// &lt;/smpl&gt;

While we're here, remove braces on if statements that only have one
statement (manually).

Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Cc: linux-gpio@vger.kernel.org
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Signed-off-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Link: https://lore.kernel.org/r/20190730181557.90391-34-swboyd@chromium.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
