<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/pinctrl/qcom, branch v6.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-08-07T08:07:06Z</updated>
<entry>
<title>treewide: rename GPIO set callbacks back to their original names</title>
<updated>2025-08-07T08:07:06Z</updated>
<author>
<name>Bartosz Golaszewski</name>
<email>bartosz.golaszewski@linaro.org</email>
</author>
<published>2025-07-17T13:21:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d9d87d90cc0b10cd56ae353f50b11417e7d21712'/>
<id>urn:sha1:d9d87d90cc0b10cd56ae353f50b11417e7d21712</id>
<content type='text'>
The conversion of all GPIO drivers to using the .set_rv() and
.set_multiple_rv() callbacks from struct gpio_chip (which - unlike their
predecessors - return an integer and allow the controller drivers to
indicate failures to users) is now complete and the legacy ones have
been removed. Rename the new callbacks back to their original names in
one sweeping change.

Signed-off-by: Bartosz Golaszewski &lt;bartosz.golaszewski@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2025-08-02T19:07:09Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-08-02T19:07:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=186f3edfdd41f2ae87fc40a9ccba52a3bf930994'/>
<id>urn:sha1:186f3edfdd41f2ae87fc40a9ccba52a3bf930994</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "Nothing stands out, apart from maybe the interesting Eswin EIC7700, a
  RISC-V SoC I've never seen before.

  Core changes:

   - Open code PINCTRL_FUNCTION_DESC() instead of defining a complex
     macro only used in one place

   - Add pinmux_generic_add_pinfunction() helper and use this in a few
     drivers

  New drivers:

   - Amlogic S7, S7D and S6 pin control support

   - Eswin EIC7700 pin control support

   - Qualcomm PMIV0104, PM7550 and Milos pin control support

     Because of unhelpful numbering schemes, the Qualcomm driver now
     needs to start to rely on SoC codenames

   - STM32 HDP pin control support

   - Mediatek MT8189 pin control support

  Improvements:

   - Switch remaining pin control drivers over to the new GPIO set
     callback that provides a return value

   - Support RSVD (reserved) pins in the STM32 driver

   - Move many fixed assignments over to pinctrl_desc definitions

   - Handle multiple TLMM regions in the Qualcomm driver"

* tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits)
  pinctrl: mediatek: Add pinctrl driver for mt8189
  dt-bindings: pinctrl: mediatek: Add support for mt8189
  pinctrl: aspeed-g6: Add PCIe RC PERST pin group
  pinctrl: ingenic: use pinmux_generic_add_pinfunction()
  pinctrl: keembay: use pinmux_generic_add_pinfunction()
  pinctrl: mediatek: moore: use pinmux_generic_add_pinfunction()
  pinctrl: airoha: use pinmux_generic_add_pinfunction()
  pinctrl: equilibrium: use pinmux_generic_add_pinfunction()
  pinctrl: provide pinmux_generic_add_pinfunction()
  pinctrl: pinmux: open-code PINCTRL_FUNCTION_DESC()
  pinctrl: ma35: use new GPIO line value setter callbacks
  MAINTAINERS: add Clément Le Goffic as STM32 HDP maintainer
  pinctrl: stm32: Introduce HDP driver
  dt-bindings: pinctrl: stm32: Introduce HDP
  pinctrl: qcom: Add Milos pinctrl driver
  dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer
  pinctrl: qcom: spmi: Add PM7550
  dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support
  pinctrl: qcom: spmi: Add PMIV0104
  dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support
  ...
</content>
</entry>
<entry>
<title>pinctrl: qcom: Add Milos pinctrl driver</title>
<updated>2025-07-14T15:50:58Z</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2025-07-02T15:56:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=620d3d1025581b9f1b883452788b6f409ff04170'/>
<id>urn:sha1:620d3d1025581b9f1b883452788b6f409ff04170</id>
<content type='text'>
Add pinctrl driver for TLMM block found in the Milos SoC.

Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Reviewed-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/20250702-sm7635-pinctrl-v2-2-c138624b9924@fairphone.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: spmi: Add PM7550</title>
<updated>2025-07-11T18:22:53Z</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2025-07-09T11:46:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=52e06d25bdcf8026cd1c951ff7f910e21c4afa04'/>
<id>urn:sha1:52e06d25bdcf8026cd1c951ff7f910e21c4afa04</id>
<content type='text'>
PM7550 is a PMIC, featuring 12 GPIOs. Describe it.

Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Link: https://lore.kernel.org/20250709-sm7635-pmxr2230-v2-4-09777dab0a95@fairphone.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: spmi: Add PMIV0104</title>
<updated>2025-07-11T18:20:19Z</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2025-07-09T11:22:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=19dca764dbb54bf5af11311016c9d8d69c1f5131'/>
<id>urn:sha1:19dca764dbb54bf5af11311016c9d8d69c1f5131</id>
<content type='text'>
PMIV0104 is a PMIC, featuring 10 GPIOs. Describe it.

Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Link: https://lore.kernel.org/20250709-sm7635-pmiv0104-v2-3-ebf18895edd6@fairphone.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: add multi TLMM region option parameter</title>
<updated>2025-07-03T21:44:21Z</updated>
<author>
<name>Yuanjie Yang</name>
<email>quic_yuanjiey@quicinc.com</email>
</author>
<published>2025-06-24T09:06:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=56ffb63749f4a1e88c282b763c458f3ed73d8c27'/>
<id>urn:sha1:56ffb63749f4a1e88c282b763c458f3ed73d8c27</id>
<content type='text'>
Add support for selecting multiple TLMM regions using the
tlmm-test tool.
The current implementation only selects the TLMM Node region
0, which can lead to incorrect region selection.

QCS 615 TLMM Node dts reg:
	tlmm: pinctrl@3100000 {
		compatible = "qcom,qcs615-tlmm";
		reg = &lt;0x0 0x03100000 0x0 0x300000&gt;,
		      &lt;0x0 0x03500000 0x0 0x300000&gt;,
		      &lt;0x0 0x03d00000 0x0 0x300000&gt;;
		reg-names = "east",
			    "west",
			    "south";

QCS615 gpio57 is in the south region with an offset of 0x39000,
and its address is 0x3d39000. However, the default region selection
is region 0 (east region), resulting in a wrong calculated address
of 0x3139000.

Add a tlmm option parameter named tlmm_reg_name to select the region.
If the user does not input the parameter, the default region is 0.

Signed-off-by: Yuanjie Yang &lt;quic_yuanjiey@quicinc.com&gt;
Link: https://lore.kernel.org/20250624090600.91063-1-quic_yuanjiey@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: msm: mark certain pins as invalid for interrupts</title>
<updated>2025-06-18T11:56:34Z</updated>
<author>
<name>Bartosz Golaszewski</name>
<email>bartosz.golaszewski@linaro.org</email>
</author>
<published>2025-06-12T09:14:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=93712205ce2f1fb047739494c0399a26ea4f0890'/>
<id>urn:sha1:93712205ce2f1fb047739494c0399a26ea4f0890</id>
<content type='text'>
On some platforms, the UFS-reset pin has no interrupt logic in TLMM but
is nevertheless registered as a GPIO in the kernel. This enables the
user-space to trigger a BUG() in the pinctrl-msm driver by running, for
example: `gpiomon -c 0 113` on RB2.

The exact culprit is requesting pins whose intr_detection_width setting
is not 1 or 2 for interrupts. This hits a BUG() in
msm_gpio_irq_set_type(). Potentially crashing the kernel due to an
invalid request from user-space is not optimal, so let's go through the
pins and mark those that would fail the check as invalid for the irq chip
as we should not even register them as available irqs.

This function can be extended if we determine that there are more
corner-cases like this.

Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver")
Cc: stable@vger.kernel.org
Reviewed-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
Signed-off-by: Bartosz Golaszewski &lt;bartosz.golaszewski@linaro.org&gt;
Link: https://lore.kernel.org/20250612091448.41546-1-brgl@bgdev.pl
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: pinctrl-qcm2290: Add missing pins</title>
<updated>2025-06-09T08:16:45Z</updated>
<author>
<name>Wojciech Slenska</name>
<email>wojciech.slenska@gmail.com</email>
</author>
<published>2025-05-23T10:14:37Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=315345610faee8a0568b522dba9e35067d1732ab'/>
<id>urn:sha1:315345610faee8a0568b522dba9e35067d1732ab</id>
<content type='text'>
Added the missing pins to the qcm2290_pins table.

Signed-off-by: Wojciech Slenska &lt;wojciech.slenska@gmail.com&gt;
Fixes: 48e049ef1238 ("pinctrl: qcom: Add QCM2290 pinctrl driver")
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/20250523101437.59092-1-wojciech.slenska@gmail.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: switch to devm_gpiochip_add_data()</title>
<updated>2025-06-09T08:16:45Z</updated>
<author>
<name>Dmitry Baryshkov</name>
<email>dmitry.baryshkov@oss.qualcomm.com</email>
</author>
<published>2025-05-13T18:38:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=56ec63a6e107e724619e61c7e605b49d365dfa07'/>
<id>urn:sha1:56ec63a6e107e724619e61c7e605b49d365dfa07</id>
<content type='text'>
In order to simplify cleanup actions, use devres-enabled version of
gpiochip_add_data().  As the msm_pinctrl_remove() function is now empty,
drop it and all its calls from the corresponding pinctrl drivers.

Signed-off-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/20250513-pinctrl-msm-fix-v2-3-249999af0fc1@oss.qualcomm.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2025-05-30T16:46:28Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-05-30T16:46:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=eafd95ea74846eda3e3eac6b2bb7f34619d8a6f8'/>
<id>urn:sha1:eafd95ea74846eda3e3eac6b2bb7f34619d8a6f8</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "An especially linear and sparse improvement and new drivers release.
  Nothing exciting. The biggest change in Bartosz changes to make
  gpiochip set/get calls return error codes (something we should have
  fixed ages ago but is now finally getting fixed.)

  Core changes:

   - Add the devres devm_pinctrl_register_mappings() call that can
     register some pin control machine mappings and have them go away
     with the associated device

  New drivers:

   - Support for the Mediatek MT6893 and MT8196 SoCs

   - Support for the Renesas RZ/V2N SoC

   - Support for the NXP Freescale i.MX943 SoC

  Improvements:

   - Per-SoC suspend/resume callbacks in the Samsung drivers

   - Set all pins as input (High-Z) at probe in the MCP23S08 driver

   - Switch most GPIO chips to use the setters/getters with a return
     value

   - EGPIO support in the Qualcomm QCM2290 driver

   - Fix up the number of available GPIO lines in Qualcomm QCS8300 and
     QCS615"

* tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
  pinctrl: freescale: Add support for imx943 pinctrl
  pinctrl: core: add devm_pinctrl_register_mappings()
  pinctrl: remove extern specifier for functions in machine.h
  pinctrl: mediatek: eint: Fix invalid pointer dereference for v1 platforms
  pinctrl: freescale: Enable driver if platform is enabled.
  pinctrl: freescale: Depend imx-scu driver on OF
  pinctrl: armada-37xx: propagate error from armada_37xx_pmx_set_by_name()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get_direction()
  pinctrl: armada-37xx: propagate error from armada_37xx_pmx_gpio_set_direction()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_direction_output()
  pinctrl: armada-37xx: set GPIO output value before setting direction
  pinctrl: armada-37xx: use correct OUTPUT_VAL register for GPIOs &gt; 31
  pinctrl: meson: Drop unused aml_pctl_find_group_by_name()
  pinctrl: at91: Fix possible out-of-boundary access
  pinctrl: add stubs for OF-specific pinconf functions
  pinctrl: qcom: correct the ngpios entry for QCS8300
  pinctrl: qcom: correct the ngpios entry for QCS615
  dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
  dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
  ...
</content>
</entry>
</feed>
