linux/drivers/pinctrl, branch v4.0

pinctrl: sun4i: GPIOs configured as irq must be set to input before reading

2015-03-18T09:56:46Z

On sun4i-a10, when GPIOs are configured as external interrupt the value for them in the data register does not seem to get updated, so set their mux to input (and restore afterwards) when reading the pin. Missed edges seem to be buffered, so this does not introduce a race condition. I've also tested this on sun5i-a13 and sun7i-a20 and those do not seem to be affected, the input value representation in the data register does seem to correctly get updated to the actual pin value while in irq mode there. Signed-off-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: at91: move lock/unlock_as_irq calls into request/release

2015-03-18T01:01:36Z

The gpiochip_lock_as_irq call can fail and return an error, while the irq_startup is not expected to fail (returns an unsigned int which is not checked by irq core code). irq_request/release_resources functions have been created to address this problem. Move gpiochip_lock/unlock_as_irq calls into irq_request/release_resources functions to prevent using a gpio as an irq if the gpiochip_lock_as_irq call failed. Signed-off-by: Boris Brezillon Acked-by: Ludovic Desroches Acked-by: Nicolas Ferre Acked-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Linus Walleij

pinctrl: update direction_output function of cherryview driver

2015-03-10T08:02:23Z

From the comments of gpiod_direction_output(), need to set @value as initial output, so update the lowlevel routine to make it work. Signed-off-by: jason.cj.chen Signed-off-by: qipeng.zha Acked-by: Mika Westerberg Signed-off-by: Linus Walleij

pinctrl: baytrail: Save pin context over system sleep

2015-03-06T11:25:07Z

The BIOS might reconfigure pins as it needs when S3 is entered. This might cause drivers using the GPIOs to fail because the state was wrong or interrupts stopped working. Fix this by saving and restoring enough pin context over system sleep. Reported-by: Hans Holmberg Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij

pinctrl: baytrail: Rework interrupt handling

2015-03-06T11:22:41Z

Instead of handling everything in the driver's first level interrupt handler, we can take advantage of already existing flow handlers that are provided by the IRQ core. This changes the functionality a bit also. Previously the driver looped over pending interrupts in a single loop, restarting the loop if some interrupt changed state. This caused problem with Lenovo Thinkpad 10 digitizer that it was not able to deassert the interrupt before the driver disabled the interrupt for good (looplimit was exhausted). Rework the interrupt handling logic a bit so that we provide proper mask, ack and unmask operations in terms of Baytrail GPIO hardware and loop over pending interrupts only once. If the interrupt remains asserted the first level handler will be re-triggered automatically. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij

pinctrl: baytrail: Clear interrupt triggering from pins that are in GPIO mode

2015-03-06T11:21:09Z

If the pin is already configured as GPIO and it has any of the triggering flags set, we may get spurious interrupts depending on the state of the pin. Prevent this by clearing the triggering flags on such pins. However, if the pin is also configured as "direct IRQ" we leave the flags as is. Otherwise it will prevent interrupts that are routed directly to IO-APIC. Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij

pinctrl: baytrail: Relax GPIO request rules

2015-03-06T11:19:51Z

Zotac ZBOX PI320, a Baytrail based mini-PC, has power button connected to a GPIO pin and it is exposed to the operating system as Windows 8 button array. This is implemented in Linux as a driver using gpio_keys. However, BIOS on this particula machine forgot to mux the pin to be a GPIO instead of native function, which results following message to be seen on the console: byt_gpio INT33FC:02: pin 16 cannot be used as GPIO. This causes power button to not work as the driver was not able to request the GPIO it needs. So instead of completely preventing this we allow turning the pin as GPIO but issue warning that something might be wrong. Reported-by: Benjamin Adler Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2015-02-11T19:23:13Z

Pull pincontrol updates from Linus Walleij: :This is the bulk of pin control changes for the v3.20 cycle: Framework changes and enhancements: - Passing -DDEBUG recursively to subdir drivers so we get debug messages properly turned on. - Infer map type from DT property in the groups parsing code in the generic pinconfig code. - Support for custom parameter passing in generic pin config. This is used when you are using the generic pin config, but want to add a few custom properties that no other driver will use. New drivers: - Driver for the Xilinx Zynq - Driver for the AmLogic Meson SoCs New features in drivers: - Sleep support (suspend/resume) for the Cherryview driver - mvebeu a38x can now mux a UART on pins MPP19 and MPP20 - Migrated the qualcomm driver to generic pin config handling of extended config options in the core code. - Support BUS1 and AUDIO in the Exynos pin controller. - Add some missing functions in the sun6i driver. - Add support for the A31S variant in the sun6i driver. - EMEv2 support in the Renesas PFC driver. - Add support for Qualcomm MSM8916 in the qcom driver. Deleted features - Drop support for the SiRF Marco that was never released to the market. - Drop SH7372 support as the support for this platform is removed from the kernel" * tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (40 commits) sh-pfc: emev2 - Fix mangled author name pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs pinctrl: imx25: fix numbering for pins pinctrl: pinctrl-imx: don't use invalid value of conf_reg pinctrl: qcom: delete pin_config_get/set pinconf operations pinctrl: qcom: Add msm8916 pinctrl driver DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding pinctrl: qcom: increase variable size for register offsets pinctrl: hide PCONFDUMP in #ifdef pinctrl: rockchip: Only mask interrupts; never disable pinctrl: zynq: Fix usb0 pins pinctrl: sh-pfc: sh7372: Remove DT binding documentation pinctrl: sh-pfc: sh7372: Remove PFC support sh-pfc: Add emev2 pinmux support sh-pfc: add macro to define pinmux without function pinctrl: add driver for Amlogic Meson SoCs staging: drivers: pinctrl: Fixed checkpatch.pl warnings pinctrl: exynos: Add AUDIO pin controller for exynos7 sh-pfc: r8a7790: add MLB+ pin group sh-pfc: r8a7791: add MLB+ pin group ...

sh-pfc: emev2 - Fix mangled author name

2015-02-05T13:51:34Z

Signed-off-by: Geert Uytterhoeven Fixes: 1e7d5d849cf4f0c5 ("sh-pfc: Add emev2 pinmux support") Signed-off-by: Linus Walleij

pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs

2015-02-04T08:59:26Z

If the pin is in HiZ mode when it is requested as GPIO its value cannot be read (it always returns 0). In order to cope with the Linux GPIO subsystem where we do not have such state at all, turn the pin to be input instead. Reported-by: Jerome Blin Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij