<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/pinctrl, branch v4.6</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.6</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.6'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-04-29T09:16:19Z</updated>
<entry>
<title>pinctrl: at91-pio4: fix pull-up/down logic</title>
<updated>2016-04-29T09:16:19Z</updated>
<author>
<name>Ludovic Desroches</name>
<email>ludovic.desroches@atmel.com</email>
</author>
<published>2016-04-19T14:03:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5305a7b7e860bb40ab226bc7d58019416073948a'/>
<id>urn:sha1:5305a7b7e860bb40ab226bc7d58019416073948a</id>
<content type='text'>
The default configuration of a pin is often with a value in the
pull-up/down field at chip reset. So, even if the internal logic of the
controller prevents writing a configuration with pull-up and pull-down at
the same time, we must ensure explicitly this condition before writing the
register.

This was leading to a pull-down condition not taken into account for
instance.

Signed-off-by: Ludovic Desroches &lt;ludovic.desroches@atmel.com&gt;
Fixes: 776180848b57 ("pinctrl: introduce driver for Atmel PIO4 controller")
Cc: stable@vger.kernel.org #v4.4 and later
Acked-by: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;
Acked-by: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: single: Fix pcs_parse_bits_in_pinctrl_entry to use __ffs than ffs</title>
<updated>2016-04-15T09:26:55Z</updated>
<author>
<name>Keerthy</name>
<email>j-keerthy@ti.com</email>
</author>
<published>2016-04-14T04:59:16Z</published>
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<id>urn:sha1:56b367c0cd67d4c3006738e7dc9dda9273fd2bfe</id>
<content type='text'>
pcs_parse_bits_in_pinctrl_entry uses ffs which gives bit indices
ranging from 1 to MAX. This leads to a corner case where we try to request
the pin number = MAX and fails.

bit_pos value is being calculted using ffs. pin_num_from_lsb uses
bit_pos value. pins array is populated with:

pin + pin_num_from_lsb.

The above is 1 more than usual bit indices as bit_pos uses ffs to compute
first set bit. Hence the last of the pins array is populated with the MAX
value and not MAX - 1 which causes error when we call pin_request.

mask_pos is rightly calculated as ((pcs-&gt;fmask) &lt;&lt; (bit_pos - 1))
Consequently val_pos and submask are correct.

Hence use __ffs which gives (ffs(x) - 1) as the first bit set.

fixes: 4e7e8017a8 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: mediatek: correct debounce time unit in mtk_gpio_set_debounce</title>
<updated>2016-04-15T08:28:04Z</updated>
<author>
<name>Yingjoe Chen</name>
<email>yingjoe.chen@mediatek.com</email>
</author>
<published>2016-04-02T06:57:49Z</published>
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<id>urn:sha1:5fedbb923936174ab4d1d5cc92bca1cf6b2e0ca2</id>
<content type='text'>
The debounce time unit for gpio_chip.set_debounce is us but
mtk_gpio_set_debounce regard it as ms.
Fix this by correct debounce time array dbnc_arr so it can find correct
debounce setting. Debounce time for first debounce setting is 500us,
correct this as well.

While I'm at it, also change the debounce time array name to
"debounce_time" for readability.

Cc: stable@vger.kernel.org
Signed-off-by: Yingjoe Chen &lt;yingjoe.chen@mediatek.com&gt;
Reviewed-by: Daniel Kurtz &lt;djkurtz@chromium.org&gt;
Acked-by: Hongzhou Yang &lt;hongzhou.yang@mediatek.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: imx: Kconfig: PINCTRL_IMX select REGMAP</title>
<updated>2016-04-14T12:19:00Z</updated>
<author>
<name>Alexander Kurz</name>
<email>akurz@blala.de</email>
</author>
<published>2016-04-10T18:41:38Z</published>
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<id>urn:sha1:6dd22a116614acf33aeef13861e32510ef9d5392</id>
<content type='text'>
Regmap functionality has been integrated into pinctrl-imx.c with commit
8626ada8 which might trigger build failures when regmap is not selected
otherwise. Hence, make Kconfig aware about this new dependency.

Signed-off-by: Alexander Kurz &lt;akurz@blala.de&gt;
Acked-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Revert "Revert "pinctrl: lantiq: Implement gpio_chip.to_irq""</title>
<updated>2016-04-01T13:21:27Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2016-04-01T13:21:27Z</published>
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<id>urn:sha1:e1641c9d174ee21b4a75a64ab6df9063cf60ac4a</id>
<content type='text'>
This reverts commit 446f59acb70b70a425ea4105277a71eb615327cd.
</content>
</entry>
<entry>
<title>pinctrl: qcom: ipq4019: fix register offsets</title>
<updated>2016-03-31T09:56:13Z</updated>
<author>
<name>Matthew McClintock</name>
<email>mmcclint@codeaurora.org</email>
</author>
<published>2016-03-23T22:04:58Z</published>
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<id>urn:sha1:a9b0b1fe9ecc6ca18ee710f23606532d6aafc05e</id>
<content type='text'>
For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

Signed-off-by: Matthew McClintock &lt;mmcclint@codeaurora.org&gt;
Acked-by: Björn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: ipq4019: fix the function enum for gpio mode</title>
<updated>2016-03-31T09:55:57Z</updated>
<author>
<name>Matthew McClintock</name>
<email>mmcclint@codeaurora.org</email>
</author>
<published>2016-03-23T22:04:57Z</published>
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<id>urn:sha1:cdbac7349f978dd3355e04a6724537964d6fdacd</id>
<content type='text'>
Without this, we would fail to set the mode to gpio if trying to
configure for that mode

Signed-off-by: Matthew McClintock &lt;mmcclint@codeaurora.org&gt;
Acked-by: Björn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: ipq4019: set ngpios to correct value</title>
<updated>2016-03-31T09:53:02Z</updated>
<author>
<name>Matthew McClintock</name>
<email>mmcclint@codeaurora.org</email>
</author>
<published>2016-03-23T22:04:56Z</published>
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<id>urn:sha1:5303f7827fcd41d1cf4da9ca9b6b7d360bc07bb7</id>
<content type='text'>
This should have been bumped to 100 when the extra pins
were added in the original pinctrl patch

Signed-off-by: Matthew McClintock &lt;mmcclint@codeaurora.org&gt;
Acked-by: Björn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: nomadik: fix pull debug print inversion</title>
<updated>2016-03-31T08:45:26Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2016-03-24T12:15:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6ee334559324a55725e22463de633b99ad99fcad'/>
<id>urn:sha1:6ee334559324a55725e22463de633b99ad99fcad</id>
<content type='text'>
Pull up was reported as pull down and vice versa. Fix this.

Fixes: 8f1774a2a971 "pinctrl: nomadik: improve GPIO debug prints"
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: implement gpio_irq_enable</title>
<updated>2016-03-30T08:57:52Z</updated>
<author>
<name>Qi Zheng</name>
<email>qi.zheng@intel.com</email>
</author>
<published>2016-03-16T18:15:26Z</published>
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<id>urn:sha1:a939bb57cd4716fdae213f6cb60a626fa6d5a60a</id>
<content type='text'>
There is unexpected gpio interrupt after irq_enable. If not
implemeted gpio_irq_enable callback, irq_enable calls irq_unmask
instead. But if there was interrupt set before the irq_enable,
unmask it may trigger the unexpected interrupt. By implementing
the gpio_irq_enable callback, do interrupt status ack, the issue
has gone.

Signed-off-by: Qi Zheng &lt;qi.zheng@intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Qipeng Zha &lt;qipeng.zha@intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
