linux/drivers/pinctrl, branch v4.8

pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33

2016-08-23T10:28:31Z

PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33 datasheets. However, the function is wrongly named "uart2" in the pinctrl driver. This patch fixes this by modifying them to be named "uart1". Cc: stable@vger.kernel.org Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Signed-off-by: Linus Walleij

pinctrl: cherryview: Do not mask all interrupts in probe

2016-08-22T13:57:04Z

The Cherryview GPIO controller has 8 or 16 wires connected to the I/O-APIC which can be used directly by the platform/BIOS or drivers. One such wire is used as SCI (System Control Interrupt) which ACPI depends on to be able to trigger GPEs (General Purpose Events). The pinctrl driver itself uses another IRQ resource which is wire OR of all the 8 (or 16) wires and follows what BIOS has programmed to the IntSel register of each pin. Currently the driver masks all interrupts at probe time and this prevents these direct interrupts from working as expected. The reason for this is that some early stage prototypes had some pins misconfigured causing lots of spurious interrupts. We fix this by leaving the interrupt mask untouched. This allows SCI and other direct interrupts work properly. What comes to the possible spurious interrupts we switch the default handler to be handle_bad_irq() instead of handle_simple_irq() (which was not correct anyway). Reported-by: Yu C Chen Reported-by: Anisse Astier Signed-off-by: Mika Westerberg Signed-off-by: Linus Walleij

pinctrl: pistachio: fix mfio pll_lock pinmux

2016-08-22T13:28:35Z

A previous patch attempted to fix the pinmuxes for mfio 84 - 89, but it omitted a change to pistachio_pin_group pistachio_groups, which results in incorrect pll_lock signals being routed. Apply the correct mux settings throughout the driver. fixes: cefc03e5995e ("pinctrl: Add Pistachio SoC pin control driver") fixes: e9adb336d0bf ("pinctrl: pistachio: fix mfio84-89 function description and pinmux.") Cc: # 4.4.x- Signed-off-by: James Hartley Reviewed-by: Sifan Naeem Signed-off-by: Linus Walleij

pinctrl: intel: merrifield: Add missed header

2016-08-10T13:46:28Z

On x86 builds the absense of makes static analyzer and compiler unhappy which fails to build the driver. CHECK drivers/pinctrl/intel/pinctrl-merrifield.c drivers/pinctrl/intel/pinctrl-merrifield.c:518:17: error: undefined identifier 'readl' drivers/pinctrl/intel/pinctrl-merrifield.c:570:17: error: undefined identifier 'readl' drivers/pinctrl/intel/pinctrl-merrifield.c:575:9: error: undefined identifier 'writel' drivers/pinctrl/intel/pinctrl-merrifield.c:645:17: error: undefined identifier 'readl' CC drivers/pinctrl/intel/pinctrl-merrifield.o drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_pin_dbg_show’: drivers/pinctrl/intel/pinctrl-merrifield.c:518:10: error: implicit declaration of function ‘readl’ [-Werror=implicit-function-declaration] value = readl(bufcfg); ^ drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_update_bufcfg’: drivers/pinctrl/intel/pinctrl-merrifield.c:575:2: error: implicit declaration of function ‘writel’ [-Werror=implicit-function-declaration] writel(value, bufcfg); ^ cc1: some warnings being treated as errors Add header to the top of the module. Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij

pinctrl/amd: Remove the default de-bounce time

2016-08-10T13:45:54Z

In the function amd_gpio_irq_enable() and amd_gpio_direction_input(), remove the code which is setting the default de-bounce time to 2.75ms. The driver code shall use the same settings as specified in BIOS. Any default assignment impacts TouchPad behaviour when the LevelTrig is set to EDGE FALLING. Cc: stable@vger.kernel.org Reviewed-by: Ken Xue Signed-off-by: Nitesh Kumar Agrawal Signed-off-by: Linus Walleij

pinctrl: pistachio: Drop pinctrl_unregister for devm_ registered device

2016-08-10T13:45:54Z

pinctrl: meson: Drop pinctrl_unregister for devm_ registered device

2016-08-10T13:45:54Z

It's not necessary to unregister pin controller device registered with devm_pinctrl_register() and using pinctrl_unregister() leads to a double free. This is detected by Coccinelle semantic patch. Fixes: e649f7ec8c5f ("pinctrl: meson: Use devm_pinctrl_register() for pinctrl registration") Signed-off-by: Wei Yongjun Reviewed-by: Dmitry Torokhov Acked-by: Kevin Hilman Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2016-07-29T00:06:51Z

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.8 kernel cycle. Nothing stands out as especially exiting: new drivers, new subdrivers, lots of cleanups and incremental features. Business as usual. New drivers: - New driver for Oxnas pin control and GPIO. This ARM-based chipset is used in a few storage (NAS) type devices. - New driver for the MAX77620/MAX20024 pin controller portions. - New driver for the Intel Merrifield pin controller. New subdrivers: - New subdriver for the Qualcomm MDM9615 - New subdriver for the STM32F746 MCU - New subdriver for the Broadcom NSP SoC. Cleanups: - Demodularization of bool compiled-in drivers. Apart from this there is just regular incremental improvements to a lot of drivers, especially Uniphier and PFC" * tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits) pinctrl: fix pincontrol definition for marvell pinctrl: xway: fix typo Revert "pinctrl: amd: make it explicitly non-modular" pinctrl: iproc: Add NSP and Stingray GPIO support pinctrl: Update iProc GPIO DT bindings pinctrl: bcm: add OF dependencies pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe() pinctrl: Add STM32F746 MCU support pinctrl: intel: Protect set wake flow by spin lock pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe() pinctrl: uniphier: add Ethernet pin-mux settings sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code pinctrl: ns2: fix return value check in ns2_pinmux_probe() pinctrl: qcom: update DT bindings with ebi2 groups pinctrl: qcom: establish proper EBI2 pin groups pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro Documentation: dt: Add new compatible to STM32 pinctrl driver bindings includes: dt-bindings: Add STM32F746 pinctrl DT bindings pinctrl: sunxi: fix nand0 function name for sun8i pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11 ...

Merge tag 'gpio-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

2016-07-27T02:16:01Z

Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.8 kernel cycle. The big news is the completion of the chardev ABI which I'm very happy about and apart from that it's an ordinary, quite busy cycle. The details are below. The patches are tested in linux-next for some time, patches to other subsystem mostly have ACKs. I got overly ambitious with configureing lines as input for IRQ lines but it turns out that some controllers have their interrupt-enable and input-enabling in orthogonal settings so the assumption that all IRQ lines are input lines does not hold. Oh well, revert and back to the drawing board with that. Core changes: - The big item is of course the completion of the character device ABI. It has now replaced and surpassed the former unmaintainable sysfs ABI: we can now hammer (bitbang) individual lines or sets of lines and read individual lines or sets of lines from userspace, and we can also register to listen to GPIO events from userspace. As a tie-in we have two new tools in tools/gpio: gpio-hammer and gpio-event-mon that illustrate the proper use of the new ABI. As someone said: the wild west days of GPIO are now over. - Continued to remove the pointless ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB Kconfig symbols. I'm patching hexagon, openrisc, powerpc, sh, unicore, ia64 and microblaze. These are either ACKed by their maintainers or patched anyways after a grace period and no response from maintainers. Some archs (ARM) come in from their trees, and others (x86) are still not fixed, so I might send a second pull request to root it out later in this merge window, or just defer to v4.9. - The GPIO tools are moved to the tools build system. New drivers: - New driver for the MAX77620/MAX20024. - New driver for the Intel Merrifield. - Enabled PCA953x for the TI PCA9536. - Enabled PCA953x for the Intel Edison. - Enabled R8A7792 in the RCAR driver. Driver improvements: - The STMPE and F7188x now supports the .get_direction() callback. - The Xilinx driver supports setting multiple lines at once. - ACPI support for the Vulcan GPIO controller. - The MMIO GPIO driver supports device tree probing. - The Acer One 10 is supported through the _DEP ACPI attribute. Cleanups: - A major cleanup of the OF/DT support code. It is way easier to read and understand now, probably this improves performance too. - Drop a few redundant .owner assignments. - Remove CLPS711x boardfile support: we are 100% DT" * tag 'gpio-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (67 commits) MAINTAINERS: Add INTEL MERRIFIELD GPIO entry gpio: dwapb: add missing fwnode_handle_put() in dwapb_gpio_get_pdata() gpio: merrifield: Protect irq_ack() and gpio_set() by lock gpio: merrifield: Introduce GPIO driver to support Merrifield gpio: intel-mid: Make it depend to X86_INTEL_MID gpio: intel-mid: Sort header block alphabetically gpio: intel-mid: Remove potentially harmful code gpio: rcar: add R8A7792 support gpiolib: remove duplicated include from gpiolib.c Revert "gpio: convince line to become input in irq helper" gpiolib: of_find_gpio(): Don't discard errors gpio: of: Allow overriding the device node gpio: free handles in fringe cases gpio: tps65218: Add platform_device_id table gpio: max77620: get gpio value based on direction gpio: lynxpoint: avoid potential warning on error path tools/gpio: add install section tools/gpio: move to tools buildsystem gpio: intel-mid: switch to devm_gpiochip_add_data() gpio: 74x164: Use spi_write() helper instead of open coding ...

pinctrl: fix pincontrol definition for marvell

2016-07-24T14:23:50Z

On Marvell mv88f6180 with pin control driver one can not use multi purpose pins 35 through 44. I'm using this controller on an embedded board and i found that the pin multiplexing is not the same as in the hardware spezification. This patch alters the pin description so that mpp pins 0 to 19 as well as 35 to 44 are usable. Pin settings i used can be found here: http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf Signed-off-by: Andreas Klinger Reviewed-by: Sebastian Hesselbarth Signed-off-by: Linus Walleij