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<title>linux/drivers/platform/chrome, branch v5.11</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.11</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.11'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-12-23T23:06:22Z</updated>
<entry>
<title>Merge tag 'tag-chrome-platform-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux</title>
<updated>2020-12-23T23:06:22Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-12-23T23:06:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a0881596757fbef5781dc3cde5e8393dc2eb7ae6'/>
<id>urn:sha1:a0881596757fbef5781dc3cde5e8393dc2eb7ae6</id>
<content type='text'>
Pull chrome platform updates from Benson Leung:
 "cros_ec_typec:

   - A series from Prashant for Type-C to implement TYPEC_STATUS,
     parsing USB PD Partner ID VDOs, and registering partner altmodes.

  cros_ec misc:

   - Don't treat RTC events as wakeup sources in cros_ec_proto"

* tag 'tag-chrome-platform-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux:
  platform/chrome: cros_ec_typec: Tolerate unrecognized mux flags
  platform/chrome: cros_ec_typec: Register partner altmodes
  platform/chrome: cros_ec_typec: Parse partner PD ID VDOs
  platform/chrome: cros_ec_typec: Introduce TYPEC_STATUS
  platform/chrome: cros_ec: Import Type C host commands
  platform/chrome: cros_ec_typec: Clear partner identity on device removal
  platform/chrome: cros_ec_typec: Fix remove partner logic
  platform/chrome: cros_ec_typec: Relocate set_port_params_v*() functions
  platform/chrome: Don't treat RTC events as wakeup sources
</content>
</entry>
<entry>
<title>Merge tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi</title>
<updated>2020-12-15T23:51:10Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-12-15T23:51:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=605ea5aafe1341ac9b2144516f898ac78ad49c40'/>
<id>urn:sha1:605ea5aafe1341ac9b2144516f898ac78ad49c40</id>
<content type='text'>
Pull spi updates from Mark Brown:
 "The big change this release has been some excellent work from Lukas
  Wunner which closes a bunch of holes in the cleanup paths for drivers,
  mainly introduced as a result of devm conversions causing bad
  interactions with the support SPI has for allocating the bus and
  driver data together.

  Together with some of the other work done it feels like we've turned
  the corner on several long standing pain points with the API.

  Summary:

   - Many cleanups around probe/remove and error handling from Lukas
     Wunner and Uwe Kleine-König, and further fixes around PM from Zhang
     Qilong.

   - Provide a mask for which bits of the mode can safely be configured
     by drivers and use that to fix an issue with the ADS7846 driver.

   - Documentation of the expected interactions between SPI and GPIO
     level chip select polarity configuration from H. Nikolaus Schaller,
     hopefully we're pretty much at the end of sorting out the
     interactions there. Thanks to Nikolaus, Sven Van Asbroeck and Linus
     Walleij for this.

   - DMA support for Allwinner sun6i controllers.

   - Support for Canaan K210 Designware implementations and Intel Adler
     Lake"

* tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (69 commits)
  spi: dt-bindings: clarify CS behavior for spi-cs-high and gpio descriptors
  spi: Limit the spi device max speed to controller's max speed
  spi: spi-geni-qcom: Use the new method of gpio CS control
  platform/chrome: cros_ec_spi: Drop bits_per_word assignment
  platform/chrome: cros_ec_spi: Don't overwrite spi::mode
  spi: dw: Add support for the Canaan K210 SoC SPI
  spi: dw: Add support for 32-bits max xfer size
  dt-bindings: spi: dw-apb-ssi: Add Canaan K210 SPI controller
  spi: Update DT binding docs to support SiFive FU740 SoC
  spi: atmel-quadspi: Fix use-after-free on unbind
  spi: npcm-fiu: Disable clock in probe error path
  spi: ar934x: Don't leak SPI master in probe error path
  spi: mt7621: Don't leak SPI master in probe error path
  spi: mt7621: Disable clock in probe error path
  media: netup_unidvb: Don't leak SPI master in probe error path
  spi: sc18is602: Don't leak SPI master in probe error path
  spi: rb4xx: Don't leak SPI master in probe error path
  spi: gpio: Don't leak SPI master in probe error path
  spi: spi-mtk-nor: Don't leak SPI master in probe error path
  spi: mxic: Don't leak SPI master in probe error path
  ...
</content>
</entry>
<entry>
<title>platform/chrome: cros_ec_typec: Tolerate unrecognized mux flags</title>
<updated>2020-12-10T21:05:16Z</updated>
<author>
<name>Prashant Malani</name>
<email>pmalani@chromium.org</email>
</author>
<published>2020-11-06T02:03:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6ae9b5ffcaeba64c290dfb8bd7b0194b1fdf0c92'/>
<id>urn:sha1:6ae9b5ffcaeba64c290dfb8bd7b0194b1fdf0c92</id>
<content type='text'>
On occasion, the Chrome Embedded Controller (EC) can send a mux
configuration which doesn't map to a particular data mode. For instance,
dedicated Type C chargers, when connected, may cause only
USB_PD_MUX_POLARITY_INVERTED to be set. This is a valid flag combination
and should not lead to a driver abort.

Modify the mux configuration handling to not return an error when an
unrecognized mux flag combination is encountered. Concordantly, make the
ensuing print a debug level print so as to not pollute the kernel logs.

Cc: Keith Short &lt;keithshort@chromium.org&gt;
Signed-off-by: Prashant Malani &lt;pmalani@chromium.org&gt;
Acked-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Signed-off-by: Benson Leung &lt;bleung@chromium.org&gt;
Link: https://lore.kernel.org/r/20201106020305.767202-1-pmalani@chromium.org
</content>
</entry>
<entry>
<title>platform/chrome: cros_ec_spi: Drop bits_per_word assignment</title>
<updated>2020-12-09T16:52:09Z</updated>
<author>
<name>Stephen Boyd</name>
<email>swboyd@chromium.org</email>
</author>
<published>2020-12-04T19:35:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7a5172b7990d97ab9ef64e6d9063aa68099ea023'/>
<id>urn:sha1:7a5172b7990d97ab9ef64e6d9063aa68099ea023</id>
<content type='text'>
This is already handed by default in spi_setup() if the bits_per_word is
0, so just drop it to shave off a line.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Gwendal Grignou &lt;gwendal@chromium.org&gt;
Reviewed-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Tested-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Acked-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Cc: Alexandru M Stan &lt;amstan@chromium.org&gt;
Signed-off-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Link: https://lore.kernel.org/r/20201204193540.3047030-3-swboyd@chromium.org
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>platform/chrome: cros_ec_spi: Don't overwrite spi::mode</title>
<updated>2020-12-09T16:52:08Z</updated>
<author>
<name>Stephen Boyd</name>
<email>swboyd@chromium.org</email>
</author>
<published>2020-12-04T19:35:38Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=74639cbf51d7c0304342544a83dfda354a6bd208'/>
<id>urn:sha1:74639cbf51d7c0304342544a83dfda354a6bd208</id>
<content type='text'>
There isn't any need to overwrite the mode here in the driver with what
has been detected by the firmware, such as DT or ACPI. In fact, if we
use the SPI CS gpio descriptor feature we will overwrite the mode with
SPI_MODE_0 where it already contains SPI_MODE_0 and more importantly
SPI_CS_HIGH. Clearing the SPI_CS_HIGH bit causes the CS line to toggle
when the device is probed when it shouldn't change, confusing the driver
and making it fail to probe. Drop the assignment and let the spi core
take care of it.

Fixes: a17d94f0b6e1 ("mfd: Add ChromeOS EC SPI driver")
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Gwendal Grignou &lt;gwendal@chromium.org&gt;
Reviewed-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Tested-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Acked-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Cc: Alexandru M Stan &lt;amstan@chromium.org&gt;
Signed-off-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Link: https://lore.kernel.org/r/20201204193540.3047030-2-swboyd@chromium.org
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>platform/chrome: cros_ec_typec: Correct the Thunderbolt rounded/non-rounded cable support</title>
<updated>2020-11-18T11:53:45Z</updated>
<author>
<name>Utkarsh Patel</name>
<email>utkarsh.h.patel@intel.com</email>
</author>
<published>2020-11-13T20:24:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5384cffd7bce4652271c80ca081f5d39118e4923'/>
<id>urn:sha1:5384cffd7bce4652271c80ca081f5d39118e4923</id>
<content type='text'>
Thunderbolt rounded/non-rounded cable support is two bits value. Correcting
it as per the Thunderbolt 3 cable discover mode VDO changes done in the
Thunderbolt 3 alternate mode header.

Signed-off-by: Utkarsh Patel &lt;utkarsh.h.patel@intel.com&gt;
Reviewed-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Acked-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
--
Changes in v2:
- Removed the fixes tag as there is no functional implication.
--
Link: https://lore.kernel.org/r/20201113202503.6559-3-utkarsh.h.patel@intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>platform/chrome: cros_ec_typec: Register partner altmodes</title>
<updated>2020-11-12T20:32:09Z</updated>
<author>
<name>Prashant Malani</name>
<email>pmalani@chromium.org</email>
</author>
<published>2020-10-29T22:27:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=de0f49487db3667f5204dcec6d3482c9bd1a0a30'/>
<id>urn:sha1:de0f49487db3667f5204dcec6d3482c9bd1a0a30</id>
<content type='text'>
Use the discovery data from the Chrome EC to register parter altmodes
with the Type C Connector Class framework. Also introduce a node
struct to keep track of the list of registered alt modes.

Signed-off-by: Prashant Malani &lt;pmalani@chromium.org&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Acked-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Cc: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201029222738.482366-8-pmalani@chromium.org
</content>
</entry>
<entry>
<title>platform/chrome: cros_ec_typec: Parse partner PD ID VDOs</title>
<updated>2020-11-12T20:32:09Z</updated>
<author>
<name>Prashant Malani</name>
<email>pmalani@chromium.org</email>
</author>
<published>2020-10-29T22:27:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f6f668118918f533676e51f3214f5a104562b59c'/>
<id>urn:sha1:f6f668118918f533676e51f3214f5a104562b59c</id>
<content type='text'>
Use EC_CMD_TYPE_DISCOVERY to retrieve and store the discovery data for
the port partner. With that data, update the PD Identity VDO values for
the partner, which were earlier not initialized.

Signed-off-by: Prashant Malani &lt;pmalani@chromium.org&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Acked-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Cc: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201029222738.482366-7-pmalani@chromium.org
</content>
</entry>
<entry>
<title>platform/chrome: cros_ec_typec: Introduce TYPEC_STATUS</title>
<updated>2020-11-12T20:32:09Z</updated>
<author>
<name>Prashant Malani</name>
<email>pmalani@chromium.org</email>
</author>
<published>2020-10-29T22:27:38Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=80f8cef60d79f23c02e546ba3de2fce84d5e8bdb'/>
<id>urn:sha1:80f8cef60d79f23c02e546ba3de2fce84d5e8bdb</id>
<content type='text'>
Make a call to the newly introduced EC_CMD_TYPEC_STATUS command.
Currently we just check to see if the SOP (port-partner) discovery was
done and emit a debug level print for it.

Subsequent patches will retrieve and parse the discovery data and fill
out the Type C connector class data structures.

Also check the EC_FEATURE_TYPEC_CMD feature flag at probe, and only call
the new TYPEC_STATUS command if the feature flag is supported.

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: Prashant Malani &lt;pmalani@chromium.org&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Link: https://lore.kernel.org/r/20201029222738.482366-6-pmalani@chromium.org
</content>
</entry>
<entry>
<title>platform/chrome: cros_ec_typec: Clear partner identity on device removal</title>
<updated>2020-11-12T20:32:09Z</updated>
<author>
<name>Prashant Malani</name>
<email>pmalani@chromium.org</email>
</author>
<published>2020-10-29T22:27:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=514acf1cefd020eb21d7c180050a8d66b723d2d8'/>
<id>urn:sha1:514acf1cefd020eb21d7c180050a8d66b723d2d8</id>
<content type='text'>
The partner identity struct isn't reset when a partner is removed,
meaning a subsequent partner can inherit an old partner's identity VDOs
before discovery is complete. So, clear that struct when a partner
removal is detected.

Signed-off-by: Prashant Malani &lt;pmalani@chromium.org&gt;
Signed-off-by: Enric Balletbo i Serra &lt;enric.balletbo@collabora.com&gt;
Link: https://lore.kernel.org/r/20201029222738.482366-4-pmalani@chromium.org
</content>
</entry>
</feed>
