<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/soc/tegra/cbb, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
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<updated>2026-03-27T14:30:54Z</updated>
<entry>
<title>soc/tegra: cbb: Fix cross-fabric target timeout lookup</title>
<updated>2026-03-27T14:30:54Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2026-01-21T10:12:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a5f51b04cbb3ae0f9cb2c4488952b775ebb0ccbf'/>
<id>urn:sha1:a5f51b04cbb3ae0f9cb2c4488952b775ebb0ccbf</id>
<content type='text'>
When a fabric receives an error interrupt, the error may have
occurred on a different fabric. The target timeout lookup was using
the wrong base address (cbb-&gt;regs) with offsets from a different
fabric's target map, causing a kernel page fault.

  Unable to handle kernel paging request at virtual address ffff80000954cc00
  pc : tegra234_cbb_get_tmo_slv+0xc/0x28
  Call trace:
   tegra234_cbb_get_tmo_slv+0xc/0x28
   print_err_notifier+0x6c0/0x7d0
   tegra234_cbb_isr+0xe4/0x1b4

Add tegra234_cbb_get_fabric() to look up the correct fabric device
using fab_id, and use its base address for accessing target timeout
registers.

Fixes: 25de5c8fe0801 ("soc/tegra: cbb: Improve handling for per SoC fabric data")
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: cbb: Fix incorrect ARRAY_SIZE in fabric lookup tables</title>
<updated>2026-03-27T14:30:50Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2026-01-21T10:12:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=499f7e5ebbdd9ff0c4d532b1c432f8a61ff585b3'/>
<id>urn:sha1:499f7e5ebbdd9ff0c4d532b1c432f8a61ff585b3</id>
<content type='text'>
Fix incorrect ARRAY_SIZE usage in fabric lookup tables which could
cause out-of-bounds access during target timeout lookup.

Fixes: 25de5c8fe0801 ("soc/tegra: cbb: Improve handling for per SoC fabric data")
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: cbb: Set ERD on resume for err interrupt</title>
<updated>2026-03-27T14:30:46Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2026-01-21T10:12:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b6ff71c5d1d4ad858ddf6f39394d169c96689596'/>
<id>urn:sha1:b6ff71c5d1d4ad858ddf6f39394d169c96689596</id>
<content type='text'>
Set the Error Response Disable (ERD) bit to mask SError responses
and use interrupt-based error reporting. When the ERD bit is set,
inband error responses to the initiator via SError are suppressed,
and fabric errors are reported via an interrupt instead.

The register is set during boot but the info is lost during system
suspend and needs to be set again on resume.

Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0")
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: cbb: Add support for CBB fabrics in Tegra238</title>
<updated>2026-03-27T14:24:54Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2026-03-25T12:57:26Z</published>
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<id>urn:sha1:ad7ffe102a52141a0da19ca766c5103bec28ddb6</id>
<content type='text'>
Add support for CBB 2.0 based fabrics in Tegra238 SoC using DT.
Fabrics reporting errors are: CBB, AON, BPMP, APE.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Resolve a spelling error in the tegra194-cbb.c</title>
<updated>2025-11-14T15:16:20Z</updated>
<author>
<name>Bruno Sobreira França</name>
<email>brunofrancadevsec@gmail.com</email>
</author>
<published>2025-10-24T01:35:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e13c1f34aa8675363f45593e85c125e15b9a4410'/>
<id>urn:sha1:e13c1f34aa8675363f45593e85c125e15b9a4410</id>
<content type='text'>
Fix a typo spotted during code reading.

Signed-off-by: Bruno Sobreira França &lt;brunofrancadevsec@gmail.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Acked-by: Uwe Kleine-König &lt;u.kleine-koenig@baylibre.com&gt;
Reviewed-by: Herve Codina &lt;herve.codina@bootlin.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: cbb: Add support for CBB fabrics in Tegra254</title>
<updated>2025-07-09T12:29:19Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2025-07-03T10:38:29Z</published>
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<id>urn:sha1:84daa158bb5e72ec279ab168892df86a25d3c459</id>
<content type='text'>
Add support for CBB 2.0 based fabrics in Tegra254 SoC using ACPI.
Fabrics reporting errors are: C2C, GPU and Display_Cluster. Tegra254
uses a hardware based lookup to get target node address, so the
target_map tables for each fabric are no longer needed.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: cbb: Add support for CBB fabrics in Tegra264</title>
<updated>2025-07-09T12:28:55Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2025-07-03T10:38:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=fa4854a9f5d6630df060a4aa5894f9b4eb8cc3ef'/>
<id>urn:sha1:fa4854a9f5d6630df060a4aa5894f9b4eb8cc3ef</id>
<content type='text'>
Add support for CBB 2.0 based fabrics in Tegra264 SoC using DT. Fabrics
reporting errors are: SYSTEM, TOP0, UPHY0 and VISION.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: cbb: Support HW lookup to get timed out target address</title>
<updated>2025-07-09T12:28:07Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2025-07-03T10:38:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5f2c2c439983ca3a208a0175f7793c355fab8566'/>
<id>urn:sha1:5f2c2c439983ca3a208a0175f7793c355fab8566</id>
<content type='text'>
Add support for hardware based lookup to get the address of the timed
out target node. This features is added in upcoming SoCs and avoids the
need for creating per fabric target_map tables in the driver.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: cbb: Improve handling for per SoC fabric data</title>
<updated>2025-07-09T12:27:41Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2025-07-03T10:38:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=25de5c8fe0801361182b41c42f086bd089feda14'/>
<id>urn:sha1:25de5c8fe0801361182b41c42f086bd089feda14</id>
<content type='text'>
Improve handling for the per SoC fabrics and targets.
The below changes make them more flexible and ready for future SoC's.
- Added SoC prefix to Fabric_ID enums.
- Rename *lookup_target_timeout() to *sw_lookup_target_timeout() to
  make it separate from HW based lookup function to be added later.
- Moved target_map within fabric_lookup table to make it easy to
  check whether SW vs HW lookup is supported and handle accordingly.
- Slight improvements to some error prints.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: cbb: Make error interrupt enable and status per SoC</title>
<updated>2025-07-09T12:27:14Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2025-07-03T10:38:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2f2c32f9cc940f908b42d070207c6d503362793c'/>
<id>urn:sha1:2f2c32f9cc940f908b42d070207c6d503362793c</id>
<content type='text'>
Make the error interrupt enable and error status fields as per SoC. Both
of these fields can change for different SoC's. Moving them to per SoC
data helps to set or clear the required bits only for a SoC.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
