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<title>linux/drivers/soc, branch v3.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v3.17</id>
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<updated>2014-09-24T04:38:32Z</updated>
<entry>
<title>drivers/soc: qcom: do not disable the iface clock in probe</title>
<updated>2014-09-24T04:38:32Z</updated>
<author>
<name>Srinivas Kandagatla</name>
<email>srinivas.kandagatla@linaro.org</email>
</author>
<published>2014-09-23T19:20:54Z</published>
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<id>urn:sha1:fa9eb3241895d2771b87f20dd23b40de664c5e4e</id>
<content type='text'>
since commit 31964ffebbb9 ("tty: serial: msm: Remove direct access to GSBI")'
serial hangs if earlyprintk are enabled.

This hang is noticed only when the GSBI driver is probed and all the
earlyprintks before gsbi probe are seen on the console.
The reason why it hangs is because GSBI driver disables hclk in its
probe function without realizing that the serial IP might be in use by
a bootconsole. As gsbi driver disables the clock in probe the
bootconsole locks up.

Turning off hclk's could be dangerous if there are system components
like earlyprintk using the hclk.

This patch fixes the issue by delegating the clock management to
probe and remove functions in gsbi rather than disabling the clock in probe.

More detailed problem description can be found here:
http://www.spinics.net/lists/linux-arm-msm/msg10589.html

Tested-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Convert PMC to a driver</title>
<updated>2014-07-17T12:58:43Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T11:19:06Z</published>
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<id>urn:sha1:7232398abc6a7186e315425638c367d50c674718</id>
<content type='text'>
This commit converts the PMC support code to a platform driver. Because
the boot process needs to call into this driver very early, also set up
a minimal environment via an early initcall.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Set up in early initcall</title>
<updated>2014-07-17T12:58:42Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T09:13:30Z</published>
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<id>urn:sha1:24fa5af81059af90c723bec6aacc3cd2b2809d14</id>
<content type='text'>
Rather than rely on explicit initialization order called from SoC setup
code, use a plain initcall and rely on initcall ordering to take care of
dependencies.

This driver exposes some functionality (querying the chip ID) needed at
very early stages of the boot process. An early initcall is good enough
provided that some of the dependencies are deferred to later stages. To
make sure any abuses are easily caught, output a warning message if the
chip ID is queried while it can't be read yet.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Implement runtime check for Tegra SoCs</title>
<updated>2014-07-17T12:58:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-16T12:01:44Z</published>
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<id>urn:sha1:a2686766c81e18fb1ab9375cf5d3cbd54a3bed2c</id>
<content type='text'>
Subsequent patches will move some of the initialization code from SoC
setup code to regular initcalls. To prevent breakage on other SoCs in
multi-platform builds, these initcalls need to check that they indeed
run on Tegra.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: fix dummy functions</title>
<updated>2014-07-17T12:38:29Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-06-16T21:05:04Z</published>
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<id>urn:sha1:2fa937a767bd0933dfe6017cabd038ce52594171</id>
<content type='text'>
The Tegra fuse header's dummy functions for the case where Tegra20 is
disabled are inconsistent with the correct prototypes, and have some
syntax errors. Fix these. While at it, fix the indentation level of
the dummy function bodies.

Fixes: 783c8f4c8445 ("soc/tegra: Add efuse driver for Tegra")
Cc: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: move APB DMA into Tegra20 fuse driver</title>
<updated>2014-07-17T12:37:12Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-06-12T15:36:40Z</published>
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<id>urn:sha1:0d827a4343b596b71a1741328c4e5687ce654e19</id>
<content type='text'>
The Tegra20 fuse driver is the only user of tegra_apb_readl_using_dma().
Therefore we can simply the code by incorporating the APB DMA handling into
the driver directly. tegra_apb_writel_using_dma() is dropped because there
are no users.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Add efuse driver for Tegra</title>
<updated>2014-07-17T12:36:01Z</updated>
<author>
<name>Peter De Schrijver</name>
<email>pdeschrijver@nvidia.com</email>
</author>
<published>2014-06-12T15:36:37Z</published>
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<id>urn:sha1:783c8f4c84451bc444e314a71b447239c6ef6fd9</id>
<content type='text'>
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This
replaces functionality previously provided in arch/arm/mach-tegra, which
is removed in this patch.

While at it, move the only user of the global tegra_revision variable
over to tegra_sku_info.revision and export tegra_fuse_readl() to allow
drivers to read calibration fuses.

Signed-off-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc: qcom: fix of_device_id table</title>
<updated>2014-05-26T19:27:09Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2014-05-26T16:07:05Z</published>
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<id>urn:sha1:1b7f0c7b931864642e825a6fd01cde5881b064cc</id>
<content type='text'>
The match tables must be zero-terminated, and Kbuild now helpfully
fails to link the kernel if that isn't the case.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>soc: qcom: Add GSBI driver</title>
<updated>2014-05-23T16:38:04Z</updated>
<author>
<name>Andy Gross</name>
<email>agross@codeaurora.org</email>
</author>
<published>2014-04-24T16:31:21Z</published>
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<id>urn:sha1:5d144e36b7c51612922fa05d37ff3a869261cc82</id>
<content type='text'>
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors.  The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.

Signed-off-by: Andy Gross &lt;agross@codeaurora.org&gt;
Signed-off-by: Kumar Gala &lt;galak@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>soc: Introduce drivers/soc place-holder for SOC specific drivers</title>
<updated>2014-05-23T16:37:46Z</updated>
<author>
<name>Santosh Shilimkar</name>
<email>santosh.shilimkar@ti.com</email>
</author>
<published>2014-04-23T23:46:17Z</published>
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<id>urn:sha1:3a6e08218f36baa9c49282ad2fe0dfbf001d8f23</id>
<content type='text'>
Based on earlier thread "https://lkml.org/lkml/2013/10/7/662" and
discussion at Kernel Summit'2013, it was agreed to create
'driver/soc' for drivers which are quite SOC specific.

Further discussion on the subject is in response to
the earlier version of the patch is here:
	http://lwn.net/Articles/588942/

Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Kumar Gala &lt;galak@codeaurora.org&gt;
Cc: Paul Walmsley &lt;paul@pwsan.com&gt;
Cc: Olof Johansson &lt;olof@lixom.net&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Sandeep Nair &lt;sandeep_n@ti.com&gt;
Signed-off-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
Signed-off-by: Kumar Gala &lt;galak@codeaurora.org&gt;
</content>
</entry>
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