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<title>linux/drivers/spi, branch v3.16</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v3.16</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v3.16'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2014-06-28T13:01:23Z</updated>
<entry>
<title>Merge remote-tracking branches 'spi/fix/pxa2xx', 'spi/fix/qup' and 'spi/fix/sh-sci' into spi-linus</title>
<updated>2014-06-28T13:01:23Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2014-06-28T13:01:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7216a4183947853f359b41ba1edb5db9b3091acc'/>
<id>urn:sha1:7216a4183947853f359b41ba1edb5db9b3091acc</id>
<content type='text'>
</content>
</entry>
<entry>
<title>spi: qup: Remove chip select function</title>
<updated>2014-06-22T10:48:09Z</updated>
<author>
<name>Andy Gross</name>
<email>agross@codeaurora.org</email>
</author>
<published>2014-06-12T19:34:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4a8573abe965115bc5b064401fd669b74e985258'/>
<id>urn:sha1:4a8573abe965115bc5b064401fd669b74e985258</id>
<content type='text'>
This patch removes the chip select function.  Chip select should instead be
supported using GPIOs, defining the DT entry "cs-gpios", and letting the SPI
core assert/deassert the chip select as it sees fit.

The chip select control inside the controller is buggy.  It is supposed to
automatically assert the chip select based on the activity in the controller,
but it is buggy and doesn't work at all.  So instead we elect to use GPIOs.

Signed-off-by: Andy Gross &lt;agross@codeaurora.org&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>spi: qup: Fix order of spi_register_master</title>
<updated>2014-06-21T10:11:54Z</updated>
<author>
<name>Andy Gross</name>
<email>agross@codeaurora.org</email>
</author>
<published>2014-06-12T19:34:11Z</published>
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<id>urn:sha1:045c243a511c8b688d36659cc3f781e84e9c2ddb</id>
<content type='text'>
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm.  If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.

Signed-off-by: Andy Gross &lt;agross@codeaurora.org&gt;
Acked-by: Ivan T. Ivanov &lt;iivanov@mm-sol.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>spi: sh-sci: fix use-after-free in sh_sci_spi_remove()</title>
<updated>2014-06-17T14:47:31Z</updated>
<author>
<name>Jürg Billeter</name>
<email>j@bitron.ch</email>
</author>
<published>2014-06-16T14:39:29Z</published>
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<id>urn:sha1:25f8a7cc5856f1c697c9aee88b0a898fcb6d788c</id>
<content type='text'>
setbits() uses sp-&gt;membase.

Signed-off-by: Jürg Billeter &lt;j@bitron.ch&gt;
Acked-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI</title>
<updated>2014-06-17T14:45:52Z</updated>
<author>
<name>Chew, Chiau Ee</name>
<email>chiau.ee.chew@intel.com</email>
</author>
<published>2014-06-13T15:57:25Z</published>
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<id>urn:sha1:e61f487fd596ce570e87ccfdc0a7fc9fa87aced9</id>
<content type='text'>
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.

Signed-off-by: Chew, Chiau Ee &lt;chiau.ee.chew@intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>spi/pxa2xx: change default supported DMA burst size to 1</title>
<updated>2014-06-06T09:52:46Z</updated>
<author>
<name>Chew, Chiau Ee</name>
<email>chiau.ee.chew@intel.com</email>
</author>
<published>2014-06-05T17:45:09Z</published>
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<id>urn:sha1:01d7aafb3fbaafe2403780ef9ed497b3289ab1b9</id>
<content type='text'>
This is to fix the SPI DMA transfer failure for speed less than 1M.
If using current DMA burst size setting (16), the Rx data bytes are
invalid due to each data byte is multiplied according to the burst
size setting.

Let's said supposedly we shall receive the following 18 bytes of data:
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18
Instead, the data bytes received consist of "16 bytes of '01' +
2 bytes of '02'" :
01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 02 02

Signed-off-by: Chew, Chiau Ee &lt;chiau.ee.chew@intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'spi/topic/workqueue' into spi-next</title>
<updated>2014-06-02T16:08:43Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2014-06-02T16:08:43Z</published>
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<id>urn:sha1:69e25c755722056b57892bebeb1892e3a6fe8774</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge remote-tracking branches 'spi/topic/oom', 'spi/topic/pxa2xx', 'spi/topic/rspi' and 'spi/topic/sirf' into spi-next</title>
<updated>2014-06-02T16:08:41Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2014-06-02T16:08:41Z</published>
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<id>urn:sha1:301d8384b5516596cf53b88478b4b379aa09208a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge remote-tracking branches 'spi/topic/dw', 'spi/topic/fsl', 'spi/topic/fsl-espi' and 'spi/topic/id-const' into spi-next</title>
<updated>2014-06-02T16:08:38Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2014-06-02T16:08:38Z</published>
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<id>urn:sha1:8fb3b066a60ec1e39dc2f91eb87e91f434e4da81</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge remote-tracking branches 'spi/topic/adi', 'spi/topic/atmel' and 'spi/topic/cadence' into spi-next</title>
<updated>2014-06-02T16:08:35Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2014-06-02T16:08:35Z</published>
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<id>urn:sha1:446fe5e2d5616eb52c928e58f16558ab7c0d2414</id>
<content type='text'>
</content>
</entry>
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