linux/drivers/tty/serial/sh-sci.c, branch v6.4

tty: serial: sh-sci: Fix end of transmission on SCI

2023-04-20T11:47:33Z

We need to set TE to "0" (i.e., disable serial transmission) to get the expected behavior of the end of serial transmission. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230412145053.114847-6-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman

tty: serial: sh-sci: Add support for tx end interrupt handling

2023-04-20T11:47:33Z

As per the RZ/G2L users hardware manual (Rev.1.20 Sep, 2022), section 23.3.7 Serial Data Transmission (Asynchronous Mode), it is mentioned that, set the SCR.TIE bit to 0 and SCR.TEIE bit to 1, after the last data to be transmitted are written to the TDR. This will generate tx end interrupt and in the handler set SCR.TE and SCR.TEIE to 0. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230412145053.114847-5-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman

tty: serial: sh-sci: Fix TE setting on SCI IP

2023-04-20T11:47:33Z

As per the RZ/G2L users hardware manual (Rev.1.20 Sep, 2022), section 23.3.7 Serial Data Transmission (Asynchronous Mode) it is mentioned that the TE (transmit enable) must be set after setting TIE (transmit interrupt enable) or these 2 bits are set to 1 simultaneously by a single instruction. So set these 2 bits in single instruction. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230412145053.114847-4-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman

tty: serial: sh-sci: Add RZ/G2L SCIFA DMA rx support

2023-04-20T11:47:33Z

SCIFA IP on RZ/G2L SoC has the same signal for both interrupt and DMA transfer request. Setting DMARS register for DMA transfer makes the signal to work as a DMA transfer request signal and subsequent interrupt requests to the interrupt controller are masked. Similarly clearing DMARS register makes signal to work as interrupt signal and subsequent interrupt requests to the interrupt controller are unmasked. Add SCIFA DMA rx support for RZ/G2L alike SoCs by disabling RXI line interrupt and setting DMARS registers by DMA api for DMA transfer request. Apart from this, we must set FIFO trigger to 1 for the expected behavior of the receive transmission. While at it replace the parameter irq to s->irqs[SCIx_RXI_IRQ] in disable_irq_nosync() to match enable_irq() in sci_dma_rx_reenable_irq(). Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230412145053.114847-3-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman

tty: serial: sh-sci: Add RZ/G2L SCIFA DMA tx support

2023-04-20T11:47:33Z

SCIFA IP on RZ/G2L SoC has the same signal for both interrupt and DMA transfer request. Setting DMARS register for DMA transfer makes the signal to work as a DMA transfer request signal and subsequent interrupt requests to the interrupt controller are masked. Similarly clearing DMARS register makes signal to work as interrupt signal and subsequent interrupt requests to the interrupt controller are unmasked. Add SCIFA DMA tx support for RZ/G2L alike SoCs by disabling TXI line interrupt and setting DMARS registers by DMA api for DMA transfer request. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230412145053.114847-2-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman

Merge 6.3-rc6 into tty-next

2023-04-10T06:51:09Z

We need the tty/serial fixes in here for testing. Signed-off-by: Greg Kroah-Hartman

tty: serial: sh-sci: Fix Rx on RZ/G2L SCI

2023-03-29T09:00:37Z

SCI IP on RZ/G2L alike SoCs do not need regshift compared to other SCI IPs on the SH platform. Currently, it does regshift and configuring Rx wrongly. Drop adding regshift for RZ/G2L alike SoCs. Fixes: dfc80387aefb ("serial: sh-sci: Compute the regshift value for SCI ports") Cc: stable@vger.kernel.org Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230321114753.75038-3-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman

tty: serial: sh-sci: Fix transmit end interrupt handler

2023-03-29T08:58:14Z

The fourth interrupt on SCI port is transmit end interrupt compared to the break interrupt on other port types. So, shuffle the interrupts to fix the transmit end interrupt handler. Fixes: e1d0be616186 ("sh-sci: Add h8300 SCI") Cc: stable Suggested-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230317150403.154094-1-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman

tty: serial: sh-sci: Remove setting {src,dst}_{addr,addr_width} based on DMA direction

2023-03-29T08:54:15Z

The direction field in the DMA config is deprecated. The sh-sci driver sets {src,dst}_{addr,addr_width} based on the DMA direction and it results in dmaengine_slave_config() failure as RZ DMAC driver validates {src,dst}_addr_width values independent of DMA direction. Fix this issue by passing both {src,dst}_{addr,addr_width} values independent of DMA direction. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230322074717.6057-1-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: mark OF related data as maybe unused

2023-03-16T12:02:17Z

The driver can be compile tested with !CONFIG_OF making certain data unused: drivers/tty/serial/sh-sci.c:3144:34: error: ‘of_sci_match’ defined but not used [-Werror=unused-const-variable=] Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230310222957.315848-1-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman