linux/drivers/tty/serial/sh-sci.h, branch v4.5

serial: sh-sci: Add BRG register definitions

2015-12-17T10:18:44Z

Add register definitions for the Baud Rate Generator for External Clock (BRG), as found in some SCIF and in HSCIF, including a new regtype for the "SH-4(A)"-derived SCIF variant with BRG. Signed-off-by: Geert Uytterhoeven Acked-by: Greg Kroah-Hartman

serial: sh-sci: Correct SCIF_ERROR_CLEAR for plain SCIF

2015-10-04T16:33:48Z

SCIF_ERROR_CLEAR includes SCIFA_ORER, which exists only on SCIFA/SCIFB and SCIF on sh7705/sh7720/sh7721. To fix this: 1. Remove SCIFA_ORER from the definition of SCIF_ERROR_CLEAR, 2. During initialization, store the error clear mask to use, incorporating the overrun bit only if it applies to the SCxSR register. Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: Prevent compiler warnings on 64-bit

2015-10-04T16:33:48Z

Expressions involving "BIT(...)" create values of type "long", which is 64-bit on 64-bit. Hence "~BIT(...)" no longer fits in 32-bit, which will cause future compiler warnings when assigning to 32-bit variables: drivers/tty/serial/sh-sci.c: In function 'sci_init_single': drivers/tty/serial/sh-sci.h:58:25: warning: large integer implicitly truncated to unsigned type [-Woverflow] #define SCI_ERROR_CLEAR ~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER) ^ drivers/tty/serial/sh-sci.c:2325:27: note: in expansion of macro 'SCI_ERROR_CLEAR' sci_port->error_clear = SCI_ERROR_CLEAR; As these values are (at most) 32-bit register values anyway, cast them to "u32" at the definition level to prevent such compiler warnings. Reported-by: kbuild test robot Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: Replace buggy big #ifdef by runtime logic

2015-10-04T16:33:48Z

The #ifdef logic to clear SCxSR bits using RMW on SCIFA/SCIFB and SCIF variants with some SCIFA features (sh7705/SH7720/sh7721) has several drawbacks: - It wasn't updated for newer R-Mobile variants (APE6), - It doesn't correctly handle SoCs with both SCIF and SCIFA/B (e.g. R-Car Gen2, but also legacy sh7723/sh7724), - It doesn't play well with ARM multi-platform kernels: on R-Car Gen2, SCIF/SCIFA/SCIFB/HSCIF were handled differently, depending on whether r8a7740 or sh73a0 support was enabled or not, Replace the #ifdef logic by runtime logic to fix this. SCIFA/SCIFB and SCIF on sh7705/sh7720/sh7721 use RMW to clear error bits, other variants use plain stores, as before. Note that this changes behavior for SCIFA on sh7723/sh7724 (these SoCs have both SCIF and SCIFA), which didn't use RMW before. Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: Replace hardcoded overrun bit values

2015-05-10T17:06:39Z

Add the missing overrun bit definition for (H)SCIF. Replace overrun_bit by overrun_mask, so we can use the existing defines instead of hardcoded values. Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: Replace hardcoded values in SCxSR_*_CLEAR macros

2015-05-10T17:06:38Z

Add the missing overrun error bit in SCxSR on SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721. Document what the corresponding bit(s) on plain SCIF are used for. Sort the components of SCIF_DEFAULT_ERROR_MASK by reverse definition order. Replace the hardcoded values in the SCxSR_*_CLEAR macros by proper defines. Use bit masks (negations of sets of bits) to make it more obvious which bits are being cleared. Assembler output (on sh) was compared before and after this commit: - For the first branch of the big "#if defined(...) || ..." construct, the code has changed slightly, as 32-bit bitmasks can be loaded in a single instruction, unlike the old large 16-bit constants (the SCxSR register is 16 bit, so we don't care about the top 16 bits), - For the second branch, the generated code is identical. Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: Standardize on using the BIT() macro to define register bits

2015-05-10T17:06:38Z

Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: Document remaining FIFO Control Register bits

2015-05-10T17:06:38Z

Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: Add SCIFA/B SCPCR register definitions

2015-05-10T17:06:38Z

Add the register definitions for the Serial Port Control and Data Registers on SCIFA/SCIFB, which are needed for RTS/CTS pin control. Extracted from patches by Magnus Damm . Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman

serial: sh-sci: Add (H)SCIF RTS/CTS pin data register bit definitions

2015-05-10T17:06:38Z

Add the missing register bit definitions to set the RTS pin and read the CTS pin on (H)SCIF. Extracted from patches by Magnus Damm . Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman