linux/drivers/tty/serial, branch v6.17

Merge tag 'tty-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

2025-09-14T17:54:54Z

Pull tty/serial fixes from Greg KH: "Here are some small tty and serial driver fixes for 6.17-rc6 that resolve some reported problems. Included in here are: - 8250 driver dt bindings fixes - broadcom serial driver binding fixes - hvc_console bugfix - xilinx serial driver bugfix - sc16is7xx serial driver bugfix All of these have been in linux-next for the past week with no reported issues" * tag 'tty-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: serial: xilinx_uartps: read reg size from DTS tty: hvc_console: Call hvc_kick in hvc_write unconditionally dt-bindings: serial: 8250: allow "main" and "uart" as clock names dt-bindings: serial: 8250: move a constraint dt-bindings: serial: brcm,bcm7271-uart: Constrain clocks serial: sc16is7xx: fix bug in flow control levels init

serial: xilinx_uartps: read reg size from DTS

2025-09-06T13:51:47Z

Current implementation uses `CDNS_UART_REGISTER_SPACE(0x1000)` for request_mem_region() and ioremap() in cdns_uart_request_port() API. The cadence/xilinx IP has register space defined from offset 0x0 to 0x48. It also mentions that the register map is defined as [6:0]. So, the upper region may/maynot be used based on the IP integration. In Axiado AX3000 SoC two UART instances are defined 0x100 apart. That is creating issue in some other instance due to overlap with addresses. Since, this address space is already being defined in the devicetree, use the same when requesting the register space. Fixes: 1f7055779001 ("arm64: dts: axiado: Add initial support for AX3000 SoC and eval board") Acked-by: Michal Simek Signed-off-by: Harshit Shah Link: https://lore.kernel.org/r/20250902-xilinx-uartps-reg-size-v3-1-d11cfa7258e3@axiado.com Signed-off-by: Greg Kroah-Hartman

serial: sc16is7xx: fix bug in flow control levels init

2025-08-14T10:08:35Z

When trying to set MCR[2], XON1 is incorrectly accessed instead. And when writing to the TCR register to configure flow control levels, we are incorrectly writing to the MSR register. The default value of $00 is then used for TCR, which means that selectable trigger levels in FCR are used in place of TCR. TCR/TLR access requires EFR[4] (enable enhanced functions) and MCR[2] to be set. EFR[4] is already set in probe(). MCR access requires LCR[7] to be zero. Since LCR is set to $BF when trying to set MCR[2], XON1 is incorrectly accessed instead because MCR shares the same address space as XON1. Since MCR[2] is unmodified and still zero, when writing to TCR we are in fact writing to MSR because TCR/TLR registers share the same address space as MSR/SPR. Fix by first removing useless reconfiguration of EFR[4] (enable enhanced functions), as it is already enabled in sc16is7xx_probe() since commit 43c51bb573aa ("sc16is7xx: make sure device is in suspend once probed"). Now LCR is $00, which means that MCR access is enabled. Also remove regcache_cache_bypass() calls since we no longer access the enhanced registers set, and TCR is already declared as volatile (in fact by declaring MSR as volatile, which shares the same address). Finally disable access to TCR/TLR registers after modifying them by clearing MCR[2]. Note: the comment about "... and internal clock div" is wrong and can be ignored/removed as access to internal clock div registers (DLL/DLH) is permitted only when LCR[7] is logic 1, not when enhanced features is enabled. And DLL/DLH access is not needed in sc16is7xx_startup(). Fixes: dfeae619d781 ("serial: sc16is7xx") Cc: stable@vger.kernel.org Signed-off-by: Hugo Villeneuve Link: https://lore.kernel.org/r/20250731124451.1108864-1-hugo@hugovil.com Signed-off-by: Greg Kroah-Hartman

module: Rename EXPORT_SYMBOL_GPL_FOR_MODULES to EXPORT_SYMBOL_FOR_MODULES

2025-08-11T14:16:36Z

Christoph suggested that the explicit _GPL_ can be dropped from the module namespace export macro, as it's intended for in-tree modules only. It would be possible to restrict it technically, but it was pointed out [2] that some cases of using an out-of-tree build of an in-tree module with the same name are legitimate. But in that case those also have to be GPL anyway so it's unnecessary to spell it out in the macro name. Link: https://lore.kernel.org/all/aFleJN_fE-RbSoFD@infradead.org/ [1] Link: https://lore.kernel.org/all/CAK7LNATRkZHwJGpojCnvdiaoDnP%2BaeUXgdey5sb_8muzdWTMkA@mail.gmail.com/ [2] Suggested-by: Christoph Hellwig Reviewed-by: Shivank Garg Acked-by: David Hildenbrand Acked-by: Nicolas Schier Reviewed-by: Daniel Gomez Reviewed-by: Christian Brauner Signed-off-by: Vlastimil Babka Link: https://lore.kernel.org/20250808-export_modules-v4-1-426945bcc5e1@suse.cz Signed-off-by: Christian Brauner

treewide: rename GPIO set callbacks back to their original names

2025-08-07T08:07:06Z

The conversion of all GPIO drivers to using the .set_rv() and .set_multiple_rv() callbacks from struct gpio_chip (which - unlike their predecessors - return an integer and allow the controller drivers to indicate failures to users) is now complete and the legacy ones have been removed. Rename the new callbacks back to their original names in one sweeping change. Signed-off-by: Bartosz Golaszewski

Merge tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2025-07-31T18:08:55Z

Pull MIPS updates from Thomas Bogendoerfer: - DT updates for ralink, mobileye and atheros/qualcomm - Clean up of mc146818 usage - Speed up delay calibration for CPS - Other cleanups and fixes * tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (50 commits) MIPS: Don't use %pK through printk MIPS: Update Joshua Kinard's e-mail address MIPS: mobileye: dts: eyeq5,eyeq6h: rename the emmc controller MIPS: mm: tlb-r4k: Uniquify TLB entries on init MIPS: SGI-IP27: Delete an unnecessary check before kfree() in hub_domain_free() mips/malta,loongson2ef: use generic mc146818_get_time function mips: remove redundant macro mc146818_decode_year mips/mach-rm: remove custom mc146818rtc.h file mips: remove unused function mc146818_set_rtc_mmss MIPS: CPS: Optimise delay CPU calibration for SMP MIPS: CPS: Improve mips_cps_first_online_in_cluster() MIPS: disable MMID when not supported by the hardware MIPS: eyeq5_defconfig: add I2C subsystem, driver and temp sensor driver MIPS: eyeq5_defconfig: add GPIO subsystem & driver MIPS: mobileye: eyeq5: add two GPIO bank nodes MIPS: mobileye: eyeq5: add evaluation board I2C temp sensor MIPS: mobileye: eyeq5: add 5 I2C controller nodes MIPS: eyeq5_defconfig: Update for v6.16-rc1 MIPS: vpe-mt: add missing prototypes for vpe_{alloc,start,stop,free} mips: boot: use 'targets' instead of extra-y in Makefile ...

MIPS: Update Joshua Kinard's e-mail address

2025-07-28T07:57:24Z

I am switching my address to a personal domain, so some files in the SGI IP30 and IOC3 files need to be updated. I will send updates for the MAINTAINERS file and rtc-ds1685 separately to linux-rtc. Signed-off-by: Joshua Kinard Signed-off-by: Thomas Bogendoerfer

serial: 8250: fix panic due to PSLVERR

2025-07-24T09:40:41Z

When the PSLVERR_RESP_EN parameter is set to 1, the device generates an error response if an attempt is made to read an empty RBR (Receive Buffer Register) while the FIFO is enabled. In serial8250_do_startup(), calling serial_port_out(port, UART_LCR, UART_LCR_WLEN8) triggers dw8250_check_lcr(), which invokes dw8250_force_idle() and serial8250_clear_and_reinit_fifos(). The latter function enables the FIFO via serial_out(p, UART_FCR, p->fcr). Execution proceeds to the serial_port_in(port, UART_RX). This satisfies the PSLVERR trigger condition. When another CPU (e.g., using printk()) is accessing the UART (UART is busy), the current CPU fails the check (value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR) in dw8250_check_lcr(), causing it to enter dw8250_force_idle(). Put serial_port_out(port, UART_LCR, UART_LCR_WLEN8) under the port->lock to fix this issue. Panic backtrace: [ 0.442336] Oops - unknown exception [#1] [ 0.442343] epc : dw8250_serial_in32+0x1e/0x4a [ 0.442351] ra : serial8250_do_startup+0x2c8/0x88e ... [ 0.442416] console_on_rootfs+0x26/0x70 Fixes: c49436b657d0 ("serial: 8250_dw: Improve unwritable LCR workaround") Link: https://lore.kernel.org/all/84cydt5peu.fsf@jogness.linutronix.de/T/ Signed-off-by: Yunhui Cui Reviewed-by: John Ogness Cc: stable Link: https://lore.kernel.org/r/20250723023322.464-2-cuiyunhui@bytedance.com Signed-off-by: Greg Kroah-Hartman

serial: qcom-geni: Enable Serial on SA8255p Qualcomm platforms

2025-07-22T16:52:51Z

The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages UART baud rates, with each baud rate represented by a performance level. The driver uses the dev_pm_opp_set_level() API to request the desired baud rate by specifying the performance level. Reviewed-by: Bryan O'Donoghue Signed-off-by: Praveen Talari Link: https://lore.kernel.org/r/20250721174532.14022-9-quic_ptalari@quicinc.com Signed-off-by: Greg Kroah-Hartman

serial: qcom-geni: Enable PM runtime for serial driver

2025-07-22T16:52:51Z

The GENI serial driver currently handles power resource management through calls to the statically defined geni_serial_resources_on() and geni_serial_resources_off() functions. This approach reduces modularity and limits support for platforms with diverse power management mechanisms, including resource managed by firmware. Improve modularity and enable better integration with platform-specific power management, introduce support for runtime PM. Use pm_runtime_resume_and_get() and pm_runtime_put_sync() within the qcom_geni_serial_pm() callback to control resource power state transitions based on UART power state changes. Reviewed-by: Bryan O'Donoghue Signed-off-by: Praveen Talari Link: https://lore.kernel.org/r/20250721174532.14022-8-quic_ptalari@quicinc.com Signed-off-by: Greg Kroah-Hartman