<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/include/asm-xtensa/pgalloc.h, branch v2.6.23</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v2.6.23</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v2.6.23'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2007-08-27T20:54:16Z</updated>
<entry>
<title>[XTENSA] Add support for cache-aliasing</title>
<updated>2007-08-27T20:54:16Z</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2007-08-22T17:14:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6656920b0b50beacb6cb64cf55273cbb686e436e'/>
<id>urn:sha1:6656920b0b50beacb6cb64cf55273cbb686e436e</id>
<content type='text'>
Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
</entry>
<entry>
<title>Don't include linux/config.h from anywhere else in include/</title>
<updated>2006-04-26T11:56:16Z</updated>
<author>
<name>David Woodhouse</name>
<email>dwmw2@infradead.org</email>
</author>
<published>2006-04-26T11:56:16Z</published>
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<id>urn:sha1:62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;dwmw2@infradead.org&gt;
</content>
</entry>
<entry>
<title>[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6</title>
<updated>2005-06-24T07:05:22Z</updated>
<author>
<name>Chris Zankel</name>
<email>czankel@tensilica.com</email>
</author>
<published>2005-06-24T05:01:26Z</published>
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<id>urn:sha1:9a8fd5589902153a134111ed7a40f9cca1f83254</id>
<content type='text'>
The attached patches provides part 6 of an architecture implementation for the
Tensilica Xtensa CPU series.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
Signed-off-by: Andrew Morton &lt;akpm@osdl.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@osdl.org&gt;
</content>
</entry>
</feed>
