linux/include/drm/bridge, branch v6.4

drm: bridge: samsung-dsim: Add i.MX8M Plus support

2023-03-28T00:05:41Z

Add extras to support i.MX8M Plus. The main change is the removal of HS/VS/DE signal inversion in the LCDIFv3-DSIM glue logic, otherwise the implementation of this IP in i.MX8M Plus is very much compatible with the i.MX8M Mini/Nano one. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Acked-by: Robert Foss Signed-off-by: Marek Vasut Signed-off-by: Jagan Teki Tested-by: Marek Szyprowski Signed-off-by: Inki Dae

drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge

2023-03-28T00:05:41Z

Samsung MIPI DSIM controller is common DSI IP that can be used in various SoCs like Exynos, i.MX8M Mini/Nano. In order to access this DSI controller between various platform SoCs, the ideal way to incorporate this in the drm stack is via the drm bridge driver. We already have a consolidated code for supporting component and bridge based DRM drivers, so keep the exynos component based code in existing exynos_drm_dsi.c and move generic bridge code as part of samsung-dsim.c Tested-by: Marek Szyprowski Reviewed-by: Marek Vasut Signed-off-by: Marek Szyprowski Signed-off-by: Jagan Teki Signed-off-by: Inki Dae

drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver

2022-04-19T16:23:48Z

General Parallel Audio (GPA) interface is one of the supported audio interface for synopsys HDMI module, which has verified for i.MX8MPlus platform. This is initial version for GPA. Signed-off-by: Shengjiu Wang Signed-off-by: Sandor Yu Reviewed-by: Neil Armstrong Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/f21ba3e8c4d9d028ac74c6f3c588ddbffe739399.1649989179.git.Sandor.yu@nxp.com

drm: bridge: dw_hdmi: add reset function for PHY GEN1

2022-04-19T16:19:03Z

PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2, and active low reset control for PHY GEN1. Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset. Add dw_hdmi_phy_gen1_reset function for PHY GEN1. Signed-off-by: Sandor Yu Reviewed-by: Neil Armstrong Acked-by: Jernej Skrabec Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/e0b3be2d63fe3e95246fb8b8b0dcd57415b29e04.1649989179.git.Sandor.yu@nxp.com

drm/bridge/synopsys: dsi: extend the prototype of mode_valid()

2022-01-04T11:53:59Z

To evaluate the validity of a video mode, some additional internal value has to be passed to the platform implementation. Extend the prototype of mode_valid(). Signed-off-by: Antonio Borneo Reviewed-by: Philippe Cornu Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/20211218215055.212421-2-antonio.borneo@foss.st.com

drm: bridge: dw-hdmi: Attach to next bridge if available

2021-07-28T13:33:13Z

On all platforms except i.MX and Rockchip, the dw-hdmi DT bindings require a video output port connected to an HDMI sink (most likely an HDMI connector, in rare cases another bridges converting HDMI to another protocol). For those platforms, retrieve the next bridge and attach it from the dw-hdmi bridge attach handler. Signed-off-by: Laurent Pinchart Reviewed-by: Neil Armstrong Tested-by: Kieran Bingham # On V3U Reviewed-by: Kieran Bingham

drm/bridge/synopsys: dw-hdmi: Add an option to suppress loading CEC driver

2021-04-20T15:22:38Z

This adds DW-HDMI driver a glue option to disable loading of the CEC sub-driver. On some SoCs, the CEC functionality is enabled in the IP config bits, but the CEC bus is non-functional like on Amlogic SoCs, where the CEC config bit is set but the DW-HDMI CEC signal is not connected to a physical pin, leading to some confusion when the DW-HDMI CEC controller can't communicate on the bus. Reviewed-by: Neil Armstrong Signed-off-by: Jernej Skrabec Signed-off-by: Neil Armstrong Acked-by: Hans Verkuil Link: https://patchwork.freedesktop.org/patch/msgid/20210416092737.1971876-2-narmstrong@baylibre.com

drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate

2020-09-11T13:01:36Z

The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. Signed-off-by: Neil Armstrong Reviewed-by: Philippe Cornu Link: https://patchwork.freedesktop.org/patch/msgid/20200904125531.15248-1-narmstrong@baylibre.com

drm: bridge: dw-hdmi: Pass drm_display_info to dw_hdmi_support_scdc()

2020-06-23T17:57:06Z

To prepare for making connector creation optional in the driver, pass the drm_display_info explicitly to dw_hdmi_support_scdc(). The pointer is passed to the callers where required, particularly to the dw_hdmi_phy_ops .init() function. Signed-off-by: Laurent Pinchart Reviewed-by: Neil Armstrong Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20200526011505.31884-19-laurent.pinchart+renesas@ideasonboard.com

drm: bridge: dw-hdmi: Constify mode argument to dw_hdmi_phy_ops .init()

2020-06-23T17:56:25Z

The PHY .init() must not modify the mode it receives. Make the pointer const to enfore that. Signed-off-by: Laurent Pinchart Reviewed-by: Neil Armstrong Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20200526011505.31884-17-laurent.pinchart+renesas@ideasonboard.com