linux/include/dt-bindings/phy, branch v5.4

dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs

2019-08-23T04:10:46Z

Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. The IP block contains settings for the PHY and a PLL. The PLL mode is configurable through a dedicated #phy-cell in .dts. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422

2019-06-05T15:37:15Z

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 101 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190113.822954939@linutronix.de Signed-off-by: Greg Kroah-Hartman

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194

2019-05-30T18:29:22Z

Based on 1 normalized pattern(s): license terms gnu general public license gpl version 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Alexios Zavras Reviewed-by: Steve Winslow Reviewed-by: Richard Fontana Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de Signed-off-by: Greg Kroah-Hartman

dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC

2019-04-17T08:43:18Z

AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1

2018-10-23T02:27:14Z

SERDES_MAX is a valid value to index ctrl->phys in drivers/phy/mscc/phy-ocelot-serdes.c. But, currently, there is an out-of-bounds bug in the mentioned driver when reading from ctrl->phys, because the size of array ctrl->phys is SERDES_MAX. Partially fix this by updating SERDES_MAX to be SERDES6G_MAX + 1. Notice that this is the first part of the solution to the out-of-bounds bug mentioned above. Although this change is not dependent on any other one. Suggested-by: Quentin Schulz Reviewed-by: Quentin Schulz Acked-by: Rob Herring Signed-off-by: Gustavo A. R. Silva Signed-off-by: David S. Miller

dt-bindings: add constants for Microsemi Ocelot SerDes driver

2018-10-05T21:36:44Z

The Microsemi Ocelot has multiple SerDes and requires that the SerDes be muxed accordingly to the hardware representation. Let's add a constant for each SerDes available in the Microsemi Ocelot. Reviewed-by: Rob Herring Signed-off-by: Quentin Schulz Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

dt-bindings: phy-qcom-usb2: Add support to override tuning values

2018-05-20T16:21:31Z

To improve eye diagram for PHYs on different boards of same SOC, some parameters may need to be changed. Provide device tree properties to override these from board specific device tree files. While at it, replace "qcom,qusb2-v2-phy" with compatible string for USB2 PHY on sdm845 which was earlier added for sdm845 only. Signed-off-by: Manu Gautam Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Add PHY_TYPE_UFS definition

2017-10-23T05:49:27Z

Add definition for UFS phy type. Signed-off-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

phy: Add binding document for Pistachio USB2.0 PHY

2015-06-21T19:53:37Z

Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by: Andrew Bresticker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Kishon Vijay Abraham I Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hartley Cc: Damien Horsley Patchwork: https://patchwork.linux-mips.org/patch/9727/ Signed-off-by: Ralf Baechle

phy: miphy365x: Use the generic phy type constants in dt-bindings/phy/phy.h

2015-04-03T12:46:20Z

Now there are generic phy type constants declared in phy.h, migrate over to using them rather than defining our own. This change has been done as one atomic commit to be bisectable. Note: The values of the defines are the same, so there is no ABI breakage with this patch. Signed-off-by: Peter Griffin Acked-by: Rob Herring Acked-by: Lee Jones Acked-by: Maxime Coquelin Signed-off-by: Kishon Vijay Abraham I