<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/include/kvm/arm_arch_timer.h, branch v4.11</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.11</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.11'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2017-02-08T15:13:37Z</updated>
<entry>
<title>KVM: arm/arm64: Emulate the EL1 phys timer registers</title>
<updated>2017-02-08T15:13:37Z</updated>
<author>
<name>Jintack Lim</name>
<email>jintack@cs.columbia.edu</email>
</author>
<published>2017-02-03T15:20:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7b6b46311a8562fb3a9e035ed6ffab6d49c28886'/>
<id>urn:sha1:7b6b46311a8562fb3a9e035ed6ffab6d49c28886</id>
<content type='text'>
Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now VMs are able to use the EL1 physical timer.

Signed-off-by: Jintack Lim &lt;jintack@cs.columbia.edu&gt;
Reviewed-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm/arm64: Initialize the emulated EL1 physical timer</title>
<updated>2017-02-08T15:13:34Z</updated>
<author>
<name>Jintack Lim</name>
<email>jintack@cs.columbia.edu</email>
</author>
<published>2017-02-03T15:20:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a91d18551e7b35e34a04b6fd199ca8568e7e9315'/>
<id>urn:sha1:a91d18551e7b35e34a04b6fd199ca8568e7e9315</id>
<content type='text'>
Initialize the emulated EL1 physical timer with the default irq number.

Signed-off-by: Jintack Lim &lt;jintack@cs.columbia.edu&gt;
Reviewed-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm/arm64: Add the EL1 physical timer context</title>
<updated>2017-02-08T15:13:34Z</updated>
<author>
<name>Jintack Lim</name>
<email>jintack@cs.columbia.edu</email>
</author>
<published>2017-02-03T15:20:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=009a5701bb2d166073f75643bc9237fe014c6bf5'/>
<id>urn:sha1:009a5701bb2d166073f75643bc9237fe014c6bf5</id>
<content type='text'>
Add the EL1 physical timer context.

Signed-off-by: Jintack Lim &lt;jintack@cs.columbia.edu&gt;
Acked-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm/arm64: Decouple kvm timer functions from virtual timer</title>
<updated>2017-02-08T15:13:33Z</updated>
<author>
<name>Jintack Lim</name>
<email>jintack@cs.columbia.edu</email>
</author>
<published>2017-02-03T15:20:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9171fa2e0951b0cb6c443e0dce2c4620de3b1dfe'/>
<id>urn:sha1:9171fa2e0951b0cb6c443e0dce2c4620de3b1dfe</id>
<content type='text'>
Now that we have a separate structure for timer context, make functions
generic so that they can work with any timer context, not just the
virtual timer context.  This does not change the virtual timer
functionality.

Signed-off-by: Jintack Lim &lt;jintack@cs.columbia.edu&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Acked-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm/arm64: Move cntvoff to each timer context</title>
<updated>2017-02-08T15:13:33Z</updated>
<author>
<name>Jintack Lim</name>
<email>jintack@cs.columbia.edu</email>
</author>
<published>2017-02-03T15:20:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=90de943a430028ee389b22bf4a7ae5867c32ce0c'/>
<id>urn:sha1:90de943a430028ee389b22bf4a7ae5867c32ce0c</id>
<content type='text'>
Make cntvoff per each timer context. This is helpful to abstract kvm
timer functions to work with timer context without considering timer
types (e.g. physical timer or virtual timer).

This also would pave the way for ever doing adjustments of the cntvoff
on a per-CPU basis if that should ever make sense.

Signed-off-by: Jintack Lim &lt;jintack@cs.columbia.edu&gt;
Signed-off-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm/arm64: Abstract virtual timer context into separate structure</title>
<updated>2017-02-08T15:13:32Z</updated>
<author>
<name>Jintack Lim</name>
<email>jintack@cs.columbia.edu</email>
</author>
<published>2017-02-03T15:19:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=fbb4aeec5fc2ab47615b2a0cbabc503e1eef4c60'/>
<id>urn:sha1:fbb4aeec5fc2ab47615b2a0cbabc503e1eef4c60</id>
<content type='text'>
Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.

This is about to become very handy when adding the EL1 physical timer.

Signed-off-by: Jintack Lim &lt;jintack@cs.columbia.edu&gt;
Acked-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: Access CNTHCTL_EL2 bit fields correctly on VHE systems</title>
<updated>2017-01-13T11:19:25Z</updated>
<author>
<name>Jintack Lim</name>
<email>jintack@cs.columbia.edu</email>
</author>
<published>2016-12-01T19:32:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=488f94d7212b00a2ec72fb886b155f1b04c5aa98'/>
<id>urn:sha1:488f94d7212b00a2ec72fb886b155f1b04c5aa98</id>
<content type='text'>
Current KVM world switch code is unintentionally setting wrong bits to
CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical
timer.  Bit positions of CNTHCTL_EL2 are changing depending on
HCR_EL2.E2H bit.  EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is
not set, but they are 11th and 10th bits respectively when E2H is set.

In fact, on VHE we only need to set those bits once, not for every world
switch. This is because the host kernel runs in EL2 with HCR_EL2.TGE ==
1, which makes those bits have no effect for the host kernel execution.
So we just set those bits once for guests, and that's it.

Signed-off-by: Jintack Lim &lt;jintack@cs.columbia.edu&gt;
Reviewed-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>clocksource: Use a plain u64 instead of cycle_t</title>
<updated>2016-12-25T10:04:12Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2016-12-21T19:32:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a5a1d1c2914b5316924c7893eb683a5420ebd3be'/>
<id>urn:sha1:a5a1d1c2914b5316924c7893eb683a5420ebd3be</id>
<content type='text'>
There is no point in having an extra type for extra confusion. u64 is
unambiguous.

Conversion was done with the following coccinelle script:

@rem@
@@
-typedef u64 cycle_t;

@fix@
typedef cycle_t;
@@
-cycle_t
+u64

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: John Stultz &lt;john.stultz@linaro.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm/arm64: Move timer IRQ map to latest possible time</title>
<updated>2016-05-20T13:39:41Z</updated>
<author>
<name>Christoffer Dall</name>
<email>christoffer.dall@linaro.org</email>
</author>
<published>2016-05-18T15:26:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=41a54482c010d8806cf56e1501bb3b61fac14cf9'/>
<id>urn:sha1:41a54482c010d8806cf56e1501bb3b61fac14cf9</id>
<content type='text'>
We are about to modify the VGIC to allocate all data structures
dynamically and store mapped IRQ information on a per-IRQ struct, which
is indeed allocated dynamically at init time.

Therefore, we cannot record the mapped IRQ info from the timer at timer
reset time like it's done now, because VCPU reset happens before timer
init.

A possible later time to do this is on the first run of a per VCPU, it
just requires us to move the enable state to be a per-VCPU state and do
the lookup of the physical IRQ number when we are about to run the VCPU.

Signed-off-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>KVM: arm/arm64: arch_timer: Remove irq_phys_map</title>
<updated>2016-05-20T13:39:39Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2016-04-13T10:03:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a7e33ad9b25552b75a2523cc598db8bcd218ede5'/>
<id>urn:sha1:a7e33ad9b25552b75a2523cc598db8bcd218ede5</id>
<content type='text'>
Now that the interface between the arch timer and the VGIC does not
require passing the irq_phys_map entry pointer anymore, let's remove
it from the virtual arch timer and use the virtual IRQ number instead
directly.
The remaining pointer returned by kvm_vgic_map_phys_irq() will be
removed in the following patch.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Eric Auger &lt;eric.auger@linaro.org&gt;
Reviewed-by: Christoffer Dall &lt;christoffer.dall@linaro.org&gt;
</content>
</entry>
</feed>
