Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ https://git.shady.money/linux/atom?h=v4.2 2015-06-26T18:54:29Z 2015-06-26T18:54:29Z Linus Torvalds torvalds@linux-foundation.org 2015-06-26T18:54:29Z urn:sha1:f5dcb68086ba2e033b2af32b0da0c7a7c7872a09 Pull ARM SoC driver updates from Kevin Hilman: "Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) drivers: soc: sunxi: Introduce SoC driver to map SRAMs arm-cci: Add aliases for PMU events arm-cci: Add CCI-500 PMU support arm-cci: Sanitise CCI400 PMU driver specific code arm-cci: Abstract handling for CCI events arm-cci: Abstract out the PMU counter details arm-cci: Cleanup PMU driver code arm-cci: Do not enable CCI-400 PMU by default firmware: qcom: scm: Add HDCP Support ARM: berlin: add an ADC node for the BG2Q ARM: berlin: remove useless chip and system ctrl compatibles clk: berlin: drop direct of_iomap of nodes reg property ARM: berlin: move BG2Q clock node ARM: berlin: move BG2CD clock node ARM: berlin: move BG2 clock node clk: berlin: prepare simple-mfd conversion pinctrl: berlin: drop SoC stub provided regmap ARM: berlin: move pinctrl to simple-mfd nodes pinctrl: berlin: prepare to use regmap provided by syscon reset: berlin: drop arch_initcall initialization ... 2015-05-13T15:59:35Z Arnd Bergmann arnd@arndb.de 2015-05-13T15:59:35Z urn:sha1:44fb3026ad28d2a2b935dc9c47ec2dffadca3f35 Merge "ARM: tegra: Add EMC driver for v4.2-rc1" from Thierry Reding: This introduces the EMC driver that's required to scale the external memory frequency. * tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Add EMC frequency debugfs entry memory: tegra: Add EMC (external memory controller) driver memory: tegra: Add API needed by the EMC driver of: Add Tegra124 EMC bindings of: Document timings subnode of nvidia,tegra-mc 2015-05-13T15:56:47Z Arnd Bergmann arnd@arndb.de 2015-05-13T15:56:47Z urn:sha1:92d19e26d67704397b70cf5728fd77bd13b74c43 Merge "ARM: tegra: RAM code access for v4.2-rc1" from Thierry Reding: The RAM code is used by the memory and external memory controllers to determine which set of timings to use for memory frequency scaling. * tag 'tegra-for-4.2-ramcode' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: fuse: Add RAM code reader helper of: Document long-ram-code property in nvidia,tegra20-apbmisc 2015-05-05T09:12:17Z Mikko Perttunen mperttunen@nvidia.com 2015-03-12T14:48:03Z urn:sha1:73a7f0a90641b09300d47308682b674c570dd6a2 Implements functionality needed to change the rate of the memory bus clock. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-05T09:10:19Z Mikko Perttunen mperttunen@nvidia.com 2015-03-12T14:48:02Z urn:sha1:3d9dd6fdd23695a038633f1a87aee0708fe4b8e0 The EMC driver needs to know the number of external memory devices and also needs to update the EMEM configuration based on the new rate of the memory bus. To know how to update the EMEM config, looks up the values of the burst regs in the DT, for a given timing. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-04T12:21:45Z David Riley davidriley@chromium.org 2015-03-18T09:52:25Z urn:sha1:7892158a96629c46c46dfae52eaf951f51222cf5 The pmc driver was previously exporting tegra_pmc_restart, which was assigned to machine_desc.init_machine, taking precedence over the restart handlers registered through register_restart_handler(). Signed-off-by: David Riley <davidriley@chromium.org> [tomeu.vizoso@collabora.com: Rebased] Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> [treding@nvidia.com: minor cleanups] Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-04T12:21:21Z Mikko Perttunen mperttunen@nvidia.com 2015-03-12T14:47:55Z urn:sha1:6ea2609ab386f6bfeebc39e1418b7497a9deb55c Needed for the EMC and MC drivers to know what timings from the DT to use. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-04T10:54:23Z Thierry Reding treding@nvidia.com 2015-01-23T08:49:25Z urn:sha1:d1313e7896e932a92e21912850ef034e58571b66 Provide clients and swgroups files in debugfs. These files show for which clients IOMMU translation is enabled and which ASID is associated with each SWGROUP. Cc: Hiroshi Doyu <hdoyu@nvidia.com> Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-04T10:54:23Z Thierry Reding treding@nvidia.com 2015-01-23T08:45:35Z urn:sha1:e660df07ab90f4f61ed743522067a8dbaa6fa567 Subsequent patches will add debugfs files that print the status of the SWGROUPs. Add a new names field and complement the SoC tables with the names of the individual SWGROUPs. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-01-09T15:13:57Z Thierry Reding treding@nvidia.com 2015-01-08T07:24:45Z urn:sha1:24ef5745dafc2eaf287a0bb9ee9e4ff9a4f64108 Add the chip ID for the NVIDIA Tegra132 SoC family. Signed-off-by: Thierry Reding <treding@nvidia.com>