<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/include/soc, branch v5.14</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.14</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.14'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-07-16T20:51:01Z</updated>
<entry>
<title>Merge tag 'memory-controller-drv-tegra-5.14-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/fixes</title>
<updated>2021-07-16T20:51:01Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2021-07-16T20:50:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b6e473d1e21262290b8e1a023eff9f091ab8041b'/>
<id>urn:sha1:b6e473d1e21262290b8e1a023eff9f091ab8041b</id>
<content type='text'>
Memory controller drivers for v5.14 - Tegra SoC, late fixes

Two fixes for recent series of changes in Tegra SoC memory controller
drivers:
1. Add a stub for tegra_mc_probe_device() to fix compile testing of
   arm-smmu without TEGRA_MC.
2. Fix arm-smmu dtschema syntax.

* tag 'memory-controller-drv-tegra-5.14-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  dt-bindings: arm-smmu: Fix json-schema syntax
  memory: tegra: Add compile-test stub for tegra_mc_probe_device()

Link: https://lore.kernel.org/r/20210625073604.13562-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2021-07-10T16:46:20Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-07-10T16:46:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=071e5aceebebf1d33b5c29ccfd2688ed39c60007'/>
<id>urn:sha1:071e5aceebebf1d33b5c29ccfd2688ed39c60007</id>
<content type='text'>
Pull ARM driver updates from Olof Johansson:

 - Reset controllers: Adding support for Microchip Sparx5 Switch.

 - Memory controllers: ARM Primecell PL35x SMC memory controller driver
   cleanups and improvements.

 - i.MX SoC drivers: Power domain support for i.MX8MM and i.MX8MN.

 - Rockchip: RK3568 power domains support + DT binding updates,
   cleanups.

 - Qualcomm SoC drivers: Amend socinfo with more SoC/PMIC details,
   including support for MSM8226, MDM9607, SM6125 and SC8180X.

 - ARM FFA driver: "Firmware Framework for ARMv8-A", defining management
   interfaces and communication (including bus model) between partitions
   both in Normal and Secure Worlds.

 - Tegra Memory controller changes, including major rework to deal with
   identity mappings at boot and integration with ARM SMMU pieces.

* tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (120 commits)
  firmware: turris-mox-rwtm: add marvell,armada-3700-rwtm-firmware compatible string
  firmware: turris-mox-rwtm: show message about HWRNG registration
  firmware: turris-mox-rwtm: fail probing when firmware does not support hwrng
  firmware: turris-mox-rwtm: report failures better
  firmware: turris-mox-rwtm: fix reply status decoding function
  soc: imx: gpcv2: add support for i.MX8MN power domains
  dt-bindings: add defines for i.MX8MN power domains
  firmware: tegra: bpmp: Fix Tegra234-only builds
  iommu/arm-smmu: Use Tegra implementation on Tegra186
  iommu/arm-smmu: tegra: Implement SID override programming
  iommu/arm-smmu: tegra: Detect number of instances at runtime
  dt-bindings: arm-smmu: Add Tegra186 compatible string
  firmware: qcom_scm: Add MDM9607 compatible
  soc: qcom: rpmpd: Add MDM9607 RPM Power Domains
  soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's
  soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's
  dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml
  memory: emif: remove unused frequency and voltage notifiers
  memory: fsl_ifc: fix leak of private memory on probe failure
  memory: fsl_ifc: fix leak of IO mapping on probe failure
  ...
</content>
</entry>
<entry>
<title>Merge tag 'arm-soc-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2021-07-10T16:22:44Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-07-10T16:22:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6e207b882159ed3e35a4cd4ff0fc155cce5e3cbc'/>
<id>urn:sha1:6e207b882159ed3e35a4cd4ff0fc155cce5e3cbc</id>
<content type='text'>
Pull ARM SoC updates from Olof Johansson:
 "A few SoC (code) changes have queued up this cycle, mostly for minor
  changes and some refactoring and cleanup of legacy platforms. This
  branch also contains a few of the fixes that weren't sent in by the
  end of the release (all fairly minor).

   - Adding an additional maintainer for the TEE subsystem (Sumit Garg)

   - Quite a significant modernization of the IXP4xx platforms by Linus
     Walleij, revisiting with a new PCI host driver/binding, removing
     legacy mach/* include dependencies and moving platform
     detection/config to drivers/soc. Also some updates/cleanup of
     platform data.

   - Core power domain support for Tegra platforms, and some
     improvements in build test coverage by adding stubs for compile
     test targets.

   - A handful of updates to i.MX platforms, adding legacy (non-PSCI)
     SMP support on i.MX7D, SoC ID setup for i.MX50, removal of platform
     data and board fixups for iMX6/7.

  ... and a few smaller changes and fixes for Samsung, OMAP, Allwinner,
  Rockchip"

* tag 'arm-soc-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (53 commits)
  MAINTAINERS: Add myself as TEE subsystem reviewer
  ixp4xx: fix spelling mistake in Kconfig "Devce" -&gt; "Device"
  hw_random: ixp4xx: Add OF support
  hw_random: ixp4xx: Add DT bindings
  hw_random: ixp4xx: Turn into a module
  hw_random: ixp4xx: Use SPDX license tag
  hw_random: ixp4xx: enable compile-testing
  pata: ixp4xx: split platform data to its own header
  soc: ixp4xx: move cpu detection to linux/soc/ixp4xx/cpu.h
  PCI: ixp4xx: Add a new driver for IXP4xx
  PCI: ixp4xx: Add device tree bindings for IXP4xx
  ARM/ixp4xx: Make NEED_MACH_IO_H optional
  ARM/ixp4xx: Move the virtual IObases
  MAINTAINERS: ARM/MStar/Sigmastar SoCs: Add a link to the MStar tree
  ARM: debug: add UART early console support for MSTAR SoCs
  ARM: dts: ux500: Fix LED probing
  ARM: imx: add smp support for imx7d
  ARM: imx6q: drop of_platform_default_populate() from init_machine
  arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory
  soc/tegra: fuse: Fix Tegra234-only builds
  ...
</content>
</entry>
<entry>
<title>mbox: add polarfire soc system controller mailbox</title>
<updated>2021-06-26T17:06:48Z</updated>
<author>
<name>Conor Dooley</name>
<email>conor.dooley@microchip.com</email>
</author>
<published>2021-06-24T15:00:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=83d7b1560810e038e1d07ca6bff41edaeae29725'/>
<id>urn:sha1:83d7b1560810e038e1d07ca6bff41edaeae29725</id>
<content type='text'>
This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add compile-test stub for tegra_mc_probe_device()</title>
<updated>2021-06-20T19:22:30Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2021-06-18T11:18:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=47661ee1821fc3a6b5ae07aac37410d6ccada976'/>
<id>urn:sha1:47661ee1821fc3a6b5ae07aac37410d6ccada976</id>
<content type='text'>
The tegra_mc_probe_device() symbol is only available when the TEGRA_MC
Kconfig option is enabled. Provide a stub if that's not the case so that
the driver can be compile-tested.

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20210618111846.1286166-1-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-5.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc</title>
<updated>2021-06-15T15:35:29Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2021-06-15T15:35:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=777cf27fb22669a50196c023676ec60de36c91b7'/>
<id>urn:sha1:777cf27fb22669a50196c023676ec60de36c91b7</id>
<content type='text'>
soc/tegra: Changes for v5.14-rc1

These changes implement the core power domain for the PMC, and fix a
couple of minor issues as well as add stubs to help some drivers be
compile tested more easily.

* tag 'tegra-for-5.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: fuse: Fix Tegra234-only builds
  soc/tegra: fuse: Don't return -ENOMEM when allocate lookups failed
  soc/tegra: regulators: Support core domain state syncing
  soc/tegra: pmc: Add driver state syncing
  soc/tegra: pmc: Add core power domain
  soc/tegra: fuse: Add stubs needed for compile-testing
  soc/tegra: Add devm_tegra_core_dev_init_opp_table()
  soc/tegra: Add stub for soc_is_tegra()
  soc/tegra: regulators: Bump voltages on system reboot
  regulator: core: Add regulator_sync_voltage_rdev()

Link: https://lore.kernel.org/r/20210611164437.3568059-2-thierry.reding@gmail.com
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Implement SID override programming</title>
<updated>2021-06-03T19:50:43Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2021-06-03T16:46:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=393d66fd2cacba3e6aa95d7bb38790bfb7b1cc3a'/>
<id>urn:sha1:393d66fd2cacba3e6aa95d7bb38790bfb7b1cc3a</id>
<content type='text'>
Instead of programming all SID overrides during early boot, perform the
operation on-demand after the SMMU translations have been set up for a
device. This reuses data from device tree to match memory clients for a
device and programs the SID specified in device tree, which corresponds
to the SID used for the SMMU context banks for the device.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20210603164632.1000458-2-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Unify drivers</title>
<updated>2021-06-03T19:49:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2021-06-02T16:33:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7355c7b9ae0d45923bac088bc1faebd5e9a66164'/>
<id>urn:sha1:7355c7b9ae0d45923bac088bc1faebd5e9a66164</id>
<content type='text'>
The Tegra210 (and earlier) driver now supports all the functionality
that the Tegra186 (and later) driver does, so they can be unified.

Note that previously the Tegra186 (and later) driver could be unloaded,
even if that was perhaps not very useful. Older chips don't support that
yet, but once they do this code can be reenabled.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20210602163302.120041-11-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Parameterize interrupt handler</title>
<updated>2021-06-03T19:49:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2021-06-02T16:32:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1079a66bc32ff04eaab792152a9ed9c7585b5efc'/>
<id>urn:sha1:1079a66bc32ff04eaab792152a9ed9c7585b5efc</id>
<content type='text'>
Tegra20 requires a slightly different interrupt handler than Tegra30 and
later, so parameterize the handler, so that each SoC implementation can
provide its own.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20210602163302.120041-8-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Make per-SoC setup more generic</title>
<updated>2021-06-03T19:49:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2021-06-02T16:32:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c64738e949940bea2bb426b104b4de0aa42a8f48'/>
<id>urn:sha1:c64738e949940bea2bb426b104b4de0aa42a8f48</id>
<content type='text'>
The current per-SoC setup code runs at a fairly arbitrary point during
probe, thereby making it less flexible for other SoC generations. Move
the call around slightly (after only the very basic, common setup that
applies to all SoC generations has been performed), which will allow
it to be used for other implementations.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20210602163302.120041-6-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
</feed>
