Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ https://git.shady.money/linux/atom?h=v4.1 2015-06-18T18:36:56Z 2015-06-18T18:36:56Z Michel Dänzer michel.daenzer@amd.com 2015-06-16T08:28:16Z urn:sha1:3bc980bf19bb62007e923691fa2869ba113be895 This tells userspace that it's safe to use the RADEON_VA_UNMAP operation of the DRM_RADEON_GEM_VA ioctl. Cc: stable@vger.kernel.org (NOTE: Backporting this commit requires at least backports of commits 26d4d129b6042197b4cbc8341c0618f99231af2f, 48afbd70ac7b6aa62e8d452091023941d8085f8a and c29c0876ec05d51a93508a39b90b92c29ba6423d as well, otherwise using RADEON_VA_UNMAP runs into trouble) Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> 2015-04-14T07:00:46Z Alexandre Courbot acourbot@nvidia.com 2015-02-26T03:44:51Z urn:sha1:996f545fbb0dc9ed4a640b5ef098f51fe28cca5c User-space use mappable BOs notably for fences, and expects that a value update by the GPU will be immediatly visible through the user-space mapping. ARM has a property that may prevent this from happening though: memory can be mapped multiple times only if the different mappings share the same caching properties. However all the lowmem memory is already identity-mapped into the kernel with cache enabled, so when user-space requests an uncached mapping, we actually get an "undefined caching policy" one and this has strange side-effects described on Freedesktop bug 86690. To prevent this from happening, allow user-space to explicitly specify which objects should be coherent, and create such objects with the TTM_PL_FLAG_UNCACHED flag. This will make TTM allocate memory using the DMA API, which will fix the identify mapping and allow us to safely map the objects to user-space uncached. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> 2015-04-08T01:13:06Z Dave Airlie airlied@redhat.com 2015-04-08T01:13:06Z urn:sha1:1ddd36eda1a577837826a8e465ab9d43b024d382 drm/tegra: Changes for v4.1-rc1 Perhaps the most noteworthy change in this set is the implementation of a hardware VBLANK counter using host1x syncpoints. The SOR registers can now be dumped via debugfs, which can be useful while debugging. The IOVA address space maintained by the driver can also be dumped via debugfs. Other than than, these changes are mostly cleanup work, such as making register names more consistent or removing unused code (that was left over after the atomic mode-setting conversion). There's also a fix for eDP that makes the driver cope with firmware that already initialized the display (such as the firmware on the Tegra-based Chromebooks). * tag 'drm/tegra/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: sor: Reset during initialization drm/tegra: gem: Return 64-bit offset for mmap(2) drm/tegra: hdmi: Name register fields consistently drm/tegra: hdmi: Resets are synchronous drm/tegra: dc: Document tegra_dc_state_setup_clock() drm/tegra: dc: Remove unused callbacks drm/tegra: dc: Remove unused function drm/tegra: dc: Use base atomic state helpers drm/atomic: Add helpers for state-subclassing drivers drm/tegra: dc: Implement hardware VBLANK counter gpu: host1x: Export host1x_syncpt_read() drm/tegra: sor: Dump registers via debugfs drm/tegra: sor: Registers are 32-bit drm/tegra: Provide debugfs file for the IOVA space drm/tegra: dc: Check for valid parent clock 2015-04-02T16:49:23Z Sean Paul seanpaul@chromium.org 2015-01-30T18:57:01Z urn:sha1:bdf765071a8b573f7b1ba14c02881fa3e623825e On 64-bit targets, tegra_gem_mmap() only returns a partial offset to userspace. As such, subsequent calls to mmap(2) may fail. Change the arguments to use a 64-bit offset to fix this. Signed-off-by: Sean Paul <seanpaul@chromium.org> Acked-by: Erik Faye-Lund <kusmabite@gmail.com> [treding@nvidia.com: tweak commit message] Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-03-31T22:21:46Z Dave Airlie airlied@redhat.com 2015-03-31T22:21:46Z urn:sha1:9e87e48f8e5de2146842fd0ff436e0256b52c4a9 This backmerges 4.0-rc6 due to the recent fixes in rc5/6 - DP link rate refactoring from Ville - byt/bsw rps tuning from Chris - kerneldoc for the shrinker code - more dynamic ppgtt pte work (Michel, Ben, ...) - vlv dpll code refactoring to prep fro bxt (Imre) - refactoring the sprite colorkey code (Ville) - rotated ggtt view support from Tvrtko - roll out struct drm_atomic_state to prep for atomic update (Ander) * tag 'drm-intel-next-2015-03-27-merge' of git://anongit.freedesktop.org/drm-intel: (473 commits) Linux 4.0-rc6 arm64: juno: Fix misleading name of UART reference clock drm/i915: Update DRIVER_DATE to 20150327 drm/i915: Skip allocating shadow batch for 0-length batches drm/i915: Handle error to get connector state when staging config drm/i915: Compare GGTT view structs instead of types drm/i915: fix simple_return.cocci warnings drm/i915: Add module param to test the load detect code drm/i915: Remove usage of encoder->new_crtc from clock computations drm/i915: Don't look at staged config crtc when changing DRRS state drm/i915: Convert intel_pipe_will_have_type() to using atomic state drm/i915: Pass an atomic state to modeset_global_resources() functions drm/i915: Add dynamic page trace events drm/i915: Finish gen6/7 dynamic page table allocation drm/i915: Remove unnecessary gen6_ppgtt_unmap_pages drm/i915: Fix i915_dma_map_single positive error code drm/i915: Prevent out of range pt in gen6_for_each_pde drm/i915: fix definition of the DRM_IOCTL_I915_GET_SPRITE_COLORKEY ioctl drm/i915: Rip out GET_SPRITE_COLORKEY ioctl watchdog: imgpdc: Fix default heartbeat ... 2015-03-27T08:10:26Z Tommi Rantala tt.rantala@gmail.com 2015-03-26T19:47:16Z urn:sha1:2c60fae1489c70206e66c28d72b69a3e496c313d Fix definition of the DRM_IOCTL_I915_GET_SPRITE_COLORKEY ioctl, so that it is different from the DRM_IOCTL_I915_SET_SPRITE_COLORKEY ioctl. Note that this is just for accuracy, the ioctl implementation itself is totally unused and already ripped out. Signed-off-by: Tommi Rantala <tt.rantala@gmail.com> [danvet: Add note that this is a dead ioctl.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> 2015-03-24T01:12:20Z Dave Airlie airlied@redhat.com 2015-03-24T01:12:20Z urn:sha1:74ccbff99787b68e4eb01ef8cf29789229ab0f5d drm-intel-next-2015-03-13-rebased: - EU count report param for gen9+ (Jeff McGee) - piles of pll/wm/... fixes for chv, finally out of preliminary hw support (Ville, Vijay) - gen9 rps support from Akash - more work to move towards atomic from Matt, Ander and others - runtime pm support for skl (Damien) - edp1.4 intermediate link clock support (Sonika) - use frontbuffer tracking for fbc (Paulo) - remove ilk rc6 (John Harrison) - a bunch of smaller things and fixes all over Includes backmerge because git rerere couldn't keep up any more. * tag 'drm-intel-next-2015-03-13-merge' of git://anongit.freedesktop.org/drm-intel: (366 commits) drm/i915: Make sure the primary plane is enabled before reading out the fb state drm/i915: Update DRIVER_DATE to 20150313 drm/i915: Fix vmap_batch page iterator overrun drm/i915: Export total subslice and EU counts drm/i915: redefine WARN_ON_ONCE to include the condition drm/i915/skl: Implement WaDisableHBR2 drm/i915: Remove the preliminary_hw_support shackles from CHV drm/i915: Read CHV_PLL_DW8 from the correct offset drm/i915: Rewrite IVB FDI bifurcation conflict checks drm/i915: Rewrite some some of the FDI lane checks drm/i915/skl: Enable the RPS interrupts programming drm/i915/skl: Enabling processing of Turbo interrupts drm/i915/skl: Updated the i915_frequency_info debugfs function drm/i915: Simplify the way BC bifurcation state consistency is kept drm/i915/skl: Updated the act_freq_mhz_show sysfs function drm/i915/skl: Updated the gen9_enable_rps function drm/i915/skl: Updated the gen6_rps_limits function drm/i915/skl: Restructured the gen6_set_rps_thresholds function drm/i915/skl: Updated the gen6_set_rps function drm/i915/skl: Updated the gen6_init_rps_frequencies function ... 2015-03-19T16:26:42Z Alex Deucher alexander.deucher@amd.com 2014-10-01T15:26:50Z urn:sha1:4535cb9cefbc736b47bc1e7f8628065aba5ca0d7 This allows us to query certain registers from userspace for profiling and harvest configuration. E.g., it can be used by the GALLIUM_HUD for profiling the status of various gfx blocks. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2015-03-19T16:26:36Z Alex Deucher alexander.deucher@amd.com 2014-09-30T15:33:30Z urn:sha1:5c363a860398e2a09e5cff7f4654cf82ed8485e1 Allow the UMDs to query the current sclk/mclk for profiling, etc. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2015-03-19T16:26:27Z Alex Deucher alexander.deucher@amd.com 2014-09-30T14:04:40Z urn:sha1:d6d2a1882a79c1a5425d6f82b2fc7b934916f893 Useful for profiling. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>