<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/include/uapi/drm, branch v6.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-07-16T20:17:36Z</updated>
<entry>
<title>drm/amdgpu: Replace HQD terminology with slots naming</title>
<updated>2025-07-16T20:17:36Z</updated>
<author>
<name>Jesse Zhang</name>
<email>jesse.zhang@amd.com</email>
</author>
<published>2025-07-04T07:17:43Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9ffab039bcb0bbfade0e659552d2fb912347a871'/>
<id>urn:sha1:9ffab039bcb0bbfade0e659552d2fb912347a871</id>
<content type='text'>
The term "HQD" is CP-specific and doesn't
accurately describe the queue resources for other IP blocks like SDMA,
VCN, or VPE. This change:

1. Renames `num_hqds` to `num_slots` in amdgpu_kms.c to better reflect
   the generic nature of the resource counting
2. Updates the UAPI struct member from `userq_num_hqds` to `userq_num_slots`
3. Maintains the same functionality while using more appropriate terminology

Signed-off-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Reviewed-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add user queue instance count in HW IP info</title>
<updated>2025-07-16T20:17:35Z</updated>
<author>
<name>Jesse Zhang</name>
<email>jesse.zhang@amd.com</email>
</author>
<published>2025-06-25T07:29:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=78d0a27ae0e2e70b22895f4b388cc0ab88e3c6ca'/>
<id>urn:sha1:78d0a27ae0e2e70b22895f4b388cc0ab88e3c6ca</id>
<content type='text'>
This change exposes the number of available user queue instances
for each hardware IP type (GFX, COMPUTE, SDMA) through the
drm_amdgpu_info_hw_ip interface.

Key changes:
1. Added userq_num_instance field to drm_amdgpu_info_hw_ip structure
2. Implemented counting of available HQD slots using:
   - mes.gfx_hqd_mask for GFX queues
   - mes.compute_hqd_mask for COMPUTE queues
   - mes.sdma_hqd_mask for SDMA queues
3. Only counts available instances when user queues are enabled
   (!disable_uq)

v2: using the adev-&gt;mes.gfx_hqd_mask[]/compute_hqd_mask[]/sdma_hqd_mask[] masks
  to determine the number of queue slots available for each engine type (Alex)
v3: rename userq_num_instance to userq_num_hqds (Alex)

Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-xe-next-2025-07-10' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next</title>
<updated>2025-07-11T09:08:53Z</updated>
<author>
<name>Simona Vetter</name>
<email>simona.vetter@ffwll.ch</email>
</author>
<published>2025-07-11T09:08:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9800bf6fae3bcee42c14bf172f7f6342c3d3d305'/>
<id>urn:sha1:9800bf6fae3bcee42c14bf172f7f6342c3d3d305</id>
<content type='text'>
UAPI Changes:
 - Documentation fixes (Shuicheng)

Cross-subsystem Changes:
 - MTD intel-dg driver for dgfx non-volatile memory device (Sasha)
 - i2c: designware changes to allow i2c integration with BMG (Heikki)

Core Changes:
 - Restructure migration in preparation for multi-device (Brost, Thomas)
 - Expose fan control and voltage regulator version on sysfs (Raag)

Driver Changes:
 - Add WildCat Lake support (Roper)
 - Add aux bus child device driver for NVM on DGFX (Sasha)
 - Some refactor and fixes to allow cleaner BMG w/a (Lucas, Maarten, Auld)
 - BMG w/a (Vinay)
 - Improve handling of aborted probe (Michal)
 - Do not wedge device on killed exec queues (Brost)
 - Init changes for flicker-free boot (Maarten)
 - Fix out-of-bounds field write in MI_STORE_DATA_IMM (Jia)
 - Enable the GuC Dynamic Inhibit Context Switch optimization (Daniele)
 - Drop bo-&gt;size (Brost)
 - Builds and KConfig fixes (Harry, Maarten)
 - Consolidate LRC offset calculations (Tvrtko)
 - Fix potential leak in hw_engine_group (Michal)
 - Future-proof for multi-tile + multi-GT cases (Roper)
 - Validate gt in pmu event (Riana)
 - SRIOV PF: Clear all LMTT pages on alloc (Michal)
 - Allocate PF queue size on pow2 boundary (Brost)
 - SRIOV VF: Make multi-GT migration less error prone (Tomasz)
 - Revert indirect ring state patch to fix random LRC context switches failures (Brost)
 - Fix compressed VRAM handling (Auld)
 - Add one additional BMG PCI ID (Ravi)
 - Recommend GuC v70.46.2 for BMG, LNL, DG2 (Julia)
 - Add GuC and HuC to PTL (Daniele)
 - Drop PTL force_probe requirement (Atwood)
 - Fix error flow in display suspend (Shuicheng)
 - Disable GuC communication on hardware initialization error (Zhanjun)
 - Devcoredump fixes and clean up (Shuicheng)
 - SRIOV PF: Downgrade some info to debug (Michal)
 - Don't allocate temporary GuC policies object (Michal)
 - Support for I2C attached MCUs (Heikki, Raag, Riana)
 - Add GPU memory bo trace points (Juston)
 - SRIOV VF: Skip some W/a (Michal)
 - Correct comment of xe_pm_set_vram_threshold (Shuicheng)
 - Cancel ongoing H2G requests when stopping CT (Michal)

Signed-off-by: Simona Vetter &lt;simona.vetter@ffwll.ch&gt;
From: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/aHA7184UnWlONORU@intel.com
</content>
</entry>
<entry>
<title>Merge tag 'drm-msm-next-2025-07-05' of https://gitlab.freedesktop.org/drm/msm into drm-next</title>
<updated>2025-07-08T12:31:19Z</updated>
<author>
<name>Simona Vetter</name>
<email>simona.vetter@ffwll.ch</email>
</author>
<published>2025-07-08T12:31:19Z</published>
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<id>urn:sha1:203dcde881561f1a4ee1084e2ee438fb4522c94a</id>
<content type='text'>
Updates for v6.17

CI:
- uprev mesa and ci-templates
- use shallow clone to speed up build jobs
- remove sdm845/cheza jobs.  These runners are no more (RIP
  dear chezas)
- fix runner tag for i915 cml runners
- uprev igt to pull in msm test fixes

Core:
- VM_BIND support!
- single source of truth for UBWC configuration.  Adds a global soc
  driver for UBWC config which is used from display and GPU.  (And
  later vidc/camera/etc)
- Decouple ties between GPU and KMS, adding a `separate_gpu_kms`
  modparam to allow the GPU and KMS to bind to separate DRM devices.
  This should better deal with more exotic SoC configurations where
  the number of GPUs is different from number of DPUs.  The default
  behavior is to still come up as a single unified DRM device to
  avoid surprising userspace.

DP:
- major rework of the I/O accessors

DPU:
- use version checks instead of feature bits
- SM8750 support
- set min_prefill_lines for SC8180X

DSI:
- SM8750 support

GPU:
- speedbin support for X1-85
- X1-45 support

MDSS:
- SM8750 support

Signed-off-by: Simona Vetter &lt;simona.vetter@ffwll.ch&gt;
From: Robin Clark &lt;robin.clark@oss.qualcomm.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/CACSVV0217R+kpoWQJeuYGHf6q_4aFyEJuKa=dZZKOnLQzFwppg@mail.gmail.com
</content>
</entry>
<entry>
<title>drm/msm: Add VM_BIND ioctl</title>
<updated>2025-07-05T00:48:38Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@chromium.org</email>
</author>
<published>2025-06-29T20:13:18Z</published>
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<id>urn:sha1:2e6a8a1fe2b262a6dfd0a65041fcd830ee1e7143</id>
<content type='text'>
Add a VM_BIND ioctl for binding/unbinding buffers into a VM.  This is
only supported if userspace has opted in to MSM_PARAM_EN_VM_BIND.

Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Rob Clark &lt;robin.clark@oss.qualcomm.com&gt;
Tested-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Reviewed-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/661524/
</content>
</entry>
<entry>
<title>drm/msm: Add VM_BIND submitqueue</title>
<updated>2025-07-05T00:48:37Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@chromium.org</email>
</author>
<published>2025-06-29T20:13:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=92395af63a9958615edfa9d4ef1ea72c92a00410'/>
<id>urn:sha1:92395af63a9958615edfa9d4ef1ea72c92a00410</id>
<content type='text'>
This submitqueue type isn't tied to a hw ringbuffer, but instead
executes on the CPU for performing async VM_BIND ops.

Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Rob Clark &lt;robin.clark@oss.qualcomm.com&gt;
Tested-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Reviewed-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/661517/
</content>
</entry>
<entry>
<title>drm/msm: Extract out syncobj helpers</title>
<updated>2025-07-05T00:48:37Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@chromium.org</email>
</author>
<published>2025-06-29T20:13:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e1341f91450525b94474b75d5e77587d1d84e52c'/>
<id>urn:sha1:e1341f91450525b94474b75d5e77587d1d84e52c</id>
<content type='text'>
We'll be re-using these for the VM_BIND ioctl.

Also, rename a few things in the uapi header to reflect that syncobj use
is not specific to the submit ioctl.

Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Rob Clark &lt;robin.clark@oss.qualcomm.com&gt;
Tested-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Reviewed-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/661512/
</content>
</entry>
<entry>
<title>drm/msm: Add _NO_SHARE flag</title>
<updated>2025-07-05T00:48:36Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@chromium.org</email>
</author>
<published>2025-06-29T20:13:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b58e12a66e47eaf95b31bbefbc260e5a0b3e638c'/>
<id>urn:sha1:b58e12a66e47eaf95b31bbefbc260e5a0b3e638c</id>
<content type='text'>
Buffers that are not shared between contexts can share a single resv
object.  This way drm_gpuvm will not track them as external objects, and
submit-time validating overhead will be O(1) for all N non-shared BOs,
instead of O(n).

Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Rob Clark &lt;robin.clark@oss.qualcomm.com&gt;
Tested-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Reviewed-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/661497/
</content>
</entry>
<entry>
<title>drm/msm: Add opt-in for VM_BIND</title>
<updated>2025-07-05T00:48:36Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@chromium.org</email>
</author>
<published>2025-06-29T20:13:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=feb8ef4636a457a1fd916a3ae575f552935e69b9'/>
<id>urn:sha1:feb8ef4636a457a1fd916a3ae575f552935e69b9</id>
<content type='text'>
Add a SET_PARAM for userspace to request to manage to the VM itself,
instead of getting a kernel managed VM.

In order to transition to a userspace managed VM, this param must be set
before any mappings are created.

Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Rob Clark &lt;robin.clark@oss.qualcomm.com&gt;
Tested-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Reviewed-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/661494/
</content>
</entry>
<entry>
<title>drm/msm: Add PRR support</title>
<updated>2025-07-05T00:48:35Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@chromium.org</email>
</author>
<published>2025-06-29T20:13:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dbbde63c9e9d472743a88f975baac412ba93f29d'/>
<id>urn:sha1:dbbde63c9e9d472743a88f975baac412ba93f29d</id>
<content type='text'>
Add PRR (Partial Resident Region) is a bypass address which make GPU
writes go to /dev/null and reads return zero.  This is used to implement
vulkan sparse residency.

To support PRR/NULL mappings, we allocate a page to reserve a physical
address which we know will not be used as part of a GEM object, and
configure the SMMU to use this address for PRR/NULL mappings.

Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Rob Clark &lt;robin.clark@oss.qualcomm.com&gt;
Tested-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Reviewed-by: Antonino Maniscalco &lt;antomani103@gmail.com&gt;
Patchwork: https://patchwork.freedesktop.org/patch/661486/
</content>
</entry>
</feed>
