<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/tools/arch/x86, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2026-04-14T21:24:45Z</updated>
<entry>
<title>Merge tag 'x86_cpu_for_7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2026-04-14T21:24:45Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-04-14T21:24:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9f2bb6c7b364f186aa37c524f6df33bd488d4efa'/>
<id>urn:sha1:9f2bb6c7b364f186aa37c524f6df33bd488d4efa</id>
<content type='text'>
Pull x86 cpu updates from Dave Hansen:

 - Complete LASS enabling: deal with vsyscall and EFI

   The existing Linear Address Space Separation (LASS) support punted
   on support for common EFI and vsyscall configs. Complete the
   implementation by supporting EFI and vsyscall=xonly.

 - Clean up CPUID usage in newer Intel "avs" audio driver and update the
   x86-cpuid-db file

* tag 'x86_cpu_for_7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.0
  ASoC: Intel: avs: Include CPUID header at file scope
  ASoC: Intel: avs: Check maximum valid CPUID leaf
  x86/cpu: Remove LASS restriction on vsyscall emulation
  x86/vsyscall: Disable LASS if vsyscall mode is set to EMULATE
  x86/vsyscall: Restore vsyscall=xonly mode under LASS
  x86/traps: Consolidate user fixups in the #GP handler
  x86/vsyscall: Reorganize the page fault emulation code
  x86/cpu: Remove LASS restriction on EFI
  x86/efi: Disable LASS while executing runtime services
  x86/cpu: Defer LASS enabling until userspace comes up
</content>
</entry>
<entry>
<title>Merge tag 'perf-core-2026-04-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2026-04-14T20:22:40Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-04-14T20:22:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=33c66eb5e9844429911bf5478c96c60f9f8af9d0'/>
<id>urn:sha1:33c66eb5e9844429911bf5478c96c60f9f8af9d0</id>
<content type='text'>
Pull performance events updates from Ingo Molnar:
 "Core updates:

   - Try to allocate task_ctx_data quickly, to optimize O(N^2) algorithm
     on large systems with O(100k) threads (Namhyung Kim)

  AMD PMU driver IBS support updates and fixes, by Ravi Bangoria:
   - Fix interrupt accounting for discarded samples
   - Fix a Zen5-specific quirk
   - Fix PhyAddrVal handling
   - Fix NMI-safety with perf_allow_kernel()
   - Fix a race between event add and NMIs

  Intel PMU driver updates:
   - Only check GP counters for PEBS constraints validation (Dapeng Mi)

  MSR driver:
   - Turn SMI_COUNT and PPERF on by default, instead of a long list of
     CPU models to enable them on (Kan Liang)

  ... and misc cleanups and fixes by Aldf Conte, Anshuman Khandual,
  Namhyung Kim, Ravi Bangoria and Yen-Hsiang Hsu"

* tag 'perf-core-2026-04-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/events: Replace READ_ONCE() with standard pgtable accessors
  perf/x86/msr: Make SMI and PPERF on by default
  perf/x86/intel/p4: Fix unused variable warning in p4_pmu_init()
  perf/x86/intel: Only check GP counters for PEBS constraints validation
  perf/x86/amd/ibs: Fix comment typo in ibs_op_data
  perf/amd/ibs: Advertise remote socket capability
  perf/amd/ibs: Enable streaming store filter
  perf/amd/ibs: Enable RIP bit63 hardware filtering
  perf/amd/ibs: Enable fetch latency filtering
  perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to eliminate RMW race
  perf/amd/ibs: Add new MSRs and CPUID bits definitions
  perf/amd/ibs: Define macro for ldlat mask and shift
  perf/amd/ibs: Avoid race between event add and NMI
  perf/amd/ibs: Avoid calling perf_allow_kernel() from the IBS NMI handler
  perf/amd/ibs: Preserve PhyAddrVal bit when clearing PhyAddr MSR
  perf/amd/ibs: Limit ldlat-&gt;l3missonly dependency to Zen5
  perf/amd/ibs: Account interrupt for discarded samples
  perf/core: Simplify __detach_global_ctx_data()
  perf/core: Try to allocate task_ctx_data quickly
  perf/core: Pass GFP flags to attach_task_ctx_data()
</content>
</entry>
<entry>
<title>Merge tag 'objtool-core-2026-04-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2026-04-14T20:00:04Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-04-14T20:00:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4b2bdc22210e39a02b3dc984cb8eb6b3293a56a7'/>
<id>urn:sha1:4b2bdc22210e39a02b3dc984cb8eb6b3293a56a7</id>
<content type='text'>
Pull objtool updates from Ingo Molnar:

 - KLP support updates and fixes (Song Liu)

 - KLP-build script updates and fixes (Joe Lawrence)

 - Support Clang RAX DRAP sequence, to address clang false positive
   (Josh Poimboeuf)

 - Reorder ORC register numbering to match regular x86 register
   numbering (Josh Poimboeuf)

 - Misc cleanups (Wentong Tian, Song Liu)

* tag 'objtool-core-2026-04-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  objtool/x86: Reorder ORC register numbering
  objtool: Support Clang RAX DRAP sequence
  livepatch/klp-build: report patch validation fuzz
  livepatch/klp-build: add terminal color output
  livepatch/klp-build: provide friendlier error messages
  livepatch/klp-build: improve short-circuit validation
  livepatch/klp-build: fix shellcheck complaints
  livepatch/klp-build: add Makefile with check target
  livepatch/klp-build: add grep-override function
  livepatch/klp-build: switch to GNU patch and recountdiff
  livepatch/klp-build: support patches that add/remove files
  objtool/klp: Correlate locals to globals
  objtool/klp: Match symbols based on demangled_name for global variables
  objtool/klp: Remove .llvm suffix in demangle_name()
  objtool/klp: Also demangle global objects
  objtool/klp: Use sym-&gt;demangled_name for symbol_name hash
  objtool/klp: Remove trailing '_' in demangle_name()
  objtool/klp: Remove redundant strcmp() in correlate_symbols()
  objtool: Use section/symbol type helpers
</content>
</entry>
<entry>
<title>Merge tag 'amd-pstate-v7.1-2026-04-02' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/superm1/linux</title>
<updated>2026-04-04T18:55:56Z</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2026-04-04T18:55:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5cdfedf68e6ee3905d36e387d49699d4d0848637'/>
<id>urn:sha1:5cdfedf68e6ee3905d36e387d49699d4d0848637</id>
<content type='text'>
Pull amd-pstate new content for 7.1 (2026-04-02) from Mario Limonciello:

"Add support for new features:
  * CPPC performance priority
  * Dynamic EPP
  * Raw EPP
  * New unit tests for new features
 Fixes for:
  * PREEMPT_RT
  * sysfs files being present when HW missing
  * Broken/outdated documentation"

* tag 'amd-pstate-v7.1-2026-04-02' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/superm1/linux: (22 commits)
  MAINTAINERS: amd-pstate: Step down as maintainer, add Prateek as reviewer
  cpufreq: Pass the policy to cpufreq_driver-&gt;adjust_perf()
  cpufreq/amd-pstate: Pass the policy to amd_pstate_update()
  cpufreq/amd-pstate-ut: Add a unit test for raw EPP
  cpufreq/amd-pstate: Add support for raw EPP writes
  cpufreq/amd-pstate: Add support for platform profile class
  cpufreq/amd-pstate: add kernel command line to override dynamic epp
  cpufreq/amd-pstate: Add dynamic energy performance preference
  Documentation: amd-pstate: fix dead links in the reference section
  cpufreq/amd-pstate: Cache the max frequency in cpudata
  Documentation/amd-pstate: Add documentation for amd_pstate_floor_{freq,count}
  Documentation/amd-pstate: List amd_pstate_prefcore_ranking sysfs file
  Documentation/amd-pstate: List amd_pstate_hw_prefcore sysfs file
  amd-pstate-ut: Add a testcase to validate the visibility of driver attributes
  amd-pstate-ut: Add module parameter to select testcases
  amd-pstate: Introduce a tracepoint trace_amd_pstate_cppc_req2()
  amd-pstate: Add sysfs support for floor_freq and floor_count
  amd-pstate: Add support for CPPC_REQ2 and FLOOR_PERF
  x86/cpufeatures: Add AMD CPPC Performance Priority feature.
  amd-pstate: Make certain freq_attrs conditionally visible
  ...
</content>
</entry>
<entry>
<title>x86/cpufeatures: Add AMD CPPC Performance Priority feature.</title>
<updated>2026-04-02T16:28:21Z</updated>
<author>
<name>Gautham R. Shenoy</name>
<email>gautham.shenoy@amd.com</email>
</author>
<published>2026-03-26T11:47:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=172100088f9b131b88bcde70724485470c20e7d2'/>
<id>urn:sha1:172100088f9b131b88bcde70724485470c20e7d2</id>
<content type='text'>
Some future AMD processors have feature named "CPPC Performance
Priority" which lets userspace specify different floor performance
levels for different CPUs. The platform firmware takes these different
floor performance levels into consideration while throttling the CPUs
under power/thermal constraints. The presence of this feature is
indicated by bit 16 of the EDX register for CPUID leaf
0x80000007. More details can be found in AMD Publication titled "AMD64
Collaborative Processor Performance Control (CPPC) Performance
Priority" Revision 1.10.

Define a new feature bit named X86_FEATURE_CPPC_PERF_PRIO to map to
CPUID 0x80000007.EDX[16].

Reviewed-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Signed-off-by: Gautham R. Shenoy &lt;gautham.shenoy@amd.com&gt;
Signed-off-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
</content>
</entry>
<entry>
<title>tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.0</title>
<updated>2026-03-28T16:28:35Z</updated>
<author>
<name>Ahmed S. Darwish</name>
<email>darwi@linutronix.de</email>
</author>
<published>2026-03-27T02:15:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=124ad3034ec0029b65178f3ab8a6cdca5a0b0519'/>
<id>urn:sha1:124ad3034ec0029b65178f3ab8a6cdca5a0b0519</id>
<content type='text'>
Update kcpuid's CSV to version 3.0, as generated by x86-cpuid-db.

Summary of the v2.5 changes:

- Reduce the verbosity of leaf and bitfields descriptions, as formerly
  requested by Boris.
- Leaf 0x8000000a: Add Page Modification Logging (PML) bit.

Summary of the v3.0 changes:

- Leaf 0x23: Introduce subleaf 2, Auto Counter Reload (ACR)
- Leaf 0x23: Introduce subleaf 4/5, PEBS capabilities and counters
- Leaf 0x1c: Return LBR depth as a bitmask instead of individual bits
- Leaf 0x0a: Use more descriptive PMU bitfield names
- Leaf 0x0a: Add various missing PMU events
- Leaf 0x06: Add missing IA32_HWP_CTL flag
- Leaf 0x0f: Add missing non-CPU (IO) Intel RDT bits

Thanks to Dave Hansen for reporting multiple missing bits.

Signed-off-by: Ahmed S. Darwish &lt;darwi@linutronix.de&gt;
Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.5/CHANGELOG.rst
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.0/CHANGELOG.rst
</content>
</entry>
<entry>
<title>tools headers UAPI: Sync x86's asm/kvm.h with the kernel sources</title>
<updated>2026-03-22T21:31:54Z</updated>
<author>
<name>Arnaldo Carvalho de Melo</name>
<email>acme@redhat.com</email>
</author>
<published>2026-03-18T18:48:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0a8b2a0857ede906f7b74a435b11778336770bea'/>
<id>urn:sha1:0a8b2a0857ede906f7b74a435b11778336770bea</id>
<content type='text'>
To pick the changes in:

  e2ffe85b6d2bb778 ("KVM: x86: Introduce KVM_X86_QUIRK_VMCS12_ALLOW_FREEZE_IN_SMM")

That just rebuilds kvm-stat.c on x86, no change in functionality.

This silences these perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/uapi/asm/kvm.h arch/x86/include/uapi/asm/kvm.h

Please see tools/include/uapi/README for further details.

Cc: Jim Mattson &lt;jmattson@google.com&gt;
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
<entry>
<title>tools arch x86: Sync the msr-index.h copy with the kernel sources</title>
<updated>2026-03-22T21:31:54Z</updated>
<author>
<name>Arnaldo Carvalho de Melo</name>
<email>acme@redhat.com</email>
</author>
<published>2026-03-18T18:42:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4ddd7588fae6175e748cff22c79faafb4d455d42'/>
<id>urn:sha1:4ddd7588fae6175e748cff22c79faafb4d455d42</id>
<content type='text'>
To pick up the changes from these csets:

  9073428bb204d921 ("x86/sev: Allow IBPB-on-Entry feature for SNP guests")

That cause no changes to tooling as it doesn't include a new MSR to be
captured by the tools/perf/trace/beauty/tracepoints/x86_msr.sh script.

Just silences this perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Cc: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Cc: Kim Phillips &lt;kim.phillips@amd.com&gt;
Signed-off-by: Arnaldo Carvalho de Melo &lt;acme@redhat.com&gt;
</content>
</entry>
<entry>
<title>objtool/x86: Reorder ORC register numbering</title>
<updated>2026-03-18T08:38:52Z</updated>
<author>
<name>Josh Poimboeuf</name>
<email>jpoimboe@kernel.org</email>
</author>
<published>2026-03-18T08:38:38Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1735858caa4bbb8b923860c0833d463b5d9c5f79'/>
<id>urn:sha1:1735858caa4bbb8b923860c0833d463b5d9c5f79</id>
<content type='text'>
Reorder the ORC register values so their ordering matches the x86
instruction set register encodings.

No functional change intended.

Suggested-by: Peter Zijlstra &lt;peterz@infradead.org&gt;
Signed-off-by: Josh Poimboeuf &lt;jpoimboe@kernel.org&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
</content>
</entry>
<entry>
<title>objtool: Support Clang RAX DRAP sequence</title>
<updated>2026-03-18T08:38:52Z</updated>
<author>
<name>Josh Poimboeuf</name>
<email>jpoimboe@kernel.org</email>
</author>
<published>2026-03-17T00:47:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=96f3b16a9de552538b810f773645d43f3b661b50'/>
<id>urn:sha1:96f3b16a9de552538b810f773645d43f3b661b50</id>
<content type='text'>
Recent Clang can use RAX as a temporary register for the DRAP stack
alignment sequence.  Add support for that.

Fixes the following warning:

  vmlinux.o: error: objtool: vmw_host_printf+0xd: unknown CFA base reg 0

Closes: https://lore.kernel.org/cefefdd1-7b82-406d-8ff4-e4b167e45ee6@app.fastmail.com
Reported-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Josh Poimboeuf &lt;jpoimboe@kernel.org&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://patch.msgid.link/3f33dc720b83dc6d3a2b7094f75a5c90a0b1cbc5.1773708458.git.jpoimboe@kernel.org
</content>
</entry>
</feed>
