linux/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h, branch master

perf arm_spe: Expose SIMD information in other operations

2025-11-19T04:31:30Z

The other operations contain SME data processing, ASE (Advanced SIMD) and floating-point operations. Expose these info in the records. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim

perf arm_spe: Report GCS in record

2025-11-19T04:31:30Z

Report GCS related info in records. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim

perf arm_spe: Report memset and memcpy in records

2025-11-19T04:31:30Z

Expose memset and memcpy related info in records. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim

perf arm_spe: Report associated info for SVE / SME operations

2025-11-19T04:31:29Z

SVE / SME operations can be predicated or Gather load / scatter store, save the relevant info into record. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim

perf arm_spe: Report MTE allocation tag in record

2025-11-19T04:31:29Z

Save MTE tag info in memory record. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim

perf arm_spe: Introduce data processing macro for SVE operations

2025-11-19T04:31:29Z

Introduce the ARM_SPE_OP_DP (data processing) macro as associated information for SVE operations. For SVE register access, only ARM_SPE_OP_SVE is set; for SVE data processing, both ARM_SPE_OP_SVE and ARM_SPE_OP_DP are set together. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim

perf arm_spe: Consolidate operation types

2025-11-19T04:31:29Z

Consolidate operation types in a way: (a) Extract the second-level types into separate enums. (b) The second-level types for memory and SIMD operations are classified by modules. E.g., an operation may relate to general register, SIMD/FP, SVE, etc. (c) The associated information tells details. E.g., an operation is load or store, whether it is atomic operation, etc. Start the enum items for the second-level types from 8 to accommodate more entries within a 32-bit integer. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim

perf arm_spe: Remove unused operation types

2025-11-19T04:31:29Z

Remove unused SVE operation types. These operations will be reintroduced in subsequent refactoring, but with a different format. Signed-off-by: Leo Yan Reviewed-by: Ian Rogers Reviewed-by: James Clark Signed-off-by: Namhyung Kim

perf arm_spe: Set HITM flag

2025-09-19T15:14:29Z

Since FEAT_SPEv1p4, Arm SPE provides two extra events: "Cache data modified" and "Data snooped". Set the snoop mode as: - If both the "Cache data modified" event and the "Data snooped" event are set, which indicates a load operation that snooped from a outside cache and hit a modified copy, set the HITM flag to inspect false sharing. - If the snooped event bit is not set, and the snooped event has been supported by the hardware, set as NONE mode (no snoop operation). - If the snooped event bit is not set, and the event is not supported or absent the events info in the meta data, set as NA mode (not available). Don't set any mode for only "Cache data modified" event, as it hits a local modified copy. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ali Saidi Cc: German Gomez Cc: Ian Rogers Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Will Deacon Signed-off-by: Arnaldo Carvalho de Melo

perf arm_spe: Fill memory levels for FEAT_SPEv1p4

2025-09-19T15:14:28Z

Starting with FEAT_SPEv1p4, Arm SPE provides information on Level 2 data cache and recently fetched events. This patch fills in the memory levels for these new events. The recently fetched events are matched to line-fill buffer (LFB). In general, the latency for accessing LFB is higher than accessing L1 cache but lower than accessing L2 cache. Thus, it locates in the memory hierarchy information between L1 cache and L2 cache. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ali Saidi Cc: German Gomez Cc: Ian Rogers Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Will Deacon Signed-off-by: Arnaldo Carvalho de Melo