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<title>linux/tools/testing/selftests/kvm/include, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
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<updated>2026-04-13T17:01:15Z</updated>
<entry>
<title>Merge tag 'kvm-s390-next-7.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD</title>
<updated>2026-04-13T17:01:15Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2026-04-13T17:01:15Z</published>
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<id>urn:sha1:6b802031877a995456c528095c41d1948546bf45</id>
<content type='text'>
- ESA nesting support
- 4k memslots
- LPSW/E fix
</content>
</entry>
<entry>
<title>Merge tag 'kvm-x86-nested-7.1' of https://github.com/kvm-x86/linux into HEAD</title>
<updated>2026-04-13T11:01:50Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2026-04-13T11:01:24Z</published>
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<id>urn:sha1:ea8bc95fbb75da215b7533c7c46f63423e84ff5e</id>
<content type='text'>
KVM nested SVM changes for 7.1 (with one common x86 fix)

 - To minimize the probability of corrupting guest state, defer KVM's
   non-architectural delivery of exception payloads (e.g. CR2 and DR6) until
   consumption of the payload is imminent, and force delivery of the payload
   in all paths where userspace saves relevant state.

 - Use vcpu-&gt;arch.cr2 when updating vmcb12's CR2 on nested #VMEXIT to fix a
   bug where L2's CR2 can get corrupted after a save/restore, e.g. if the VM
   is migrated while L2 is faulting in memory.

 - Fix a class of nSVM bugs where some fields written by the CPU are not
   synchronized from vmcb02 to cached vmcb12 after VMRUN, and so are not
   up-to-date when saved by KVM_GET_NESTED_STATE.

 - Fix a class of bugs where the ordering between KVM_SET_NESTED_STATE and
   KVM_SET_{S}REGS could cause vmcb02 to be incorrectly initialized after
   save+restore.

 - Add a variety of missing nSVM consistency checks.

 - Fix several bugs where KVM failed to correctly update VMCB fields on nested
   #VMEXIT.

 - Fix several bugs where KVM failed to correctly synthesize #UD or #GP for
   SVM-related instructions.

 - Add support for save+restore of virtualized LBRs (on SVM).

 - Refactor various helpers and macros to improve clarity and (hopefully) make
   the code easier to maintain.

 - Aggressively sanitize fields when copying from vmcb12 to guard against
   unintentionally allowing L1 to utilize yet-to-be-defined features.

 - Fix several bugs where KVM botched rAX legality checks when emulating SVM
   instructions.  Note, KVM is still flawed in that KVM doesn't address size
   prefix overrides for 64-bit guests; this should probably be documented as a
   KVM erratum.

 - Fail emulation of VMRUN/VMLOAD/VMSAVE if mapping vmcb12 fails instead of
   somewhat arbitrarily synthesizing #GP (i.e. don't bastardize AMD's already-
   sketchy behavior of generating #GP if for "unsupported" addresses).

 - Cache all used vmcb12 fields to further harden against TOCTOU bugs.
</content>
</entry>
<entry>
<title>Merge tag 'kvm-x86-selftests-7.1' of https://github.com/kvm-x86/linux into HEAD</title>
<updated>2026-04-13T09:53:46Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2026-04-13T09:53:46Z</published>
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<id>urn:sha1:c13008ed3d76142a001ebc56d8e391431cac2411</id>
<content type='text'>
KVM selftests changes for 7.1

 - Add support for Hygon CPUs in KVM selftests.

 - Fix a bug in the MSR test where it would get false failures on AMD/Hygon
   CPUs with exactly one of RDPID or RDTSCP.

 - Add an MADV_COLLAPSE testcase for guest_memfd as a regression test for a
   bug where the kernel would attempt to collapse guest_memfd folios against
   KVM's will.
</content>
</entry>
<entry>
<title>Merge tag 'kvmarm-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD</title>
<updated>2026-04-13T09:49:54Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2026-04-13T09:49:54Z</published>
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<id>urn:sha1:e74c3a8891c05f88eeb87121de7e12dc95766a4a</id>
<content type='text'>
KVM/arm64 updates for 7.1

* New features:

- Add support for tracing in the standalone EL2 hypervisor code,
  which should help both debugging and performance analysis.
  This comes with a full infrastructure for 'remote' trace buffers
  that can be exposed by non-kernel entities such as firmware.

- Add support for GICv5 Per Processor Interrupts (PPIs), as the
  starting point for supporting the new GIC architecture in KVM.

- Finally add support for pKVM protected guests, with anonymous
  memory being used as a backing store. About time!

* Improvements and bug fixes:

- Rework the dreaded user_mem_abort() function to make it more
  maintainable, reducing the amount of state being exposed to
  the various helpers and rendering a substantial amount of
  state immutable.

- Expand the Stage-2 page table dumper to support NV shadow
  page tables on a per-VM basis.

- Tidy up the pKVM PSCI proxy code to be slightly less hard
  to follow.

- Fix both SPE and TRBE in non-VHE configurations so that they
  do not generate spurious, out of context table walks that
  ultimately lead to very bad HW lockups.

- A small set of patches fixing the Stage-2 MMU freeing in error
  cases.

- Tighten-up accepted SMC immediate value to be only #0 for host
  SMCCC calls.

- The usual cleanups and other selftest churn.
</content>
</entry>
<entry>
<title>Merge tag 'loongarch-kvm-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD</title>
<updated>2026-04-13T09:46:11Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2026-04-13T09:46:11Z</published>
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<id>urn:sha1:05578316ca7246b45fb7d9eaf81308c0e0f3ee10</id>
<content type='text'>
LoongArch KVM changes for v7.1

1. Use CSR_CRMD_PLV in kvm_arch_vcpu_in_kernel().
2. Let vcpu_is_preempted() a macro &amp; some enhanments.
3. Add DMSINTC irqchip in kernel support.
4. Add KVM PMU test cases for tools/selftests.
</content>
</entry>
<entry>
<title>KVM: LoongArch: selftests: Add PMU overflow interrupt test</title>
<updated>2026-04-09T10:56:38Z</updated>
<author>
<name>Song Gao</name>
<email>gaosong@loongson.cn</email>
</author>
<published>2026-04-09T10:56:38Z</published>
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<id>urn:sha1:e47b8e1db9a9bbef6765e85b11e87f48e6b56846</id>
<content type='text'>
Extend the PMU test suite to cover overflow interrupts. The test enables
the PMI (Performance Monitor Interrupt), sets counter 0 to one less than
the overflow value, and verifies that an interrupt is raised when the
counter overflows. A guest interrupt handler checks the interrupt cause
and disables further PMU interrupts upon success.

Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Signed-off-by: Huacai Chen &lt;chenhuacai@loongson.cn&gt;
</content>
</entry>
<entry>
<title>KVM: LoongArch: selftests: Add basic PMU event counting test</title>
<updated>2026-04-09T10:56:37Z</updated>
<author>
<name>Song Gao</name>
<email>gaosong@loongson.cn</email>
</author>
<published>2026-04-09T10:56:37Z</published>
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<id>urn:sha1:11c840192768a5a63b6aed75273c5e8e416230ee</id>
<content type='text'>
Introduce a basic PMU test that verifies hardware event counting for
four performance counters. The test enables the events for CPU cycles,
instructions retired, branch instructions, and branch misses, runs a
fixed number of loops, and checks that the counter values fall within
expected ranges. It also validates that the host supports PMU and that
the VM feature is enabled.

Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Signed-off-by: Huacai Chen &lt;chenhuacai@loongson.cn&gt;
</content>
</entry>
<entry>
<title>KVM: LoongArch: selftests: Add cpucfg read/write helpers</title>
<updated>2026-04-09T10:56:37Z</updated>
<author>
<name>Song Gao</name>
<email>gaosong@loongson.cn</email>
</author>
<published>2026-04-09T10:56:37Z</published>
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<id>urn:sha1:fa19ea9a7bdb97575e05d72305a4c40a3a631357</id>
<content type='text'>
Add helper macros and functions to read and write CPU configuration
registers (cpucfg) from the guest and from the VMM. This interface is
required in upcoming selftests for querying and setting CPU features,
such as PMU capabilities.

Signed-off-by: Song Gao &lt;gaosong@loongson.cn&gt;
Signed-off-by: Huacai Chen &lt;chenhuacai@loongson.cn&gt;
</content>
</entry>
<entry>
<title>KVM: selftests: Remove 1M alignment requirement for s390</title>
<updated>2026-04-07T15:07:27Z</updated>
<author>
<name>Claudio Imbrenda</name>
<email>imbrenda@linux.ibm.com</email>
</author>
<published>2026-04-02T15:01:33Z</published>
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<id>urn:sha1:c10e2771c745a206a2642cb03eec40ace2e0a7b5</id>
<content type='text'>
Remove the 1M memslot alignment requirement for s390, since it is not
needed anymore.

Reviewed-by: Steffen Eiden &lt;seiden@linux.ibm.com&gt;
Signed-off-by: Claudio Imbrenda &lt;imbrenda@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: KVM: selftests: Fix firmware counter read in sbi_pmu_test</title>
<updated>2026-03-27T14:32:11Z</updated>
<author>
<name>Jiakai Xu</name>
<email>xujiakai2025@iscas.ac.cn</email>
</author>
<published>2026-03-16T01:45:33Z</published>
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<id>urn:sha1:198c7ce9801abd63c44176c3f034577b887c0070</id>
<content type='text'>
The current sbi_pmu_test attempts to read firmware counters without
configuring them first with SBI_EXT_PMU_COUNTER_CFG_MATCH.

Previously this did not fail because KVM incorrectly allowed the read
and accessed fw_event[] with an out-of-bounds index when the counter
was unconfigured. After fixing that bug, the read now correctly returns
SBI_ERR_INVALID_PARAM, causing the selftest to fail.

Update the test to configure a firmware event before reading the
counter. Also add a negative test to ensure that attempting to read an
unconfigured firmware counter fails gracefully.

Signed-off-by: Jiakai Xu &lt;xujiakai2025@iscas.ac.cn&gt;
Signed-off-by: Jiakai Xu &lt;jiakaiPeanut@gmail.com&gt;
Reviewed-by: Andrew Jones &lt;andrew.jones@oss.qualcomm.com&gt;
Reviewed-by: Nutty Liu &lt;nutty.liu@hotmail.com&gt;
Link: https://lore.kernel.org/r/20260316014533.2312254-3-xujiakai2025@iscas.ac.cn
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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