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<title>linux/tools/testing/selftests/riscv/vector/Makefile, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
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<updated>2026-02-09T22:27:33Z</updated>
<entry>
<title>selftests: riscv: test ptrace vector interface</title>
<updated>2026-02-09T22:27:33Z</updated>
<author>
<name>Sergey Matyukevich</name>
<email>geomatsi@gmail.com</email>
</author>
<published>2026-01-26T04:09:57Z</published>
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<id>urn:sha1:600f72ded8c877be95322ce806d23345ea5e89bc</id>
<content type='text'>
Add a test case to check ptrace behavior in the case when vector
extension is supported by the system, but vector context is not
yet enabled for the traced process.

Signed-off-by: Sergey Matyukevich &lt;geomatsi@gmail.com&gt;
Reviewed-by: Andy Chiu &lt;andybnac@gmail.com&gt;
Tested-by: Andy Chiu &lt;andybnac@gmail.com&gt;
Link: https://patch.msgid.link/20251214163537.1054292-6-geomatsi@gmail.com
[pjw@kernel.org: dropped duplicate sys/wait.h include]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>selftests: riscv: Add test for the Vector ptrace interface</title>
<updated>2025-11-19T16:19:28Z</updated>
<author>
<name>Yong-Xuan Wang</name>
<email>yongxuan.wang@sifive.com</email>
</author>
<published>2025-11-18T04:19:30Z</published>
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<id>urn:sha1:f0ae09a89267552bde346c8cb27acb838a21eb1c</id>
<content type='text'>
Add a test case that does some basic verification of the Vector ptrace
interface. This forks a child process then using ptrace to inspect and
manipulate the v31 register of the child.

Signed-off-by: Yong-Xuan Wang &lt;yongxuan.wang@sifive.com&gt;
Reviewed-by: Andy Chiu &lt;andybnac@gmail.com&gt;
Tested-by: Andy Chiu &lt;andybnac@gmail.com&gt;
Link: https://patch.msgid.link/20251013091318.467864-3-yongxuan.wang@sifive.com
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
</content>
</entry>
<entry>
<title>selftests: riscv: Fix vector tests</title>
<updated>2025-01-18T20:33:37Z</updated>
<author>
<name>Charlie Jenkins</name>
<email>charlie@rivosinc.com</email>
</author>
<published>2024-11-14T02:21:18Z</published>
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<id>urn:sha1:57d7713af93e4b7344d3022fad9ddf0f10f815ec</id>
<content type='text'>
Overhaul the riscv vector tests to use kselftest_harness to help the
test cases correctly report the results and decouple the individual test
cases from each other. With this refactoring, only run the test cases if
vector is reported and properly report the test case as skipped
otherwise. The v_initval_nolibc test was previously not checking if
vector was supported and used a function (malloc) which invalidates
the state of the vector registers.

Signed-off-by: Charlie Jenkins &lt;charlie@rivosinc.com&gt;
Tested-by: Yangyu Chen &lt;cyy@cyyself.name&gt;
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-12-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>selftests: Test RISC-V Vector's first-use handler</title>
<updated>2023-07-01T14:38:22Z</updated>
<author>
<name>Andy Chiu</name>
<email>andy.chiu@sifive.com</email>
</author>
<published>2023-06-27T01:55:55Z</published>
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<id>urn:sha1:5c93c4c72fbc69f0f1cdf43c9402b923314e67c8</id>
<content type='text'>
This add a test to check if the kernel zero-initializes all V registers
after the first-use trap handler returns.

If V registers are not zero-initialized, then the test should fail one
out of several runs:

```
 root@sifive-fpga:~# ./v_initval_nolibc
 # vl = 256
 not ok 1 detect stale values on v-regesters
 0 0 0 0 0 0 0 0   0 0 0 0 0 0 0 0
 0 4c 41 4e 47 3d 43 0   50 41 54 48 3d 2f 75 73
 72 2f 6c 6f 63 61 6c 2f   73 62 69 6e 3a 2f 75 73
 72 2f 6c 6f 63 61 6c 2f   62 69 6e 3a 2f 75 73 72
 ff ff 81 0 0 0 0 0   0 0 0 0 0 0 0 0
```

Otherwise, the test passes without errors each run.

Signed-off-by: Andy Chiu &lt;andy.chiu@sifive.com&gt;
Reviewed-by: Björn Töpel &lt;bjorn@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20230627015556.12329-3-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>selftests: Test RISC-V Vector prctl interface</title>
<updated>2023-06-08T14:16:58Z</updated>
<author>
<name>Andy Chiu</name>
<email>andy.chiu@sifive.com</email>
</author>
<published>2023-06-05T11:07:23Z</published>
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<id>urn:sha1:7cf6198ce22d92590f9aaa13431001fa97bc0b2b</id>
<content type='text'>
This add a test for prctl interface that controls the use of userspace
Vector.

Signed-off-by: Andy Chiu &lt;andy.chiu@sifive.com&gt;
Link: https://lore.kernel.org/r/20230605110724.21391-27-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
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