diff options
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3588-base.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 157 |
1 files changed, 156 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 70f03e68ba55..e2500e31c434 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -621,6 +621,16 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; }; + csidphy0_grf: syscon@fd5b4000 { + compatible = "rockchip,rk3588-csidphy-grf", "syscon"; + reg = <0x0 0xfd5b4000 0x0 0x1000>; + }; + + csidphy1_grf: syscon@fd5b5000 { + compatible = "rockchip,rk3588-csidphy-grf", "syscon"; + reg = <0x0 0xfd5b5000 0x0 0x1000>; + }; + pipe_phy0_grf: syscon@fd5bc000 { compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; reg = <0x0 0xfd5bc000 0x0 0x100>; @@ -841,7 +851,7 @@ status = "okay"; /* These power domains are grouped by VD_NPU */ - power-domain@RK3588_PD_NPU { + pd_npu: power-domain@RK3588_PD_NPU { reg = <RK3588_PD_NPU>; #power-domain-cells = <0>; #address-cells = <1>; @@ -1140,6 +1150,97 @@ }; }; + rknn_core_0: npu@fdab0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdab0000 0x0 0x1000>, + <0x0 0xfdab1000 0x0 0x1000>, + <0x0 0xfdab3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPUTOP>; + iommus = <&rknn_mmu_0>; + status = "disabled"; + }; + + rknn_mmu_0: iommu@fdab9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdab9000 0x0 0x100>, + <0x0 0xfdaba000 0x0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPUTOP>; + status = "disabled"; + }; + + rknn_core_1: npu@fdac0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdac0000 0x0 0x1000>, + <0x0 0xfdac1000 0x0 0x1000>, + <0x0 0xfdac3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPU1>; + iommus = <&rknn_mmu_1>; + status = "disabled"; + }; + + rknn_mmu_1: iommu@fdac9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdaca000 0x0 0x100>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPU1>; + status = "disabled"; + }; + + rknn_core_2: npu@fdad0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdad0000 0x0 0x1000>, + <0x0 0xfdad1000 0x0 0x1000>, + <0x0 0xfdad3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN2>, <&cru SRST_H_RKNN2>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPU2>; + iommus = <&rknn_mmu_2>; + status = "disabled"; + }; + + rknn_mmu_2: iommu@fdad9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdada000 0x0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPU2>; + status = "disabled"; + }; + vpu121: video-codec@fdb50000 { compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; reg = <0x0 0xfdb50000 0x0 0x800>; @@ -1472,6 +1573,36 @@ }; }; + dp0: dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde50000 0x0 0x4000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru CLK_AUX16M_0>; + assigned-clock-rates = <16000000>; + clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, + <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, + <&cru MCLK_SPDIF2_DP0>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + phys = <&usbdp_phy0 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_DP0>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp0_in: port@0 { + reg = <0>; + }; + + dp0_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi0: hdmi@fde80000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfde80000 0x0 0x20000>; @@ -3055,6 +3186,30 @@ status = "disabled"; }; + csi_dphy0: phy@fedc0000 { + compatible = "rockchip,rk3588-csi-dphy"; + reg = <0x0 0xfedc0000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY0>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names = "apb", "phy"; + rockchip,grf = <&csidphy0_grf>; + status = "disabled"; + }; + + csi_dphy1: phy@fedc8000 { + compatible = "rockchip,rk3588-csi-dphy"; + reg = <0x0 0xfedc8000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY1>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>; + reset-names = "apb", "phy"; + rockchip,grf = <&csidphy1_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; |