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2015-11-18drm/i915: Streamline gpio_mmio_base deductionVille Syrjälä-8/+7
2015-11-18drm/i915: Store DVO SRCDIM register offset under intel_dvo_deviceVille Syrjälä-14/+10
2015-11-18drm/i915: s/is_sdvob/enum port/Ville Syrjälä-23/+32
2015-11-18drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to i...Ville Syrjälä-23/+19
2015-11-18pci: Decouple quirks.c from i915_reg.hVille Syrjälä-1/+3
2015-11-18drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_p...Rodrigo Vivi-13/+6
2015-11-18drm/i915: Stop tracking last calculated Sink CRC.Rodrigo Vivi-32/+9
2015-11-18drm/i915: Make Sink crc calculation waiting for counter to reset.Rodrigo Vivi-1/+18
2015-11-18drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop.Rodrigo Vivi-0/+4
2015-11-17drm/i915/skl: Remove unused suspend and resume callbacksPatrik Jakobsson-17/+0
2015-11-17drm/i915/gen9: Add boot parameter for disabling DC6Patrik Jakobsson-3/+18
2015-11-17drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson-35/+90
2015-11-17drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson-0/+4
2015-11-17drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()Patrik Jakobsson-3/+0
2015-11-17drm/i915: Add a modeset power domainPatrik Jakobsson-0/+3
2015-11-17drm/i915: Remove distinction between DDI 2 vs 4 lanesPatrik Jakobsson-78/+45
2015-11-17drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINSVille Syrjälä-5/+1
2015-11-17drm/i915: Introduce a gmbus power domainVille Syrjälä-40/+13
2015-11-17drm/i915: Clean up AUX power domain handlingVille Syrjälä-34/+59
2015-11-17drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6Patrik Jakobsson-18/+17
2015-11-17drm/i915: Don't trust CSR program memory contentsPatrik Jakobsson-7/+3
2015-11-17drm/i915: fix handling of the disable_power_well module optionImre Deak-2/+16
2015-11-17drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enablingImre Deak-5/+0
2015-11-17drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLKImre Deak-10/+4
2015-11-17drm/i915/skl: disable DC states before display core init/uninitImre Deak-0/+4
2015-11-17drm/i915/gen9: simplify DC toggling codeImre Deak-36/+28
2015-11-17drm/i915/skl: don't toggle PW1 and MISC power wells on-demandImre Deak-27/+9
2015-11-17drm/i915/skl: init/uninit display core as part of the HW power domain stateImre Deak-21/+61
2015-11-17drm/i915: rename intel_power_domains_resume to *_sync_hwImre Deak-2/+2
2015-11-17drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau-4/+35
2015-11-17drm/i915: fix lookup_power_well for power wells without any domainImre Deak-2/+4
2015-11-17drm/i915: fix the power well ID for always on wellsImre Deak-1/+5
2015-11-17drm/i915: get runtime PM reference around GEM set_tiling IOCTLImre Deak-0/+4
2015-11-17drm/i915: Serialise updates to GGTT with access through GGTT on BraswellChris Wilson-0/+25
2015-11-17drm/i915: force link training when requested by SinkShubhangi Shrivastava-1/+3
2015-11-17drm/i915: Cleanup test data during long/short hotplugShubhangi Shrivastava-8/+22
2015-11-17drm/i915/skl: Correct other-pipe watermark update condition check (v2)Kumar, Mahesh-7/+5
2015-11-16drm/i915: Model PSR AUX register selection more like the normal AUX codeVille Syrjälä-6/+21
2015-11-16drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä-21/+27
2015-11-16drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]Ville Syrjälä-10/+85
2015-11-16drm/i915: Remove the magic AUX_CTL is at DP + foo tricksVille Syrjälä-76/+105
2015-11-16drm/i915: Parametrize AUX registersVille Syrjälä-63/+62
2015-11-16drm/i915: Replace the aux ddc name switch statement with kasprintf()Ville Syrjälä-29/+46
2015-11-16drm/i915: Replace aux_ch_ctl_reg check with port checkVille Syrjälä-1/+1
2015-11-13drm/i915/skl: Update DDI translation tables for SKLjim.bride@linux.intel.com-11/+11
2015-11-13drm/i915: Fix SKL i_boost levelAnder Conselvan de Oliveira-3/+3
2015-11-12drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6Animesh Manna-1/+0
2015-11-12drm/i915/gen9: flush DMC fw loading work during system suspendImre Deak-0/+3
2015-11-12drm/i915/gen9: Use flush_work to synchronize with dmc loaderAnimesh Manna-2/+2
2015-11-12drm/i915: Use request_firmware and our own async workDaniel Vetter-13/+14
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