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2025-09-08drm/panel-edp: Add 4 more panels needed by mt8189 ChromebooksZhongtian Wu1-0/+11
Add a few generic edp panels used by mt8189 chromebooks. For BOE-NV140WUM-N44 , the enable timing required 80ms. For CSW-MNE007QB3-1, the hpd_absent timing rquired 80ms, the enable timing required 50ms, the disable timing required 50ms. For CSW-MNE007QS3-6, the enable timing required 50ms. For CMN-N140JCA-ELK, the enable timing required 80ms and disable timing required 50ms. BOE NV140WUM-N44 V8.2 edid-decode (hex): 00 ff ff ff ff ff ff 00 09 e5 6a 0a 00 00 00 00 2e 20 01 04 a5 1e 13 78 03 fb f5 96 5d 5a 91 29 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 61 40 80 04 71 b0 3c 40 30 20 36 00 2d bc 10 00 00 1a 81 33 80 04 71 b0 3c 40 30 20 36 00 2d bc 10 00 00 1a 00 00 00 fd 00 28 3c 4c 4c 10 01 0a 20 20 20 20 20 20 00 00 00 fe 00 4e 56 31 34 30 57 55 4d 2d 4e 34 34 0a 01 7c 02 03 0d 00 68 1a 00 00 01 01 28 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 CSW MNE007QB3-1: edid-decode (hex): 00 ff ff ff ff ff ff 00 0e 77 6e 14 00 00 00 00 00 23 01 04 a5 1e 13 78 07 ee 95 a3 54 4c 99 26 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 35 3c 80 a0 70 b0 23 40 30 20 36 00 2d bc 10 00 00 18 2b 30 80 a0 70 b0 23 40 30 20 36 00 2d bc 10 00 00 18 00 00 00 fd 00 28 3c 4a 4a 0f 01 0a 20 20 20 20 20 20 00 00 00 fc 00 4d 4e 45 30 30 37 51 42 33 2d 31 0a 20 01 69 70 20 79 02 00 21 00 1d c8 0b 5d 07 80 07 b0 04 00 3d 8a 54 cd a4 99 66 62 0f 02 45 54 40 5e 40 5e 00 44 12 78 2e 00 06 00 44 40 5e 40 5e 81 00 20 74 1a 00 00 03 01 28 3c 00 00 00 00 00 00 3c 00 00 00 00 8d 00 e3 05 04 00 e6 06 01 00 60 60 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 90 CSW MNE007QS3-6: edid-decode (hex): 00 ff ff ff ff ff ff 00 0e 77 3f 14 00 00 00 00 00 22 01 04 a5 1e 13 78 03 2c c5 94 5c 59 95 29 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 ea 3d 80 c8 70 b0 2e 40 30 20 36 00 2e bd 10 00 00 1a 88 31 80 c8 70 b0 2e 40 30 20 36 00 2e bd 10 00 00 1a 00 00 00 fd 00 28 3c 4b 4b 10 01 0a 20 20 20 20 20 20 00 00 00 fc 00 4d 4e 45 30 30 37 51 53 33 2d 36 0a 20 01 80 70 20 79 02 00 81 00 14 74 1a 00 00 03 01 28 3c 00 00 00 00 00 00 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9e 90 CMN N140JCA-ELK: edid-decode (hex): 00 ff ff ff ff ff ff 00 0d ae 41 14 00 00 00 00 25 21 01 04 a5 1e 13 78 03 28 65 97 59 54 8e 27 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 42 3c 80 a0 70 b0 24 40 30 20 a6 00 2d bc 10 00 00 18 35 30 80 a0 70 b0 24 40 30 20 a6 00 2d bc 10 00 00 18 00 00 00 fd 00 28 3c 4b 4b 10 01 0a 20 20 20 20 20 20 00 00 00 fe 00 4e 31 34 30 4a 43 41 2d 45 4c 4b 0a 20 01 14 02 03 0d 00 68 1a 00 00 01 01 28 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250908063732.764289-1-wuzhongtian@huaqin.corp-partner.google.com
2025-09-08drm/amdgpu: Wait for bootloader after PSPv11 resetLijo Lazar1-15/+4
Some PSPv11 SOCs take a longer time for PSP based mode-1 reset. Instead of checking for C2PMSG_33 status, add the callback wait_for_bootloader. Wait for bootloader to be back to steady state is already part of the generic mode-1 reset flow. Increase the retry count for bootloader wait and also fix the mask to prevent fake pass. Fixes: 8345a71fc54b ("drm/amdgpu: Add more checks to PSP mailbox") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4531 Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 32f73741d6ee41fd5db8791c1163931e313d0fdc)
2025-09-08drm/xe/configfs: Use config_group_put()Lucas De Marchi1-1/+1
configfs has a config_group_put() helper that was adopted by commit 88df7939d728 ("drm/xe/configfs: Rename struct xe_config_device"). Another pending work to add psmi later landed in commit afe902848b41 ("drm/xe/configfs: Allow to enable PSMI") and didn't use the helper. Use config_group_put() consistently to hide the inner workings of configfs. No change in behavior since it does exactly the same thing as currently being done. Cc: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://lore.kernel.org/r/20250905162236.578117-2-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-09-08drm/msm/a6xx: Enable IFPC on A750 GPUAkhil P Oommen1-1/+2
A750 GPU has similar IFPC related configurations like X1-85. Add the IFPC QUIRK to enable IFPC feature. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673386/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/a6xx: Enable IFPC on Adreno X1-85Akhil P Oommen3-5/+79
Add the IFPC restore register list and enable IFPC support on Adreno X1-85 gpu. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673384/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/a6xx: Make crashstate capture IFPC safeAkhil P Oommen3-11/+30
Now with IFPC, GX domain can collapse as soon as GPU becomes IDLE. So add gx_is_on check before accessing any GX registers during crashstate capture and recovery. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673383/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/adreno: Disable IFPC when sysprof is activeAkhil P Oommen6-0/+47
Moving to IFPC state clears the 'Perfcounter Select' register setup by the userspace. So, lets block the IFPC when sysprof is active by using the perfcounter oob signal to the GMU. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673380/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/a6xx: Fix hangcheck for IFPCAkhil P Oommen1-2/+13
From the hangcheck handler, KMD checks a few registers in GX domain to see if the GPU made any progress. But it cannot access those registers when IFPC is enabled. Since HW based hang detection is pretty decent, lets rely on it instead of these registers when IFPC is enabled. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673378/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm: Add support for IFPCAkhil P Oommen3-8/+32
Add a new quirk to denote IFPC (Inter-Frame Power Collapse) support for a gpu. Based on this flag send the feature ctrl hfi message to GMU to enable IFPC support. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673375/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/a6xx: Poll AHB fence status in GPU IRQ handlerAkhil P Oommen2-0/+29
Even though the GX power domain is kept ON when there is a pending GPU interrupt, there is a small window of potential race with GMU where it may move the AHB fence to 'Drop' mode. Once the GMU sees the pending IRQ, it will move back the fence state to ALLOW mode. Close this race window by polling for AHB fence to ensure that it is in 'Allow' mode. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673377/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/a6xx: Switch to GMU AO counterAkhil P Oommen1-14/+16
CP_ALWAYS_ON counter falls under GX domain which is collapsed during IFPC. So switch to GMU_ALWAYS_ON counter for any CPU reads since it is not impacted by IFPC. Both counters are clocked by same xo clock source. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673373/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/a6xx: Set Keep-alive votes to block IFPCAkhil P Oommen2-9/+37
Set Keepalive votes at appropriate places to block IFPC power collapse until we access all the required registers. This is required during gpu IRQ handling and also during preemption. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673369/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/adreno: Add fenced regwrite supportAkhil P Oommen3-11/+90
There are some special registers which are accessible even when GX power domain is collapsed during an IFPC sleep. Accessing these registers wakes up GPU from power collapse and allow programming these registers without additional handshake with GMU. This patch adds support for this special register write sequence. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673368/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm: Add an ftrace for gpu register accessAkhil P Oommen2-0/+20
With IFPC, there is a probability of accessing a GX domain register when it is collapsed, which leads to gmu fence errors. To debug this, we need to trace every gpu register accesses and identify the one just before a gmu fence error. So, add an ftrace to track all gpu register accesses. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673366/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm: a6xx: Refactor a6xx_sptprac_enable()Akhil P Oommen2-4/+7
A minor refactor to combine the subroutines for legacy a6xx GMUs under a single check. This helps to avoid an unnecessary check and return early from the subroutine for majority of a6xx gpus. Also, document an intermediate unknown low power state which is not exposed by the GMU firmware. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673364/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/a6xx: Fix PDC sleep sequenceAkhil P Oommen2-11/+23
Since the PDC resides out of the GPU subsystem and cannot be reset in case it enters bad state, utmost care must be taken to trigger the PDC wake/sleep routines in the correct order. The PDC wake sequence can be exercised only after a PDC sleep sequence. Additionally, GMU firmware should initialize a few registers before the KMD can trigger a PDC sleep sequence. So PDC sleep can't be done if the GMU firmware has not initialized. Track these dependencies using a new status variable and trigger PDC sleep/wake sequences appropriately. Cc: stable@vger.kernel.org Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673362/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/a6xx: Poll additional DRV statusAkhil P Oommen1-0/+16
A7XX_GEN2 generation has additional TCS slots. Poll the respective DRV status registers before pm suspend. Fixes: 1f8c29e80066 ("drm/msm/a6xx: Add A740 support") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673361/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm: a6xx: Fix gx_is_on check for a7x familyAkhil P Oommen1-0/+7
Bitfield definition for REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS register is different in A7XX family. Check the correct bits to see if GX is collapsed on A7XX series. Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673358/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm: Update GMU register xmlAkhil P Oommen1-0/+11
Update GMU register xml with additional definitions for a7x family. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/673356/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/mdp4: use msm_kms_init_vm() instead of duplicating itDmitry Baryshkov5-29/+9
Use the msm_kms_init_vm() function to allocate memory manager instead of hand-coding a copy of it. Although MDP4 platforms don't have MDSS device, it's still safe to use the function as all MDP4 devices have IOMMU and the parent of the MDP4 is the root SoC device. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/672563/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm: don't return NULL from msm_iommu_new()Dmitry Baryshkov5-18/+16
As we've dropped no-IOMMU support, there is no reason to specially handle the no-IOMMU case inside msm_iommu_new(). Make it return -ENODEV if there is no IOMMU (instead of returning NULL) and simplify all calling sites accordingly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/672561/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm: stop supporting no-IOMMU configurationDmitry Baryshkov1-3/+2
With the switch to GPUVM the msm driver no longer supports the no-IOMMU configurations (even without the actual GPU). Return an error in case we face the lack of the IOMMU. Fixes: 111fdd2198e6 ("drm/msm: drm_gpuvm conversion") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/672559/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/mdp4: stop supporting no-IOMMU configurationDmitry Baryshkov1-3/+3
With the switch to GPUVM the msm driver no longer supports the no-IOMMU configurations (even without the actual GPU). Return an error in case we face the lack of the IOMMU for an MDP4 device. Fixes: 111fdd2198e6 ("drm/msm: drm_gpuvm conversion") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/672557/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/msm/adreno: Add speedbin data for A623 GPUAkhil P Oommen1-0/+5
Add the speedbin mappings for Adreno 623 GPU. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/672462/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-08drm/tiny/bochs: Convert dev_err() to drm_err()Leander Kieweg1-1/+1
The DRM subsystem has a set of preferred, prefixed logging functions (drm_info, drm_warn, drm_err) which improve debuggability by including the driver and function name in the log output. As part of the ongoing effort to modernize logging calls, convert a dev_err() call in the bochs hardware initialization function to its drm_err() equivalent. This work was suggested by the DRM TODO list. Signed-off-by: Leander Kieweg <kieweg.leander@gmail.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20250818113530.187440-1-kieweg.leander@gmail.com
2025-09-08overflow: add range_overflows() and range_end_overflows()Jani Nikula1-70/+0
Move the range_overflows() and range_end_overflows() along with the _t variants over from drm/i915 and drm/buddy to overflow.h. Cc: Kees Cook <kees@kernel.org> Cc: "Gustavo A. R. Silva" <gustavoars@kernel.org> Cc: linux-hardening@vger.kernel.org Reviewed-by: Kees Cook <kees@kernel.org> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20250829174601.2163064-3-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-08drm/i915: document range_overflows() and range_end_overflows() macrosJani Nikula1-0/+46
Document the macros in preparation for making them more generally available. Cc: Kees Cook <kees@kernel.org> Cc: "Gustavo A. R. Silva" <gustavoars@kernel.org> Cc: linux-hardening@vger.kernel.org Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250829174601.2163064-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-08drm/i915: rename range_overflows_end() to range_end_overflows()Jani Nikula3-6/+6
Rename range_overflows_end() to range_end_overflows(), along with the _t variant. It's all rather subjective, but I think range_end_overflows() reads better. Cc: Kees Cook <kees@kernel.org> Cc: "Gustavo A. R. Silva" <gustavoars@kernel.org> Cc: linux-hardening@vger.kernel.org Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250829174601.2163064-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-08drm/{i915,xe}/panic: pass struct intel_panic to intel_panic_setup()Jani Nikula6-14/+18
Reduce the struct intel_framebuffer usage within the panic implementation. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/2a016167b1f6f0b432aed0a630f9dbcd07fadb7b.1756835342.git.jani.nikula@intel.com
2025-09-08drm/{i915,xe}/panic: convert intel_panic_finish() to struct intel_panicJani Nikula6-13/+7
The intel_panic_finish() function really needs the struct intel_panic pointer, not struct intel_framebuffer. Make it so. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/3fdbcbe17e0e90c4a590f2a2486a9ec79a90cf62.1756835342.git.jani.nikula@intel.com
2025-09-08drm/{i915,xe}/panic: move framebuffer allocation where it belongsJani Nikula6-32/+31
The struct intel_framebuffer allocation naturally belongs in intel_fb.c, not hidden inside panic implementation. Separate the panic allocation. Drop the unnecessary struct i915_framebuffer and struct xe_framebuffer types. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/d29f63e0118d002fc8edd368caea7e8185418e17.1756835342.git.jani.nikula@intel.com
2025-09-08drm/{i915,xe}/panic: rename struct {i915,xe}_panic_data to struct intel_panicJani Nikula3-13/+14
Prepare for better shared interfaces between panic implementations. The struct intel_panic remains an opaque data type, with unique implementations in i915 and xe. This allows us to change the panic data pointer from void * to struct intel_panic *, helping type safety. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/884ffc80c8b5fef1b92956e644a4e559560cc2ba.1756835342.git.jani.nikula@intel.com
2025-09-08drm/{i915,xe}/fb: add panic pointer member to struct intel_framebufferJani Nikula3-22/+19
Add a panic data pointer member in struct intel_framebuffer in preparation for breaking the artificial subclassing between intel_framebuffer and panic structures. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/41f42e1de8545409274d54854aa12e0fb390e394.1756835342.git.jani.nikula@intel.com
2025-09-08drm/{i915,xe}/panic: rename intel_bo_panic_*() to intel_panic_*()Jani Nikula4-8/+8
Rename the intel_bo_panic_*() functions according to the functionality, dropping the misleading intel_bo reference. Keep intel_bo_alloc_framebuffer() for now; it'll be refactored later. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/a3be8f8b5e7dd208027a1131e89452d9a214054f.1756835342.git.jani.nikula@intel.com
2025-09-08drm/{i915,xe}/panic: split out intel_panic.[ch]Jani Nikula12-110/+136
intel_bo.[ch] is not the appropriate location for the panic functionality. Split out intel_panic.[ch] and xe_panic.c in i915 and xe. Keep the function names for now. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/d98b831a011a028ffd33ce99b0ba62be061ee235.1756835342.git.jani.nikula@intel.com
2025-09-08drm/i915/fb: add intel_framebuffer_alloc()Jani Nikula4-4/+11
Add intel_framebuffer_alloc() to hide intel_bo_alloc_framebuffer(), as that doesn't feel like the correct abstraction. Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Maarten Lankhorst <dev@lankhorst.se> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://lore.kernel.org/r/379c306c692c50f6af3b6f2488c213f12627954f.1756835342.git.jani.nikula@intel.com
2025-09-08drm/i915/display: Remove FBC modulo 4 restriction for ADL-P+Uma Shankar1-2/+2
WA:22010751166 does not apply past display version 12. Or, in other words, the FBC restriction where FBC is disabled for non-modulo 4 plane sizes (including plane size + yoffset) is fixed from display version 13 and onwards. Relax the restriction for the same. v4: Dropped redundant commit message v3: Update comments for clarity (Jonathan Cavitt) v2: Update the macro for display version check (Vinod) Suggested-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://lore.kernel.org/r/20250904095338.300813-2-uma.shankar@intel.com
2025-09-08drm/i915/gvt: Remove redundant ternary operatorsLiao Yuanhong1-1/+1
For ternary operators in the form of "a ? false : true", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Signed-off-by: Liao Yuanhong <liaoyuanhong@vivo.com> Link: https://lore.kernel.org/r/20250904112644.350512-1-liaoyuanhong@vivo.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-08drm/i915/ddi: abstract figuring out encoder nameJani Nikula1-31/+38
The encoder name deduction has become a bit cumbersome within intel_ddi_init(). Split it out to a separate function to declutter intel_ddi_init(), even if that means having to use a temp seq buffer for the name. Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250903101050.3671305-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-08drm/i915/power: fix size for for_each_set_bit() in abox iterationJani Nikula1-3/+3
for_each_set_bit() expects size to be in bits, not bytes. The abox mask iteration uses bytes, but it works by coincidence, because the local variable holding the mask is unsigned long, and the mask only ever has bit 2 as the highest bit. Using a smaller type could lead to subtle and very hard to track bugs. Fixes: 62afef2811e4 ("drm/i915/rkl: RKL uses ABOX0 for pixel transfers") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: stable@vger.kernel.org # v5.9+ Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20250905104149.1144751-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-09-08drm/i915/psr: Panel Replay SU cap dpcd read return valueJouni Högander1-5/+7
Currently return value of drm_dpcd_readb is not checked when reading sink Panel Replay Selective Update capabilities. Fix this and switch to drm_dpcd_read_byte. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://lore.kernel.org/r/20250827060809.2461725-1-jouni.hogander@intel.com
2025-09-08drm/rcar-du: dsi: Implement DSI command supportMarek Vasut2-0/+350
Implement support for DSI command transfer. Transmission of both Short Packet and Long Packet is implemented, so is command transmission to request response from peripheral device and transmission of non-read command with BTA. The AXI memory access mode is currently not implemented, each transfer is performed purely using controller register interface. Short Packet transfer can transfer up to 2 Bytes of data, Long Packet transfer can transfer up to 16 Bytes of data. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20250831190507.327848-1-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-09-08drm: rcar-du: lvds: Convert to RUNTIME_PM_OPS()Geert Uytterhoeven1-2/+2
Convert the Renesas R-Car Display Unit LVDS driver from SET_RUNTIME_PM_OPS() to RUNTIME_PM_OPS(), and pm_ptr(). This reduces kernel size in case CONFIG_PM is disabled. While DRM_RCAR_LVDS depends on PM, the code may still serve as an example for new drivers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/2264ff4f21a7e17384822e0efba176cf78ae184d.1756999823.git.geert+renesas@glider.be Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-09-08drm/i915/psr: Add poll for checking PSR is idle before starting updateJouni Högander1-0/+3
We are currently observing crc failures after we started using dsb for PSR updates as well. This seems to happen because PSR HW is still sending couple of updates using old framebuffers on wake-up. Fix this by adding poll ensuring PSR is idle before starting update. v2: pass new_crtc_state->dsb_commit to intel_psr_wait_for_idle_dsb Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/20250905072708.2659411-5-jouni.hogander@intel.com
2025-09-08drm/i915/psr: New interface adding PSR idle poll into dsb commitJouni Högander2-4/+37
We are currently observing crc failures after we started using dsb for PSR updates as well. This seems to happen because PSR HW is still sending couple of updates using old framebuffers on wake-up. This patch is preparing to fix that by adding interface which can be used to add poll ensuring PSR HW is idle into dsb commit. v3: add intel_dsb as a parameter to intel_psr_wait_for_idle_dsb v2: add pass crtc_state->dsb_commit as parameter Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/20250905072708.2659411-4-jouni.hogander@intel.com
2025-09-08drm/i915/psr: Add new define for PSR idle timeoutJouni Högander1-8/+12
Currently we are using value 50ms as timeout for waiting PSR to idle. Add own define for this purpose. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250905072708.2659411-3-jouni.hogander@intel.com
2025-09-08drm/i915/psr: Pass intel_crtc_state instead of intel_dp in wait_for_idleJouni Högander1-8/+10
This is preparation to add own function for polling PSR being ready for update when doing dsb commit. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250905072708.2659411-2-jouni.hogander@intel.com
2025-09-06drm/msm/adreno: Add speedbins for A663 GPUAkhil P Oommen1-0/+5
Add speedbin mappings for A663 GPU. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/670096/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-06drm/msm: make sure to not queue up recovery more than onceAntonino Maniscalco1-0/+3
If two fault IRQs arrive in short succession recovery work will be queued up twice. When recovery runs a second time it may end up killing an unrelated context. Prevent this by masking off interrupts when triggering recovery. Signed-off-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/670023/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-09-06drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPUNeil Armstrong1-0/+11
The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core scale the interconnect ddr path. Declare the Bus Control Modules (BCMs) and the corresponding parameters in the GPU info struct to allow the GMU to vote for the bandwidth. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/665778/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-25 11:18:17 +0000