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path: root/drivers/gpu
AgeCommit message (Expand)AuthorLines
2017-06-08drm/i915/gvt: Make mmio_attribute as type u8 to save 1.5MB memoryChangbin Du-3/+4
2017-06-08drm/i915/gvt: Cleanup struct intel_gvt_mmio_infoChangbin Du-16/+3
2017-06-08drm/i915/gvt: Optimize MMIO register handling for some large MMIO blocksChangbin Du-114/+147
2017-06-08drm/i915/gvt: add gtt_invalidate API to flush the GTT TLBChuanxiao Dong-6/+9
2017-06-08drm/i915/gvt: Add runtime_pm get/put to proctect MMIO accessingChuanxiao Dong-0/+22
2017-06-08drm/i915/gvt: remove redundant -WallNick Desaulniers-1/+1
2017-06-08drm/i915/gvt: Legacy HSW related MMIO handler clean upfred gao-25/+15
2017-06-08drm/i915/gvt: Trigger scheduling after context completePing Gao-0/+4
2017-06-08drm/i915/gvt: Support event based schedulingPing Gao-6/+18
2017-06-08drm/i915/gvt: Delete gvt_dbg_cmd() in cmd_parser_exec()Xiong Zhang-6/+0
2017-06-08drm/i915/gvt: Change flood gvt dmesg into traceXiong Zhang-18/+119
2017-06-08drm/i915/gvt: clean up the unused last_ctx_submit_time of struct intel_vgpuChangbin Du-2/+0
2017-06-08drm/i915/gvt: add RING_INSTDONE and SC_INSTDONE mmio handler in GVT-gWeinan Li-7/+15
2017-06-08drm/i915/gvt: implement per-vm mmio switching optimizationChangbin Du-12/+80
2017-06-08drm/i915/gvt: refactor function intel_vgpu_submit_execlistChangbin Du-33/+23
2017-06-08drm/i915/gvt: rewrite the trace gvt:gvt_command using trace style approachChangbin Du-96/+32
2017-06-07drm/amdgpu/gfx: consolidate mqd buffer setup codeAlex Deucher-132/+74
2017-06-07drm/amdgpu/gfx: move mec parameter setup into sw_initAlex Deucher-47/+47
2017-06-07drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.cAlex Deucher-211/+122
2017-06-07drm/amdgpu: move mec queue helpers to amdgpu_gfx.hAlex Deucher-39/+40
2017-06-07drm/amdgpu/gfx9: remove spurious line in kiq setupAlex Deucher-1/+0
2017-06-07drm/amdgpu/gfx8: whitespace changeAlex Deucher-1/+2
2017-06-07drm/amdgpu/gfx9: Raven has two MECsAlex Deucher-0/+1
2017-06-07drm/amdgpu: move gfx_v*_0_compute_queue_acquire to common codeAlex Deucher-114/+42
2017-06-07drm/amdgpu: fix mec queue policy on single MEC asicsAlex Deucher-9/+27
2017-06-07drm/pl111: Fix offset calculation for the primary plane.Eric Anholt-13/+2
2017-06-07drm/atmel-hlcdc: Fix panel registrationBoris Brezillon-2/+0
2017-06-07drm/bridge: Build the panel wrapper in drm_kms_helperMaarten Lankhorst-1/+1
2017-06-07drm/i915: Unify GT* and GT3 definitionsRodrigo Vivi-30/+27
2017-06-07drm/i915: Remove unnecessary PORT3 definition.Rodrigo Vivi-4/+2
2017-06-07drm/i915/cnl: Also need power well sanitize.Rodrigo Vivi-2/+1
2017-06-07drm/i915/cnl: Add power wells for CNLVille Syrjälä-4/+137
2017-06-07drm/i915/gen10: Set value of Indirect Context Offset for gen10Michel Thierry-0/+5
2017-06-07drm/i915/cnl: Cannonlake has same MOCS table than Skylake.Rodrigo Vivi-1/+1
2017-06-07drm/i915/cnl: Configure EU slice power gating.Rodrigo Vivi-4/+3
2017-06-07drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipeJames Irwin-1/+1
2017-06-07drm/i915/cnl: add IS_CNL_REVID macroPaulo Zanoni-0/+6
2017-06-07drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.Rodrigo Vivi-0/+1
2017-06-07drm/i915/cnl: Cannonlake uses CNP PCH.Rodrigo Vivi-0/+4
2017-06-07drm/i915/cnl: Introduce Cannonlake platform defition.Rodrigo Vivi-0/+12
2017-06-07drm/meson: Fix driver bind when only CVBS is availableNeil Armstrong-5/+15
2017-06-07drm/i915: Fix 90/270 rotated coordinates for FBCVille Syrjälä-12/+7
2017-06-07drm/i915: Restore has_fbc=1 for ILK-MVille Syrjälä-1/+1
2017-06-07drm/i915: Workaround VLV/CHV DSI scanline counter hardware failVille Syrjälä-0/+30
2017-06-07drm/i915: Fix logical inversion for gen4 quirkingChris Wilson-1/+1
2017-06-07drm/i915: Guard against i915_ggtt_disable_guc() being invoked unconditionallyChris Wilson-1/+2
2017-06-07drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2.Maarten Lankhorst-0/+9
2017-06-07drm/i915: Prevent the system suspend complete optimizationImre Deak-0/+9
2017-06-07drm/i915/psr: disable psr2 for resolution greater than 32X20Nagaraju, Vathsala-2/+3
2017-06-07drm/i915: Hold a wakeref for probing the ring registersChris Wilson-1/+17
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