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2025-07-29Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' ↵Stephen Boyd10-240/+210
and 'clk-amlogic' into clk-next * clk-renesas: (42 commits) clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs clk: renesas: r9a09g057: Add XSPI clock/reset clk: renesas: r9a09g056: Add XSPI clock/reset clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting clk: renesas: r9a09g057: Add support for xspi mux and divider clk: renesas: r9a09g056: Add support for xspi mux and divider clk: renesas: r9a09g077: Add RIIC module clocks clk: renesas: r9a09g077: Add PLL2 and SDHI clock support clk: renesas: rzv2h: Drop redundant base pointer from pll_clk clk: renesas: r9a09g057: Add entries for the RSPIs dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock clk: renesas: rzv2h: Add missing include file clk: renesas: rzv2h: Use devm_kmemdup_array() clk: renesas: Add CPG/MSSR support to RZ/N2H SoC clk: renesas: r9a09g077: Add PCLKL core clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID ... * clk-samsung: clk: samsung: exynosautov920: add block hsi2 clock support dt-bindings: clock: exynosautov920: add hsi2 clock definitions dt-bindings: clock: exynosautov920: sort clock definitions clk: samsung: exynos850: fix a comment clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD * clk-spacemit: clk: spacemit: ccu_pll: fix error return value in recalc_rate callback reset: spacemit: add support for SpacemiT CCU resets clk: spacemit: mark K1 pll1_d8 as critical clk: spacemit: define three reset-only CCUs clk: spacemit: set up reset auxiliary devices soc: spacemit: create a header for clock/reset registers dt-bindings: soc: spacemit: define spacemit,k1-ccu resets * clk-allwinner: clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate() clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll clk: sunxi-ng: v3s: Fix de clock definition clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset * clk-amlogic: clk: amlogic: s4: remove unused data clk: amlogic: drop clk_regmap tables clk: amlogic: get regmap with clk_regmap_init clk: amlogic: remove unnecessary headers clk: amlogic: axg-audio: use the auxiliary reset driver
2025-07-29Merge tag 'soc-newsoc-6.17' of ↵Linus Torvalds1-0/+279
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new SoC support from Arnd Bergmann: "These five newly supported chips come with both devicetree descriptions and the changes to wire them up to the build system for easier bisection. The chips in question are: - Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell in the product line that started with the Digital StrongARM SA1100 based PDAs and continued with the Intel PXA2xx that dominated early smartphones. This one only made it only into a few products before the entire product line was cut in 2015. - The QiLai SoC is made by RISC-V core designer Andes Technologies and is in the 'Voyager' reference board in MicroATX form factor. It uses four in-order AX45MP cores, which is the midrange product from Andes. - CIX P1 is one of the few Arm chips designed for small workstations, and this one uses 12 Cortex-A720/A520 cores, making it also one of the only ARMv9.2 machines that one can but at the moment. - Axiado AX3000 is an embedded chip with relative small Cortex-A53 CPU cores described as a "Trusted Control/Compute Unit" that can be used as a BMC in servers. In addition to the usual I/O, this one comes with 10GBit ethernet and and a 4TOPS NPU. - Sophgo SG2000 is an embedded chip that comes with both RISC-V and Arm cores that can run Linux. This was already supported for RISC-V but now it also works on Arm One more chip, the Black Sesame C1200 did not make it in tirm for the merge window" * tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) arm64: defconfig: Enable rudimentary Sophgo SG2000 support arm64: Add SOPHGO SOC family Kconfig support arm64: dts: sophgo: Add Duo Module 01 Evaluation Board arm64: dts: sophgo: Add Duo Module 01 arm64: dts: sophgo: Add initial SG2000 SoC device tree MAINTAINERS: Add entry for Axiado arm64: defconfig: enable the Axiado family arm64: dts: axiado: Add initial support for AX3000 SoC and eval board arm64: add Axiado SoC family dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller dt-bindings: serial: cdns: add Axiado AX3000 UART controller dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant dt-bindings: gpio: cdns: convert to YAML dt-bindings: arm: axiado: add AX3000 EVK compatible strings dt-bindings: vendor-prefixes: Add Axiado Corporation MAINTAINERS: Add CIX SoC maintainer entry arm64: dts: cix: Add sky1 base dts initial support dt-bindings: clock: cix: Add CIX sky1 scmi clock id arm64: defconfig: Enable CIX SoC mailbox: add CIX mailbox driver ...
2025-07-29Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds7-0/+861
Pull SoC devicetree updates from Arnd Bergmann: "There are a few new variants of existing chips: - mt6572 is an older mobile phone chip from mediatek that was extremely popular a decade ago but never got upstreamed until now - exynos2200 is a recent high-end mobile phone chip used in a few Samsung phones like the Galaxy S22 - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M (R8A779H0) and used in automotive applications - Tegra264 is a new chip from NVIDIA, but support is fairly minimal for now, and not much information is public about it There are five more chips in a separate branch, as those are new chip families that I merged along with the necessary infrastructure. New board support is not that exciting, with a total of 33 newly added machines here: - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo sg2042 - Six 32-bit industrial boards based on stm32, imx6 and am33 chips, plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and imx95 - Two newly added ASPEED BMC based motherboards, and one that got removed - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit msm8976 SoCs - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1 - A set-top box based on Amlogic meson-gxm Updates for existing machines are spread over all the above families. One notable change here is support for the RP1 I/O chip used in Raspberry Pi 5" * tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ...
2025-07-22Merge tag 'qcom-arm64-for-6.17' of ↵Arnd Bergmann2-0/+191
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm64 DeviceTree updates for v6.17 79b896e7da7e arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree 6516961352a1 arm64: dts: qcom: Add support for X1-based Asus Zenbook A14 The DB410c D3 camera mezzanine is converted to an overlay. On MSM8976 SDC2 pinctrl definitions are introduced and BLSP DMA controller is marked to be managed by another entity. Add camera subsystem on the QCM2290 platform. Add and enable remoteproc and related devices on QCS615. Add and enable Video encoder/decoder on QCS8300 and SA8775P. Also on SA8775P add CPU OPP tables for scaling DDR/L3 bandwidth based on CPU frequency, add L3 interconnect definitions, DSI and video encoder/decoder support. Enable the SLPI remoteproc on SDM850-based Lenovo Yoga C630. On SM6350, add the video clock controller, APR and some audio related services. Describe the camera subsystem on SM8550 and add Iris video encoder/decoder node for SM8650. On SM8750 introduce UFS and Soundwire support, enable these and describe the sound hardware on MTP and QRD. Add camera clock controller on SC8180X. On X Elite, for the Dell XPS13, add WiFi and Bluetooth pwrseq and enable the fingerprint sensor. For HP Omnibook X14 USB1 SS1 SBU mux and do some misc cleanup. Replace the thermal zones inherited from X Elite with X Plus-specific ones. Add missing interrupts and clean up unrelated clocks for PCIe controllers across a variety of platforms. * tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (67 commits) arm64: dts: qcom: sm8150: Drop unrelated clocks from PCIe hosts arm64: dts: qcom: sc8180x: Drop unrelated clocks from PCIe hosts arm64: dts: qcom: x1-asus-zenbook: support sound arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodes arm64: dts: qcom: sm6115: add debug UART pins arm64: dts: qcom: sm8650: add iris DT node arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree arm64: dts: qcom: msm8976: Add sdc2 GPIOs dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely arm64: dts: qcom: sa8775p: Correct the interrupt for remoteproc arm64: dts: qcom: sm8550: Add support for camss arm64: dts: qcom: qcs615: disable the CTI device of the camera block arm64: dts: qcom: qcs615-ride: enable remoteprocs arm64: dts: qcom: qcs615: add ADSP and CDSP nodes arm64: dts: qcom: qcs615: Add IMEM and PIL info region arm64: dts: qcom: qcs615: Add mproc node for SEMP2P arm64: dts: qcom: Add support for X1-based Asus Zenbook A14 arm64: dts: qcom: sc7180: Expand IMEM region arm64: dts: qcom: sdm845: Expand IMEM region ... Link: https://lore.kernel.org/r/20250716031059.76348-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-22Merge tag 'spacemit-dt-for-6.17-1' of https://github.com/spacemit-com/linux ↵Arnd Bergmann1-0/+141
into soc/dt RISC-V SpacemiT DT changes for 6.17 - Add DMA translation buses - Add PWM support - Add Reset support - Add eMMC node * tag 'spacemit-dt-for-6.17-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: Move eMMC under storage-bus for K1 riscv: dts: spacemit: Move UARTs under dma-bus for K1 riscv: dts: spacemit: Add DMA translation buses for K1 riscv: dts: spacemit: add pwm14_1 pinctrl setting riscv: dts: spacemit: add PWM support for K1 SoC riscv: dts: spacemit: add reset support for the K1 SoC dt-bindings: soc: spacemit: define spacemit,k1-ccu resets riscv: dts: spacemit: enable eMMC for K1 SoC Link: https://lore.kernel.org/r/20250715014214-GYA540030@gentoo Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-22Merge tag 'tegra-for-6.17-dt-bindings' of ↵Arnd Bergmann1-0/+466
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt dt-bindings: Updates for v6.17-rc1 Add Tegra264 compatible strings for some core components and extend bindings where necessary to accomodate the new hardware generation. Also document some new platforms, for both old and new chips. * tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: arm: tegra: Add Asus Portable AiO P1801-T dt-bindings: arm: tegra: Add Asus VivoTab RT TF600T dt-bindings: Add Tegra264 clock and reset definitions dt-bindings: tegra: Document P3971-0089+P3834-0008 Platform dt-bindings: rtc: tegra: Document Tegra264 RTC dt-bindings: dma: Add Tegra264 compatible string dt-bindings: misc: Document Tegra264 APBMISC compatible dt-bindings: firmware: Document Tegra264 BPMP dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts dt-bindings: tegra: pmc: Add Tegra264 compatible dt-bindings: memory: tegra: Add Tegra264 support Link: https://lore.kernel.org/r/20250711220943.2389322-3-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge branch 'newsoc/cix-p1' into soc/newsocArnd Bergmann1-0/+279
Patches from Peter Chen <peter.chen@cixtech.com>: Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC. Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief introduction for SoC and related boards at: https://radxa.com/products/orion/o6#overview Currently, to run upstream kernel at Orion O6 board, you need to use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs. https://docs.radxa.com/en/orion/o6/bios/install-bios In this series, we add initial SoC and board support for Kernel building. Since mailbox is used for SCMI clock communication, mailbox driver is added in this series for the minimum SoC support. Patch 1-2: add dt-binding doc for CIX and its sky1 SoC Patch 3: add Arm64 build support Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol. Patch 6: add Arm64 defconfig support Patch 7-8: add initial dts support for SoC and Orion O6 board Patch 9: add MAINTAINERS entry * newsoc/cix-p1: MAINTAINERS: Add CIX SoC maintainer entry arm64: dts: cix: Add sky1 base dts initial support dt-bindings: clock: cix: Add CIX sky1 scmi clock id arm64: defconfig: Enable CIX SoC mailbox: add CIX mailbox driver dt-bindings: mailbox: add cix,sky1-mbox arm64: Kconfig: add ARCH_CIX for cix silicons dt-bindings: arm: add CIX P1 (SKY1) SoC dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21dt-bindings: clock: cix: Add CIX sky1 scmi clock idGary Yang1-0/+279
Add device tree bindings for the scmi clock id on Cix sky1 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Gary Yang <gary.yang@cixtech.com> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21Merge tag 'renesas-dts-for-v6.17-tag2' of ↵Arnd Bergmann2-0/+2
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.17 (take two) - Add support for the Renesas Gray Hawk Single board with R-Car V4M-7 (R8A779H2), - Add eMMC and microSD expansion board support for the RZ/V2H and RZ/V2N EVK development boards, - Add GPIO keys and Ethernet support for the RZ/G3E SoM and SMARC Carrier-II EVK development board, - Add QSPI FLASH support for the RZ/V2H and RZ/V2N SoCs and their EVK development boards, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH arm64: dts: renesas: r9a09g057: Add XSPI node arm64: dts: renesas: r9a09g056: Add XSPI node arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1 arm64: dts: renesas: r8a779g3-sparrow-hawk-fan-pwm: Add missing install target arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support arm64: dts: renesas: Add Renesas R8A779H2 SoC support arm64: dts: renesas: Factor out Gray Hawk Single board support dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock Link: https://lore.kernel.org/r/cover.1752090401.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSRPeng Fan1-0/+13
Add i.MX94 LVDS/DISPLAY CSR compatible string. Add clock index for the two CSRs. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250707-imx95-blk-ctl-7-1-v3-1-c1b676ec13be@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Video Clock ControllerLuca Weiss1-0/+36
Add bindings documentation for the Milos (e.g. SM7635) Video Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-10-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos GPU Clock ControllerLuca Weiss1-0/+56
Add bindings documentation for the Milos (e.g. SM7635) Graphics Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-8-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Display Clock ControllerLuca Weiss1-0/+61
Add bindings documentation for the Milos (e.g. SM7635) Display Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Camera Clock ControllerLuca Weiss1-0/+131
Add bindings documentation for the Milos (e.g. SM7635) Camera Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-4-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom: document the Milos Global Clock ControllerLuca Weiss1-0/+210
Add bindings documentation for the Milos (e.g. SM7635) Global Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-2-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resetsStephan Gerhold1-0/+2
Add the missing video resets that are needed for the iris video codec. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-4-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Video clock controllerTaniya Das1-0/+30
Add DT bindings for the Video clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controllerTaniya Das1-0/+39
Add DT bindings for the Graphics clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Display clock controllerTaniya Das1-0/+52
Add DT bindings for the Display clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16dt-bindings: clock: Add Qualcomm QCS615 Camera clock controllerTaniya Das1-0/+110
Add DT bindings for the Camera clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-16Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into ↵Bjorn Andersson1-0/+16
clk-for-6.17 Merge the IPQ5018 CMN PLL binding through a topic branch, to allow merging the clock defines into DeviceTree branch as well.
2025-07-16dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoCGeorge Moussalem1-0/+16
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-07-11dt-bindings: Add Tegra264 clock and reset definitionsThierry Reding1-0/+466
The BPMP firmware on Tegra264 defines a set of IDs for clock and reset resources. These are not enumerations but provided by hardware, and 0 is a reserved value, hence the numbering starts at 1. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-07-10dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2Jacky Chou1-0/+2
Add ASPEED_RESET_MAC1 and ASPEED_RESET_MAC2 reset definitions to the ast2600-clock binding header. These are required for proper reset control of the MAC1 and MAC2 ethernet controllers on the AST2600 SoC. Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://patch.msgid.link/20250709070809.2560688-3-jacky_chou@aspeedtech.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-07-03clk: sunxi-ng: v3s: Fix CSI SCLK clock namePaul Kocialkowski1-1/+1
The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the documentation. Fix the name in the driver, header and device-tree. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Reviewed-By: Icenowy Zheng <uwu@icenowy.me> Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-03dt-bindings: soc: spacemit: define spacemit,k1-ccu resetsAlex Elder1-0/+141
There are additional SpacemiT syscon CCUs whose registers control both clocks and resets: RCPU, RCPU2, and APBC2. Unlike those defined previously, these will (initially) support only resets. They do not incorporate power domain functionality. Previously the clock properties were required for all compatible nodes. Make that requirement only apply to the three existing CCUs (APBC, APMU, and MPMU), so that the new reset-only CCUs can go without specifying them. Define the index values for resets associated with all SpacemiT K1 syscon nodes, including those with clocks already defined, as well as the new ones (without clocks). Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250702113709.291748-2-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-07-02Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17Geert Uytterhoeven2-0/+2
Renesas RZ/V2N and RZ/V2H XSPI Clock DT Binding Definitions Expanded Serial Peripheral Interface (XSPI) clock DT binding definitions for the Renesas RZ/V2N (R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared by driver and DT source files.
2025-07-02Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17Geert Uytterhoeven2-0/+2
Renesas RZ/T2H and RZ/N2H SDHI Clock DT Binding Definitions SDHI clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
2025-07-02dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock IDLad Prabhakar2-0/+2
Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as a core clock for the SDHI IP and operates at 800MHz. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clockLad Prabhakar2-0/+2
Add XSPI core clock definitions to the clock bindings for the Renesas R9A09G056 and R9A09G057 SoCs. These clocks IDs are used to support XSPI interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250627204237.214635-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17Geert Uytterhoeven1-0/+28
Renesas RZ/N2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087) SoC, shared by driver and DT source files.
2025-06-19Merge tag 'renesas-r9a09g077-dt-binding-defs-tag2' into renesas-clk-for-v6.17Geert Uytterhoeven1-0/+1
Renesas RZ/T2H PCLKL Clock DT Binding Definition Peripheral Module Clock L (PCLKL) DT binding definition for the Renesas RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
2025-06-19dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H supportLad Prabhakar1-0/+28
Document support for Module Standby and Software Reset found on the Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP is similar to that found on the RZ/T2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock IDLad Prabhakar1-0/+1
Add the Peripheral Module Clock L (PCLKL) core clock ID for the RZ/T2H (R9A09G077) SoC. This clock is used by peripherals such as IIC, WDT, and others. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617155757.149597-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-18Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' ↵Bjorn Andersson1-0/+22
into clk-for-6.17 Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the newly introduced clock constants to be made available to the DeviceTree branch as well.
2025-06-18dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoCLuo Jie1-0/+22
The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference input clock. The output clocks are the same as IPQ9574 SoC, except for the clock rate of output clocks to PPE and NSS. Also, add the new header file to export the CMN PLL output clock specifiers for IPQ5424 SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-12dt-bindings: clock: exynosautov920: add hsi2 clock definitionsRaghav Sharma1-0/+9
Add device tree clock binding definitions for CMU_HSI2 Signed-off-by: Raghav Sharma <raghav.s@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250529112640.1646740-3-raghav.s@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-10dt-bindings: clock: Add Qualcomm SC8180X Camera clock controllerSatya Priya Kakitapalli1-0/+181
Add device tree bindings for the camera clock controller on Qualcomm SC8180X platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10dt-bindings: clock: qcom: Add missing bindings on gcc-sc8180xSatya Priya Kakitapalli1-0/+10
The multi-media AHB clocks are needed to create HW dependency in the multimedia CC dt blocks and avoid any issues. They were not defined in the initial bindings. Add all the missing clock bindings for gcc-sc8180x. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-1-8fb1d3265f52@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-06-10dt-bindings: clock: rzg2l: Drop power domain IDsClaudiu Beznea4-240/+0
Since the configuration order between the individual MSTOP and CLKON bits cannot be preserved with the power domain abstraction, drop the power domain IDs. The corresponding code has also been removed. Currently, there are no device tree users for these IDs. Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250527112403.1254122-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17Geert Uytterhoeven1-0/+27
Renesas RZ/T2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
2025-06-09dt-bindings: clock: Add RaspberryPi RP1 clock bindingsAndrea della Porta1-0/+61
Add device tree bindings for the clock generator found in RP1 multi function device, and relative entries in MAINTAINERS file. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-05-31Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-2/+2
Pull SoC devicetree updates from Arnd Bergmann: "There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straight reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets" * tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits) MAINTAINERS, mailmap: update Sven Peter's email address arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency arm64: dts: nuvoton: Add pinctrl ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings arm64: dts: blaize-blzp1600: Enable GPIO support dt-bindings: clock: socfpga: convert to yaml arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes arm64: dts: mt6359: Rename RTC node to match binding expectations arm64: dts: mt8365-evk: Add goodix touchscreen support arm64: dts: mediatek: mt8188: Add missing #reset-cells property arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board ...
2025-05-29Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' ↵Stephen Boyd4-0/+44
into clk-next * clk-amlogic: clk: meson: Do not enable by default during compile testing clk: meson-g12a: add missing fclk_div2 to spicc * clk-allwinner: clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support dt-bindings: allwinner: add H616 DE33 clock binding clk: sunxi-ng: h616: Add LVDS reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset clk: sunxi: Do not enable by default during compile testing clk: sunxi-ng: Do not enable by default during compile testing * clk-rockchip: clk: rockchip: rk3528: add slab.h header include clk: rockchip: rk3576: add missing slab.h include clk: rockchip: rename gate-grf clk file clk: rockchip: rename branch_muxgrf to branch_grf_mux clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks clk: rockchip: rk3036: mark ddrphy as critical clk: rockchip: rk3036: fix implementation of usb480m clock mux dt-bindings: clock: rk3036: add SCLK_USB480M clock-id clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region clk: rockchip: Support MMC clocks in GRF region dt-bindings: clock: Add GRF clock definition for RK3528 clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576 clk: rockchip: introduce GRF gates clk: rockchip: introduce auxiliary GRFs dt-bindings: clock: rk3576: add IOC gated clocks clk: rockchip: rk3568: Add PLL rate for 33.3MHz clk: rockchip: Drop empty init callback for rk3588 PLL type clk: rockchip: rk3588: Add PLL rate for 1500 MHz * clk-qcom: clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 clk: qcom: rpmh: make clkaN optional clk: qcom: Add support for Camera Clock Controller on QCS8300 clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz dt-bindings: clock: add SM6350 QCOM video clock bindings clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: Fix missing error check for dev_pm_domain_attach()
2025-05-29Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' ↵Stephen Boyd4-0/+265
into clk-next * clk-socfpga: clk: socfpga: stratix10: Optimize local variables clk: socfpga: clk-pll: Optimize local variables * clk-sophgo: clk: sophgo: Add clock controller support for SG2044 SoC clk: sophgo: Add PLL clock controller support for SG2044 SoC dt-bindings: clock: sophgo: add clock controller for SG2044 dt-bindings: soc: sophgo: Add SG2044 top syscon device clk: sophgo: Add support for newly added precise compatible dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC * clk-thead: clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC dt-bindings: clock: thead: Add TH1520 VO clock controller * clk-samsung: clk: samsung: correct clock summary for hsi1 block clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition clk: samsung: exynosautov920: add cpucl1/2 clock support dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl0 clock support dt-bindings: clock: exynosautov920: add cpucl0 clock definitions clk: samsung: Use samsung CCF common function
2025-05-29Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and ↵Stephen Boyd4-0/+278
'clk-cleanup' into clk-next * clk-bindings: dt-bindings: clock: Drop st,stm32h7-rcc.txt dt-bindings: clock: convert bcm2835-aux-clock to yaml dt-bindings: clock: Drop maxim,max77686.txt dt-bindings: clock: convert vf610-clock.txt to yaml format * clk-renesas: (26 commits) clk: renesas: r9a09g047: Add XSPI clock/reset clk: renesas: r9a09g047: Add support for xspi mux and divider dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks clk: renesas: Use str_on_off() helper clk: renesas: r9a09g057: Add clock and reset entries for USB2 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h: Support static dividers without RMW clk: renesas: rzv2h: Add macro for defining static dividers clk: renesas: rzv2h: Add support for static mux clocks clk: renesas: r9a09g047: Add clock and reset entries for GE3D clk: renesas: rzv2h: Fix a typo clk: renesas: rzv2h: Add support for RZ/V2N SoC clk: renesas: rzv2h: Sort compatible list based on SoC part number dt-bindings: pinctrl: renesas: Document RZ/V2N SoC dt-bindings: clock: renesas: Document RZ/V2N SoC CPG dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert() ... * clk-spacemit: clk: spacemit: k1: Add TWSI8 bus and function clocks clk: spacemit: Add clock support for SpacemiT K1 SoC dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon * clk-cleanup: clk: test: Forward-declare struct of_phandle_args in kunit/clk.h clk: davinci: Use of_get_available_child_by_name() clk: bcm: rpi: Add NULL check in raspberrypi_clk_register() clk: bcm: rpi: Drop module alias clk: bcm: kona: Remove unused scaled_div_build
2025-05-26dt-bindings: clock: renesas,cpg-mssr: Document RZ/T2H supportThierry Bultel1-0/+27
Document RZ/T2H (a.k.a. r9a09g077) cpg-mssr (Clock Pulse Generator) binding. Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250515141828.43444-3-thierry.bultel.yh@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-22Merge tag 'v6.16-rockchip-dts64-2' of ↵Arnd Bergmann2-0/+16
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New SoC the RK3562 (4xA53, Mali-G52) with one evaluation board. New boards: - Cobra and PP1516 from Theobroma-Systems (build around the PX30) - Radxa Rock 5B+ (rk3588) - Rockchip RK3399 industrial eval board New peripherals: - GMAC + SDMMC/SDIO on rk3528 - SAI + HDMI-audio on rk3576 Interesting general updates: - move rk3528 i2c + uart aliases as requested - rk3568 PCIe3 MSI to use GIC ITS - update deprecated dwmac reset properties on some px30 boards - updates for cypress usb hubs on some Theobroma boards Binding taken with Greg's blessing https://lore.kernel.org/all/2025051550-polish-prude-ed56@gregkh/ * tag 'v6.16-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (35 commits) arm64: dts: rockchip: Improve LED config for NanoPi R5S arm64: dts: rockchip: add px30-pp1516 base dtsi and board variants dt-bindings: arm: rockchip: add PX30-PP1516 boards from Theobroma Systems arm64: dts: rockchip: add px30-cobra base dtsi and board variants dt-bindings: arm: rockchip: add PX30-Cobra boards from Theobroma Systems arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneck arm64: dts: rockchip: add basic mdio node to px30 arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma with Haikou arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma arm64: dts: rockchip: fix internal USB hub instability on RK3399 Puma dt-bindings: usb: cypress,hx3: Add support for all variants arm64: dts: rockchip: move rk3528 i2c+uart aliases to board files arm64: dts: rockchip: drop wrong spdif clock from edp1 on rk3588 arm64: dts: rockchip: Add RK3562 evb2 devicetree arm64: dts: rockchip: add core dtsi for RK3562 SoC dt-bindings: arm: rockchip: Add rk3562 evb2 board dt-bindings: soc: rockchip: Add rk3562 syscon compatibles dt-bindings: rockchip: pmu: Add rk3562 compatible arm64: dts: rockchip: Enable Ethernet controller on Radxa E20C arm64: dts: rockchip: Add GMAC nodes for RK3528 ... Link: https://lore.kernel.org/r/3998939.iIbC2pHGDl@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-21Merge tag 'stm32-dt-for-v6.16-1' of ↵Arnd Bergmann1-2/+2
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.16, round 1 Highlights: ---------- - MCU: - Add low power timer on STM32F746 - Add STM32H747 High end MCU support. It embeds: - dual-core (Cortex-M7 + Cortex-M4) - up to 2 Mbytes flash - 1 Mbyte of internal RAM - Add STM32H747i-disco board support. Detailed information can be found at: https://www.st.com/en/evaluation-tools/stm32h747i-disco.html - MPU: - STM32MP13: - Add VREFINT calibration support based on ADC. - STMP32MP15: - Add new Ultratronik Fly board support: - based on STM32MP157C SoC - 1GB of DDR3 - Several connections are available on this boards: 2*USB2.0, 1*USB2.0 MiniUSB, Debug UART, 1*UART, 1*USART, SDcard, RJ45, ... - STM32MP25: - Add OCTOSPI support on STM32MP25 SoCs - Add SPI NOR flash support on STM32MP257F-EV1 connected to OSPI1 - Add Low power timer TIMER (LPTIM) on STM32MP25 SoCs and use LPTIM3 as low power broadcast timer on STM32MP257F-EV1. * tag 'stm32-dt-for-v6.16-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (22 commits) ARM: dts: stm32: add initial support for stm32mp157-ultra-fly-sbc board MAINTAINERS: Add entry for ULTRATRONIK BOARD SUPPORT dt-bindings: arm: stm32: Document Ultratronik's Fly board DT binding dt-bindings: vendor-prefixes: Add Ultratronik arm64: dts: st: use lptimer3 as tick broadcast source on stm32mp257f-ev1 arm64: dts: st: add low-power timer nodes on stm32mp251 arm64: defconfig: enable STM32 LP timer clockevent driver arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 board arm64: dts: st: Add ospi port1 pinctrl entries in stm32mp25-pinctrl.dtsi arm64: dts: st: Add OMM node on stm32mp251 ARM: dts: stm32: support STM32h747i-disco board ARM: dts: stm32: add an extra pin map for USART1 on stm32h743 ARM: dts: stm32: add pin map for UART8 controller on stm32h743 ARM: dts: stm32: add uart8 node for stm32h743 MCU dt-bindings: clock: stm32h7: rename USART{7,8}_CK to UART{7,8}_CK ARM: stm32: add a new SoC - STM32H747 dt-bindings: arm: stm32: add compatible for stm32h747i-disco board ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phandles ARM: dts: st: stm32: Align wifi node name with bindings ARM: dts: stm32: add low power timer on STM32F746 ... Link: https://lore.kernel.org/r/2f101efb-6d58-48d8-983a-57e30a34827c@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-21Merge tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux ↵Arnd Bergmann1-0/+247
into soc/dt RISC-V SpacemiT DT changes for 6.16 - Add clock driver, fix for pinctrl/uart - Add gpio support, enable LED heartbeat * tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: add gpio LED for system heartbeat riscv: dts: spacemit: add gpio support for K1 SoC riscv: dts: spacemit: Acquire clocks for UART riscv: dts: spacemit: Acquire clocks for pinctrl riscv: dts: spacemit: Add clock tree for SpacemiT K1 dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon Link: https://lore.kernel.org/r/20250514044841-GYA524674@gentoo Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.1) at 2026-01-04 14:21:21 +0000