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2025-09-15tee: add close_context to TEE driver operationAmirreza Zarrabi1-2/+48
The tee_context can be used to manage TEE user resources, including those allocated by the driver for the TEE on behalf of the user. The release() callback is invoked only when all resources, such as tee_shm, are released and there are no references to the tee_context. When a user closes the device file, the driver should notify the TEE to release any resources it may hold and drop the context references. To achieve this, a close_context() callback is introduced to initiate resource release in the TEE driver when the device file is closed. Relocate teedev_ctx_get, teedev_ctx_put, tee_device_get, and tee_device_get functions to tee_core.h to make them accessible outside the TEE subsystem. Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Harshal Dev <quic_hdev@quicinc.com> Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15Merge branch ↵Jens Wiklander2-0/+21
'20250911-qcom-tee-using-tee-ss-without-mem-obj-v12-2-17f07a942b8d@oss.qualcomm.com' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux firmware: qcom: tzmem: export shm_bridge create/delete firmware: qcom: scm: add support for object invocation Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15io_uring/uring_cmd: correct signature for io_uring_mshot_cmd_post_cqe()Jens Axboe1-1/+1
The !CONFIG_IO_URING signature is wrong, fix that up. The non stub signature got updated for the io_br_sel changes that happened before this patch went in, but the stub one did not. Fixes: 620a50c92700 ("io_uring: uring_cmd: add multishot support") Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-09-15EDAC: Add a driver for the AMD Versal NET DDR controllerShubhrajyoti Datta1-0/+28
Add a driver for the AMD Versal NET DDR memory controller which supports single bit error correction, double bit error detection and other system errors from various IP subsystems (e.g., RPU, NOCs, HNICX, PL). The driver listens for notifications from the NMC (Network management controller) using RPMsg (Remote Processor Messaging). The channel used for communicating to RPMsg is named "error_edac". Upon receipt of a notification, the driver sends a RAS event trace. [ bp: - Fixup title - Rewrite commit message - Fixup Kconfig text - Zap unused defines and align them - Simplify rpmsg_cb() considerably - Drop silly double-brackets in conditionals - Use proper void * type in mcdi_request() - Do not clear chinfo in rpmsg_probe() unnecessarily - Fix indentation - Do a proper err unwind path in init_versalnet() - Redo the error unwind path in mc_probe() properly - Fix the ordering in mc_remove() ] Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/20250908115649.22903-1-shubhrajyoti.datta@amd.com Link: https://lore.kernel.org/r/20250703173105.GLaGa-WQCESDNsqygm@fat_crate.local
2025-09-15Merge tag 'scmi-updates-6.18' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers Arm SCMI updates/fixes for v6.18 These SCMI changes bring a mix of improvements, fixes, and cleanups: 1. Device Tree bindings - allow multiple SCMI instances by suffixing node names (Nikunj Kela). 2. Code hardening - constify both scmi_{transport,voltage_proto}_ops so they reside in read-only memory (Christophe JAILLET). 3. VirtIO transport initialization - set DRIVER_OK before SCMI probing to prevent potential stalls; while recent rework removes the practical risk, this ensures correctness (Junnan Wu). 4. Quirk handling - fix a critical bug by preventing writes to string constants, avoiding faults in read-only memory (Johan Hovold). 5. i.MX SCMI MISC protocol - extend support to discover board info, retrieve configuration and build data, and document the new MISC_BOARD_INFO command; all handled gracefully if unsupported (Peng Fan). 6. Logging cleanup - simplify device tree node name logging by using the %pOF format to print full paths (Krzysztof Kozlowski). * tag 'scmi-updates-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: firmware: arm_scmi: Simplify printks with pOF format firmware: arm_scmi: imx: Discover MISC board info from the system manager firmware: arm_scmi: imx: Support retrieving MISC protocol configuration info firmware: arm_scmi: imx: Discover MISC build info from the system manager firmware: arm_scmi: imx: Add documentation for MISC_BOARD_INFO firmware: arm_scmi: quirk: Prevent writes to string constants firmware: arm_scmi: Fix function name typo in scmi_perf_proto_ops struct firmware: arm_scmi: Mark VirtIO ready before registering scmi_virtio_driver firmware: arm_scmi: Constify struct scmi_transport_ops firmware: arm_scmi: Constify struct scmi_voltage_proto_ops dt-bindings: firmware: arm,scmi: Allow multiple instances Link: https://lore.kernel.org/r/20250915101341.2987516-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15cdx: Export Symbols for MCDI RPC and InitializationShubhrajyoti Datta1-0/+7
The cdx_mcdi_init(), cdx_mcdi_process_cmd(), and cdx_mcdi_rpc() functions are needed by the VersalNET EDAC module that interact with the MCDI (Management Controller Direct Interface) framework. These functions facilitate communication between different hardware components by enabling command execution and status management. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Nikhil Agarwal <nikhil.agarwal@amd.com> Link: https://lore.kernel.org/20250908115649.22903-1-shubhrajyoti.datta@amd.com
2025-09-15Merge tag 'tee-prot-dma-buf-for-v6.18' of ↵Arnd Bergmann3-0/+100
git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers TEE protected DMA-bufs for v6.18 - Allocates protected DMA-bufs from a DMA-heap instantiated from the TEE subsystem. - The DMA-heap uses a protected memory pool provided by the backend TEE driver, allowing it to choose how to allocate the protected physical memory. - Three use-cases (Secure Video Playback, Trusted UI, and Secure Video Recording) have been identified so far to serve as examples of what can be expected. - The use-cases have predefined DMA-heap names, "protected,secure-video", "protected,trusted-ui", and "protected,secure-video-record". The backend driver registers protected memory pools for the use-cases it supports. * tag 'tee-prot-dma-buf-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee: optee: smc abi: dynamic protected memory allocation optee: FF-A: dynamic protected memory allocation optee: support protected memory allocation tee: add tee_shm_alloc_dma_mem() tee: new ioctl to a register tee_shm from a dmabuf file descriptor tee: refactor params_from_user() tee: implement protected DMA-heap dma-buf: dma-heap: export declared functions optee: sync secure world ABI headers Link: https://lore.kernel.org/r/20250912101752.GA1453408@rayden Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15fs: rename generic_delete_inode() and generic_drop_inode()Mateusz Guzik1-2/+2
generic_delete_inode() is rather misleading for what the routine is doing. inode_just_drop() should be much clearer. The new naming is inconsistent with generic_drop_inode(), so rename that one as well with inode_ as the suffix. No functional changes. Signed-off-by: Mateusz Guzik <mjguzik@gmail.com> Reviewed-by: Jan Kara <jack@suse.cz> Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-09-15Merge tag 'qcom-drivers-for-6.18' of ↵Arnd Bergmann1-4/+3
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v6.18 Allowlist the uefisec application, to provide UEFI variable access on Dell Inspiron 7441 and Latitude 7455, the Hamoa EVK, and the Lenovo Thinkbook 16. Disable tzmem on the SC7180 platform, as this causes problems with rmtfs. Clean up unused, lingering, parameters in the MDT loader API. Unconditinally clear TCS trigger bit, to avoid false completion IRQs in the RPMh/RSC driver. Fix endianess issue in SMEM driver. Add pd-mapper support for SM8750. * tag 'qcom-drivers-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: firmware: qcom: tzmem: disable sc7180 platform soc: qcom: use devm_kcalloc() for array space allocation dt-bindings: firmware: qcom,scm: Add MSM8937 firmware: qcom: scm: Allow QSEECOM on Dell Inspiron 7441 / Latitude 7455 firmware: qcom: scm: Allow QSEECOM on Lenovo Thinkbook 16 soc: qcom: rpmh-rsc: Unconditionally clear _TRIGGER bit for TCS soc: qcom: pd-mapper: Add SM8750 compatible soc: qcom: icc-bwmon: Fix handling dev_pm_opp_find_bw_*() errors soc: remove unneeded 'fast_io' parameter in regmap_config soc: qcom: smem: Fix endian-unaware access of num_entries dt-bindings: soc: qcom,rpmh-rsc: Remove double colon from description dt-bindings: sram: qcom,imem: Document IPQ5424 compatible firmware: qcom: scm: Allow QSEECOM on HAMOA-IOT-EVK soc: qcom: mdt_loader: Remove unused parameter soc: qcom: mdt_loader: Remove pas id parameter soc: qcom: mdt_loader: Remove unused parameter firmware: qcom: scm: preserve assign_mem() error return value Link: https://lore.kernel.org/r/20250911215017.3020481-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15cdx: Split mcdi.h and reorganize headersShubhrajyoti Datta2-0/+282
Move bitfield.h from the CDX controller directory to include/linux/cdx to make them accessible to other drivers. As part of this refactoring, split mcdi.h into two headers: - mcdi.h: retains interface-level declarations - mcdid.h: contains internal definitions and macros This is in preparation for VersalNET EDAC driver that relies on it. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Nikhil Agarwal <nikhil.agarwal@amd.com> Link: https://lore.kernel.org/20250908115649.22903-1-shubhrajyoti.datta@amd.com
2025-09-15Merge tag 'arm-soc/for-6.18/drivers' of https://github.com/Broadcom/stblinux ↵Arnd Bergmann1-0/+4
into soc/drivers This pull request contains Broadcom SoC drivers updates for 6.18: - Andrea adds the missing MIPI DSI clock defines for the RP1 and then continues to implement the remaining clocks for the RP1 chip (ADC, I2S, Audio in/out, DMA, MIPI, PWM, SDIO, UART, encoder) - Akhilesh fixes a spelling typo in the bcm47xx_sprom driver - Brian converts the RP1 clock driver to use the new determine_rate() API * tag 'arm-soc/for-6.18/drivers' of https://github.com/Broadcom/stblinux: clk: rp1: convert from round_rate() to determine_rate() drivers: firmware: bcm47xx_sprom: fix spelling clk: rp1: Implement remaining clock tree dt-bindings: clock: rp1: Add missing MIPI DSI defines Link: https://lore.kernel.org/r/20250910171910.666401-4-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'reset-for-v6.18' of https://git.pengutronix.de/git/pza/linux into ↵Arnd Bergmann1-0/+7
soc/drivers Reset controller updates for v6.18 * Fix the reset tree git repository link in MAINTAINERS. * Add support for bcm63xx ephy reset control to reset-bcm6345. * Add support for the AST2700 reset controller, as an auxiliary device driver to the corresponding clock controller driver. * Add support for the remaining TH1520 VO subsystem reset controls to reset-th1520. * Drop unnecessary .fast_io setting from MMIO regmap_configs. * tag 'reset-for-v6.18' of https://git.pengutronix.de/git/pza/linux: reset: remove unneeded 'fast_io' parameter in regmap_config reset: th1520: add resets for display pipeline dt-bindings: reset: thead,th1520-reset: add more VOSYS resets reset: aspeed: register AST2700 reset auxiliary bus device reset: bcm6345: add support for bcm63xx ephy control register dt-bindings: reset: add compatible for bcm63xx ephy control MAINTAINERS: Use https:// protocol for Reset Controller Framework tree Link: https://lore.kernel.org/r/20250904154135.2385905-1-p.zabel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge branch ↵Bjorn Andersson2-0/+21
'20250911-qcom-tee-using-tee-ss-without-mem-obj-v12-2-17f07a942b8d@oss.qualcomm.com' into drivers-for-6.18 Merge the addition of support for object invocation into the SCM driver though a topic branch, to enable sharing this with TEE subsystem.
2025-09-15firmware: qcom: scm: add support for object invocationAmirreza Zarrabi1-0/+6
Qualcomm TEE (QTEE) hosts Trusted Applications (TAs) and services in the secure world, accessed via objects. A QTEE client can invoke these objects to request services. Similarly, QTEE can request services from the nonsecure world using objects exported to the secure world. Add low-level primitives to facilitate the invocation of objects hosted in QTEE, as well as those hosted in the nonsecure world. If support for object invocation is available, the qcom_scm allocates a dedicated child platform device. The driver for this device communicates with QTEE using low-level primitives. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Harshal Dev <quic_hdev@quicinc.com> Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250911-qcom-tee-using-tee-ss-without-mem-obj-v12-2-17f07a942b8d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-15firmware: qcom: tzmem: export shm_bridge create/deleteAmirreza Zarrabi1-0/+15
Anyone with access to contiguous physical memory should be able to share memory with QTEE using shm_bridge. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Harshal Dev <quic_hdev@quicinc.com> Reviewed-by: Kuldeep Singh <quic_kuldsing@quicinc.com> Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250911-qcom-tee-using-tee-ss-without-mem-obj-v12-1-17f07a942b8d@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-15Merge tag 'tegra-for-6.18-dt-bindings' of ↵Arnd Bergmann2-1/+15
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt dt-bindings: Changes for v6.18-rc1 Support for the Tegra264 generation of I2C is documented as well as some older Tegra devices, such as the Xiaomi Mi Pad and the ASUS 101 devices. Contained are also some additions to existing bindings for Tegra114 and a fix for the power supply feeding VI/CSI. * tag 'tegra-for-6.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: arm: tegra: Add ASUS TF101G and SL101 dt-bindings: reset: Add Tegra114 CAR header dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101) dt-bindings: clock: tegra30: Add IDs for CSI pad clocks dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C Link: https://lore.kernel.org/r/20250914063927.89981-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'qcom-arm64-for-6.18' of ↵Arnd Bergmann3-0/+13
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm64 DeviceTree updates for v6.18 Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude 7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the Lemans EVK. The SDM845 Cheza development boards are removed, as they are not longer in use. For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO buses are added and the internal GE PHY. IPQ5424 gets CPU frequency scaling and a missing UART. The SA8775P SoC is remaned Lemans, to reduce confusion about the chip name. The IoT memory map introduced and made the default, GDSP FastRPC and GPR nodes are added. Touch keys are enabled on the BQ Aquaris X5 Plus. On QCM2290 the video accelerator is enabled, so is HS timing modes for eMMC. The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi PCIe controller is introduced. On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is eMMC support and generic packer router (GPR). On the Monaco Ride board, the eMMC controller is enabled. On QRB220 RB1, the venus video accelerator is enabled. For SC7280 the first PCIe controller and PHY is introduced. SoundWire, LPASS, and USB offload support is added, the codecs and sound card is then described on the QCM6490 IDP. The MDSS core reset is introduced, to clear bootloader configuration on SC7280-based devices. On Fairphone5, USB audio offload is added. AudioReach support on SC7280 (QCS6490) is introduced and used to enable sound on the RB3Gen2 board. The video clock controller is added to SC8180X. On SC8280XP the GPI DMA controllers are described and enabled. Display and GPU is enabled for the Fairphone 3 and charging is enabled on the Google Pixel 3a. The routing for the second USB connector on the Lenovo Yoga C630 is described. On SM6150 ADSP and CDSP FastRPC is introduced, as is the video encoder/decoder (venus). On SM6350 RPMh statistics is enabled, the USB audio offload DAI is introduced and on Fairphone4 the USB audio offload support is enabled. On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery functionality. On SM8650 ACD levels are added for the GPU. Camera and video clock controllers power-domains are updated on SM8450, SM8550, and SM8650, now that support for multiple power-domains is accepted. SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes. The DWC3 glue and core nodes are flattened on a number of platforms. USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a variety of platforms, now that the QMP PHY driver supports this. Platform specific RPMh PD constants are replaced with generic constants wherever possible. On X Elite the PM8010 is disabled by default, removing boot splats on a variety of boards without this PMIC, the video clock controller is added. For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is marked as valid for the external DisplayPorts. The fingerprint reader found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled. The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support. GPU support is added for the X Plus SoC. * tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (208 commits) arm64: dts: qcom: x1e80100: Update GPU OPP table arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC arm64: dts: qcom: add initial support for Samsung Galaxy S20 dt-bindings: arm: qcom: document x1q board binding arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi arm64: dts: qcom: lemans-evk: Add sound card arm64: dts: qcom: lemans: Add gpr node arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec arm64: dts: qcom: sm6150: add venus node to devicetree arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT arm64: dts: qcom: qrb2210-rb1: Enable Venus arm64: dts: qcom: qcm2290: Add Venus video node arm64: dts: qcom: monaco-evk: Add sound card arm64: dts: qcom: qcs8300: Add gpr node arm64: dts: qcom: qcs8300: Add Monaco EVK board dt-bindings: arm: qcom: Add Monaco EVK support arm64: dts: qcom: qcm6490-idp: Add sound card arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec arm64: dts: qcom: qcs6490-rb3gen2: Add sound card ... Link: https://lore.kernel.org/r/20250911233600.3033675-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Input: MT - add INPUT_MT_TOTAL_FORCE flagsAngela Czubak1-0/+1
Add a flag to generate ABS_PRESSURE as sum of ABS_MT_PRESSURE across all slots. This flag should be set if one knows a device reports true force and would like to report total force to the userspace. Signed-off-by: Angela Czubak <aczubak@google.com> Co-developed-by: Jonathan Denose <jdenose@google.com> Signed-off-by: Jonathan Denose <jdenose@google.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Benjamin Tissoires <bentiss@kernel.org>
2025-09-15Input: add INPUT_PROP_HAPTIC_TOUCHPADAngela Czubak1-0/+1
INPUT_PROP_HAPTIC_TOUCHPAD property is to be set for a device with simple haptic capabilities. Signed-off-by: Angela Czubak <aczubak@google.com> Co-developed-by: Jonathan Denose <jdenose@google.com> Signed-off-by: Jonathan Denose <jdenose@google.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Benjamin Tissoires <bentiss@kernel.org>
2025-09-15Input: add FF_HAPTIC effect typeAngela Czubak1-1/+21
FF_HAPTIC effect type can be used to trigger haptic feedback with HID simple haptic usages. Signed-off-by: Angela Czubak <aczubak@google.com> Co-developed-by: Jonathan Denose <jdenose@google.com> Signed-off-by: Jonathan Denose <jdenose@google.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Benjamin Tissoires <bentiss@kernel.org>
2025-09-15HID: add haptics page definesAngela Czubak1-0/+29
Introduce haptic usages as defined in HID Usage Tables specification. Add HID units for newton and gram. Signed-off-by: Angela Czubak <aczubak@google.com> Co-developed-by: Jonathan Denose <jdenose@google.com> Signed-off-by: Jonathan Denose <jdenose@google.com> Signed-off-by: Benjamin Tissoires <bentiss@kernel.org>
2025-09-15srcu: Document __srcu_read_{,un}lock_fast() implicit RCU readersPaul E. McKenney1-15/+27
This commit documents the implicit RCU readers that are implied by the this_cpu_inc() and atomic_long_inc() operations in __srcu_read_lock_fast() and __srcu_read_unlock_fast(). While in the area, fix the documentation of the memory pairing of atomic_long_inc() in __srcu_read_lock_fast(). [ paulmck: Apply Joel Fernandes feedback. ] Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: <bpf@vger.kernel.org>
2025-09-15pidfs: validate extensible ioctlsChristian Brauner1-0/+14
Validate extensible ioctls stricter than we do now. Reviewed-by: Aleksa Sarai <cyphar@cyphar.com> Reviewed-by: Jan Kara <jack@suse.cz> Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-09-15drm/bridge: samsung-dsim: add driver support for exynos7870 DSIM bridgeKaustabh Chakraborty1-0/+1
Add support for Exynos7870's DSIM IP block in the bridge driver. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: add ability to define clock names for every variantKaustabh Chakraborty1-1/+1
Presently, all devices refer to clock names from a single array. The only controlling parameter is the number of clocks (num_clks field of samsung_dsim_driver_data) which uses the first n clocks of that array. As new devices are added, this approach turns out to be cumbersome. Separate the clock names in individual arrays required by each variant, in a struct clk_bulk_data. Add a pointer field to the driver data struct which points to their respective clock names, and rework the clock usage code to use the clk_bulk_* API instead. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring the PLL_STABLE bitKaustabh Chakraborty1-0/+1
The PLL_STABLE bit of DSIM_DPHY_STATUS is hardcoded to BIT(31), but Exynos7870's DSIM has it in BIT(24) as per downstream kernel sources. In order to support both, move this bit value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring PLL_M and PLL_S offsetsKaustabh Chakraborty1-0/+2
Currently, PLL_P offset of DSIM_PLLCTRL is configurable in the driver data, while PLL_M and PLL_S offsets are hardcoded as 4-bit and 1-bit offsets respectively, but Exynos7870's DSIM have them at 3-bit and 0-bit offsets as per downstream kernel sources. In order to support both, move both offset values to the driver data struct and define it for every driver compatible. Reference the values from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring the VIDEO_MODE bitKaustabh Chakraborty1-0/+1
The VIDEO_MODE bit of DSIM_CONFIG is hardcoded to BIT(25), but Exynos7870's DSIM has it in BIT(18) as per downstream kernel sources. In order to support both, move this bit value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring the MAIN_VSA offsetKaustabh Chakraborty1-0/+1
The MAIN_VSA offset of DSIM_MSYNC is hardcoded to a 22-bit offset, but Exynos7870's DSIM has it in a 16-bit offset as per the downstream kernel sources. In order to support both, move this offset value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: allow configuring bits and offsets of CLKCTRL registerKaustabh Chakraborty1-0/+5
DSIM_CLKCTRL bit and offset values hardcoded in the driver: name | bit/offset value --------------------------+----------------- DSIM_LANE_ESC_CLK_EN_CLK | 19 DSIM_LANE_ESC_CLK_EN_DATA | 20 DSIM_BYTE_CLKEN | 24 DSIM_ESC_CLKEN | 28 DSIM_TX_REQUEST_HSCLK | 31 DSIM_CLKCTRL bit and offset values in Exynos7870 DSIM as per downstream kernel sources: name | bit/offset value --------------------------+----------------- DSIM_LANE_ESC_CLK_EN_CLK | 8 DSIM_LANE_ESC_CLK_EN_DATA | 9 DSIM_BYTE_CLKEN | 17 DSIM_ESC_CLKEN | 16 DSIM_TX_REQUEST_HSCLK | 20 In order to support both, move all values to the driver data struct and define it for every driver compatible. Reference the values from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: add flag to control header FIFO waitKaustabh Chakraborty1-0/+1
Exynos7870's DSIM device doesn't require waiting for the header FIFO during a MIPI DSI transfer. Add a flag in the driver data in order to control said behavior. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com
2025-09-15drm/bridge: samsung-dsim: add SFRCTRL registerKaustabh Chakraborty1-0/+1
On Exynos7870 devices, enabling the display requires disabling standby by writing to the SFRCTRL register. Add the register and related bit values. Since this behavior isn't available on other SoCs, implement a flag in the driver data struct indicating the availability of this feature. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15drm/bridge: samsung-dsim: support separate LINK and DPHY status registersKaustabh Chakraborty1-0/+1
Exynos7870's DSIM has separate registers for LINK and DPHY status. This is in contrast to older variants in the driver which use a single register for both. Add a driver data flag which indicates that the device variant supports the legacy status register. Change the register read calls appropriately. Suggested-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15fs/resctrl: Introduce mbm_assign_on_mkdir to enable assignments on mkdirBabu Moger1-0/+3
The "mbm_event" counter assignment mode allows users to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. Introduce a user-configurable option that determines if a counter will automatically be assigned to an RMID, event pair when its associated monitor group is created via mkdir. Accessible when "mbm_event" counter assignment mode is enabled. Suggested-by: Peter Newman <peternewman@google.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Add event configuration directory under info/L3_MON/Babu Moger1-0/+3
The "mbm_event" counter assignment mode allows the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. The user can specify the memory transaction(s) for the counter to track. When this mode is supported, the /sys/fs/resctrl/info/L3_MON/event_configs directory contains a sub-directory for each MBM event that can be assigned to a counter. The MBM event sub-directory contains a file named "event_filter" that is used to view and modify which memory transactions the MBM event is configured with. Create /sys/fs/resctrl/info/L3_MON/event_configs directory on resctrl mount and pre-populate it with directories for the two existing MBM events: mbm_total_bytes and mbm_local_bytes. Create the "event_filter" file within each MBM event directory with the needed *show() that displays the memory transactions with which the MBM event is configured. Example: $ mount -t resctrl resctrl /sys/fs/resctrl $ cd /sys/fs/resctrl/ $ cat info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,remote_reads,local_non_temporal_writes, remote_non_temporal_writes,local_reads_slow_memory, remote_reads_slow_memory,dirty_victim_writes_all $ cat info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Introduce counter ID read, reset calls in mbm_event modeBabu Moger1-0/+38
When supported, "mbm_event" counter assignment mode allows users to assign a hardware counter to an RMID, event pair and monitor the bandwidth usage as long as it is assigned. The hardware continues to track the assigned counter until it is explicitly unassigned by the user. Introduce the architecture calls resctrl_arch_cntr_read() and resctrl_arch_reset_cntr() to read and reset event counters when "mbm_event" mode is supported. Function names match existing resctrl_arch_rmid_read() and resctrl_arch_reset_rmid(). Suggested-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15x86,fs/resctrl: Implement resctrl_arch_config_cntr() to assign a counter ↵Babu Moger1-0/+19
with ABMC The ABMC feature allows users to assign a hardware counter to an RMID, event pair and monitor bandwidth usage as long as it is assigned. The hardware continues to track the assigned counter until it is explicitly unassigned by the user. Implement an x86 architecture-specific handler to configure a counter. This architecture specific handler is called by resctrl fs when a counter is assigned or unassigned as well as when an already assigned counter's configuration should be updated. Configure counters by writing to the L3_QOS_ABMC_CFG MSR, specifying the counter ID, bandwidth source (RMID), and event configuration. The ABMC feature details are documented in APM [1] available from [2]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
2025-09-15ACPICA: CEDT: Add Back-Invalidate restriction to CXL WindowDavidlohr Bueso1-0/+1
This is added in newer version (3.0+) of the CXL Spec to support the HDM-DB coherency model. Link: https://github.com/acpica/acpica/commit/a6886da1 Signed-off-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-09-15ACPICA: Update version to 20250807Saket Dumbre1-1/+1
Link: https://github.com/acpica/acpica/commit/0845a773 Signed-off-by: Saket Dumbre <saket.dumbre@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-09-15ACPICA: Print error messages for too few or too many argumentsSaket Dumbre1-2/+8
Fix Issue #1027 by displaying error messages when there are too few or too many arguments in the caller vs the definition of an ASL/AML method. Link: https://github.com/acpica/acpica/commit/cbc243e4 Reported-by: Peter Williams <peter@newton.cx> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Tested-by: Hans de Goede <hansg@kernel.org> Signed-off-by: Saket Dumbre <saket.dumbre@intel.com>
2025-09-15ACPICA: Apply ACPI_NONSTRINGAhmed Salem1-1/+1
Add ACPI_NONSTRING for destination char arrays without a terminating NUL character. This is a follow-up to commit 2b82118845e0 ("ACPICA: Apply ACPI_NONSTRING") where a few more destination arrays were missed. Link: https://github.com/acpica/acpica/commit/f359e5ed Fixes: 2b82118845e0 ("ACPICA: Apply ACPI_NONSTRING") Signed-off-by: Ahmed Salem <x0rw3ll@gmail.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-09-15ACPICA: Allow to skip Global Lock initializationHuacai Chen1-0/+6
Introduce acpi_gbl_use_global_lock, which allows to skip the Global Lock initialization. This is useful for systems without Global Lock (such as loong_arch), so as to avoid error messages during boot phase: ACPI Error: Could not enable global_lock event (20240827/evxfevnt-182) ACPI Error: No response from Global Lock hardware, disabling lock (20240827/evglock-59) Link: https://github.com/acpica/acpica/commit/463cb0fe Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-09-15fs/resctrl: Introduce event configuration field in struct mon_evtBabu Moger1-0/+2
When supported, mbm_event counter assignment mode allows the user to configure events to track specific types of memory transactions. Introduce an evt_cfg field in struct mon_evt to define the type of memory transactions tracked by a monitoring event. Also add a helper function to get the evt_cfg value. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Introduce mbm_cntr_cfg to track assignable counters per domainBabu Moger1-0/+15
The "mbm_event" counter assignment mode allows users to assign a hardware counter to an RMID, event pair and monitor bandwidth usage as long as it is assigned. The hardware continues to track the assigned counter until it is explicitly unassigned by the user. Counters are assigned/unassigned at monitoring domain level. Manage a monitoring domain's hardware counters using a per monitoring domain array of struct mbm_cntr_cfg that is indexed by the hardware counter ID. A hardware counter's configuration contains the MBM event ID and points to the monitoring group that it is assigned to, with a NULL pointer meaning that the hardware counter is available for assignment. There is no direct way to determine which hardware counters are assigned to a particular monitoring group. Check every entry of every hardware counter configuration array in every monitoring domain to query which MBM events of a monitoring group is tracked by hardware. Such queries are acceptable because of a very small number of assignable counters (32 to 64). Suggested-by: Peter Newman <peternewman@google.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15x86/resctrl: Add support to enable/disable AMD ABMC featureBabu Moger1-0/+20
Add the functionality to enable/disable the AMD ABMC feature. The AMD ABMC feature is enabled by setting enabled bit(0) in the L3_QOS_EXT_CFG MSR. When the state of ABMC is changed, the MSR needs to be updated on all the logical processors in the QOS Domain. Hardware counters will reset when ABMC state is changed. [ bp: Massage commit message. ] Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
2025-09-15x86,fs/resctrl: Detect Assignable Bandwidth Monitoring feature detailsBabu Moger1-0/+4
ABMC feature details are reported via CPUID Fn8000_0020_EBX_x5. Bits Description 15:0 MAX_ABMC Maximum Supported Assignable Bandwidth Monitoring Counter ID + 1 The ABMC feature details are documented in APM [1] available from [2]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Detect the feature and number of assignable counters supported. For backward compatibility, upon detecting the assignable counter feature, enable the mbm_total_bytes and mbm_local_bytes events that users are familiar with as part of original L3 MBM support. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
2025-09-15x86,fs/resctrl: Consolidate monitoring related data from rdt_resourceBabu Moger1-5/+13
The cache allocation and memory bandwidth allocation feature properties are consolidated into struct resctrl_cache and struct resctrl_membw respectively. In preparation for more monitoring properties that will clobber the existing resource struct more, re-organize the monitoring specific properties to also be in a separate structure. Also convert "bandwidth sources" terminology to "memory transactions" to have consistency within resctrl for related monitoring features. [ bp: Massage commit message. ] Suggested-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15Merge back earlier cpufreq material for 6.18Rafael J. Wysocki1-4/+3
2025-09-15x86,fs/resctrl: Prepare for more monitor eventsTony Luck2-4/+22
There's a rule in computer programming that objects appear zero, once, or many times. So code accordingly. There are two MBM events and resctrl is coded with a lot of if (local) do one thing if (total) do a different thing Change the rdt_mon_domain and rdt_hw_mon_domain structures to hold arrays of pointers to per event data instead of explicit fields for total and local bandwidth. Simplify by coding for many events using loops on which are enabled. Move resctrl_is_mbm_event() to <linux/resctrl.h> so it can be used more widely. Also provide a for_each_mbm_event_id() helper macro. Cleanup variable names in functions touched to consistently use "eventid" for those with type enum resctrl_event_id. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15KVM: Avoid synchronize_srcu() in kvm_io_bus_register_dev()Keir Fraser1-0/+1
Device MMIO registration may happen quite frequently during VM boot, and the SRCU synchronization each time has a measurable effect on VM startup time. In our experiments it can account for around 25% of a VM's startup time. Replace the synchronization with a deferred free of the old kvm_io_bus structure. Tested-by: Li RongQing <lirongqing@baidu.com> Signed-off-by: Keir Fraser <keirf@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-27 08:17:24 +0000