From 6a3f890196b31b166a3e3e32735ff5c8116661cc Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 27 Aug 2025 16:54:25 +0200 Subject: ARM: at91: pm: fix .uhp_udp_mask specification for current SoCs All SoCs using this structure field .uhp_udp_mask in configuration index 4 don't have the bit 7 specified: sam9x60 nor sam9x75. Remove this bit from the mask definition to match register layout. This mask is used in function at91_pm_verify_clocks(). Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20250827145427.46819-2-nicolas.ferre@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 3aa20038ad93..35058b99069c 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -1364,7 +1364,7 @@ static const struct pmc_info pmc_infos[] __initconst = { .version = AT91_PMC_V1, }, { - .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, + .uhp_udp_mask = AT91SAM926x_PMC_UHP, .mckr = 0x28, .version = AT91_PMC_V2, }, -- cgit v1.2.3 From 296302d3d81360e09fa956e9be9edc8223b69a12 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 27 Aug 2025 16:54:26 +0200 Subject: ARM: at91: pm: fix MCKx restore routine The at91_mckx_ps_restore() assembly function is responsible for setting back MCKx system bus clocks after exiting low power modes. Fix a typo and use tmp3 variable instead of tmp2 to correctly set MCKx to previously saved state. Tmp2 was used without the needed changes in CSS and DIV. Moreover the required bit 7, telling that MCR register's content is to be changed (CMD/write), was not set. Fix function comment to match tmp variables actually used. Signed-off-by: Nicolas Ferre Fixes: 28eb1d40fe57 ("ARM: at91: pm: add support for MCK1..4 save/restore for ulp modes") Link: https://lore.kernel.org/r/20250827145427.46819-3-nicolas.ferre@microchip.com Reviewed-by: Alexandre Belloni [claudiu.beznea: s/sate/state in commit description] Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm_suspend.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index e23b86834096..7e6c94f8edee 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -904,7 +904,7 @@ e_done: /** * at91_mckx_ps_restore: restore MCKx settings * - * Side effects: overwrites tmp1, tmp2 + * Side effects: overwrites tmp1, tmp2 and tmp3 */ .macro at91_mckx_ps_restore #ifdef CONFIG_SOC_SAMA7 @@ -980,7 +980,7 @@ r_ps: bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK orr tmp3, tmp3, tmp1 orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD - str tmp2, [pmc, #AT91_PMC_MCR_V2] + str tmp3, [pmc, #AT91_PMC_MCR_V2] wait_mckrdy tmp1 -- cgit v1.2.3 From 3cae7d18392feacf04354feac994c1b48eed91af Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 27 Aug 2025 16:54:27 +0200 Subject: ARM: at91: pm: save and restore ACR during PLL disable/enable Add a new word in assembly to store ACR value during the calls to at91_plla_disable/at91_plla_enable macros and use it. Signed-off-by: Nicolas Ferre [cristian.birsan@microchip.com: remove ACR_DEFAULT_PLLA loading] Signed-off-by: Cristian Birsan Link: https://lore.kernel.org/r/20250827145427.46819-4-nicolas.ferre@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm_suspend.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index 7e6c94f8edee..aad53ec9e957 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -689,6 +689,10 @@ sr_dis_exit: bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID str tmp2, [pmc, #AT91_PMC_PLL_UPDT] + /* save acr */ + ldr tmp2, [pmc, #AT91_PMC_PLL_ACR] + str tmp2, .saved_acr + /* save div. */ mov tmp1, #0 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] @@ -758,7 +762,7 @@ sr_dis_exit: str tmp1, [pmc, #AT91_PMC_PLL_UPDT] /* step 2. */ - ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA + ldr tmp1, .saved_acr str tmp1, [pmc, #AT91_PMC_PLL_ACR] /* step 3. */ @@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram) #endif .saved_mckr: .word 0 +.saved_acr: + .word 0 .saved_pllar: .word 0 .saved_sam9_lpr: -- cgit v1.2.3 From 747436750bc0ef73be32391bd5d0d7dcd185da7f Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 10 Sep 2025 09:20:38 -0700 Subject: ARM: at91: pm: Remove 2.5V regulator Remove 2.5V regulator since enabling and disabling this regulator is no longer supported. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/a6785a40648b315a07152bca261a42bbf0f356af.1757519351.git.Ryan.Wanner@microchip.com Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm_suspend.S | 29 ----------------------------- include/soc/at91/sama7-sfrbu.h | 7 ------- 2 files changed, 36 deletions(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index aad53ec9e957..2e639f9ed648 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -87,29 +87,6 @@ tmp3 .req r6 .endm -/** - * Set state for 2.5V low power regulator - * @ena: 0 - disable regulator - * 1 - enable regulator - * - * Side effects: overwrites r7, r8, r9, r10 - */ - .macro at91_2_5V_reg_set_low_power ena -#ifdef CONFIG_SOC_SAMA7 - ldr r7, .sfrbu - mov r8, #\ena - ldr r9, [r7, #AT91_SFRBU_25LDOCR] - orr r9, r9, #AT91_SFRBU_25LDOCR_LP - cmp r8, #1 - beq lp_done_\ena - bic r9, r9, #AT91_SFRBU_25LDOCR_LP -lp_done_\ena: - ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY - orr r9, r9, r10 - str r9, [r7, #AT91_SFRBU_25LDOCR] -#endif - .endm - .macro at91_backup_set_lpm reg #ifdef CONFIG_SOC_SAMA7 orr \reg, \reg, #0x200000 @@ -1023,9 +1000,6 @@ save_mck: at91_plla_disable - /* Enable low power mode for 2.5V regulator. */ - at91_2_5V_reg_set_low_power 1 - ldr tmp3, .pm_mode cmp tmp3, #AT91_PM_ULP1 beq ulp1_mode @@ -1038,9 +1012,6 @@ ulp1_mode: b ulp_exit ulp_exit: - /* Disable low power mode for 2.5V regulator. */ - at91_2_5V_reg_set_low_power 0 - ldr pmc, .pmc_base at91_plla_enable diff --git a/include/soc/at91/sama7-sfrbu.h b/include/soc/at91/sama7-sfrbu.h index 76b740810d34..8cee48d1ae2c 100644 --- a/include/soc/at91/sama7-sfrbu.h +++ b/include/soc/at91/sama7-sfrbu.h @@ -18,13 +18,6 @@ #define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ #define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ -#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ -#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ -#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ -#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ -#define AT91_SFRBU_PD_VALUE_MSK (0x3) -#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ - #define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ #define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ -- cgit v1.2.3