From acc379c63ade8e247fb792ccdd4ae9a208530c1a Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Thu, 29 May 2025 15:50:38 +0200 Subject: dt-bindings: clock: Add RaspberryPi RP1 clock bindings Add device tree bindings for the clock generator found in RP1 multi function device, and relative entries in MAINTAINERS file. Signed-off-by: Andrea della Porta Reviewed-by: Krzysztof Kozlowski Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com Signed-off-by: Florian Fainelli --- .../bindings/clock/raspberrypi,rp1-clocks.yaml | 58 ++++++++++++++++++++ include/dt-bindings/clock/raspberrypi,rp1-clocks.h | 61 ++++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml create mode 100644 include/dt-bindings/clock/raspberrypi,rp1-clocks.h diff --git a/Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml b/Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml new file mode 100644 index 000000000000..cc4491f7ee5f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/raspberrypi,rp1-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RaspberryPi RP1 clock generator + +maintainers: + - A. della Porta + +description: | + The RP1 contains a clock generator designed as three PLLs (CORE, AUDIO, + VIDEO), and each PLL output can be programmed through dividers to generate + the clocks to drive the sub-peripherals embedded inside the chipset. + + Link to datasheet: + https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf + +properties: + compatible: + const: raspberrypi,rp1-clocks + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The available clocks are defined in + include/dt-bindings/clock/raspberrypi,rp1-clocks.h. + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - clocks + +additionalProperties: false + +examples: + - | + #include + + rp1 { + #address-cells = <2>; + #size-cells = <2>; + + clocks@c040018000 { + compatible = "raspberrypi,rp1-clocks"; + reg = <0xc0 0x40018000 0x0 0x10038>; + #clock-cells = <1>; + clocks = <&clk_rp1_xosc>; + }; + }; diff --git a/include/dt-bindings/clock/raspberrypi,rp1-clocks.h b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h new file mode 100644 index 000000000000..248efb895f35 --- /dev/null +++ b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 Raspberry Pi Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1 +#define __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1 + +#define RP1_PLL_SYS_CORE 0 +#define RP1_PLL_AUDIO_CORE 1 +#define RP1_PLL_VIDEO_CORE 2 + +#define RP1_PLL_SYS 3 +#define RP1_PLL_AUDIO 4 +#define RP1_PLL_VIDEO 5 + +#define RP1_PLL_SYS_PRI_PH 6 +#define RP1_PLL_SYS_SEC_PH 7 +#define RP1_PLL_AUDIO_PRI_PH 8 + +#define RP1_PLL_SYS_SEC 9 +#define RP1_PLL_AUDIO_SEC 10 +#define RP1_PLL_VIDEO_SEC 11 + +#define RP1_CLK_SYS 12 +#define RP1_CLK_SLOW_SYS 13 +#define RP1_CLK_DMA 14 +#define RP1_CLK_UART 15 +#define RP1_CLK_ETH 16 +#define RP1_CLK_PWM0 17 +#define RP1_CLK_PWM1 18 +#define RP1_CLK_AUDIO_IN 19 +#define RP1_CLK_AUDIO_OUT 20 +#define RP1_CLK_I2S 21 +#define RP1_CLK_MIPI0_CFG 22 +#define RP1_CLK_MIPI1_CFG 23 +#define RP1_CLK_PCIE_AUX 24 +#define RP1_CLK_USBH0_MICROFRAME 25 +#define RP1_CLK_USBH1_MICROFRAME 26 +#define RP1_CLK_USBH0_SUSPEND 27 +#define RP1_CLK_USBH1_SUSPEND 28 +#define RP1_CLK_ETH_TSU 29 +#define RP1_CLK_ADC 30 +#define RP1_CLK_SDIO_TIMER 31 +#define RP1_CLK_SDIO_ALT_SRC 32 +#define RP1_CLK_GP0 33 +#define RP1_CLK_GP1 34 +#define RP1_CLK_GP2 35 +#define RP1_CLK_GP3 36 +#define RP1_CLK_GP4 37 +#define RP1_CLK_GP5 38 +#define RP1_CLK_VEC 39 +#define RP1_CLK_DPI 40 +#define RP1_CLK_MIPI0_DPI 41 +#define RP1_CLK_MIPI1_DPI 42 + +/* Extra PLL output channels - RP1B0 only */ +#define RP1_PLL_VIDEO_PRI_PH 43 +#define RP1_PLL_AUDIO_TERN 44 + +#endif -- cgit v1.2.3 From 6486341721a2cd1cbc9c08a9bc90235c0b42f25b Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Thu, 29 May 2025 15:50:41 +0200 Subject: clk: rp1: Add support for clocks provided by RP1 RaspberryPi RP1 is an MFD providing, among other peripherals, several clock generators and PLLs that drives the sub-peripherals. Add the driver to support the clock providers. Signed-off-by: Andrea della Porta Tested-by: Randy Dunlap # build-tested Link: https://lore.kernel.org/r/20250529135052.28398-4-andrea.porta@suse.com Signed-off-by: Florian Fainelli --- drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-rp1.c | 1494 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1504 insertions(+) create mode 100644 drivers/clk/clk-rp1.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 19c1ed280fd7..b5a77669ed23 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -88,6 +88,15 @@ config COMMON_CLK_RK808 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. Clkout1 is always on, Clkout2 can off by control register. +config COMMON_CLK_RP1 + tristate "Raspberry Pi RP1-based clock support" + depends on MISC_RP1 || COMPILE_TEST + default MISC_RP1 + help + Enable common clock framework support for Raspberry Pi RP1. + This multi-function device has 3 main PLLs and several clock + generators to drive the internal sub-peripherals. + config COMMON_CLK_HI655X tristate "Clock driver for Hi655x" if EXPERT depends on (MFD_HI655X_PMIC || COMPILE_TEST) diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 42867cd37c33..3d04f3463452 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o +obj-$(CONFIG_COMMON_CLK_RP1) += clk-rp1.o obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SCMI) += clk-scmi.o diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c new file mode 100644 index 000000000000..afff90d48734 --- /dev/null +++ b/drivers/clk/clk-rp1.c @@ -0,0 +1,1494 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Raspberry Pi Ltd. + * + * Clock driver for RP1 PCIe multifunction chip. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PLL_SYS_OFFSET 0x08000 +#define PLL_SYS_CS (PLL_SYS_OFFSET + 0x00) +#define PLL_SYS_PWR (PLL_SYS_OFFSET + 0x04) +#define PLL_SYS_FBDIV_INT (PLL_SYS_OFFSET + 0x08) +#define PLL_SYS_FBDIV_FRAC (PLL_SYS_OFFSET + 0x0c) +#define PLL_SYS_PRIM (PLL_SYS_OFFSET + 0x10) +#define PLL_SYS_SEC (PLL_SYS_OFFSET + 0x14) + +#define PLL_AUDIO_OFFSET 0x0c000 +#define PLL_AUDIO_CS (PLL_AUDIO_OFFSET + 0x00) +#define PLL_AUDIO_PWR (PLL_AUDIO_OFFSET + 0x04) +#define PLL_AUDIO_FBDIV_INT (PLL_AUDIO_OFFSET + 0x08) +#define PLL_AUDIO_FBDIV_FRAC (PLL_AUDIO_OFFSET + 0x0c) +#define PLL_AUDIO_PRIM (PLL_AUDIO_OFFSET + 0x10) +#define PLL_AUDIO_SEC (PLL_AUDIO_OFFSET + 0x14) +#define PLL_AUDIO_TERN (PLL_AUDIO_OFFSET + 0x18) + +#define PLL_VIDEO_OFFSET 0x10000 +#define PLL_VIDEO_CS (PLL_VIDEO_OFFSET + 0x00) +#define PLL_VIDEO_PWR (PLL_VIDEO_OFFSET + 0x04) +#define PLL_VIDEO_FBDIV_INT (PLL_VIDEO_OFFSET + 0x08) +#define PLL_VIDEO_FBDIV_FRAC (PLL_VIDEO_OFFSET + 0x0c) +#define PLL_VIDEO_PRIM (PLL_VIDEO_OFFSET + 0x10) +#define PLL_VIDEO_SEC (PLL_VIDEO_OFFSET + 0x14) + +#define GPCLK_OE_CTRL 0x00000 + +#define CLK_SYS_OFFSET 0x00014 +#define CLK_SYS_CTRL (CLK_SYS_OFFSET + 0x00) +#define CLK_SYS_DIV_INT (CLK_SYS_OFFSET + 0x04) +#define CLK_SYS_SEL (CLK_SYS_OFFSET + 0x0c) + +#define CLK_SLOW_OFFSET 0x00024 +#define CLK_SLOW_SYS_CTRL (CLK_SLOW_OFFSET + 0x00) +#define CLK_SLOW_SYS_DIV_INT (CLK_SLOW_OFFSET + 0x04) +#define CLK_SLOW_SYS_SEL (CLK_SLOW_OFFSET + 0x0c) + +#define CLK_DMA_OFFSET 0x00044 +#define CLK_DMA_CTRL (CLK_DMA_OFFSET + 0x00) +#define CLK_DMA_DIV_INT (CLK_DMA_OFFSET + 0x04) +#define CLK_DMA_SEL (CLK_DMA_OFFSET + 0x0c) + +#define CLK_UART_OFFSET 0x00054 +#define CLK_UART_CTRL (CLK_UART_OFFSET + 0x00) +#define CLK_UART_DIV_INT (CLK_UART_OFFSET + 0x04) +#define CLK_UART_SEL (CLK_UART_OFFSET + 0x0c) + +#define CLK_ETH_OFFSET 0x00064 +#define CLK_ETH_CTRL (CLK_ETH_OFFSET + 0x00) +#define CLK_ETH_DIV_INT (CLK_ETH_OFFSET + 0x04) +#define CLK_ETH_SEL (CLK_ETH_OFFSET + 0x0c) + +#define CLK_PWM0_OFFSET 0x00074 +#define CLK_PWM0_CTRL (CLK_PWM0_OFFSET + 0x00) +#define CLK_PWM0_DIV_INT (CLK_PWM0_OFFSET + 0x04) +#define CLK_PWM0_DIV_FRAC (CLK_PWM0_OFFSET + 0x08) +#define CLK_PWM0_SEL (CLK_PWM0_OFFSET + 0x0c) + +#define CLK_PWM1_OFFSET 0x00084 +#define CLK_PWM1_CTRL (CLK_PWM1_OFFSET + 0x00) +#define CLK_PWM1_DIV_INT (CLK_PWM1_OFFSET + 0x04) +#define CLK_PWM1_DIV_FRAC (CLK_PWM1_OFFSET + 0x08) +#define CLK_PWM1_SEL (CLK_PWM1_OFFSET + 0x0c) + +#define CLK_AUDIO_IN_OFFSET 0x00094 +#define CLK_AUDIO_IN_CTRL (CLK_AUDIO_IN_OFFSET + 0x00) +#define CLK_AUDIO_IN_DIV_INT (CLK_AUDIO_IN_OFFSET + 0x04) +#define CLK_AUDIO_IN_SEL (CLK_AUDIO_IN_OFFSET + 0x0c) + +#define CLK_AUDIO_OUT_OFFSET 0x000a4 +#define CLK_AUDIO_OUT_CTRL (CLK_AUDIO_OUT_OFFSET + 0x00) +#define CLK_AUDIO_OUT_DIV_INT (CLK_AUDIO_OUT_OFFSET + 0x04) +#define CLK_AUDIO_OUT_SEL (CLK_AUDIO_OUT_OFFSET + 0x0c) + +#define CLK_I2S_OFFSET 0x000b4 +#define CLK_I2S_CTRL (CLK_I2S_OFFSET + 0x00) +#define CLK_I2S_DIV_INT (CLK_I2S_OFFSET + 0x04) +#define CLK_I2S_SEL (CLK_I2S_OFFSET + 0x0c) + +#define CLK_MIPI0_CFG_OFFSET 0x000c4 +#define CLK_MIPI0_CFG_CTRL (CLK_MIPI0_CFG_OFFSET + 0x00) +#define CLK_MIPI0_CFG_DIV_INT (CLK_MIPI0_CFG_OFFSET + 0x04) +#define CLK_MIPI0_CFG_SEL (CLK_MIPI0_CFG_OFFSET + 0x0c) + +#define CLK_MIPI1_CFG_OFFSET 0x000d4 +#define CLK_MIPI1_CFG_CTRL (CLK_MIPI1_CFG_OFFSET + 0x00) +#define CLK_MIPI1_CFG_DIV_INT (CLK_MIPI1_CFG_OFFSET + 0x04) +#define CLK_MIPI1_CFG_SEL (CLK_MIPI1_CFG_OFFSET + 0x0c) + +#define CLK_PCIE_AUX_OFFSET 0x000e4 +#define CLK_PCIE_AUX_CTRL (CLK_PCIE_AUX_OFFSET + 0x00) +#define CLK_PCIE_AUX_DIV_INT (CLK_PCIE_AUX_OFFSET + 0x04) +#define CLK_PCIE_AUX_SEL (CLK_PCIE_AUX_OFFSET + 0x0c) + +#define CLK_USBH0_MICROFRAME_OFFSET 0x000f4 +#define CLK_USBH0_MICROFRAME_CTRL (CLK_USBH0_MICROFRAME_OFFSET + 0x00) +#define CLK_USBH0_MICROFRAME_DIV_INT (CLK_USBH0_MICROFRAME_OFFSET + 0x04) +#define CLK_USBH0_MICROFRAME_SEL (CLK_USBH0_MICROFRAME_OFFSET + 0x0c) + +#define CLK_USBH1_MICROFRAME_OFFSET 0x00104 +#define CLK_USBH1_MICROFRAME_CTRL (CLK_USBH1_MICROFRAME_OFFSET + 0x00) +#define CLK_USBH1_MICROFRAME_DIV_INT (CLK_USBH1_MICROFRAME_OFFSET + 0x04) +#define CLK_USBH1_MICROFRAME_SEL (CLK_USBH1_MICROFRAME_OFFSET + 0x0c) + +#define CLK_USBH0_SUSPEND_OFFSET 0x00114 +#define CLK_USBH0_SUSPEND_CTRL (CLK_USBH0_SUSPEND_OFFSET + 0x00) +#define CLK_USBH0_SUSPEND_DIV_INT (CLK_USBH0_SUSPEND_OFFSET + 0x04) +#define CLK_USBH0_SUSPEND_SEL (CLK_USBH0_SUSPEND_OFFSET + 0x0c) + +#define CLK_USBH1_SUSPEND_OFFSET 0x00124 +#define CLK_USBH1_SUSPEND_CTRL (CLK_USBH1_SUSPEND_OFFSET + 0x00) +#define CLK_USBH1_SUSPEND_DIV_INT (CLK_USBH1_SUSPEND_OFFSET + 0x04) +#define CLK_USBH1_SUSPEND_SEL (CLK_USBH1_SUSPEND_OFFSET + 0x0c) + +#define CLK_ETH_TSU_OFFSET 0x00134 +#define CLK_ETH_TSU_CTRL (CLK_ETH_TSU_OFFSET + 0x00) +#define CLK_ETH_TSU_DIV_INT (CLK_ETH_TSU_OFFSET + 0x04) +#define CLK_ETH_TSU_SEL (CLK_ETH_TSU_OFFSET + 0x0c) + +#define CLK_ADC_OFFSET 0x00144 +#define CLK_ADC_CTRL (CLK_ADC_OFFSET + 0x00) +#define CLK_ADC_DIV_INT (CLK_ADC_OFFSET + 0x04) +#define CLK_ADC_SEL (CLK_ADC_OFFSET + 0x0c) + +#define CLK_SDIO_TIMER_OFFSET 0x00154 +#define CLK_SDIO_TIMER_CTRL (CLK_SDIO_TIMER_OFFSET + 0x00) +#define CLK_SDIO_TIMER_DIV_INT (CLK_SDIO_TIMER_OFFSET + 0x04) +#define CLK_SDIO_TIMER_SEL (CLK_SDIO_TIMER_OFFSET + 0x0c) + +#define CLK_SDIO_ALT_SRC_OFFSET 0x00164 +#define CLK_SDIO_ALT_SRC_CTRL (CLK_SDIO_ALT_SRC_OFFSET + 0x00) +#define CLK_SDIO_ALT_SRC_DIV_INT (CLK_SDIO_ALT_SRC_OFFSET + 0x04) +#define CLK_SDIO_ALT_SRC_SEL (CLK_SDIO_ALT_SRC_OFFSET + 0x0c) + +#define CLK_GP0_OFFSET 0x00174 +#define CLK_GP0_CTRL (CLK_GP0_OFFSET + 0x00) +#define CLK_GP0_DIV_INT (CLK_GP0_OFFSET + 0x04) +#define CLK_GP0_DIV_FRAC (CLK_GP0_OFFSET + 0x08) +#define CLK_GP0_SEL (CLK_GP0_OFFSET + 0x0c) + +#define CLK_GP1_OFFSET 0x00184 +#define CLK_GP1_CTRL (CLK_GP1_OFFSET + 0x00) +#define CLK_GP1_DIV_INT (CLK_GP1_OFFSET + 0x04) +#define CLK_GP1_DIV_FRAC (CLK_GP1_OFFSET + 0x08) +#define CLK_GP1_SEL (CLK_GP1_OFFSET + 0x0c) + +#define CLK_GP2_OFFSET 0x00194 +#define CLK_GP2_CTRL (CLK_GP2_OFFSET + 0x00) +#define CLK_GP2_DIV_INT (CLK_GP2_OFFSET + 0x04) +#define CLK_GP2_DIV_FRAC (CLK_GP2_OFFSET + 0x08) +#define CLK_GP2_SEL (CLK_GP2_OFFSET + 0x0c) + +#define CLK_GP3_OFFSET 0x001a4 +#define CLK_GP3_CTRL (CLK_GP3_OFFSET + 0x00) +#define CLK_GP3_DIV_INT (CLK_GP3_OFFSET + 0x04) +#define CLK_GP3_DIV_FRAC (CLK_GP3_OFFSET + 0x08) +#define CLK_GP3_SEL (CLK_GP3_OFFSET + 0x0c) + +#define CLK_GP4_OFFSET 0x001b4 +#define CLK_GP4_CTRL (CLK_GP4_OFFSET + 0x00) +#define CLK_GP4_DIV_INT (CLK_GP4_OFFSET + 0x04) +#define CLK_GP4_DIV_FRAC (CLK_GP4_OFFSET + 0x08) +#define CLK_GP4_SEL (CLK_GP4_OFFSET + 0x0c) + +#define CLK_GP5_OFFSET 0x001c4 +#define CLK_GP5_CTRL (CLK_GP5_OFFSET + 0x00) +#define CLK_GP5_DIV_INT (CLK_GP5_OFFSET + 0x04) +#define CLK_GP5_DIV_FRAC (CLK_GP5_OFFSET + 0x08) +#define CLK_GP5_SEL (CLK_GP5_OFFSET + 0x0c) + +#define CLK_SYS_RESUS_CTRL 0x0020c + +#define CLK_SLOW_SYS_RESUS_CTRL 0x00214 + +#define FC0_OFFSET 0x0021c +#define FC0_REF_KHZ (FC0_OFFSET + 0x00) +#define FC0_MIN_KHZ (FC0_OFFSET + 0x04) +#define FC0_MAX_KHZ (FC0_OFFSET + 0x08) +#define FC0_DELAY (FC0_OFFSET + 0x0c) +#define FC0_INTERVAL (FC0_OFFSET + 0x10) +#define FC0_SRC (FC0_OFFSET + 0x14) +#define FC0_STATUS (FC0_OFFSET + 0x18) +#define FC0_RESULT (FC0_OFFSET + 0x1c) +#define FC_SIZE 0x20 +#define FC_COUNT 8 +#define FC_NUM(idx, off) ((idx) * 32 + (off)) + +#define AUX_SEL 1 + +#define VIDEO_CLOCKS_OFFSET 0x4000 +#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000) +#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004) +#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c) +#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010) +#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014) +#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c) +#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020) +#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024) +#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028) +#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c) +#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030) +#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034) +#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038) +#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c) + +#define DIV_INT_8BIT_MAX GENMASK(7, 0) /* max divide for most clocks */ +#define DIV_INT_16BIT_MAX GENMASK(15, 0) /* max divide for GPx, PWM */ +#define DIV_INT_24BIT_MAX GENMASK(23, 0) /* max divide for CLK_SYS */ + +#define FC0_STATUS_DONE BIT(4) +#define FC0_STATUS_RUNNING BIT(8) +#define FC0_RESULT_FRAC_SHIFT 5 + +#define PLL_PRIM_DIV1_MASK GENMASK(18, 16) +#define PLL_PRIM_DIV2_MASK GENMASK(14, 12) + +#define PLL_SEC_DIV_MASK GENMASK(12, 8) + +#define PLL_CS_LOCK BIT(31) +#define PLL_CS_REFDIV_MASK BIT(1) + +#define PLL_PWR_PD BIT(0) +#define PLL_PWR_DACPD BIT(1) +#define PLL_PWR_DSMPD BIT(2) +#define PLL_PWR_POSTDIVPD BIT(3) +#define PLL_PWR_4PHASEPD BIT(4) +#define PLL_PWR_VCOPD BIT(5) +#define PLL_PWR_MASK GENMASK(5, 0) + +#define PLL_SEC_RST BIT(16) +#define PLL_SEC_IMPL BIT(31) + +/* PLL phase output for both PRI and SEC */ +#define PLL_PH_EN BIT(4) +#define PLL_PH_PHASE_SHIFT 0 + +#define RP1_PLL_PHASE_0 0 +#define RP1_PLL_PHASE_90 1 +#define RP1_PLL_PHASE_180 2 +#define RP1_PLL_PHASE_270 3 + +/* Clock fields for all clocks */ +#define CLK_CTRL_ENABLE BIT(11) +#define CLK_CTRL_AUXSRC_MASK GENMASK(9, 5) +#define CLK_CTRL_SRC_SHIFT 0 +#define CLK_DIV_FRAC_BITS 16 + +#define LOCK_TIMEOUT_US 100000 +#define LOCK_POLL_DELAY_US 5 + +#define MAX_CLK_PARENTS 16 + +#define PLL_DIV_INVALID 19 +/* + * Secondary PLL channel output divider table. + * Divider values range from 8 to 19, where + * 19 means invalid. + */ +static const struct clk_div_table pll_sec_div_table[] = { + { 0x00, PLL_DIV_INVALID }, + { 0x01, PLL_DIV_INVALID }, + { 0x02, PLL_DIV_INVALID }, + { 0x03, PLL_DIV_INVALID }, + { 0x04, PLL_DIV_INVALID }, + { 0x05, PLL_DIV_INVALID }, + { 0x06, PLL_DIV_INVALID }, + { 0x07, PLL_DIV_INVALID }, + { 0x08, 8 }, + { 0x09, 9 }, + { 0x0a, 10 }, + { 0x0b, 11 }, + { 0x0c, 12 }, + { 0x0d, 13 }, + { 0x0e, 14 }, + { 0x0f, 15 }, + { 0x10, 16 }, + { 0x11, 17 }, + { 0x12, 18 }, + { 0x13, PLL_DIV_INVALID }, + { 0x14, PLL_DIV_INVALID }, + { 0x15, PLL_DIV_INVALID }, + { 0x16, PLL_DIV_INVALID }, + { 0x17, PLL_DIV_INVALID }, + { 0x18, PLL_DIV_INVALID }, + { 0x19, PLL_DIV_INVALID }, + { 0x1a, PLL_DIV_INVALID }, + { 0x1b, PLL_DIV_INVALID }, + { 0x1c, PLL_DIV_INVALID }, + { 0x1d, PLL_DIV_INVALID }, + { 0x1e, PLL_DIV_INVALID }, + { 0x1f, PLL_DIV_INVALID }, + { 0 } +}; + +struct rp1_clockman { + struct device *dev; + void __iomem *regs; + struct regmap *regmap; + spinlock_t regs_lock; /* spinlock for all clocks */ + + /* Must be last */ + struct clk_hw_onecell_data onecell; +}; + +struct rp1_pll_core_data { + u32 cs_reg; + u32 pwr_reg; + u32 fbdiv_int_reg; + u32 fbdiv_frac_reg; + u32 fc0_src; +}; + +struct rp1_pll_data { + u32 ctrl_reg; + u32 fc0_src; +}; + +struct rp1_pll_ph_data { + unsigned int phase; + unsigned int fixed_divider; + u32 ph_reg; + u32 fc0_src; +}; + +struct rp1_pll_divider_data { + u32 sec_reg; + u32 fc0_src; +}; + +struct rp1_clock_data { + int num_std_parents; + int num_aux_parents; + u32 oe_mask; + u32 clk_src_mask; + u32 ctrl_reg; + u32 div_int_reg; + u32 div_frac_reg; + u32 sel_reg; + u32 div_int_max; + unsigned long max_freq; + u32 fc0_src; +}; + +struct rp1_clk_desc { + struct clk_hw *(*clk_register)(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc); + const void *data; + struct clk_hw hw; + struct rp1_clockman *clockman; + unsigned long cached_rate; + struct clk_divider div; +}; + +static inline +void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val) +{ + regmap_write(clockman->regmap, reg, val); +} + +static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg) +{ + u32 val; + + regmap_read(clockman->regmap, reg, &val); + + return val; +} + +static int rp1_pll_core_is_on(struct clk_hw *hw) +{ + struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + u32 pwr = clockman_read(clockman, data->pwr_reg); + + return (pwr & PLL_PWR_PD) || (pwr & PLL_PWR_POSTDIVPD); +} + +static int rp1_pll_core_on(struct clk_hw *hw) +{ + struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + u32 fbdiv_frac, val; + int ret; + + spin_lock(&clockman->regs_lock); + + if (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) { + /* Reset to a known state. */ + clockman_write(clockman, data->pwr_reg, PLL_PWR_MASK); + clockman_write(clockman, data->fbdiv_int_reg, 20); + clockman_write(clockman, data->fbdiv_frac_reg, 0); + clockman_write(clockman, data->cs_reg, PLL_CS_REFDIV_MASK); + } + + /* Come out of reset. */ + fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg); + clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); + spin_unlock(&clockman->regs_lock); + + /* Wait for the PLL to lock. */ + ret = regmap_read_poll_timeout(clockman->regmap, data->cs_reg, val, + val & PLL_CS_LOCK, + LOCK_POLL_DELAY_US, LOCK_TIMEOUT_US); + if (ret) + dev_err(clockman->dev, "%s: can't lock PLL\n", + clk_hw_get_name(hw)); + + return ret; +} + +static void rp1_pll_core_off(struct clk_hw *hw) +{ + struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->pwr_reg, 0); + spin_unlock(&clockman->regs_lock); +} + +static inline unsigned long get_pll_core_divider(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u32 *div_int, u32 *div_frac) +{ + u32 fbdiv_int, fbdiv_frac; + unsigned long calc_rate; + u64 shifted_fbdiv_int; + u64 div_fp64; /* 32.32 fixed point fraction. */ + + /* Factor of reference clock to VCO frequency. */ + div_fp64 = (u64)(rate) << 32; + div_fp64 = DIV_ROUND_CLOSEST_ULL(div_fp64, parent_rate); + + /* Round the fractional component at 24 bits. */ + div_fp64 += 1 << (32 - 24 - 1); + + fbdiv_int = div_fp64 >> 32; + fbdiv_frac = (div_fp64 >> (32 - 24)) & 0xffffff; + + shifted_fbdiv_int = (u64)fbdiv_int << 24; + calc_rate = (u64)parent_rate * (shifted_fbdiv_int + fbdiv_frac); + calc_rate += BIT(23); + calc_rate >>= 24; + + *div_int = fbdiv_int; + *div_frac = fbdiv_frac; + + return calc_rate; +} + +static int rp1_pll_core_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + unsigned long calc_rate; + u32 fbdiv_int, fbdiv_frac; + + /* Disable dividers to start with. */ + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->fbdiv_int_reg, 0); + clockman_write(clockman, data->fbdiv_frac_reg, 0); + spin_unlock(&clockman->regs_lock); + + calc_rate = get_pll_core_divider(hw, rate, parent_rate, + &fbdiv_int, &fbdiv_frac); + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); + clockman_write(clockman, data->fbdiv_int_reg, fbdiv_int); + clockman_write(clockman, data->fbdiv_frac_reg, fbdiv_frac); + spin_unlock(&clockman->regs_lock); + + /* Check that reference frequency is no greater than VCO / 16. */ + if (WARN_ON_ONCE(parent_rate > (rate / 16))) + return -ERANGE; + + pll_core->cached_rate = calc_rate; + + spin_lock(&clockman->regs_lock); + /* Don't need to divide ref unless parent_rate > (output freq / 16) */ + clockman_write(clockman, data->cs_reg, + clockman_read(clockman, data->cs_reg) | + PLL_CS_REFDIV_MASK); + spin_unlock(&clockman->regs_lock); + + return 0; +} + +static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll_core->clockman; + const struct rp1_pll_core_data *data = pll_core->data; + u32 fbdiv_int, fbdiv_frac; + unsigned long calc_rate; + u64 shifted_fbdiv_int; + + fbdiv_int = clockman_read(clockman, data->fbdiv_int_reg); + fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg); + + shifted_fbdiv_int = (u64)fbdiv_int << 24; + calc_rate = (u64)parent_rate * (shifted_fbdiv_int + fbdiv_frac); + calc_rate += BIT(23); + calc_rate >>= 24; + + return calc_rate; +} + +static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 fbdiv_int, fbdiv_frac; + + return get_pll_core_divider(hw, rate, *parent_rate, + &fbdiv_int, &fbdiv_frac); +} + +static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate, + u32 *divider1, u32 *divider2) +{ + unsigned int div1, div2; + unsigned int best_div1 = 7, best_div2 = 7; + unsigned long best_rate_diff = + abs_diff(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate); + unsigned long rate_diff, calc_rate; + + for (div1 = 1; div1 <= 7; div1++) { + for (div2 = 1; div2 <= div1; div2++) { + calc_rate = DIV_ROUND_CLOSEST(parent_rate, div1 * div2); + rate_diff = abs_diff(calc_rate, rate); + + if (calc_rate == rate) { + best_div1 = div1; + best_div2 = div2; + goto done; + } else if (rate_diff < best_rate_diff) { + best_div1 = div1; + best_div2 = div2; + best_rate_diff = rate_diff; + } + } + } + +done: + *divider1 = best_div1; + *divider2 = best_div2; +} + +static int rp1_pll_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll->clockman; + const struct rp1_pll_data *data = pll->data; + + u32 prim, prim_div1, prim_div2; + + get_pll_prim_dividers(rate, parent_rate, &prim_div1, &prim_div2); + + spin_lock(&clockman->regs_lock); + prim = clockman_read(clockman, data->ctrl_reg); + prim &= ~PLL_PRIM_DIV1_MASK; + prim |= FIELD_PREP(PLL_PRIM_DIV1_MASK, prim_div1); + prim &= ~PLL_PRIM_DIV2_MASK; + prim |= FIELD_PREP(PLL_PRIM_DIV2_MASK, prim_div2); + clockman_write(clockman, data->ctrl_reg, prim); + spin_unlock(&clockman->regs_lock); + + return 0; +} + +static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll->clockman; + const struct rp1_pll_data *data = pll->data; + u32 prim, prim_div1, prim_div2; + + prim = clockman_read(clockman, data->ctrl_reg); + prim_div1 = FIELD_GET(PLL_PRIM_DIV1_MASK, prim); + prim_div2 = FIELD_GET(PLL_PRIM_DIV2_MASK, prim); + + if (!prim_div1 || !prim_div2) { + dev_err(clockman->dev, "%s: (%s) zero divider value\n", + __func__, clk_hw_get_name(hw)); + return 0; + } + + return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2); +} + +static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 div1, div2; + + get_pll_prim_dividers(rate, *parent_rate, &div1, &div2); + + return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2); +} + +static int rp1_pll_ph_is_on(struct clk_hw *hw) +{ + struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll_ph->clockman; + const struct rp1_pll_ph_data *data = pll_ph->data; + + return !!(clockman_read(clockman, data->ph_reg) & PLL_PH_EN); +} + +static int rp1_pll_ph_on(struct clk_hw *hw) +{ + struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll_ph->clockman; + const struct rp1_pll_ph_data *data = pll_ph->data; + u32 ph_reg; + + spin_lock(&clockman->regs_lock); + ph_reg = clockman_read(clockman, data->ph_reg); + ph_reg |= data->phase << PLL_PH_PHASE_SHIFT; + ph_reg |= PLL_PH_EN; + clockman_write(clockman, data->ph_reg, ph_reg); + spin_unlock(&clockman->regs_lock); + + return 0; +} + +static void rp1_pll_ph_off(struct clk_hw *hw) +{ + struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = pll_ph->clockman; + const struct rp1_pll_ph_data *data = pll_ph->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->ph_reg, + clockman_read(clockman, data->ph_reg) & ~PLL_PH_EN); + spin_unlock(&clockman->regs_lock); +} + +static unsigned long rp1_pll_ph_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); + const struct rp1_pll_ph_data *data = pll_ph->data; + + return parent_rate / data->fixed_divider; +} + +static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw); + const struct rp1_pll_ph_data *data = pll_ph->data; + + return *parent_rate / data->fixed_divider; +} + +static int rp1_pll_divider_is_on(struct clk_hw *hw) +{ + struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + + return !(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_RST); +} + +static int rp1_pll_divider_on(struct clk_hw *hw) +{ + struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + + spin_lock(&clockman->regs_lock); + /* Check the implementation bit is set! */ + WARN_ON(!(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_IMPL)); + clockman_write(clockman, data->ctrl_reg, + clockman_read(clockman, data->ctrl_reg) & ~PLL_SEC_RST); + spin_unlock(&clockman->regs_lock); + + return 0; +} + +static void rp1_pll_divider_off(struct clk_hw *hw) +{ + struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->ctrl_reg, + clockman_read(clockman, data->ctrl_reg) | PLL_SEC_RST); + spin_unlock(&clockman->regs_lock); +} + +static int rp1_pll_divider_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clockman *clockman = divider->clockman; + const struct rp1_pll_data *data = divider->data; + u32 div, sec; + + div = DIV_ROUND_UP_ULL(parent_rate, rate); + div = clamp(div, 8u, 19u); + + spin_lock(&clockman->regs_lock); + sec = clockman_read(clockman, data->ctrl_reg); + sec &= ~PLL_SEC_DIV_MASK; + sec |= FIELD_PREP(PLL_SEC_DIV_MASK, div); + + /* Must keep the divider in reset to change the value. */ + sec |= PLL_SEC_RST; + clockman_write(clockman, data->ctrl_reg, sec); + + /* must sleep 10 pll vco cycles */ + ndelay(div64_ul(10ULL * div * NSEC_PER_SEC, parent_rate)); + + sec &= ~PLL_SEC_RST; + clockman_write(clockman, data->ctrl_reg, sec); + spin_unlock(&clockman->regs_lock); + + return 0; +} + +static unsigned long rp1_pll_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return clk_divider_ops.recalc_rate(hw, parent_rate); +} + +static long rp1_pll_divider_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate) +{ + return clk_divider_ops.round_rate(hw, rate, parent_rate); +} + +static int rp1_clock_is_on(struct clk_hw *hw) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + + return !!(clockman_read(clockman, data->ctrl_reg) & CLK_CTRL_ENABLE); +} + +static unsigned long rp1_clock_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + u64 calc_rate; + u64 div; + u32 frac; + + div = clockman_read(clockman, data->div_int_reg); + frac = (data->div_frac_reg != 0) ? + clockman_read(clockman, data->div_frac_reg) : 0; + + /* If the integer portion of the divider is 0, treat it as 2^16 */ + if (!div) + div = 1 << 16; + + div = (div << CLK_DIV_FRAC_BITS) | (frac >> (32 - CLK_DIV_FRAC_BITS)); + + calc_rate = (u64)parent_rate << CLK_DIV_FRAC_BITS; + calc_rate = div64_u64(calc_rate, div); + + return calc_rate; +} + +static int rp1_clock_on(struct clk_hw *hw) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->ctrl_reg, + clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE); + /* If this is a GPCLK, turn on the output-enable */ + if (data->oe_mask) + clockman_write(clockman, GPCLK_OE_CTRL, + clockman_read(clockman, GPCLK_OE_CTRL) | data->oe_mask); + spin_unlock(&clockman->regs_lock); + + return 0; +} + +static void rp1_clock_off(struct clk_hw *hw) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + + spin_lock(&clockman->regs_lock); + clockman_write(clockman, data->ctrl_reg, + clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE); + /* If this is a GPCLK, turn off the output-enable */ + if (data->oe_mask) + clockman_write(clockman, GPCLK_OE_CTRL, + clockman_read(clockman, GPCLK_OE_CTRL) & ~data->oe_mask); + spin_unlock(&clockman->regs_lock); +} + +static u32 rp1_clock_choose_div(unsigned long rate, unsigned long parent_rate, + const struct rp1_clock_data *data) +{ + u64 div; + + /* + * Due to earlier rounding, calculated parent_rate may differ from + * expected value. Don't fail on a small discrepancy near unity divide. + */ + if (!rate || rate > parent_rate + (parent_rate >> CLK_DIV_FRAC_BITS)) + return 0; + + /* + * Always express div in fixed-point format for fractional division; + * If no fractional divider is present, the fraction part will be zero. + */ + if (data->div_frac_reg) { + div = (u64)parent_rate << CLK_DIV_FRAC_BITS; + div = DIV_ROUND_CLOSEST_ULL(div, rate); + } else { + div = DIV_ROUND_CLOSEST_ULL(parent_rate, rate); + div <<= CLK_DIV_FRAC_BITS; + } + + div = clamp(div, + 1ull << CLK_DIV_FRAC_BITS, + (u64)data->div_int_max << CLK_DIV_FRAC_BITS); + + return div; +} + +static u8 rp1_clock_get_parent(struct clk_hw *hw) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + u32 sel, ctrl; + u8 parent; + + /* Sel is one-hot, so find the first bit set */ + sel = clockman_read(clockman, data->sel_reg); + parent = ffs(sel) - 1; + + /* sel == 0 implies the parent clock is not enabled yet. */ + if (!sel) { + /* Read the clock src from the CTRL register instead */ + ctrl = clockman_read(clockman, data->ctrl_reg); + parent = (ctrl & data->clk_src_mask) >> CLK_CTRL_SRC_SHIFT; + } + + if (parent >= data->num_std_parents) + parent = AUX_SEL; + + if (parent == AUX_SEL) { + /* + * Clock parent is an auxiliary source, so get the parent from + * the AUXSRC register field. + */ + ctrl = clockman_read(clockman, data->ctrl_reg); + parent = FIELD_GET(CLK_CTRL_AUXSRC_MASK, ctrl); + parent += data->num_std_parents; + } + + return parent; +} + +static int rp1_clock_set_parent(struct clk_hw *hw, u8 index) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + u32 ctrl, sel; + + spin_lock(&clockman->regs_lock); + ctrl = clockman_read(clockman, data->ctrl_reg); + + if (index >= data->num_std_parents) { + /* This is an aux source request */ + if (index >= data->num_std_parents + data->num_aux_parents) { + spin_unlock(&clockman->regs_lock); + return -EINVAL; + } + + /* Select parent from aux list */ + ctrl &= ~CLK_CTRL_AUXSRC_MASK; + ctrl |= FIELD_PREP(CLK_CTRL_AUXSRC_MASK, index - data->num_std_parents); + /* Set src to aux list */ + ctrl &= ~data->clk_src_mask; + ctrl |= (AUX_SEL << CLK_CTRL_SRC_SHIFT) & data->clk_src_mask; + } else { + ctrl &= ~data->clk_src_mask; + ctrl |= (index << CLK_CTRL_SRC_SHIFT) & data->clk_src_mask; + } + + clockman_write(clockman, data->ctrl_reg, ctrl); + spin_unlock(&clockman->regs_lock); + + sel = rp1_clock_get_parent(hw); + if (sel != index) + return -EINVAL; + + return 0; +} + +static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u8 parent) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clockman *clockman = clock->clockman; + const struct rp1_clock_data *data = clock->data; + u32 div = rp1_clock_choose_div(rate, parent_rate, data); + + spin_lock(&clockman->regs_lock); + + clockman_write(clockman, data->div_int_reg, div >> CLK_DIV_FRAC_BITS); + if (data->div_frac_reg) + clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS)); + + spin_unlock(&clockman->regs_lock); + + if (parent != 0xff) + return rp1_clock_set_parent(hw, parent); + + return 0; +} + +static int rp1_clock_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return rp1_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff); +} + +static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, + int parent_idx, + unsigned long rate, + unsigned long *prate, + unsigned long *calc_rate) +{ + struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); + const struct rp1_clock_data *data = clock->data; + struct clk_hw *parent; + u32 div; + u64 tmp; + + parent = clk_hw_get_parent_by_index(hw, parent_idx); + + *prate = clk_hw_get_rate(parent); + div = rp1_clock_choose_div(rate, *prate, data); + + if (!div) { + *calc_rate = 0; + return; + } + + /* Recalculate to account for rounding errors */ + tmp = (u64)*prate << CLK_DIV_FRAC_BITS; + tmp = div_u64(tmp, div); + + /* + * Prevent overclocks - if all parent choices result in + * a downstream clock in excess of the maximum, then the + * call to set the clock will fail. + */ + if (tmp > data->max_freq) + *calc_rate = 0; + else + *calc_rate = tmp; +} + +static int rp1_clock_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *parent, *best_parent = NULL; + unsigned long best_rate = 0; + unsigned long best_prate = 0; + unsigned long best_rate_diff = ULONG_MAX; + unsigned long prate, calc_rate; + size_t i; + + /* + * If the NO_REPARENT flag is set, try to use existing parent. + */ + if ((clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT)) { + i = rp1_clock_get_parent(hw); + parent = clk_hw_get_parent_by_index(hw, i); + if (parent) { + rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate, + &calc_rate); + if (calc_rate > 0) { + req->best_parent_hw = parent; + req->best_parent_rate = prate; + req->rate = calc_rate; + return 0; + } + } + } + + /* + * Select parent clock that results in the closest rate (lower or + * higher) + */ + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + parent = clk_hw_get_parent_by_index(hw, i); + if (!parent) + continue; + + rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate, + &calc_rate); + + if (abs_diff(calc_rate, req->rate) < best_rate_diff) { + best_parent = parent; + best_prate = prate; + best_rate = calc_rate; + best_rate_diff = abs_diff(calc_rate, req->rate); + + if (best_rate_diff == 0) + break; + } + } + + if (best_rate == 0) + return -EINVAL; + + req->best_parent_hw = best_parent; + req->best_parent_rate = best_prate; + req->rate = best_rate; + + return 0; +} + +static const struct clk_ops rp1_pll_core_ops = { + .is_prepared = rp1_pll_core_is_on, + .prepare = rp1_pll_core_on, + .unprepare = rp1_pll_core_off, + .set_rate = rp1_pll_core_set_rate, + .recalc_rate = rp1_pll_core_recalc_rate, + .round_rate = rp1_pll_core_round_rate, +}; + +static const struct clk_ops rp1_pll_ops = { + .set_rate = rp1_pll_set_rate, + .recalc_rate = rp1_pll_recalc_rate, + .round_rate = rp1_pll_round_rate, +}; + +static const struct clk_ops rp1_pll_ph_ops = { + .is_prepared = rp1_pll_ph_is_on, + .prepare = rp1_pll_ph_on, + .unprepare = rp1_pll_ph_off, + .recalc_rate = rp1_pll_ph_recalc_rate, + .round_rate = rp1_pll_ph_round_rate, +}; + +static const struct clk_ops rp1_pll_divider_ops = { + .is_prepared = rp1_pll_divider_is_on, + .prepare = rp1_pll_divider_on, + .unprepare = rp1_pll_divider_off, + .set_rate = rp1_pll_divider_set_rate, + .recalc_rate = rp1_pll_divider_recalc_rate, + .round_rate = rp1_pll_divider_round_rate, +}; + +static const struct clk_ops rp1_clk_ops = { + .is_prepared = rp1_clock_is_on, + .prepare = rp1_clock_on, + .unprepare = rp1_clock_off, + .recalc_rate = rp1_clock_recalc_rate, + .get_parent = rp1_clock_get_parent, + .set_parent = rp1_clock_set_parent, + .set_rate_and_parent = rp1_clock_set_rate_and_parent, + .set_rate = rp1_clock_set_rate, + .determine_rate = rp1_clock_determine_rate, +}; + +static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc) +{ + int ret; + + desc->clockman = clockman; + + ret = devm_clk_hw_register(clockman->dev, &desc->hw); + if (ret) + return ERR_PTR(ret); + + return &desc->hw; +} + +static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc) +{ + const struct rp1_pll_data *divider_data = desc->data; + int ret; + + desc->div.reg = clockman->regs + divider_data->ctrl_reg; + desc->div.shift = __ffs(PLL_SEC_DIV_MASK); + desc->div.width = __ffs(~(PLL_SEC_DIV_MASK >> desc->div.shift)); + desc->div.flags = CLK_DIVIDER_ROUND_CLOSEST; + desc->div.lock = &clockman->regs_lock; + desc->div.hw.init = desc->hw.init; + desc->div.table = pll_sec_div_table; + + desc->clockman = clockman; + + ret = devm_clk_hw_register(clockman->dev, &desc->div.hw); + if (ret) + return ERR_PTR(ret); + + return &desc->div.hw; +} + +static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc) +{ + const struct rp1_clock_data *clock_data = desc->data; + int ret; + + if (WARN_ON_ONCE(MAX_CLK_PARENTS < + clock_data->num_std_parents + clock_data->num_aux_parents)) + return ERR_PTR(-EINVAL); + + /* There must be a gap for the AUX selector */ + if (WARN_ON_ONCE(clock_data->num_std_parents > AUX_SEL && + desc->hw.init->parent_data[AUX_SEL].index != -1)) + return ERR_PTR(-EINVAL); + + desc->clockman = clockman; + + ret = devm_clk_hw_register(clockman->dev, &desc->hw); + if (ret) + return ERR_PTR(ret); + + return &desc->hw; +} + +/* Assignment helper macros for different clock types. */ +#define _REGISTER(f, ...) { .clk_register = f, __VA_ARGS__ } + +#define CLK_DATA(type, ...) .data = &(struct type) { __VA_ARGS__ } + +#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, \ + __VA_ARGS__) + +#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \ + __VA_ARGS__) + +#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, \ + __VA_ARGS__) + +static struct rp1_clk_desc pll_sys_core_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_core", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_pll_core_ops, + CLK_IS_CRITICAL + ), + CLK_DATA(rp1_pll_core_data, + .cs_reg = PLL_SYS_CS, + .pwr_reg = PLL_SYS_PWR, + .fbdiv_int_reg = PLL_SYS_FBDIV_INT, + .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, + ) +); + +static struct rp1_clk_desc pll_audio_core_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_core", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_pll_core_ops, + CLK_IS_CRITICAL + ), + CLK_DATA(rp1_pll_core_data, + .cs_reg = PLL_AUDIO_CS, + .pwr_reg = PLL_AUDIO_PWR, + .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, + .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, + ) +); + +static struct rp1_clk_desc pll_video_core_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_core", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_pll_core_ops, + CLK_IS_CRITICAL + ), + CLK_DATA(rp1_pll_core_data, + .cs_reg = PLL_VIDEO_CS, + .pwr_reg = PLL_VIDEO_PWR, + .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, + .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, + ) +); + +static struct rp1_clk_desc pll_sys_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys", + (const struct clk_parent_data[]) { + { .hw = &pll_sys_core_desc.hw } + }, + &rp1_pll_ops, + 0 + ), + CLK_DATA(rp1_pll_data, + .ctrl_reg = PLL_SYS_PRIM, + .fc0_src = FC_NUM(0, 2), + ) +); + +static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_sec", + (const struct clk_parent_data[]) { + { .hw = &pll_sys_core_desc.hw } + }, + &rp1_pll_divider_ops, + 0 + ), + CLK_DATA(rp1_pll_data, + .ctrl_reg = PLL_SYS_SEC, + .fc0_src = FC_NUM(2, 2), + ) +); + +static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_eth_tsu", + (const struct clk_parent_data[]) { { .index = 0 } }, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_ETH_TSU_CTRL, + .div_int_reg = CLK_ETH_TSU_DIV_INT, + .sel_reg = CLK_ETH_TSU_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 7), + ) +); + +static const struct clk_parent_data clk_eth_parents[] = { + { .hw = &pll_sys_sec_desc.div.hw }, + { .hw = &pll_sys_desc.hw }, +}; + +static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_eth", + clk_eth_parents, + &rp1_clk_ops, + 0 + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 0, + .num_aux_parents = 2, + .ctrl_reg = CLK_ETH_CTRL, + .div_int_reg = CLK_ETH_DIV_INT, + .sel_reg = CLK_ETH_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 125 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 6), + ) +); + +static const struct clk_parent_data clk_sys_parents[] = { + { .index = 0 }, + { .index = -1 }, + { .hw = &pll_sys_desc.hw }, +}; + +static struct rp1_clk_desc clk_sys_desc = REGISTER_CLK( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sys", + clk_sys_parents, + &rp1_clk_ops, + CLK_IS_CRITICAL + ), + CLK_DATA(rp1_clock_data, + .num_std_parents = 3, + .num_aux_parents = 0, + .ctrl_reg = CLK_SYS_CTRL, + .div_int_reg = CLK_SYS_DIV_INT, + .sel_reg = CLK_SYS_SEL, + .div_int_max = DIV_INT_24BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 4), + .clk_src_mask = 0x3, + ) +); + +static struct rp1_clk_desc pll_sys_pri_ph_desc = REGISTER_PLL( + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_pri_ph", + (const struct clk_parent_data[]) { + { .hw = &pll_sys_desc.hw } + }, + &rp1_pll_ph_ops, + 0 + ), + CLK_DATA(rp1_pll_ph_data, + .ph_reg = PLL_SYS_PRIM, + .fixed_divider = 2, + .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(1, 2), + ) +); + +static struct rp1_clk_desc *const clk_desc_array[] = { + [RP1_PLL_SYS_CORE] = &pll_sys_core_desc, + [RP1_PLL_AUDIO_CORE] = &pll_audio_core_desc, + [RP1_PLL_VIDEO_CORE] = &pll_video_core_desc, + [RP1_PLL_SYS] = &pll_sys_desc, + [RP1_CLK_ETH_TSU] = &clk_eth_tsu_desc, + [RP1_CLK_ETH] = &clk_eth_desc, + [RP1_CLK_SYS] = &clk_sys_desc, + [RP1_PLL_SYS_PRI_PH] = &pll_sys_pri_ph_desc, + [RP1_PLL_SYS_SEC] = &pll_sys_sec_desc, +}; + +static const struct regmap_range rp1_reg_ranges[] = { + regmap_reg_range(PLL_SYS_CS, PLL_SYS_SEC), + regmap_reg_range(PLL_AUDIO_CS, PLL_AUDIO_TERN), + regmap_reg_range(PLL_VIDEO_CS, PLL_VIDEO_SEC), + regmap_reg_range(GPCLK_OE_CTRL, GPCLK_OE_CTRL), + regmap_reg_range(CLK_SYS_CTRL, CLK_SYS_DIV_INT), + regmap_reg_range(CLK_SYS_SEL, CLK_SYS_SEL), + regmap_reg_range(CLK_SLOW_SYS_CTRL, CLK_SLOW_SYS_DIV_INT), + regmap_reg_range(CLK_SLOW_SYS_SEL, CLK_SLOW_SYS_SEL), + regmap_reg_range(CLK_DMA_CTRL, CLK_DMA_DIV_INT), + regmap_reg_range(CLK_DMA_SEL, CLK_DMA_SEL), + regmap_reg_range(CLK_UART_CTRL, CLK_UART_DIV_INT), + regmap_reg_range(CLK_UART_SEL, CLK_UART_SEL), + regmap_reg_range(CLK_ETH_CTRL, CLK_ETH_DIV_INT), + regmap_reg_range(CLK_ETH_SEL, CLK_ETH_SEL), + regmap_reg_range(CLK_PWM0_CTRL, CLK_PWM0_SEL), + regmap_reg_range(CLK_PWM1_CTRL, CLK_PWM1_SEL), + regmap_reg_range(CLK_AUDIO_IN_CTRL, CLK_AUDIO_IN_DIV_INT), + regmap_reg_range(CLK_AUDIO_IN_SEL, CLK_AUDIO_IN_SEL), + regmap_reg_range(CLK_AUDIO_OUT_CTRL, CLK_AUDIO_OUT_DIV_INT), + regmap_reg_range(CLK_AUDIO_OUT_SEL, CLK_AUDIO_OUT_SEL), + regmap_reg_range(CLK_I2S_CTRL, CLK_I2S_DIV_INT), + regmap_reg_range(CLK_I2S_SEL, CLK_I2S_SEL), + regmap_reg_range(CLK_MIPI0_CFG_CTRL, CLK_MIPI0_CFG_DIV_INT), + regmap_reg_range(CLK_MIPI0_CFG_SEL, CLK_MIPI0_CFG_SEL), + regmap_reg_range(CLK_MIPI1_CFG_CTRL, CLK_MIPI1_CFG_DIV_INT), + regmap_reg_range(CLK_MIPI1_CFG_SEL, CLK_MIPI1_CFG_SEL), + regmap_reg_range(CLK_PCIE_AUX_CTRL, CLK_PCIE_AUX_DIV_INT), + regmap_reg_range(CLK_PCIE_AUX_SEL, CLK_PCIE_AUX_SEL), + regmap_reg_range(CLK_USBH0_MICROFRAME_CTRL, CLK_USBH0_MICROFRAME_DIV_INT), + regmap_reg_range(CLK_USBH0_MICROFRAME_SEL, CLK_USBH0_MICROFRAME_SEL), + regmap_reg_range(CLK_USBH1_MICROFRAME_CTRL, CLK_USBH1_MICROFRAME_DIV_INT), + regmap_reg_range(CLK_USBH1_MICROFRAME_SEL, CLK_USBH1_MICROFRAME_SEL), + regmap_reg_range(CLK_USBH0_SUSPEND_CTRL, CLK_USBH0_SUSPEND_DIV_INT), + regmap_reg_range(CLK_USBH0_SUSPEND_SEL, CLK_USBH0_SUSPEND_SEL), + regmap_reg_range(CLK_USBH1_SUSPEND_CTRL, CLK_USBH1_SUSPEND_DIV_INT), + regmap_reg_range(CLK_USBH1_SUSPEND_SEL, CLK_USBH1_SUSPEND_SEL), + regmap_reg_range(CLK_ETH_TSU_CTRL, CLK_ETH_TSU_DIV_INT), + regmap_reg_range(CLK_ETH_TSU_SEL, CLK_ETH_TSU_SEL), + regmap_reg_range(CLK_ADC_CTRL, CLK_ADC_DIV_INT), + regmap_reg_range(CLK_ADC_SEL, CLK_ADC_SEL), + regmap_reg_range(CLK_SDIO_TIMER_CTRL, CLK_SDIO_TIMER_DIV_INT), + regmap_reg_range(CLK_SDIO_TIMER_SEL, CLK_SDIO_TIMER_SEL), + regmap_reg_range(CLK_SDIO_ALT_SRC_CTRL, CLK_SDIO_ALT_SRC_DIV_INT), + regmap_reg_range(CLK_SDIO_ALT_SRC_SEL, CLK_SDIO_ALT_SRC_SEL), + regmap_reg_range(CLK_GP0_CTRL, CLK_GP0_SEL), + regmap_reg_range(CLK_GP1_CTRL, CLK_GP1_SEL), + regmap_reg_range(CLK_GP2_CTRL, CLK_GP2_SEL), + regmap_reg_range(CLK_GP3_CTRL, CLK_GP3_SEL), + regmap_reg_range(CLK_GP4_CTRL, CLK_GP4_SEL), + regmap_reg_range(CLK_GP5_CTRL, CLK_GP5_SEL), + regmap_reg_range(CLK_SYS_RESUS_CTRL, CLK_SYS_RESUS_CTRL), + regmap_reg_range(CLK_SLOW_SYS_RESUS_CTRL, CLK_SLOW_SYS_RESUS_CTRL), + regmap_reg_range(FC0_REF_KHZ, FC0_RESULT), + regmap_reg_range(VIDEO_CLK_VEC_CTRL, VIDEO_CLK_VEC_DIV_INT), + regmap_reg_range(VIDEO_CLK_VEC_SEL, VIDEO_CLK_DPI_DIV_INT), + regmap_reg_range(VIDEO_CLK_DPI_SEL, VIDEO_CLK_MIPI1_DPI_SEL), +}; + +static const struct regmap_access_table rp1_reg_table = { + .yes_ranges = rp1_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(rp1_reg_ranges), +}; + +static const struct regmap_config rp1_clk_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = PLL_VIDEO_SEC, + .name = "rp1-clk", + .rd_table = &rp1_reg_table, + .disable_locking = true, +}; + +static int rp1_clk_probe(struct platform_device *pdev) +{ + const size_t asize = ARRAY_SIZE(clk_desc_array); + struct rp1_clk_desc *desc; + struct device *dev = &pdev->dev; + struct rp1_clockman *clockman; + struct clk_hw **hws; + unsigned int i; + + clockman = devm_kzalloc(dev, struct_size(clockman, onecell.hws, asize), + GFP_KERNEL); + if (!clockman) + return -ENOMEM; + + spin_lock_init(&clockman->regs_lock); + clockman->dev = dev; + + clockman->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clockman->regs)) + return PTR_ERR(clockman->regs); + + clockman->regmap = devm_regmap_init_mmio(dev, clockman->regs, + &rp1_clk_regmap_cfg); + if (IS_ERR(clockman->regmap)) { + dev_err_probe(dev, PTR_ERR(clockman->regmap), + "could not init clock regmap\n"); + return PTR_ERR(clockman->regmap); + } + + clockman->onecell.num = asize; + hws = clockman->onecell.hws; + + for (i = 0; i < asize; i++) { + desc = clk_desc_array[i]; + if (desc && desc->clk_register && desc->data) + hws[i] = desc->clk_register(clockman, desc); + } + + platform_set_drvdata(pdev, clockman); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &clockman->onecell); +} + +static const struct of_device_id rp1_clk_of_match[] = { + { .compatible = "raspberrypi,rp1-clocks" }, + {} +}; +MODULE_DEVICE_TABLE(of, rp1_clk_of_match); + +static struct platform_driver rp1_clk_driver = { + .driver = { + .name = "rp1-clk", + .of_match_table = rp1_clk_of_match, + }, + .probe = rp1_clk_probe, +}; + +module_platform_driver(rp1_clk_driver); + +MODULE_AUTHOR("Naushir Patuck "); +MODULE_AUTHOR("Andrea della Porta "); +MODULE_DESCRIPTION("RP1 clock driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 4732f079cd19f313516047726d934fabc58e9119 Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Thu, 29 May 2025 15:50:42 +0200 Subject: pinctrl: rp1: Implement RaspberryPi RP1 gpio support The RP1 is an MFD supporting a gpio controller and /pinmux/pinctrl. Add minimum support for the gpio only portion. The driver is in pinctrl folder since upcoming patches will add the pinmux/pinctrl support where the gpio part can be seen as an addition. Signed-off-by: Andrea della Porta Reviewed-by: Linus Walleij Reviewed-by: Stefan Wahren Link: https://lore.kernel.org/r/20250529135052.28398-5-andrea.porta@suse.com Signed-off-by: Florian Fainelli --- drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-rp1.c | 790 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 802 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-rp1.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 33db9104df17..eb1b37af81fb 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -624,6 +624,17 @@ config PINCTRL_MLXBF3 each pin. This driver can also be built as a module called pinctrl-mlxbf3. +config PINCTRL_RP1 + tristate "Pinctrl driver for RP1" + depends on MISC_RP1 + default MISC_RP1 + select PINMUX + select PINCONF + select GENERIC_PINCONF + help + Enable the gpio and pinctrl/mux driver for RaspberryPi RP1 + multi function device. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index ac27e88677d1..65dac8e38798 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o +obj-$(CONFIG_PINCTRL_RP1) += pinctrl-rp1.o obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o diff --git a/drivers/pinctrl/pinctrl-rp1.c b/drivers/pinctrl/pinctrl-rp1.c new file mode 100644 index 000000000000..07d54bb6bc19 --- /dev/null +++ b/drivers/pinctrl/pinctrl-rp1.c @@ -0,0 +1,790 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Raspberry Pi RP1 GPIO unit + * + * Copyright (C) 2023 Raspberry Pi Ltd. + * + * This driver is inspired by: + * pinctrl-bcm2835.c, please see original file for copyright information + */ + +#include +#include +#include +#include + +#define MODULE_NAME "pinctrl-rp1" +#define RP1_NUM_GPIOS 54 +#define RP1_NUM_BANKS 3 + +#define RP1_INT_EDGE_FALLING BIT(0) +#define RP1_INT_EDGE_RISING BIT(1) +#define RP1_INT_LEVEL_LOW BIT(2) +#define RP1_INT_LEVEL_HIGH BIT(3) +#define RP1_INT_MASK GENMASK(3, 0) +#define RP1_INT_EDGE_BOTH (RP1_INT_EDGE_FALLING | \ + RP1_INT_EDGE_RISING) + +#define RP1_FSEL_COUNT 9 + +#define RP1_FSEL_ALT0 0x00 +#define RP1_FSEL_GPIO 0x05 +#define RP1_FSEL_NONE 0x09 +#define RP1_FSEL_NONE_HW 0x1f + +#define RP1_PAD_DRIVE_2MA 0x0 +#define RP1_PAD_DRIVE_4MA 0x1 +#define RP1_PAD_DRIVE_8MA 0x2 +#define RP1_PAD_DRIVE_12MA 0x3 + +enum { + RP1_PUD_OFF = 0, + RP1_PUD_DOWN = 1, + RP1_PUD_UP = 2, +}; + +enum { + RP1_DIR_OUTPUT = 0, + RP1_DIR_INPUT = 1, +}; + +enum { + RP1_OUTOVER_PERI = 0, + RP1_OUTOVER_INVPERI = 1, + RP1_OUTOVER_LOW = 2, + RP1_OUTOVER_HIGH = 3, +}; + +enum { + RP1_OEOVER_PERI = 0, + RP1_OEOVER_INVPERI = 1, + RP1_OEOVER_DISABLE = 2, + RP1_OEOVER_ENABLE = 3, +}; + +enum { + RP1_INOVER_PERI = 0, + RP1_INOVER_INVPERI = 1, + RP1_INOVER_LOW = 2, + RP1_INOVER_HIGH = 3, +}; + +enum { + RP1_GPIO_CTRL_IRQRESET_SET = 0, + RP1_GPIO_CTRL_INT_CLR = 1, + RP1_GPIO_CTRL_INT_SET = 2, + RP1_GPIO_CTRL_OEOVER = 3, + RP1_GPIO_CTRL_FUNCSEL = 4, + RP1_GPIO_CTRL_OUTOVER = 5, + RP1_GPIO_CTRL = 6, +}; + +enum { + RP1_INTE_SET = 0, + RP1_INTE_CLR = 1, +}; + +enum { + RP1_RIO_OUT_SET = 0, + RP1_RIO_OUT_CLR = 1, + RP1_RIO_OE = 2, + RP1_RIO_OE_SET = 3, + RP1_RIO_OE_CLR = 4, + RP1_RIO_IN = 5, +}; + +enum { + RP1_PAD_SLEWFAST = 0, + RP1_PAD_SCHMITT = 1, + RP1_PAD_PULL = 2, + RP1_PAD_DRIVE = 3, + RP1_PAD_IN_ENABLE = 4, + RP1_PAD_OUT_DISABLE = 5, +}; + +static const struct reg_field rp1_gpio_fields[] = { + [RP1_GPIO_CTRL_IRQRESET_SET] = REG_FIELD(0x2004, 28, 28), + [RP1_GPIO_CTRL_INT_CLR] = REG_FIELD(0x3004, 20, 23), + [RP1_GPIO_CTRL_INT_SET] = REG_FIELD(0x2004, 20, 23), + [RP1_GPIO_CTRL_OEOVER] = REG_FIELD(0x0004, 14, 15), + [RP1_GPIO_CTRL_FUNCSEL] = REG_FIELD(0x0004, 0, 4), + [RP1_GPIO_CTRL_OUTOVER] = REG_FIELD(0x0004, 12, 13), + [RP1_GPIO_CTRL] = REG_FIELD(0x0004, 0, 31), +}; + +static const struct reg_field rp1_inte_fields[] = { + [RP1_INTE_SET] = REG_FIELD(0x2000, 0, 0), + [RP1_INTE_CLR] = REG_FIELD(0x3000, 0, 0), +}; + +static const struct reg_field rp1_rio_fields[] = { + [RP1_RIO_OUT_SET] = REG_FIELD(0x2000, 0, 0), + [RP1_RIO_OUT_CLR] = REG_FIELD(0x3000, 0, 0), + [RP1_RIO_OE] = REG_FIELD(0x0004, 0, 0), + [RP1_RIO_OE_SET] = REG_FIELD(0x2004, 0, 0), + [RP1_RIO_OE_CLR] = REG_FIELD(0x3004, 0, 0), + [RP1_RIO_IN] = REG_FIELD(0x0008, 0, 0), +}; + +static const struct reg_field rp1_pad_fields[] = { + [RP1_PAD_SLEWFAST] = REG_FIELD(0, 0, 0), + [RP1_PAD_SCHMITT] = REG_FIELD(0, 1, 1), + [RP1_PAD_PULL] = REG_FIELD(0, 2, 3), + [RP1_PAD_DRIVE] = REG_FIELD(0, 4, 5), + [RP1_PAD_IN_ENABLE] = REG_FIELD(0, 6, 6), + [RP1_PAD_OUT_DISABLE] = REG_FIELD(0, 7, 7), +}; + +struct rp1_iobank_desc { + int min_gpio; + int num_gpios; + int gpio_offset; + int inte_offset; + int ints_offset; + int rio_offset; + int pads_offset; +}; + +struct rp1_pin_info { + u8 num; + u8 bank; + u8 offset; + u8 fsel; + u8 irq_type; + + struct regmap_field *gpio[ARRAY_SIZE(rp1_gpio_fields)]; + struct regmap_field *rio[ARRAY_SIZE(rp1_rio_fields)]; + struct regmap_field *inte[ARRAY_SIZE(rp1_inte_fields)]; + struct regmap_field *pad[ARRAY_SIZE(rp1_pad_fields)]; +}; + +struct rp1_pinctrl { + struct device *dev; + void __iomem *gpio_base; + void __iomem *rio_base; + void __iomem *pads_base; + int irq[RP1_NUM_BANKS]; + struct rp1_pin_info pins[RP1_NUM_GPIOS]; + + struct pinctrl_dev *pctl_dev; + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range gpio_range; + + raw_spinlock_t irq_lock[RP1_NUM_BANKS]; +}; + +static const struct rp1_iobank_desc rp1_iobanks[RP1_NUM_BANKS] = { + /* gpio inte ints rio pads */ + { 0, 28, 0x0000, 0x011c, 0x0124, 0x0000, 0x0004 }, + { 28, 6, 0x4000, 0x411c, 0x4124, 0x4000, 0x4004 }, + { 34, 20, 0x8000, 0x811c, 0x8124, 0x8000, 0x8004 }, +}; + +static int rp1_pinconf_set(struct rp1_pin_info *pin, + unsigned int offset, unsigned long *configs, + unsigned int num_configs); + +static struct rp1_pin_info *rp1_get_pin(struct gpio_chip *chip, + unsigned int offset) +{ + struct rp1_pinctrl *pc = gpiochip_get_data(chip); + + if (pc && offset < RP1_NUM_GPIOS) + return &pc->pins[offset]; + return NULL; +} + +static void rp1_input_enable(struct rp1_pin_info *pin, int value) +{ + regmap_field_write(pin->pad[RP1_PAD_IN_ENABLE], !!value); +} + +static void rp1_output_enable(struct rp1_pin_info *pin, int value) +{ + regmap_field_write(pin->pad[RP1_PAD_OUT_DISABLE], !value); +} + +static u32 rp1_get_fsel(struct rp1_pin_info *pin) +{ + u32 oeover, fsel; + + regmap_field_read(pin->gpio[RP1_GPIO_CTRL_OEOVER], &oeover); + regmap_field_read(pin->gpio[RP1_GPIO_CTRL_FUNCSEL], &fsel); + + if (oeover != RP1_OEOVER_PERI || fsel >= RP1_FSEL_COUNT) + fsel = RP1_FSEL_NONE; + + return fsel; +} + +static void rp1_set_fsel(struct rp1_pin_info *pin, u32 fsel) +{ + if (fsel >= RP1_FSEL_COUNT) + fsel = RP1_FSEL_NONE_HW; + + rp1_input_enable(pin, 1); + rp1_output_enable(pin, 1); + + if (fsel == RP1_FSEL_NONE) { + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_OEOVER], RP1_OEOVER_DISABLE); + } else { + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_OUTOVER], RP1_OUTOVER_PERI); + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_OEOVER], RP1_OEOVER_PERI); + } + + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_FUNCSEL], fsel); +} + +static int rp1_get_dir(struct rp1_pin_info *pin) +{ + unsigned int val; + + regmap_field_read(pin->rio[RP1_RIO_OE], &val); + + return !val ? RP1_DIR_INPUT : RP1_DIR_OUTPUT; +} + +static void rp1_set_dir(struct rp1_pin_info *pin, bool is_input) +{ + int reg = is_input ? RP1_RIO_OE_CLR : RP1_RIO_OE_SET; + + regmap_field_write(pin->rio[reg], 1); +} + +static int rp1_get_value(struct rp1_pin_info *pin) +{ + unsigned int val; + + regmap_field_read(pin->rio[RP1_RIO_IN], &val); + + return !!val; +} + +static void rp1_set_value(struct rp1_pin_info *pin, int value) +{ + /* Assume the pin is already an output */ + int reg = value ? RP1_RIO_OUT_SET : RP1_RIO_OUT_CLR; + + regmap_field_write(pin->rio[reg], 1); +} + +static int rp1_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rp1_pin_info *pin = rp1_get_pin(chip, offset); + int ret; + + if (!pin) + return -EINVAL; + + ret = rp1_get_value(pin); + + return ret; +} + +static void rp1_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct rp1_pin_info *pin = rp1_get_pin(chip, offset); + + if (pin) + rp1_set_value(pin, value); +} + +static int rp1_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct rp1_pin_info *pin = rp1_get_pin(chip, offset); + u32 fsel; + + if (!pin) + return -EINVAL; + + fsel = rp1_get_fsel(pin); + if (fsel != RP1_FSEL_GPIO) + return -EINVAL; + + return (rp1_get_dir(pin) == RP1_DIR_OUTPUT) ? + GPIO_LINE_DIRECTION_OUT : + GPIO_LINE_DIRECTION_IN; +} + +static int rp1_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct rp1_pin_info *pin = rp1_get_pin(chip, offset); + + if (!pin) + return -EINVAL; + rp1_set_dir(pin, RP1_DIR_INPUT); + rp1_set_fsel(pin, RP1_FSEL_GPIO); + + return 0; +} + +static int rp1_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct rp1_pin_info *pin = rp1_get_pin(chip, offset); + + if (!pin) + return -EINVAL; + rp1_set_value(pin, value); + rp1_set_dir(pin, RP1_DIR_OUTPUT); + rp1_set_fsel(pin, RP1_FSEL_GPIO); + + return 0; +} + +static int rp1_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + struct rp1_pin_info *pin = rp1_get_pin(chip, offset); + unsigned long configs[] = { config }; + + return rp1_pinconf_set(pin, offset, configs, + ARRAY_SIZE(configs)); +} + +static const struct gpio_chip rp1_gpio_chip = { + .label = MODULE_NAME, + .owner = THIS_MODULE, + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .direction_input = rp1_gpio_direction_input, + .direction_output = rp1_gpio_direction_output, + .get_direction = rp1_gpio_get_direction, + .get = rp1_gpio_get, + .set = rp1_gpio_set, + .base = -1, + .set_config = rp1_gpio_set_config, + .ngpio = RP1_NUM_GPIOS, + .can_sleep = false, +}; + +static void rp1_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct irq_chip *host_chip = irq_desc_get_chip(desc); + struct rp1_pinctrl *pc = gpiochip_get_data(chip); + const struct rp1_iobank_desc *bank; + int irq = irq_desc_get_irq(desc); + unsigned long ints; + int bit_pos; + + if (pc->irq[0] == irq) + bank = &rp1_iobanks[0]; + else if (pc->irq[1] == irq) + bank = &rp1_iobanks[1]; + else + bank = &rp1_iobanks[2]; + + chained_irq_enter(host_chip, desc); + + ints = readl(pc->gpio_base + bank->ints_offset); + for_each_set_bit(bit_pos, &ints, 32) { + struct rp1_pin_info *pin = rp1_get_pin(chip, bit_pos); + + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_IRQRESET_SET], 1); + generic_handle_irq(irq_find_mapping(pc->gpio_chip.irq.domain, + bank->gpio_offset + bit_pos)); + } + + chained_irq_exit(host_chip, desc); +} + +static void rp1_gpio_irq_config(struct rp1_pin_info *pin, bool enable) +{ + int reg = enable ? RP1_INTE_SET : RP1_INTE_CLR; + + regmap_field_write(pin->inte[reg], 1); + if (!enable) + /* Clear any latched events */ + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_IRQRESET_SET], 1); +} + +static void rp1_gpio_irq_enable(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + unsigned int gpio = irqd_to_hwirq(data); + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio); + + rp1_gpio_irq_config(pin, true); +} + +static void rp1_gpio_irq_disable(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + unsigned int gpio = irqd_to_hwirq(data); + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio); + + rp1_gpio_irq_config(pin, false); +} + +static int rp1_irq_set_type(struct rp1_pin_info *pin, unsigned int type) +{ + u32 irq_flags; + + switch (type) { + case IRQ_TYPE_NONE: + irq_flags = 0; + break; + case IRQ_TYPE_EDGE_RISING: + irq_flags = RP1_INT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + irq_flags = RP1_INT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + irq_flags = RP1_INT_EDGE_RISING | RP1_INT_EDGE_FALLING; + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_flags = RP1_INT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + irq_flags = RP1_INT_LEVEL_LOW; + break; + + default: + return -EINVAL; + } + + /* Clear them all */ + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_INT_CLR], RP1_INT_MASK); + + /* Set those that are needed */ + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_INT_SET], irq_flags); + pin->irq_type = type; + + return 0; +} + +static int rp1_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + unsigned int gpio = irqd_to_hwirq(data); + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio); + struct rp1_pinctrl *pc = gpiochip_get_data(chip); + int bank = pin->bank; + unsigned long flags; + int ret; + + raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); + + ret = rp1_irq_set_type(pin, type); + if (!ret) { + if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(data, handle_edge_irq); + else + irq_set_handler_locked(data, handle_level_irq); + } + + raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); + + return ret; +} + +static void rp1_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + unsigned int gpio = irqd_to_hwirq(data); + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio); + + /* Clear any latched events */ + regmap_field_write(pin->gpio[RP1_GPIO_CTRL_IRQRESET_SET], 1); +} + +static struct irq_chip rp1_gpio_irq_chip = { + .name = MODULE_NAME, + .irq_enable = rp1_gpio_irq_enable, + .irq_disable = rp1_gpio_irq_disable, + .irq_set_type = rp1_gpio_irq_set_type, + .irq_ack = rp1_gpio_irq_ack, + .irq_mask = rp1_gpio_irq_disable, + .irq_unmask = rp1_gpio_irq_enable, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void rp1_pull_config_set(struct rp1_pin_info *pin, unsigned int arg) +{ + regmap_field_write(pin->pad[RP1_PAD_PULL], arg & 0x3); +} + +static int rp1_pinconf_set(struct rp1_pin_info *pin, unsigned int offset, + unsigned long *configs, unsigned int num_configs) +{ + u32 param, arg; + int i; + + if (!pin) + return -EINVAL; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + rp1_pull_config_set(pin, RP1_PUD_OFF); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + rp1_pull_config_set(pin, RP1_PUD_DOWN); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + rp1_pull_config_set(pin, RP1_PUD_UP); + break; + + case PIN_CONFIG_INPUT_ENABLE: + rp1_input_enable(pin, arg); + break; + + case PIN_CONFIG_OUTPUT_ENABLE: + rp1_output_enable(pin, arg); + break; + + case PIN_CONFIG_OUTPUT: + rp1_set_value(pin, arg); + rp1_set_dir(pin, RP1_DIR_OUTPUT); + rp1_set_fsel(pin, RP1_FSEL_GPIO); + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + regmap_field_write(pin->pad[RP1_PAD_SCHMITT], !!arg); + break; + + case PIN_CONFIG_SLEW_RATE: + regmap_field_write(pin->pad[RP1_PAD_SLEWFAST], !!arg); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + switch (arg) { + case 2: + arg = RP1_PAD_DRIVE_2MA; + break; + case 4: + arg = RP1_PAD_DRIVE_4MA; + break; + case 8: + arg = RP1_PAD_DRIVE_8MA; + break; + case 12: + arg = RP1_PAD_DRIVE_12MA; + break; + default: + return -ENOTSUPP; + } + regmap_field_write(pin->pad[RP1_PAD_DRIVE], arg); + break; + + default: + return -ENOTSUPP; + + } /* switch param type */ + } /* for each config */ + + return 0; +} + +static const struct of_device_id rp1_pinctrl_match[] = { + { .compatible = "raspberrypi,rp1-gpio" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rp1_pinctrl_match); + +static struct rp1_pinctrl rp1_pinctrl_data = {}; + +static const struct regmap_config rp1_pinctrl_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, + .name = "rp1-pinctrl", +}; + +static int rp1_gen_regfield(struct device *dev, + const struct reg_field *array, + size_t array_size, + int reg_off, + int pin_off, + bool additive_offset, + struct regmap *regmap, + struct regmap_field *out[]) +{ + struct reg_field regfield; + int k; + + for (k = 0; k < array_size; k++) { + regfield = array[k]; + regfield.reg = (additive_offset ? regfield.reg : 0) + reg_off; + if (pin_off >= 0) { + regfield.lsb = pin_off; + regfield.msb = regfield.lsb; + } + out[k] = devm_regmap_field_alloc(dev, regmap, regfield); + + if (IS_ERR(out[k])) + return PTR_ERR(out[k]); + } + + return 0; +} + +static int rp1_pinctrl_probe(struct platform_device *pdev) +{ + struct regmap *gpio_regmap, *rio_regmap, *pads_regmap; + struct rp1_pinctrl *pc = &rp1_pinctrl_data; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct gpio_irq_chip *girq; + int err, i; + + pc->dev = dev; + pc->gpio_chip = rp1_gpio_chip; + pc->gpio_chip.parent = dev; + + pc->gpio_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pc->gpio_base)) + return dev_err_probe(dev, PTR_ERR(pc->gpio_base), "could not get GPIO IO memory\n"); + + pc->rio_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(pc->rio_base)) + return dev_err_probe(dev, PTR_ERR(pc->rio_base), "could not get RIO IO memory\n"); + + pc->pads_base = devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(pc->pads_base)) + return dev_err_probe(dev, PTR_ERR(pc->pads_base), "could not get PADS IO memory\n"); + + gpio_regmap = devm_regmap_init_mmio(dev, pc->gpio_base, + &rp1_pinctrl_regmap_cfg); + if (IS_ERR(gpio_regmap)) + return dev_err_probe(dev, PTR_ERR(gpio_regmap), "could not init GPIO regmap\n"); + + rio_regmap = devm_regmap_init_mmio(dev, pc->rio_base, + &rp1_pinctrl_regmap_cfg); + if (IS_ERR(rio_regmap)) + return dev_err_probe(dev, PTR_ERR(rio_regmap), "could not init RIO regmap\n"); + + pads_regmap = devm_regmap_init_mmio(dev, pc->pads_base, + &rp1_pinctrl_regmap_cfg); + if (IS_ERR(pads_regmap)) + return dev_err_probe(dev, PTR_ERR(pads_regmap), "could not init PADS regmap\n"); + + for (i = 0; i < RP1_NUM_BANKS; i++) { + const struct rp1_iobank_desc *bank = &rp1_iobanks[i]; + int j; + + for (j = 0; j < bank->num_gpios; j++) { + struct rp1_pin_info *pin = + &pc->pins[bank->min_gpio + j]; + int reg_off; + + pin->num = bank->min_gpio + j; + pin->bank = i; + pin->offset = j; + + reg_off = bank->gpio_offset + pin->offset * + sizeof(u32) * 2; + err = rp1_gen_regfield(dev, + rp1_gpio_fields, + ARRAY_SIZE(rp1_gpio_fields), + reg_off, + -1, + true, + gpio_regmap, + pin->gpio); + + if (err) + return dev_err_probe(dev, err, + "Unable to allocate regmap for gpio\n"); + + reg_off = bank->inte_offset; + err = rp1_gen_regfield(dev, + rp1_inte_fields, + ARRAY_SIZE(rp1_inte_fields), + reg_off, + pin->offset, + true, + gpio_regmap, + pin->inte); + + if (err) + return dev_err_probe(dev, err, + "Unable to allocate regmap for inte\n"); + + reg_off = bank->rio_offset; + err = rp1_gen_regfield(dev, + rp1_rio_fields, + ARRAY_SIZE(rp1_rio_fields), + reg_off, + pin->offset, + true, + rio_regmap, + pin->rio); + + if (err) + return dev_err_probe(dev, err, + "Unable to allocate regmap for rio\n"); + + reg_off = bank->pads_offset + pin->offset * sizeof(u32); + err = rp1_gen_regfield(dev, + rp1_pad_fields, + ARRAY_SIZE(rp1_pad_fields), + reg_off, + -1, + false, + pads_regmap, + pin->pad); + + if (err) + return dev_err_probe(dev, err, + "Unable to allocate regmap for pad\n"); + } + + raw_spin_lock_init(&pc->irq_lock[i]); + } + + girq = &pc->gpio_chip.irq; + girq->chip = &rp1_gpio_irq_chip; + girq->parent_handler = rp1_gpio_irq_handler; + girq->num_parents = RP1_NUM_BANKS; + girq->parents = pc->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + + /* + * Use the same handler for all groups: this is necessary + * since we use one gpiochip to cover all lines - the + * irq handler then needs to figure out which group and + * bank that was firing the IRQ and look up the per-group + * and bank data. + */ + for (i = 0; i < RP1_NUM_BANKS; i++) { + pc->irq[i] = irq_of_parse_and_map(np, i); + if (!pc->irq[i]) { + girq->num_parents = i; + break; + } + } + + platform_set_drvdata(pdev, pc); + + err = devm_gpiochip_add_data(dev, &pc->gpio_chip, pc); + if (err) + return dev_err_probe(dev, err, "could not add GPIO chip\n"); + + return 0; +} + +static struct platform_driver rp1_pinctrl_driver = { + .probe = rp1_pinctrl_probe, + .driver = { + .name = MODULE_NAME, + .of_match_table = rp1_pinctrl_match, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(rp1_pinctrl_driver); + +MODULE_AUTHOR("Phil Elwell "); +MODULE_AUTHOR("Andrea della Porta "); +MODULE_DESCRIPTION("RP1 pinctrl/gpio driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 49d63971f96349cdcff89d21786e3c804e7cd4c0 Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Thu, 29 May 2025 15:50:44 +0200 Subject: misc: rp1: RaspberryPi RP1 misc driver The RaspberryPi RP1 is a PCI multi function device containing peripherals ranging from Ethernet to USB controller, I2C, SPI and others. Implement a bare minimum driver to operate the RP1, leveraging actual OF based driver implementations for the on-board peripherals by loading a devicetree overlay during driver probe if the RP1 node is not already present in the DT. The peripherals are accessed by mapping MMIO registers starting from PCI BAR1 region. With the overlay approach we can achieve more generic and agnostic approach to managing this chipset, being that it is a PCI endpoint and could possibly be reused in other hw implementations. The presented approach is also used by Bootlin's Microchip LAN966x patchset (see link) as well, for a similar chipset. In this case, the inclusion tree for the DT overlay is as follow (the arrow points to the includer): rp1-pci.dtso <---- rp1-common.dtsi On the other hand, to ensure compatibility with downstream, this driver can also work with a DT already comprising the RP1 node, so the dynamically loaded overlay will not be used if the DT is already fully defined. The reason why this driver is contained in drivers/misc has been paved by Bootlin's LAN966X driver, which first used the overlay approach to implement non discoverable peripherals behind a PCI bus. For RP1, the same arguments apply: it's not used as an SoC since the driver code is not running on-chip and is not like an MFD since it does not really need all the MFD infrastructure (shared regs, etc.). So, for this particular use, misc has been proposed and deemed as a good choice. For further details about that please check the links. This driver is heavily based on downstream code from RaspberryPi Foundation, and the original author is Phil Elwell. Link: https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf Link: https://lore.kernel.org/all/20240612140208.GC1504919@google.com/ Link: https://lore.kernel.org/all/83f7fa09-d0e6-4f36-a27d-cee08979be2a@app.fastmail.com/ Link: https://lore.kernel.org/all/2024081356-mutable-everyday-6f9d@gregkh/ Link: https://lore.kernel.org/all/20240808154658.247873-1-herve.codina@bootlin.com/ Signed-off-by: Andrea della Porta Acked-by: Bjorn Helgaas # quirks.c, pci_ids.h Acked-by: Greg Kroah-Hartman Link: https://lore.kernel.org/r/20250529135052.28398-7-andrea.porta@suse.com Signed-off-by: Florian Fainelli --- drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/rp1/Kconfig | 20 +++ drivers/misc/rp1/Makefile | 3 + drivers/misc/rp1/rp1-pci.dtso | 25 ++++ drivers/misc/rp1/rp1_pci.c | 333 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/quirks.c | 1 + include/linux/pci_ids.h | 3 + 8 files changed, 387 insertions(+) create mode 100644 drivers/misc/rp1/Kconfig create mode 100644 drivers/misc/rp1/Makefile create mode 100644 drivers/misc/rp1/rp1-pci.dtso create mode 100644 drivers/misc/rp1/rp1_pci.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b9ca56930003..b9c11f67315f 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -660,4 +660,5 @@ source "drivers/misc/pvpanic/Kconfig" source "drivers/misc/mchp_pci1xxxx/Kconfig" source "drivers/misc/keba/Kconfig" source "drivers/misc/amd-sbi/Kconfig" +source "drivers/misc/rp1/Kconfig" endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 917b9a7183aa..e2e66f5f4fb8 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -75,3 +75,4 @@ lan966x-pci-objs += lan966x_pci.dtbo.o obj-$(CONFIG_MCHP_LAN966X_PCI) += lan966x-pci.o obj-y += keba/ obj-y += amd-sbi/ +obj-$(CONFIG_MISC_RP1) += rp1/ diff --git a/drivers/misc/rp1/Kconfig b/drivers/misc/rp1/Kconfig new file mode 100644 index 000000000000..5232e70d3079 --- /dev/null +++ b/drivers/misc/rp1/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# RaspberryPi RP1 misc device +# + +config MISC_RP1 + tristate "RaspberryPi RP1 misc device" + depends on OF_IRQ && OF_OVERLAY && PCI_MSI && PCI_QUIRKS + select PCI_DYNAMIC_OF_NODES + help + Support the RP1 peripheral chip found on Raspberry Pi 5 board. + + This device supports several sub-devices including e.g. Ethernet + controller, USB controller, I2C, SPI and UART. + + The driver is responsible for enabling the DT node once the PCIe + endpoint has been configured, and handling interrupts. + + This driver uses an overlay to load other drivers to support for + RP1 internal sub-devices. diff --git a/drivers/misc/rp1/Makefile b/drivers/misc/rp1/Makefile new file mode 100644 index 000000000000..508b4cb05627 --- /dev/null +++ b/drivers/misc/rp1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MISC_RP1) += rp1-pci.o +rp1-pci-objs := rp1_pci.o rp1-pci.dtbo.o diff --git a/drivers/misc/rp1/rp1-pci.dtso b/drivers/misc/rp1/rp1-pci.dtso new file mode 100644 index 000000000000..eea826b36e02 --- /dev/null +++ b/drivers/misc/rp1/rp1-pci.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * The dts overlay is included from the dts directory so + * it can be possible to check it with CHECK_DTBS while + * also compile it from the driver source directory. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path=""; + __overlay__ { + compatible = "pci1de4,1"; + #address-cells = <3>; + #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + #include "arm64/broadcom/rp1-common.dtsi" + }; + }; +}; diff --git a/drivers/misc/rp1/rp1_pci.c b/drivers/misc/rp1/rp1_pci.c new file mode 100644 index 000000000000..803832006ec8 --- /dev/null +++ b/drivers/misc/rp1/rp1_pci.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2025 Raspberry Pi Ltd. + * + * All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RP1_HW_IRQ_MASK GENMASK(5, 0) + +#define REG_SET 0x800 +#define REG_CLR 0xc00 + +/* MSI-X CFG registers start at 0x8 */ +#define MSIX_CFG(x) (0x8 + (4 * (x))) + +#define MSIX_CFG_IACK_EN BIT(3) +#define MSIX_CFG_IACK BIT(2) +#define MSIX_CFG_ENABLE BIT(0) + +/* Address map */ +#define RP1_PCIE_APBS_BASE 0x108000 + +/* Interrupts */ +#define RP1_INT_END 61 + +/* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.lib */ +extern char __dtbo_rp1_pci_begin[]; +extern char __dtbo_rp1_pci_end[]; + +struct rp1_dev { + struct pci_dev *pdev; + struct irq_domain *domain; + struct irq_data *pcie_irqds[64]; + void __iomem *bar1; + int ovcs_id; /* overlay changeset id */ + bool level_triggered_irq[RP1_INT_END]; +}; + +static void msix_cfg_set(struct rp1_dev *rp1, unsigned int hwirq, u32 value) +{ + iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq)); +} + +static void msix_cfg_clr(struct rp1_dev *rp1, unsigned int hwirq, u32 value) +{ + iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); +} + +static void rp1_mask_irq(struct irq_data *irqd) +{ + struct rp1_dev *rp1 = irqd->domain->host_data; + struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq]; + + pci_msi_mask_irq(pcie_irqd); +} + +static void rp1_unmask_irq(struct irq_data *irqd) +{ + struct rp1_dev *rp1 = irqd->domain->host_data; + struct irq_data *pcie_irqd = rp1->pcie_irqds[irqd->hwirq]; + + pci_msi_unmask_irq(pcie_irqd); +} + +static int rp1_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct rp1_dev *rp1 = irqd->domain->host_data; + unsigned int hwirq = (unsigned int)irqd->hwirq; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + dev_dbg(&rp1->pdev->dev, "MSIX IACK EN for IRQ %u\n", hwirq); + msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK_EN); + rp1->level_triggered_irq[hwirq] = true; + break; + case IRQ_TYPE_EDGE_RISING: + msix_cfg_clr(rp1, hwirq, MSIX_CFG_IACK_EN); + rp1->level_triggered_irq[hwirq] = false; + break; + default: + return -EINVAL; + } + + return 0; +} + +static struct irq_chip rp1_irq_chip = { + .name = "rp1_irq_chip", + .irq_mask = rp1_mask_irq, + .irq_unmask = rp1_unmask_irq, + .irq_set_type = rp1_irq_set_type, +}; + +static void rp1_chained_handle_irq(struct irq_desc *desc) +{ + unsigned int hwirq = desc->irq_data.hwirq & RP1_HW_IRQ_MASK; + struct rp1_dev *rp1 = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int virq; + + chained_irq_enter(chip, desc); + + virq = irq_find_mapping(rp1->domain, hwirq); + generic_handle_irq(virq); + if (rp1->level_triggered_irq[hwirq]) + msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK); + + chained_irq_exit(chip, desc); +} + +static int rp1_irq_xlate(struct irq_domain *d, struct device_node *node, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, unsigned int *out_type) +{ + struct rp1_dev *rp1 = d->host_data; + struct irq_data *pcie_irqd; + unsigned long hwirq; + int pcie_irq; + int ret; + + ret = irq_domain_xlate_twocell(d, node, intspec, intsize, + &hwirq, out_type); + if (ret) + return ret; + + pcie_irq = pci_irq_vector(rp1->pdev, hwirq); + pcie_irqd = irq_get_irq_data(pcie_irq); + rp1->pcie_irqds[hwirq] = pcie_irqd; + *out_hwirq = hwirq; + + return 0; +} + +static int rp1_irq_activate(struct irq_domain *d, struct irq_data *irqd, + bool reserve) +{ + struct rp1_dev *rp1 = d->host_data; + + msix_cfg_set(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE); + + return 0; +} + +static void rp1_irq_deactivate(struct irq_domain *d, struct irq_data *irqd) +{ + struct rp1_dev *rp1 = d->host_data; + + msix_cfg_clr(rp1, (unsigned int)irqd->hwirq, MSIX_CFG_ENABLE); +} + +static const struct irq_domain_ops rp1_domain_ops = { + .xlate = rp1_irq_xlate, + .activate = rp1_irq_activate, + .deactivate = rp1_irq_deactivate, +}; + +static void rp1_unregister_interrupts(struct pci_dev *pdev) +{ + struct rp1_dev *rp1 = pci_get_drvdata(pdev); + int irq, i; + + if (rp1->domain) { + for (i = 0; i < RP1_INT_END; i++) { + irq = irq_find_mapping(rp1->domain, i); + irq_dispose_mapping(irq); + } + + irq_domain_remove(rp1->domain); + } + + pci_free_irq_vectors(pdev); +} + +static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + u32 dtbo_size = __dtbo_rp1_pci_end - __dtbo_rp1_pci_begin; + void *dtbo_start = __dtbo_rp1_pci_begin; + struct device *dev = &pdev->dev; + struct device_node *rp1_node; + bool skip_ovl = true; + struct rp1_dev *rp1; + int err = 0; + int i; + + /* + * Either use rp1_nexus node if already present in DT, or + * set a flag to load it from overlay at runtime + */ + rp1_node = of_find_node_by_name(NULL, "rp1_nexus"); + if (!rp1_node) { + rp1_node = dev_of_node(dev); + skip_ovl = false; + } + + if (!rp1_node) { + dev_err(dev, "Missing of_node for device\n"); + err = -EINVAL; + goto err_put_node; + } + + rp1 = devm_kzalloc(&pdev->dev, sizeof(*rp1), GFP_KERNEL); + if (!rp1) { + err = -ENOMEM; + goto err_put_node; + } + + rp1->pdev = pdev; + + if (pci_resource_len(pdev, 1) <= 0x10000) { + dev_err(&pdev->dev, + "Not initialized - is the firmware running?\n"); + err = -EINVAL; + goto err_put_node; + } + + err = pcim_enable_device(pdev); + if (err < 0) { + err = dev_err_probe(&pdev->dev, err, + "Enabling PCI device has failed"); + goto err_put_node; + } + + rp1->bar1 = pcim_iomap(pdev, 1, 0); + if (!rp1->bar1) { + dev_err(&pdev->dev, "Cannot map PCI BAR\n"); + err = -EIO; + goto err_put_node; + } + + pci_set_master(pdev); + + err = pci_alloc_irq_vectors(pdev, RP1_INT_END, RP1_INT_END, + PCI_IRQ_MSIX); + if (err < 0) { + err = dev_err_probe(&pdev->dev, err, + "Failed to allocate MSI-X vectors\n"); + goto err_put_node; + } else if (err != RP1_INT_END) { + dev_err(&pdev->dev, "Cannot allocate enough interrupts\n"); + err = -EINVAL; + goto err_put_node; + } + + pci_set_drvdata(pdev, rp1); + rp1->domain = irq_domain_add_linear(rp1_node, RP1_INT_END, + &rp1_domain_ops, rp1); + if (!rp1->domain) { + dev_err(&pdev->dev, "Error creating IRQ domain\n"); + err = -ENOMEM; + goto err_unregister_interrupts; + } + + for (i = 0; i < RP1_INT_END; i++) { + unsigned int irq = irq_create_mapping(rp1->domain, i); + + if (!irq) { + dev_err(&pdev->dev, "Failed to create IRQ mapping\n"); + err = -EINVAL; + goto err_unregister_interrupts; + } + + irq_set_chip_and_handler(irq, &rp1_irq_chip, handle_level_irq); + irq_set_probe(irq); + irq_set_chained_handler_and_data(pci_irq_vector(pdev, i), + rp1_chained_handle_irq, rp1); + } + + if (!skip_ovl) { + err = of_overlay_fdt_apply(dtbo_start, dtbo_size, &rp1->ovcs_id, + rp1_node); + if (err) + goto err_unregister_interrupts; + } + + err = of_platform_default_populate(rp1_node, NULL, dev); + if (err) { + dev_err_probe(&pdev->dev, err, "Error populating devicetree\n"); + goto err_unload_overlay; + } + + return 0; + +err_unload_overlay: + of_overlay_remove(&rp1->ovcs_id); +err_unregister_interrupts: + rp1_unregister_interrupts(pdev); +err_put_node: + if (skip_ovl) + of_node_put(rp1_node); + + return err; +} + +static void rp1_remove(struct pci_dev *pdev) +{ + struct rp1_dev *rp1 = pci_get_drvdata(pdev); + struct device *dev = &pdev->dev; + + of_platform_depopulate(dev); + of_overlay_remove(&rp1->ovcs_id); + rp1_unregister_interrupts(pdev); +} + +static const struct pci_device_id dev_id_table[] = { + { PCI_DEVICE(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0), }, + { } +}; +MODULE_DEVICE_TABLE(pci, dev_id_table); + +static struct pci_driver rp1_driver = { + .name = KBUILD_MODNAME, + .id_table = dev_id_table, + .probe = rp1_probe, + .remove = rp1_remove, +}; + +module_pci_driver(rp1_driver); + +MODULE_AUTHOR("Phil Elwell "); +MODULE_AUTHOR("Andrea della Porta "); +MODULE_DESCRIPTION("RaspberryPi RP1 misc device"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d7f4ee634263..cf483d82572c 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6303,6 +6303,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0, of_pci_make_dev_node); /* * Devices known to require a longer delay before first config space access diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index e2d71b6fdd84..92ffc4373f6d 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2624,6 +2624,9 @@ #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 +#define PCI_VENDOR_ID_RPI 0x1de4 +#define PCI_DEVICE_ID_RPI_RP1_C0 0x0001 + #define PCI_VENDOR_ID_ALIBABA 0x1ded #define PCI_VENDOR_ID_CXL 0x1e98 -- cgit v1.2.3 From e3ce7b897388339b407d57969acaa26063e38209 Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Tue, 24 Jun 2025 17:36:22 +0200 Subject: pinctrl: rp1: Implement RaspberryPi RP1 pinmux/pinconf support The current implementation for the pin controller peripheral on the RP1 chipset supports gpio functionality and just the basic configuration of pin hw capabilities. Add support for selecting the pin alternate function (pinmux) and full configuration of the pin (pinconf). Related pins are also gathered into groups. Signed-off-by: Andrea della Porta Acked-by: Linus Walleij Link: https://lore.kernel.org/all/8c282b89b1aa8b9e3c00f6bd3980332c47d82df7.1750778806.git.andrea.porta@suse.com/ Signed-off-by: Florian Fainelli --- drivers/pinctrl/pinctrl-rp1.c | 1049 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1044 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rp1.c b/drivers/pinctrl/pinctrl-rp1.c index 07d54bb6bc19..d300f28c52cd 100644 --- a/drivers/pinctrl/pinctrl-rp1.c +++ b/drivers/pinctrl/pinctrl-rp1.c @@ -10,9 +10,16 @@ #include #include +#include +#include #include +#include #include +#include "pinmux.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + #define MODULE_NAME "pinctrl-rp1" #define RP1_NUM_GPIOS 54 #define RP1_NUM_BANKS 3 @@ -135,6 +142,104 @@ static const struct reg_field rp1_pad_fields[] = { [RP1_PAD_OUT_DISABLE] = REG_FIELD(0, 7, 7), }; +#define FUNC(f) \ + [func_##f] = #f +#define RP1_MAX_FSEL 8 +#define PIN(i, f0, f1, f2, f3, f4, f5, f6, f7, f8) \ + [i] = { \ + .funcs = { \ + func_##f0, \ + func_##f1, \ + func_##f2, \ + func_##f3, \ + func_##f4, \ + func_##f5, \ + func_##f6, \ + func_##f7, \ + func_##f8, \ + }, \ + } + +#define LEGACY_MAP(n, f0, f1, f2, f3, f4, f5) \ + [n] = { \ + func_gpio, \ + func_gpio, \ + func_##f5, \ + func_##f4, \ + func_##f0, \ + func_##f1, \ + func_##f2, \ + func_##f3, \ + } + +enum funcs { + func_alt0, + func_alt1, + func_alt2, + func_alt3, + func_alt4, + func_gpio, + func_alt6, + func_alt7, + func_alt8, + func_none, + func_aaud, + func_dpi, + func_dsi0_te_ext, + func_dsi1_te_ext, + func_gpclk0, + func_gpclk1, + func_gpclk2, + func_gpclk3, + func_gpclk4, + func_gpclk5, + func_i2c0, + func_i2c1, + func_i2c2, + func_i2c3, + func_i2c4, + func_i2c5, + func_i2c6, + func_i2s0, + func_i2s1, + func_i2s2, + func_ir, + func_mic, + func_pcie_clkreq_n, + func_pio, + func_proc_rio, + func_pwm0, + func_pwm1, + func_sd0, + func_sd1, + func_spi0, + func_spi1, + func_spi2, + func_spi3, + func_spi4, + func_spi5, + func_spi6, + func_spi7, + func_spi8, + func_uart0, + func_uart1, + func_uart2, + func_uart3, + func_uart4, + func_uart5, + func_vbus0, + func_vbus1, + func_vbus2, + func_vbus3, + func__, + func_count = func__, + func_invalid = func__, +}; + +struct rp1_pin_funcs { + u8 funcs[RP1_FSEL_COUNT]; +}; + struct rp1_iobank_desc { int min_gpio; int num_gpios; @@ -173,6 +278,389 @@ struct rp1_pinctrl { raw_spinlock_t irq_lock[RP1_NUM_BANKS]; }; +/* pins are just named GPIO0..GPIO53 */ +#define RP1_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) +static struct pinctrl_pin_desc rp1_gpio_pins[] = { + RP1_GPIO_PIN(0), + RP1_GPIO_PIN(1), + RP1_GPIO_PIN(2), + RP1_GPIO_PIN(3), + RP1_GPIO_PIN(4), + RP1_GPIO_PIN(5), + RP1_GPIO_PIN(6), + RP1_GPIO_PIN(7), + RP1_GPIO_PIN(8), + RP1_GPIO_PIN(9), + RP1_GPIO_PIN(10), + RP1_GPIO_PIN(11), + RP1_GPIO_PIN(12), + RP1_GPIO_PIN(13), + RP1_GPIO_PIN(14), + RP1_GPIO_PIN(15), + RP1_GPIO_PIN(16), + RP1_GPIO_PIN(17), + RP1_GPIO_PIN(18), + RP1_GPIO_PIN(19), + RP1_GPIO_PIN(20), + RP1_GPIO_PIN(21), + RP1_GPIO_PIN(22), + RP1_GPIO_PIN(23), + RP1_GPIO_PIN(24), + RP1_GPIO_PIN(25), + RP1_GPIO_PIN(26), + RP1_GPIO_PIN(27), + RP1_GPIO_PIN(28), + RP1_GPIO_PIN(29), + RP1_GPIO_PIN(30), + RP1_GPIO_PIN(31), + RP1_GPIO_PIN(32), + RP1_GPIO_PIN(33), + RP1_GPIO_PIN(34), + RP1_GPIO_PIN(35), + RP1_GPIO_PIN(36), + RP1_GPIO_PIN(37), + RP1_GPIO_PIN(38), + RP1_GPIO_PIN(39), + RP1_GPIO_PIN(40), + RP1_GPIO_PIN(41), + RP1_GPIO_PIN(42), + RP1_GPIO_PIN(43), + RP1_GPIO_PIN(44), + RP1_GPIO_PIN(45), + RP1_GPIO_PIN(46), + RP1_GPIO_PIN(47), + RP1_GPIO_PIN(48), + RP1_GPIO_PIN(49), + RP1_GPIO_PIN(50), + RP1_GPIO_PIN(51), + RP1_GPIO_PIN(52), + RP1_GPIO_PIN(53), +}; + +#define PIN_ARRAY(...) \ + (const unsigned int []) {__VA_ARGS__} +#define PIN_ARRAY_SIZE(...) \ + (sizeof((unsigned int[]) {__VA_ARGS__}) / sizeof(unsigned int)) +#define RP1_GROUP(name, ...) \ + PINCTRL_PINGROUP(#name, PIN_ARRAY(__VA_ARGS__), \ + PIN_ARRAY_SIZE(__VA_ARGS__)) + +static const struct pingroup rp1_gpio_groups[] = { + RP1_GROUP(uart0, 14, 15), + RP1_GROUP(uart0_ctrl, 4, 5, 6, 7, 16, 17), + RP1_GROUP(uart1, 0, 1), + RP1_GROUP(uart1_ctrl, 2, 3), + RP1_GROUP(uart2, 4, 5), + RP1_GROUP(uart2_ctrl, 6, 7), + RP1_GROUP(uart3, 8, 9), + RP1_GROUP(uart3_ctrl, 10, 11), + RP1_GROUP(uart4, 12, 13), + RP1_GROUP(uart4_ctrl, 14, 15), + RP1_GROUP(uart5_0, 30, 31), + RP1_GROUP(uart5_0_ctrl, 32, 33), + RP1_GROUP(uart5_1, 36, 37), + RP1_GROUP(uart5_1_ctrl, 38, 39), + RP1_GROUP(uart5_2, 40, 41), + RP1_GROUP(uart5_2_ctrl, 42, 43), + RP1_GROUP(uart5_3, 48, 49), + RP1_GROUP(sd0, 22, 23, 24, 25, 26, 27), + RP1_GROUP(sd1, 28, 29, 30, 31, 32, 33), + RP1_GROUP(i2s0, 18, 19, 20, 21), + RP1_GROUP(i2s0_dual, 18, 19, 20, 21, 22, 23), + RP1_GROUP(i2s0_quad, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27), + RP1_GROUP(i2s1, 18, 19, 20, 21), + RP1_GROUP(i2s1_dual, 18, 19, 20, 21, 22, 23), + RP1_GROUP(i2s1_quad, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27), + RP1_GROUP(i2s2_0, 28, 29, 30, 31), + RP1_GROUP(i2s2_0_dual, 28, 29, 30, 31, 32, 33), + RP1_GROUP(i2s2_1, 42, 43, 44, 45), + RP1_GROUP(i2s2_1_dual, 42, 43, 44, 45, 46, 47), + RP1_GROUP(i2c4_0, 28, 29), + RP1_GROUP(i2c4_1, 34, 35), + RP1_GROUP(i2c4_2, 40, 41), + RP1_GROUP(i2c4_3, 46, 47), + RP1_GROUP(i2c6_0, 38, 39), + RP1_GROUP(i2c6_1, 51, 52), + RP1_GROUP(i2c5_0, 30, 31), + RP1_GROUP(i2c5_1, 36, 37), + RP1_GROUP(i2c5_2, 44, 45), + RP1_GROUP(i2c5_3, 49, 50), + RP1_GROUP(i2c0_0, 0, 1), + RP1_GROUP(i2c0_1, 8, 9), + RP1_GROUP(i2c1_0, 2, 3), + RP1_GROUP(i2c1_1, 10, 11), + RP1_GROUP(i2c2_0, 4, 5), + RP1_GROUP(i2c2_1, 12, 13), + RP1_GROUP(i2c3_0, 6, 7), + RP1_GROUP(i2c3_1, 14, 15), + RP1_GROUP(i2c3_2, 22, 23), + RP1_GROUP(dpi_16bit, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19), + RP1_GROUP(dpi_16bit_cpadhi, 0, 1, 2, 3, 4, 5, 6, 7, 8, + 12, 13, 14, 15, 16, 17, 20, 21, 22, 23, 24), + RP1_GROUP(dpi_16bit_pad666, 0, 1, 2, 3, 5, 6, 7, 8, 9, + 12, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25), + RP1_GROUP(dpi_18bit, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21), + RP1_GROUP(dpi_18bit_cpadhi, 0, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 12, 13, 14, 15, 16, 17, 20, 21, 22, 23, 24, + 25), + RP1_GROUP(dpi_24bit, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 27), + RP1_GROUP(spi0, 9, 10, 11), + RP1_GROUP(spi0_quad, 0, 1, 9, 10, 11), + RP1_GROUP(spi1, 19, 20, 21), + RP1_GROUP(spi2, 1, 2, 3), + RP1_GROUP(spi3, 5, 6, 7), + RP1_GROUP(spi4, 9, 10, 11), + RP1_GROUP(spi5, 13, 14, 15), + RP1_GROUP(spi6_0, 28, 29, 30), + RP1_GROUP(spi6_1, 40, 41, 42), + RP1_GROUP(spi7_0, 46, 47, 48), + RP1_GROUP(spi7_1, 49, 50, 51), + RP1_GROUP(spi8_0, 37, 38, 39), + RP1_GROUP(spi8_1, 49, 50, 51), + RP1_GROUP(aaud_0, 12, 13), + RP1_GROUP(aaud_1, 38, 39), + RP1_GROUP(aaud_2, 40, 41), + RP1_GROUP(aaud_3, 49, 50), + RP1_GROUP(aaud_4, 51, 52), + RP1_GROUP(vbus0_0, 28, 29), + RP1_GROUP(vbus0_1, 34, 35), + RP1_GROUP(vbus1, 42, 43), + RP1_GROUP(vbus2, 50, 51), + RP1_GROUP(vbus3, 52, 53), + RP1_GROUP(mic_0, 25, 26, 27), + RP1_GROUP(mic_1, 34, 35, 36), + RP1_GROUP(mic_2, 37, 38, 39), + RP1_GROUP(mic_3, 46, 47, 48), + RP1_GROUP(ir, 2, 3), +}; + +#define GRP_ARRAY(...) \ + (const char * []) {__VA_ARGS__} +#define GRP_ARRAY_SIZE(...) \ + (sizeof((char *[]) {__VA_ARGS__}) / sizeof(char *)) +#define RP1_FNC(f, ...) \ + [func_##f] = PINCTRL_PINFUNCTION(#f, GRP_ARRAY(__VA_ARGS__), \ + GRP_ARRAY_SIZE(__VA_ARGS__)) +#define RP1_NULL_FNC(f) \ + [func_##f] = PINCTRL_PINFUNCTION(#f, NULL, 0) +#define RP1_ALL_LEGACY_PINS \ + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", \ + "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", \ + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", \ + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", \ + "gpio20", "gpio21", "gpio22", "gpio32", "gpio24", \ + "gpio25", "gpio26", "gpio27" +#define RP1_ALL_PINS RP1_ALL_LEGACY_PINS, \ + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", \ + "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", \ + "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", \ + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", \ + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", \ + "gpio53" + +static const struct pinfunction rp1_func_names[] = { + RP1_NULL_FNC(alt0), + RP1_NULL_FNC(alt1), + RP1_NULL_FNC(alt2), + RP1_NULL_FNC(alt3), + RP1_NULL_FNC(alt4), + RP1_FNC(gpio, RP1_ALL_PINS), + RP1_NULL_FNC(alt6), + RP1_NULL_FNC(alt7), + RP1_NULL_FNC(alt8), + RP1_NULL_FNC(none), + RP1_FNC(aaud, "aaud_0", "aaud_1", "aaud_2", "aaud_3", "aaud_4", + "gpio12", "gpio13", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio49", "gpio50", "gpio51", "gpio52"), + RP1_FNC(dpi, "dpi_16bit", "dpi_16bit_cpadhi", + "dpi_16bit_pad666", "dpi_18bit, dpi_18bit_cpadhi", + "dpi_24bit", RP1_ALL_LEGACY_PINS), + RP1_FNC(dsi0_te_ext, "gpio16", "gpio38", "gpio46"), + RP1_FNC(dsi1_te_ext, "gpio17", "gpio39", "gpio47"), + RP1_FNC(gpclk0, "gpio4", "gpio20"), + RP1_FNC(gpclk1, "gpio5", "gpio18", "gpio21"), + RP1_FNC(gpclk2, "gpio6"), + RP1_FNC(gpclk3, "gpio32", "gpio34", "gpio46"), + RP1_FNC(gpclk4, "gpio33", "gpio43"), + RP1_FNC(gpclk5, "gpio42", "gpio44", "gpio47"), + RP1_FNC(i2c0, "i2c0_0", "i2c0_1", "gpio0", "gpio1", "gpio8", "gpio9"), + RP1_FNC(i2c1, "i2c1_0", "i2c1_1", "gpio2", "gpio3", "gpio10", "gpio11"), + RP1_FNC(i2c2, "i2c2_0", "i2c2_1", "gpio4", "gpio5", "gpio12", "gpio13"), + RP1_FNC(i2c3, "i2c3_0", "i2c3_1", "i2c3_2", "gpio6", "gpio7", "gpio14", + "gpio15", "gpio22", "gpio23"), + RP1_FNC(i2c4, "i2c4_0", "i2c4_1", "i2c4_2", "i2c4_3", "gpio28", + "gpio29", "gpio34", "gpio35", "gpio40", "gpio41", "gpio46", + "gpio47"), + RP1_FNC(i2c5, "i2c5_0", "i2c5_1", "i2c5_2", "i2c5_3", "gpio30", + "gpio31", "gpio36", "gpio37", "gpio44", "gpio45", "gpio49", + "gpio50"), + RP1_FNC(i2c6, "i2c6_0", "i2c6_1", "gpio38", "gpio39", "gpio51", + "gpio52"), + RP1_FNC(i2s0, "i2s0", "i2s0_dual", "i2s0_quad", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", + "gpio26", "gpio27"), + RP1_FNC(i2s1, "i2s1", "i2s1_dual", "i2s1_quad", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", + "gpio26", "gpio27"), + RP1_FNC(i2s2, "i2s2_0", "i2s2_0_dual", "i2s2_1", "i2s2_1_dual", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47"), + RP1_FNC(ir, "gpio2", "gpio3"), + RP1_FNC(mic, "mic_0", "mic_1", "mic_2", "mic_3", "gpio25", "gpio26", + "gpio27", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", + "gpio39", "gpio46", "gpio47", "gpio48"), + RP1_FNC(pcie_clkreq_n, "gpio36", "gpio37", "gpio48", "gpio53"), + RP1_FNC(pio, RP1_ALL_LEGACY_PINS), + RP1_FNC(proc_rio, RP1_ALL_PINS), + RP1_FNC(pwm0, "gpio12", "gpio13", "gpio14", "gpio15", "gpio18", + "gpio19"), + RP1_FNC(pwm1, "gpio34", "gpio35", "gpio40", "gpio41", "gpio44", + "gpio45", "gpio48"), + RP1_FNC(sd0, "sd0", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27"), + RP1_FNC(sd1, "sd1", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33"), + RP1_FNC(spi0, "spi0", "spi0_quad", "gpio0", "gpio1", "gpio2", "gpio3", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11"), + RP1_FNC(spi1, "spi1", "gpio19", "gpio20", "gpio21", "gpio16", "gpio17", + "gpio18", "gpio27"), + RP1_FNC(spi2, "spi2", "gpio0", "gpio1", "gpio2", "gpio3", "gpio24"), + RP1_FNC(spi3, "spi3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio25"), + RP1_FNC(spi4, "spi4", "gpio8", "gpio9", "gpio10", "gpio11"), + RP1_FNC(spi5, "spi5", "gpio12", "gpio13", "gpio14", "gpio15", "gpio26"), + RP1_FNC(spi6, "spi6_0", "spi6_1", "gpio28", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45"), + RP1_FNC(spi7, "spi7_0", "spi7_1", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio53"), + RP1_FNC(spi8, "spi8_0", "spi8_1", "gpio35", "gpio36", "gpio37", + "gpio38", "gpio39", "gpio49", "gpio50", "gpio51", "gpio52", + "gpio53"), + RP1_FNC(uart0, "uart0", "uart0_ctrl", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio14", "gpio15", "gpio16", "gpio17"), + RP1_FNC(uart1, "uart1", "uart1_ctrl", "gpio0", "gpio1", "gpio2", + "gpio3"), + RP1_FNC(uart2, "uart2", "uart2_ctrl", "gpio4", "gpio5", "gpio6", + "gpio7"), + RP1_FNC(uart3, "uart3", "uart3_ctrl", "gpio8", "gpio9", "gpio10", + "gpio11"), + RP1_FNC(uart4, "uart4", "uart4_ctrl", "gpio12", "gpio13", "gpio14", + "gpio15"), + RP1_FNC(uart5, "uart5_0", "uart5_0_ctrl", "uart5_1", "uart5_1_ctrl", + "uart5_2", "uart5_2_ctrl", "uart5_3"), + RP1_FNC(vbus0, "vbus0_0", "vbus0_1", "gpio28", "gpio29", "gpio34", + "gpio35"), + RP1_FNC(vbus1, "vbus1", "gpio42", "gpio43"), + RP1_FNC(vbus2, "vbus2", "gpio50", "gpio51"), + RP1_FNC(vbus3, "vbus3", "gpio52", "gpio53"), + RP1_NULL_FNC(invalid), //[func_invalid] = "?" +}; + +static const struct rp1_pin_funcs rp1_gpio_pin_funcs[] = { + PIN(0, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2), + PIN(1, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2), + PIN(2, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2), + PIN(3, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2), + PIN(4, gpclk0, dpi, uart2, i2c2, uart0, gpio, proc_rio, pio, spi3), + PIN(5, gpclk1, dpi, uart2, i2c2, uart0, gpio, proc_rio, pio, spi3), + PIN(6, gpclk2, dpi, uart2, i2c3, uart0, gpio, proc_rio, pio, spi3), + PIN(7, spi0, dpi, uart2, i2c3, uart0, gpio, proc_rio, pio, spi3), + PIN(8, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4), + PIN(9, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4), + PIN(10, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4), + PIN(11, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4), + PIN(12, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5), + PIN(13, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5), + PIN(14, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5), + PIN(15, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5), + PIN(16, spi1, dpi, dsi0_te_ext, _, uart0, gpio, proc_rio, pio, _), + PIN(17, spi1, dpi, dsi1_te_ext, _, uart0, gpio, proc_rio, pio, _), + PIN(18, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, gpclk1), + PIN(19, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, _), + PIN(20, spi1, dpi, i2s0, gpclk0, i2s1, gpio, proc_rio, pio, _), + PIN(21, spi1, dpi, i2s0, gpclk1, i2s1, gpio, proc_rio, pio, _), + PIN(22, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _), + PIN(23, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _), + PIN(24, sd0, dpi, i2s0, _, i2s1, gpio, proc_rio, pio, spi2), + PIN(25, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi3), + PIN(26, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi5), + PIN(27, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi1), + PIN(28, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _), + PIN(29, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _), + PIN(30, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _), + PIN(31, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _), + PIN(32, sd1, gpclk3, i2s2, spi6, uart5, gpio, proc_rio, _, _), + PIN(33, sd1, gpclk4, i2s2, spi6, uart5, gpio, proc_rio, _, _), + PIN(34, pwm1, gpclk3, vbus0, i2c4, mic, gpio, proc_rio, _, _), + PIN(35, spi8, pwm1, vbus0, i2c4, mic, gpio, proc_rio, _, _), + PIN(36, spi8, uart5, pcie_clkreq_n, i2c5, mic, gpio, proc_rio, _, _), + PIN(37, spi8, uart5, mic, i2c5, pcie_clkreq_n, gpio, proc_rio, _, _), + PIN(38, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi0_te_ext, _), + PIN(39, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi1_te_ext, _), + PIN(40, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _), + PIN(41, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _), + PIN(42, gpclk5, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _), + PIN(43, gpclk4, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _), + PIN(44, gpclk5, i2c5, pwm1, spi6, i2s2, gpio, proc_rio, _, _), + PIN(45, pwm1, i2c5, spi7, spi6, i2s2, gpio, proc_rio, _, _), + PIN(46, gpclk3, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi0_te_ext, _), + PIN(47, gpclk5, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi1_te_ext, _), + PIN(48, pwm1, pcie_clkreq_n, spi7, mic, uart5, gpio, proc_rio, _, _), + PIN(49, spi8, spi7, i2c5, aaud, uart5, gpio, proc_rio, _, _), + PIN(50, spi8, spi7, i2c5, aaud, vbus2, gpio, proc_rio, _, _), + PIN(51, spi8, spi7, i2c6, aaud, vbus2, gpio, proc_rio, _, _), + PIN(52, spi8, _, i2c6, aaud, vbus3, gpio, proc_rio, _, _), + PIN(53, spi8, spi7, _, pcie_clkreq_n, vbus3, gpio, proc_rio, _, _), +}; + +static const u8 legacy_fsel_map[][8] = { + LEGACY_MAP(0, i2c0, _, dpi, spi2, uart1, _), + LEGACY_MAP(1, i2c0, _, dpi, spi2, uart1, _), + LEGACY_MAP(2, i2c1, _, dpi, spi2, uart1, _), + LEGACY_MAP(3, i2c1, _, dpi, spi2, uart1, _), + LEGACY_MAP(4, gpclk0, _, dpi, spi3, uart2, i2c2), + LEGACY_MAP(5, gpclk1, _, dpi, spi3, uart2, i2c2), + LEGACY_MAP(6, gpclk2, _, dpi, spi3, uart2, i2c3), + LEGACY_MAP(7, spi0, _, dpi, spi3, uart2, i2c3), + LEGACY_MAP(8, spi0, _, dpi, _, uart3, i2c0), + LEGACY_MAP(9, spi0, _, dpi, _, uart3, i2c0), + LEGACY_MAP(10, spi0, _, dpi, _, uart3, i2c1), + LEGACY_MAP(11, spi0, _, dpi, _, uart3, i2c1), + LEGACY_MAP(12, pwm0, _, dpi, spi5, uart4, i2c2), + LEGACY_MAP(13, pwm0, _, dpi, spi5, uart4, i2c2), + LEGACY_MAP(14, uart0, _, dpi, spi5, uart4, _), + LEGACY_MAP(15, uart0, _, dpi, spi5, uart4, _), + LEGACY_MAP(16, _, _, dpi, uart0, spi1, _), + LEGACY_MAP(17, _, _, dpi, uart0, spi1, _), + LEGACY_MAP(18, i2s0, _, dpi, _, spi1, pwm0), + LEGACY_MAP(19, i2s0, _, dpi, _, spi1, pwm0), + LEGACY_MAP(20, i2s0, _, dpi, _, spi1, gpclk0), + LEGACY_MAP(21, i2s0, _, dpi, _, spi1, gpclk1), + LEGACY_MAP(22, sd0, _, dpi, _, _, i2c3), + LEGACY_MAP(23, sd0, _, dpi, _, _, i2c3), + LEGACY_MAP(24, sd0, _, dpi, _, _, spi2), + LEGACY_MAP(25, sd0, _, dpi, _, _, spi3), + LEGACY_MAP(26, sd0, _, dpi, _, _, spi5), + LEGACY_MAP(27, sd0, _, dpi, _, _, _), +}; + +static const char * const irq_type_names[] = { + [IRQ_TYPE_NONE] = "none", + [IRQ_TYPE_EDGE_RISING] = "edge-rising", + [IRQ_TYPE_EDGE_FALLING] = "edge-falling", + [IRQ_TYPE_EDGE_BOTH] = "edge-both", + [IRQ_TYPE_LEVEL_HIGH] = "level-high", + [IRQ_TYPE_LEVEL_LOW] = "level-low", +}; + +static bool persist_gpio_outputs = true; +module_param(persist_gpio_outputs, bool, 0644); +MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed"); + static const struct rp1_iobank_desc rp1_iobanks[RP1_NUM_BANKS] = { /* gpio inte ints rio pads */ { 0, 28, 0x0000, 0x011c, 0x0124, 0x0000, 0x0004 }, @@ -180,7 +668,7 @@ static const struct rp1_iobank_desc rp1_iobanks[RP1_NUM_BANKS] = { { 34, 20, 0x8000, 0x811c, 0x8124, 0x8000, 0x8004 }, }; -static int rp1_pinconf_set(struct rp1_pin_info *pin, +static int rp1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int offset, unsigned long *configs, unsigned int num_configs); @@ -194,6 +682,16 @@ static struct rp1_pin_info *rp1_get_pin(struct gpio_chip *chip, return NULL; } +static struct rp1_pin_info *rp1_get_pin_pctl(struct pinctrl_dev *pctldev, + unsigned int offset) +{ + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + + if (pc && offset < RP1_NUM_GPIOS) + return &pc->pins[offset]; + return NULL; +} + static void rp1_input_enable(struct rp1_pin_info *pin, int value) { regmap_field_write(pin->pad[RP1_PAD_IN_ENABLE], !!value); @@ -335,10 +833,10 @@ static int rp1_gpio_direction_output(struct gpio_chip *chip, unsigned int offset static int rp1_gpio_set_config(struct gpio_chip *chip, unsigned int offset, unsigned long config) { - struct rp1_pin_info *pin = rp1_get_pin(chip, offset); + struct rp1_pinctrl *pc = gpiochip_get_data(chip); unsigned long configs[] = { config }; - return rp1_pinconf_set(pin, offset, configs, + return rp1_pinconf_set(pc->pctl_dev, offset, configs, ARRAY_SIZE(configs)); } @@ -490,6 +988,29 @@ static void rp1_gpio_irq_ack(struct irq_data *data) regmap_field_write(pin->gpio[RP1_GPIO_CTRL_IRQRESET_SET], 1); } +static int rp1_gpio_irq_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct rp1_pinctrl *pc = gpiochip_get_data(chip); + const struct rp1_iobank_desc *bank; + struct irq_data *parent_data = NULL; + int i; + + for (i = 0; i < 3; i++) { + bank = &rp1_iobanks[i]; + if (data->hwirq >= bank->min_gpio && + data->hwirq < bank->min_gpio + bank->num_gpios) { + parent_data = irq_get_irq_data(pc->irq[i]); + break; + } + } + + if (parent_data && parent_data->chip->irq_set_affinity) + return parent_data->chip->irq_set_affinity(parent_data, dest, force); + + return -EINVAL; +} + static struct irq_chip rp1_gpio_irq_chip = { .name = MODULE_NAME, .irq_enable = rp1_gpio_irq_enable, @@ -498,18 +1019,394 @@ static struct irq_chip rp1_gpio_irq_chip = { .irq_ack = rp1_gpio_irq_ack, .irq_mask = rp1_gpio_irq_disable, .irq_unmask = rp1_gpio_irq_enable, + .irq_set_affinity = rp1_gpio_irq_set_affinity, .flags = IRQCHIP_IMMUTABLE, GPIOCHIP_IRQ_RESOURCE_HELPERS, }; +static int rp1_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(rp1_gpio_groups) + ARRAY_SIZE(rp1_gpio_pins); +} + +static const char *rp1_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + unsigned int ngroups = ARRAY_SIZE(rp1_gpio_groups); + + if (selector < ngroups) + return rp1_gpio_groups[selector].name; + + return rp1_gpio_pins[selector - ngroups].name; +} + +static enum funcs rp1_get_fsel_func(unsigned int pin, unsigned int fsel) +{ + if (pin < RP1_NUM_GPIOS) { + if (fsel < RP1_FSEL_COUNT) + return rp1_gpio_pin_funcs[pin].funcs[fsel]; + else if (fsel == RP1_FSEL_NONE) + return func_none; + } + return func_invalid; +} + +static int rp1_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + unsigned int ngroups = ARRAY_SIZE(rp1_gpio_groups); + + if (selector < ngroups) { + *pins = rp1_gpio_groups[selector].pins; + *num_pins = rp1_gpio_groups[selector].npins; + } else { + *pins = &rp1_gpio_pins[selector - ngroups].number; + *num_pins = 1; + } + + return 0; +} + +static void rp1_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int offset) +{ + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *chip = &pc->gpio_chip; + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset); + u32 fsel = rp1_get_fsel(pin); + enum funcs func = rp1_get_fsel_func(offset, fsel); + int value = rp1_get_value(pin); + int irq = irq_find_mapping(chip->irq.domain, offset); + + seq_printf(s, "function %s (%s) in %s; irq %d (%s)", + rp1_func_names[fsel].name, rp1_func_names[func].name, + value ? "hi" : "lo", + irq, irq_type_names[pin->irq_type]); +} + +static void rp1_pctl_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *maps, unsigned int num_maps) +{ + int i; + + for (i = 0; i < num_maps; i++) + if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(maps[i].data.configs.configs); + + kfree(maps); +} + +static int rp1_pctl_legacy_map_func(struct rp1_pinctrl *pc, + struct device_node *np, u32 pin, u32 fnum, + struct pinctrl_map *maps, + unsigned int *num_maps) +{ + struct pinctrl_map *map = &maps[*num_maps]; + enum funcs func; + + if (fnum >= ARRAY_SIZE(legacy_fsel_map[0])) { + dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum); + return -EINVAL; + } + + if (pin < ARRAY_SIZE(legacy_fsel_map)) { + func = legacy_fsel_map[pin][fnum]; + } else if (fnum < 2) { + func = func_gpio; + } else { + dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n", + np, pin); + return -EINVAL; + } + + map->type = PIN_MAP_TYPE_MUX_GROUP; + map->data.mux.group = rp1_pctl_get_group_name(pc->pctl_dev, + ARRAY_SIZE(rp1_gpio_groups) + + pin); + map->data.mux.function = rp1_func_names[func].name; + (*num_maps)++; + + return 0; +} + +static int rp1_pctl_legacy_map_pull(struct rp1_pinctrl *pc, + struct device_node *np, u32 pin, u32 pull, + struct pinctrl_map *maps, + unsigned int *num_maps) +{ + struct pinctrl_map *map = &maps[*num_maps]; + enum pin_config_param param; + unsigned long *configs; + + switch (pull) { + case RP1_PUD_OFF: + param = PIN_CONFIG_BIAS_DISABLE; + break; + case RP1_PUD_DOWN: + param = PIN_CONFIG_BIAS_PULL_DOWN; + break; + case RP1_PUD_UP: + param = PIN_CONFIG_BIAS_PULL_UP; + break; + default: + dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull); + return -EINVAL; + } + + configs = kzalloc(sizeof(*configs), GFP_KERNEL); + if (!configs) + return -ENOMEM; + + configs[0] = pinconf_to_config_packed(param, 0); + map->type = PIN_MAP_TYPE_CONFIGS_PIN; + map->data.configs.group_or_pin = rp1_gpio_pins[pin].name; + map->data.configs.configs = configs; + map->data.configs.num_configs = 1; + (*num_maps)++; + + return 0; +} + +static int rp1_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + struct property *pins, *funcs, *pulls; + int num_pins, num_funcs, num_pulls, maps_per_pin; + struct pinctrl_map *maps; + unsigned long *configs = NULL; + const char *function = NULL; + unsigned int reserved_maps; + int num_configs = 0; + int i, err; + u32 pin, func, pull; + + /* Check for legacy pin declaration */ + pins = of_find_property(np, "brcm,pins", NULL); + + if (!pins) /* Assume generic bindings in this node */ + return pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps); + + funcs = of_find_property(np, "brcm,function", NULL); + if (!funcs) + of_property_read_string(np, "function", &function); + + pulls = of_find_property(np, "brcm,pull", NULL); + if (!pulls) + pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); + + if (!function && !funcs && !num_configs && !pulls) { + dev_err(pc->dev, + "%pOF: no function, brcm,function, brcm,pull, etc.\n", + np); + return -EINVAL; + } + + num_pins = pins->length / 4; + num_funcs = funcs ? (funcs->length / 4) : 0; + num_pulls = pulls ? (pulls->length / 4) : 0; + + if (num_funcs > 1 && num_funcs != num_pins) { + dev_err(pc->dev, + "%pOF: brcm,function must have 1 or %d entries\n", + np, num_pins); + return -EINVAL; + } + + if (num_pulls > 1 && num_pulls != num_pins) { + dev_err(pc->dev, + "%pOF: brcm,pull must have 1 or %d entries\n", + np, num_pins); + return -EINVAL; + } + + maps_per_pin = 0; + if (function || num_funcs) + maps_per_pin++; + if (num_configs || num_pulls) + maps_per_pin++; + reserved_maps = num_pins * maps_per_pin; + maps = kcalloc(reserved_maps, sizeof(*maps), GFP_KERNEL); + if (!maps) + return -ENOMEM; + + *num_maps = 0; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(np, "brcm,pins", i, &pin); + if (err) + goto out; + if (num_funcs) { + err = of_property_read_u32_index(np, "brcm,function", + (num_funcs > 1) ? i : 0, + &func); + if (err) + goto out; + err = rp1_pctl_legacy_map_func(pc, np, pin, func, + maps, num_maps); + } else if (function) { + err = pinctrl_utils_add_map_mux(pctldev, &maps, + &reserved_maps, num_maps, + rp1_gpio_groups[pin].name, + function); + } + + if (err) + goto out; + + if (num_pulls) { + err = of_property_read_u32_index(np, "brcm,pull", + (num_pulls > 1) ? i : 0, + &pull); + if (err) + goto out; + err = rp1_pctl_legacy_map_pull(pc, np, pin, pull, + maps, num_maps); + } else if (num_configs) { + err = pinctrl_utils_add_map_configs(pctldev, &maps, + &reserved_maps, num_maps, + rp1_gpio_groups[pin].name, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_PIN); + } + + if (err) + goto out; + } + + *map = maps; + + return 0; + +out: + rp1_pctl_dt_free_map(pctldev, maps, reserved_maps); + return err; +} + +static const struct pinctrl_ops rp1_pctl_ops = { + .get_groups_count = rp1_pctl_get_groups_count, + .get_group_name = rp1_pctl_get_group_name, + .get_group_pins = rp1_pctl_get_group_pins, + .pin_dbg_show = rp1_pctl_pin_dbg_show, + .dt_node_to_map = rp1_pctl_dt_node_to_map, + .dt_free_map = rp1_pctl_dt_free_map, +}; + +static int rp1_pmx_free(struct pinctrl_dev *pctldev, unsigned int offset) +{ + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset); + u32 fsel = rp1_get_fsel(pin); + + /* Return all pins to GPIO_IN, unless persist_gpio_outputs is set */ + if (persist_gpio_outputs && fsel == RP1_FSEL_GPIO) + return 0; + + rp1_set_dir(pin, RP1_DIR_INPUT); + rp1_set_fsel(pin, RP1_FSEL_GPIO); + + return 0; +} + +static int rp1_pmx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return func_count; +} + +static const char *rp1_pmx_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return (selector < func_count) ? rp1_func_names[selector].name : NULL; +} + +static int rp1_pmx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = rp1_func_names[selector].groups; + *num_groups = rp1_func_names[selector].ngroups; + + return 0; +} + +static int rp1_pmx_set(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + struct rp1_pin_info *pin; + const unsigned int *pins; + const u8 *pin_funcs; + unsigned int num_pins; + int offset, fsel; + + rp1_pctl_get_group_pins(pctldev, group_selector, &pins, &num_pins); + + for (offset = 0; offset < num_pins; ++offset) { + pin = rp1_get_pin_pctl(pctldev, pins[offset]); + /* func_selector is an enum funcs, so needs translation */ + if (func_selector >= RP1_FSEL_COUNT) { + /* Convert to an fsel number */ + pin_funcs = rp1_gpio_pin_funcs[pin->num].funcs; + for (fsel = 0; fsel < RP1_FSEL_COUNT; fsel++) { + if (pin_funcs[fsel] == func_selector) + break; + } + } else { + fsel = (int)func_selector; + } + + if (fsel >= RP1_FSEL_COUNT && fsel != RP1_FSEL_NONE) + return -EINVAL; + + rp1_set_fsel(pin, fsel); + } + + return 0; +} + +static void rp1_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + (void)rp1_pmx_free(pctldev, offset); +} + +static int rp1_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, + bool input) +{ + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset); + + rp1_set_dir(pin, input); + rp1_set_fsel(pin, RP1_FSEL_GPIO); + + return 0; +} + +static const struct pinmux_ops rp1_pmx_ops = { + .free = rp1_pmx_free, + .get_functions_count = rp1_pmx_get_functions_count, + .get_function_name = rp1_pmx_get_function_name, + .get_function_groups = rp1_pmx_get_function_groups, + .set_mux = rp1_pmx_set, + .gpio_disable_free = rp1_pmx_gpio_disable_free, + .gpio_set_direction = rp1_pmx_gpio_set_direction, +}; + static void rp1_pull_config_set(struct rp1_pin_info *pin, unsigned int arg) { regmap_field_write(pin->pad[RP1_PAD_PULL], arg & 0x3); } -static int rp1_pinconf_set(struct rp1_pin_info *pin, unsigned int offset, +static int rp1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int offset, unsigned long *configs, unsigned int num_configs) { + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset); u32 param, arg; int i; @@ -584,8 +1481,140 @@ static int rp1_pinconf_set(struct rp1_pin_info *pin, unsigned int offset, return 0; } +static int rp1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int offset, + unsigned long *config) +{ + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 padctrl; + u32 arg; + + if (!pin) + return -EINVAL; + + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: + regmap_field_read(pin->pad[RP1_PAD_IN_ENABLE], &padctrl); + arg = !!padctrl; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + regmap_field_read(pin->pad[RP1_PAD_OUT_DISABLE], &padctrl); + arg = !padctrl; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + regmap_field_read(pin->pad[RP1_PAD_SCHMITT], &padctrl); + arg = !!padctrl; + break; + case PIN_CONFIG_SLEW_RATE: + regmap_field_read(pin->pad[RP1_PAD_SLEWFAST], &padctrl); + arg = !!padctrl; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + regmap_field_read(pin->pad[RP1_PAD_DRIVE], &padctrl); + switch (padctrl) { + case RP1_PAD_DRIVE_2MA: + arg = 2; + break; + case RP1_PAD_DRIVE_4MA: + arg = 4; + break; + case RP1_PAD_DRIVE_8MA: + arg = 8; + break; + case RP1_PAD_DRIVE_12MA: + arg = 12; + break; + } + break; + case PIN_CONFIG_BIAS_DISABLE: + regmap_field_read(pin->pad[RP1_PAD_PULL], &padctrl); + arg = ((padctrl == RP1_PUD_OFF)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + regmap_field_read(pin->pad[RP1_PAD_PULL], &padctrl); + arg = ((padctrl == RP1_PUD_DOWN)); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + regmap_field_read(pin->pad[RP1_PAD_PULL], &padctrl); + arg = ((padctrl == RP1_PUD_UP)); + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int rp1_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned long *config) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret = rp1_pctl_get_group_pins(pctldev, selector, &pins, &npins); + if (ret < 0) + return ret; + + if (!npins) + return -ENODEV; + + ret = rp1_pinconf_get(pctldev, pins[0], config); + + return ret; +} + +static int rp1_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned long *configs, unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int ret, i; + + ret = rp1_pctl_get_group_pins(pctldev, selector, &pins, &npins); + if (ret < 0) + return ret; + + for (i = 0; i < npins; i++) { + ret = rp1_pinconf_set(pctldev, pins[i], configs, num_configs); + if (ret < 0) + return ret; + } + + return 0; +} + +static const struct pinconf_ops rp1_pinconf_ops = { + .is_generic = true, + .pin_config_get = rp1_pinconf_get, + .pin_config_set = rp1_pinconf_set, + .pin_config_group_get = rp1_pinconf_group_get, + .pin_config_group_set = rp1_pinconf_group_set, +}; + +static struct pinctrl_desc rp1_pinctrl_desc = { + .name = MODULE_NAME, + .pins = rp1_gpio_pins, + .npins = ARRAY_SIZE(rp1_gpio_pins), + .pctlops = &rp1_pctl_ops, + .pmxops = &rp1_pmx_ops, + .confops = &rp1_pinconf_ops, + .owner = THIS_MODULE, +}; + +static struct pinctrl_gpio_range rp1_pinctrl_gpio_range = { + .name = MODULE_NAME, + .npins = RP1_NUM_GPIOS, +}; + static const struct of_device_id rp1_pinctrl_match[] = { - { .compatible = "raspberrypi,rp1-gpio" }, + { + .compatible = "raspberrypi,rp1-gpio", + .data = &rp1_pinconf_ops, + }, {}, }; MODULE_DEVICE_TABLE(of, rp1_pinctrl_match); @@ -742,6 +1771,11 @@ static int rp1_pinctrl_probe(struct platform_device *pdev) raw_spin_lock_init(&pc->irq_lock[i]); } + pc->pctl_dev = devm_pinctrl_register(dev, &rp1_pinctrl_desc, pc); + if (IS_ERR(pc->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(pc->pctl_dev), + "Could not register pin controller\n"); + girq = &pc->gpio_chip.irq; girq->chip = &rp1_gpio_irq_chip; girq->parent_handler = rp1_gpio_irq_handler; @@ -771,6 +1805,11 @@ static int rp1_pinctrl_probe(struct platform_device *pdev) if (err) return dev_err_probe(dev, err, "could not add GPIO chip\n"); + pc->gpio_range = rp1_pinctrl_gpio_range; + pc->gpio_range.base = pc->gpio_chip.base; + pc->gpio_range.gc = &pc->gpio_chip; + pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); + return 0; } -- cgit v1.2.3