From a7352c849492a30b5d8491fcb9314ab376a3942f Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Mon, 21 Jul 2025 11:17:33 +0200 Subject: dt-bindings: npu: rockchip,rknn: Add bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the bindings for the Neural Processing Unit IP from Rockchip. v2: - Adapt to new node structure (one node per core, each with its own IOMMU) - Several misc. fixes from Sebastian Reichel v3: - Split register block in its constituent subblocks, and only require the ones that the kernel would ever use (Nicolas Frattaroli) - Group supplies (Rob Herring) - Explain the way in which the top core is special (Rob Herring) v4: - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) - Remove unneeded items: (Krzysztof Kozlowski) - Fix use of minItems/maxItems (Krzysztof Kozlowski) - Add reg-names to list of required properties (Krzysztof Kozlowski) - Fix example (Krzysztof Kozlowski) v5: - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) - Streamline compatible property (Krzysztof Kozlowski) v6: - Remove mention to NVDLA, as the hardware is only incidentally related (Kever Yang) - Mark pclk and npu clocks as required by all clocks (Rob Herring) v7: - Remove allOf section, not needed now that all nodes require 4 clocks (Heiko Stübner) v8: - Remove notion of top core (Robin Murphy) Signed-off-by: Sebastian Reichel Reviewed-by: Krzysztof Kozlowski Tested-by: Heiko Stuebner Signed-off-by: Tomeu Vizoso Reviewed-by: Rob Herring (Arm) Signed-off-by: Jeff Hugo Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-6-77ebd484941e@tomeuvizoso.net --- .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 112 +++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml new file mode 100644 index 000000000000..caca2a4903cd --- /dev/null +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Neural Processing Unit IP from Rockchip + +maintainers: + - Tomeu Vizoso + +description: + Rockchip IP for accelerating inference of neural networks. + + There is to be a node per each NPU core in the SoC, and each core should reference all the + resources that it needs to function, such as clocks, power domains, and resets. + +properties: + $nodename: + pattern: '^npu@[a-f0-9]+$' + + compatible: + enum: + - rockchip,rk3588-rknn-core + + reg: + maxItems: 3 + + reg-names: + items: + - const: pc # Program Control-related registers + - const: cna # Convolution Neural Network Accelerator registers + - const: core # Main NPU core processing unit registers + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aclk + - const: hclk + - const: npu + - const: pclk + + interrupts: + maxItems: 1 + + iommus: + maxItems: 1 + + npu-supply: true + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: srst_a + - const: srst_h + + sram-supply: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - iommus + - power-domains + - resets + - reset-names + - npu-supply + - sram-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + npu@fdab0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdab0000 0x0 0x1000>, + <0x0 0xfdab1000 0x0 0x1000>, + <0x0 0xfdab3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + interrupts = ; + iommus = <&rknn_mmu_0>; + npu-supply = <&vdd_npu_s0>; + power-domains = <&power RK3588_PD_NPUTOP>; + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; + reset-names = "srst_a", "srst_h"; + sram-supply = <&vdd_npu_mem_s0>; + }; + }; +... -- cgit v1.2.3 From 784c99331c8d54a51d4f3e772c81f7fb82b7a1f8 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 30 Jul 2025 08:54:23 +0300 Subject: dt-bindings: display: bridge: Document Solomon SSD2825 Add bindings for Solomon SSD2825 MIPI master bridge chip that connects an application processor with traditional parallel LCD interface and an LCD driver with MIPI slave interface. The SSD2825 supports both parallel RGB interface and serial SPI interface. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250730055424.6718-2-clamor95@gmail.com Signed-off-by: Dmitry Baryshkov --- .../bindings/display/bridge/solomon,ssd2825.yaml | 141 +++++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml b/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml new file mode 100644 index 000000000000..e2d293d623b8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/solomon,ssd2825.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Solomon SSD2825 RGB to MIPI-DSI bridge + +maintainers: + - Svyatoslav Ryhel + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: solomon,ssd2825 + + reg: + maxItems: 1 + + reset-gpios: true + + dvdd-supply: + description: Regulator for 1.2V digital power supply. + + avdd-supply: + description: Regulator for 1.2V analog power supply. + + vddio-supply: + description: Regulator for 1.8V IO power supply. + + spi-max-frequency: + maximum: 1000000 + + spi-cpha: true + spi-cpol: true + + clocks: + maxItems: 1 + description: Reference TX_CLK used before PLL is locked. + + solomon,hs-zero-delay-ns: + description: + HS zero delay period + minimum: 0 + maximum: 1700 + default: 133 + + solomon,hs-prep-delay-ns: + description: + HS prep delay period + minimum: 0 + maximum: 1728 + default: 40 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Video port for RGB input + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + bus-width: + enum: [ 16, 18, 24 ] + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for DSI output (panel or connector) + + required: + - port@0 + - port@1 + +required: + - compatible + - ports + +additionalProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + dsi@2 { + compatible = "solomon,ssd2825"; + reg = <2>; + + spi-max-frequency = <1000000>; + + spi-cpha; + spi-cpol; + + reset-gpios = <&gpio 114 GPIO_ACTIVE_LOW>; + + dvdd-supply = <&vdd_1v2>; + avdd-supply = <&vdd_1v2>; + vddio-supply = <&vdd_1v8_io>; + + solomon,hs-zero-delay-ns = <300>; + solomon,hs-prep-delay-ns = <65>; + + clocks = <&ssd2825_tx_clk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + bus-width = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + }; -- cgit v1.2.3 From d680a7959b9d7cce9526b1b391cc7b13e313a096 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Thu, 31 Jul 2025 23:55:08 +0200 Subject: dt-bindings: display: panel: samsung,atna40cu11: document ATNA40CU11 The Samsung ATNA40CU11 panel is a 14" AMOLED eDP panel. It is similar to the ATNA33XC20 except that it is larger and has a different resolution. It is found in some arm64 laptops, eg. Asus Zenbook A14 UX3407RA. Raw panel edid: 00 ff ff ff ff ff ff 00 4c 83 9d 41 00 00 00 00 00 20 01 04 b5 1e 13 78 03 cf d1 ae 51 3e b6 23 0b 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 cb fe 40 64 b0 08 38 77 20 08 88 00 2e bd 10 00 00 1b 00 00 00 fd 00 30 78 da da 42 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe 00 41 54 4e 41 34 30 43 55 31 31 2d 30 20 01 2a 70 20 79 02 00 20 00 0c 4c 83 00 9d 41 00 00 00 00 00 20 00 21 00 1d b8 0b 6c 07 40 0b 08 07 00 ee ea 50 ec d3 b6 3d 42 0b 01 45 54 40 5e d0 60 18 10 23 78 26 00 09 07 06 03 00 00 00 50 00 00 22 00 14 e7 f3 09 85 3f 0b 63 00 1f 00 07 00 07 07 17 00 07 00 07 00 81 00 1f 73 1a 00 00 03 03 30 78 00 a0 74 02 60 02 78 00 00 00 00 8d e3 05 80 00 e6 06 05 01 74 60 02 00 00 00 00 00 91 90 Acked-by: Krzysztof Kozlowski Signed-off-by: Aleksandrs Vinarskis Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20250731215635.206702-2-alex.vinarskis@gmail.com --- Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml index e36659340ef3..5e2ce200025f 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml @@ -21,6 +21,8 @@ properties: - enum: # Samsung 13" 3K (2880×1920 pixels) eDP AMOLED panel - samsung,atna30dw01 + # Samsung 14" WQXGA+ (2880x1800 pixels) eDP AMOLED panel + - samsung,atna40cu11 # Samsung 14" WQXGA+ (2880×1800 pixels) eDP AMOLED panel - samsung,atna40yk20 # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel -- cgit v1.2.3 From d7c2aad1254a1b4e6d76947cbdd18813b02a0e24 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Thu, 31 Jul 2025 23:55:09 +0200 Subject: dt-bindings: display: panel: samsung,atna40ct06: document ATNA40CT06 The Samsung ATNA40CT06 panel is a 14" AMOLED eDP panel. It is similar to the ATNA33XC20 except that it is larger and has a different resolution. It is found in some arm64 laptops, eg. Asus Zenbook A14 UX3407QA. Raw panel edid: 00 ff ff ff ff ff ff 00 4c 83 0d 42 00 00 00 00 00 22 01 04 b5 1e 13 78 02 0c f1 ae 52 3c b9 23 0c 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 42 3c 80 a0 70 b0 24 40 30 20 88 00 2e bd 10 00 00 1b 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc 00 41 54 4e 41 34 30 43 54 30 36 2d 30 20 01 7d 70 20 79 02 00 20 00 0c 4c 83 00 0d 42 00 00 00 00 00 22 00 21 00 1d ca 0b 5e 07 80 07 b0 04 00 e1 fa 51 cb 13 b9 3d d2 0c 01 45 54 40 5e d0 60 18 10 23 78 26 00 09 07 06 03 00 00 00 50 00 00 22 00 14 8d 5a 02 85 7f 07 9f 00 2f 00 1f 00 af 04 23 00 07 00 07 00 81 00 0b e3 05 80 00 e6 06 05 01 74 60 02 2e 00 06 00 45 40 5e d0 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0 90 Acked-by: Krzysztof Kozlowski Signed-off-by: Aleksandrs Vinarskis Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20250731215635.206702-3-alex.vinarskis@gmail.com --- Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml index 5e2ce200025f..ccb574caed28 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml @@ -21,6 +21,8 @@ properties: - enum: # Samsung 13" 3K (2880×1920 pixels) eDP AMOLED panel - samsung,atna30dw01 + # Samsung 14" FHD+ (1920x1200 pixels) eDP AMOLED panel + - samsung,atna40ct06 # Samsung 14" WQXGA+ (2880x1800 pixels) eDP AMOLED panel - samsung,atna40cu11 # Samsung 14" WQXGA+ (2880×1800 pixels) eDP AMOLED panel -- cgit v1.2.3 From 1da71a08080bb5cf5601f237e94c3dd5cede446b Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 2 Jul 2025 10:22:29 +0200 Subject: dt-bindings: display: simple: Add Olimex LCD-OLinuXino-5CTS Add the Olimex LCD-OLinuXino-5CTS, a 5-inch TFT LCD panel. Signed-off-by: Paul Kocialkowski Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250702082230.1291953-1-paulk@sys-base.io --- Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 1ac1f0219079..a03a9f1dd9f6 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -236,6 +236,8 @@ properties: - okaya,rs800480t-7x0gp # Olimex 4.3" TFT LCD panel - olimex,lcd-olinuxino-43-ts + # Olimex 5.0" TFT LCD panel + - olimex,lcd-olinuxino-5-cts # On Tat Industrial Company 5" DPI TFT panel. - ontat,kd50g21-40nt-a1 # On Tat Industrial Company 7" DPI TFT panel. -- cgit v1.2.3 From f3e1caef597e7f29dd2326dae7fa5964ae46c91d Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Mon, 21 Jul 2025 20:08:59 +0530 Subject: dt-bindings: display: panel: document Samsung AMS561RA01 panel with S6E8AA5X01 controller Samsung AMS561RA01 is an AMOLED panel, using the Samsung S6E8AA5X01 MIPI DSI panel controller. Document the compatible and devicetree properties of this hardware. It has a reset GPIO and two voltage regulators. Acked-by: Conor Dooley Signed-off-by: Kaustabh Chakraborty Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250721-panel-samsung-s6e8aa5x01-v5-1-1a315aba530b@disroot.org --- .../panel/samsung,s6e8aa5x01-ams561ra01.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml new file mode 100644 index 000000000000..eccfc66d7fe2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung AMS561RA01 panel with S6E8AA5X01 controller + +maintainers: + - Kaustabh Chakraborty + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: samsung,s6e8aa5x01-ams561ra01 + + reg: + maxItems: 1 + + vdd-supply: + description: core voltage supply + + vci-supply: + description: voltage supply for analog circuits + + reset-gpios: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6e8aa5x01-ams561ra01"; + reg = <0>; + + vdd-supply = <&panel_vdd_reg>; + vci-supply = <&panel_vci_reg>; + + reset-gpios = <&gpd3 4 GPIO_ACTIVE_HIGH>; + }; + }; + +... -- cgit v1.2.3 From bd068333ef090d63a7cf952d70040e768b0aa4cf Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 17 Jul 2025 16:57:51 +0300 Subject: dt-bindings: display: panel: Document Hydis HV101HD1 DSI panel Hydis HV101HD1 is a 2-lane 1366x768 MIPI DSI panel found in ASUS VivoTab RT TF600T tablet. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250717135752.55958-2-clamor95@gmail.com --- .../bindings/display/panel/hydis,hv101hd1.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml b/Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml new file mode 100644 index 000000000000..f429e84ee65d --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/hydis,hv101hd1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hydis HV101HD1 DSI Display Panel + +maintainers: + - Svyatoslav Ryhel + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: hydis,hv101hd1 + + reg: + maxItems: 1 + + vdd-supply: true + vio-supply: true + + backlight: true + port: true + +required: + - compatible + - vdd-supply + - vio-supply + - backlight + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "hydis,hv101hd1"; + reg = <0>; + + vdd-supply = <&vdd_lcd>; + vio-supply = <&vddio_lcd>; + + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; +... -- cgit v1.2.3 From 01048738d6b618fc1dba564b38b3df06b0937eb0 Mon Sep 17 00:00:00 2001 From: Joseph Guo Date: Wed, 6 Aug 2025 10:33:32 +0900 Subject: dt-bindings: display: bridge: Add waveshare DSI2DPI unit support Add dt-binding documentation for waveshare DSI2DPI unit Signed-off-by: Joseph Guo Suggested-by: Liu Ying Reviewed-by: Rob Herring (Arm) Acked-by: Liu Ying Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250806-waveshare-v3-1-fd28e01f064f@nxp.com --- .../bindings/display/bridge/waveshare,dsi2dpi.yaml | 103 +++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml new file mode 100644 index 000000000000..5e8498c8303d --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/waveshare,dsi2dpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Waveshare MIPI-DSI to DPI Converter bridge + +maintainers: + - Joseph Guo + +description: + Waveshare bridge board is part of Waveshare panel which converts DSI to DPI. + +properties: + compatible: + const: waveshare,dsi2dpi + + reg: + maxItems: 1 + description: base I2C address of the device + + power-supply: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Video port for MIPI DSI input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + items: + - const: 1 + - const: 2 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for MIPI DPI output panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + - power-supply + +additionalProperties: false + +examples: + - | + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@45 { + compatible = "waveshare,dsi2dpi"; + reg = <0x45>; + power-supply = <®_3p3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + waveshare_from_dsim: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&dsim_to_waveshare>; + }; + }; + + port@1 { + reg = <1>; + + waveshare_to_panel: endpoint { + remote-endpoint = <&panel_to_waveshare>; + }; + }; + }; + }; + }; + +... -- cgit v1.2.3 From 80b0eb11f8e0a504078c3b405b54cddaf535ff97 Mon Sep 17 00:00:00 2001 From: Joseph Guo Date: Wed, 6 Aug 2025 10:33:33 +0900 Subject: dt-bindings: display: panel: Add waveshare DPI panel support Add dt-binding documentation for waveshare DPI panel Signed-off-by: Joseph Guo Suggested-by: Liu Ying Acked-by: Rob Herring (Arm) Acked-by: Liu Ying Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250806-waveshare-v3-2-fd28e01f064f@nxp.com --- Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index a03a9f1dd9f6..5e8dc9afa1fd 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -323,6 +323,10 @@ properties: - vivax,tpc9150-panel # VXT 800x480 color TFT LCD panel - vxt,vl050-8048nt-c01 + # Waveshare 13.3" FHD (1920x1080) LCD panel + - waveshare,13.3inch-panel + # Waveshare 7.0" WSVGA (1024x600) LCD panel + - waveshare,7.0inch-c-panel # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel - winstar,wf35ltiacd # Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel -- cgit v1.2.3 From 605d902bb6b6f5b12a5baeaca0dc359ced7685cb Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 7 Aug 2025 16:43:57 -0500 Subject: ASoC: dt-bindings: Drop imx-audio-sgtl5000.txt The "fsl,imx-audio-sgtl5000" binding is already covered by fsl-asoc-card.yaml, so remove the old text binding. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250807214358.4172451-1-robh@kernel.org Acked-by: Conor Dooley Signed-off-by: Mark Brown --- .../bindings/sound/imx-audio-sgtl5000.txt | 56 ---------------------- 1 file changed, 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt deleted file mode 100644 index 2f89db88fd57..000000000000 --- a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt +++ /dev/null @@ -1,56 +0,0 @@ -Freescale i.MX audio complex with SGTL5000 codec - -Required properties: - - - compatible : "fsl,imx-audio-sgtl5000" - - - model : The user-visible name of this sound complex - - - ssi-controller : The phandle of the i.MX SSI controller - - - audio-codec : The phandle of the SGTL5000 audio codec - - - audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, SGTL5000 - pins, and the jacks on the board: - - Power supplies: - * Mic Bias - - SGTL5000 pins: - * MIC_IN - * LINE_IN - * HP_OUT - * LINE_OUT - - Board connectors: - * Mic Jack - * Line In Jack - * Headphone Jack - * Line Out Jack - * Ext Spk - - - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) - - - mux-ext-port : The external port of the i.MX audio muxer - -Note: The AUDMUX port numbering should start at 1, which is consistent with -hardware manual. - -Example: - -sound { - compatible = "fsl,imx51-babbage-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx51-babbage-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; -}; -- cgit v1.2.3 From 82f0907931f016c04bcb992f764bd65992c7008e Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 31 Jul 2025 18:44:41 +0800 Subject: dt-bindings: regulator: add PF0900 regulator yaml Add device binding doc for PF0900 PMIC driver. Can not get the I2C_CRC_EN config by reading register. If the PMIC OTP_I2C_CRC_EN is enable, need to add the nxp,i2c-crc-enable property. Signed-off-by: Joy Zou Link: https://patch.msgid.link/20250731-b4-pf09-v2-v3-1-4c2659516582@nxp.com Reviewed-by: Rob Herring (Arm) Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/nxp,pf0900.yaml | 163 +++++++++++++++++++++ 1 file changed, 163 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/nxp,pf0900.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/nxp,pf0900.yaml b/Documentation/devicetree/bindings/regulator/nxp,pf0900.yaml new file mode 100644 index 000000000000..8c8fc2cd4ced --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/nxp,pf0900.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/nxp,pf0900.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PF0900 Power Management Integrated Circuit regulators + +maintainers: + - Joy Zou + +description: + The PF0900 is a power management integrated circuit (PMIC) optimized + for high performance i.MX9x based applications. It features five high + efficiency buck converters, three linear and one vaon regulators. It + provides low quiescent current in Standby and low power off Modes. + +properties: + compatible: + enum: + - nxp,pf0900 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + + properties: + vaon: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + patternProperties: + "^ldo[1-3]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^sw[1-5]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + nxp,i2c-crc-enable: + type: boolean + description: + The CRC enabled during register read/write. Controlled by customer + unviewable fuse bits OTP_I2C_CRC_EN. Check chip part number. + +required: + - compatible + - reg + - interrupts + - regulators + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@8 { + compatible = "nxp,pf0900"; + reg = <0x08>; + interrupt-parent = <&pcal6524>; + interrupts = <89 IRQ_TYPE_LEVEL_LOW>; + nxp,i2c-crc-enable; + + regulators { + vaon { + regulator-name = "VAON"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw1 { + regulator-name = "SW1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <650000>; + regulator-suspend-min-microvolt = <650000>; + }; + }; + + sw2 { + regulator-name = "SW2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + }; + + sw3 { + regulator-name = "SW3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + }; + + sw4 { + regulator-name = "SW4"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + }; + + sw5 { + regulator-name = "SW5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + }; + + ldo1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; -- cgit v1.2.3 From 83656699ba3ab61a86b83daf4579cb5598d68c55 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:08 -0700 Subject: dt-bindings: arm: aspeed: add Facebook Wedge400-data64 board Document the new compatibles used on Meta/Facebook Wedge400-data64 board. Signed-off-by: Tao Ren Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250728055618.61616-7-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 456dbf7b5ec8..5a01e2f4ce20 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -46,6 +46,7 @@ properties: - facebook,yamp-bmc - facebook,yosemitev2-bmc - facebook,wedge400-bmc + - facebook,wedge400-data64-bmc - hxt,stardragon4800-rep2-bmc - ibm,mihawk-bmc - ibm,mowgli-bmc -- cgit v1.2.3 From 36296b06cd50e790d1769bb1299670b5c83ba3a7 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:11 -0700 Subject: dt-bindings: arm: aspeed: add Facebook Fuji-data64 board Document the new compatibles used on Meta/Facebook Fuji-data64 board. Signed-off-by: Tao Ren Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250728055618.61616-10-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 5a01e2f4ce20..e06a2e75e00d 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -85,6 +85,7 @@ properties: - facebook,cloudripper-bmc - facebook,elbert-bmc - facebook,fuji-bmc + - facebook,fuji-data64-bmc - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc -- cgit v1.2.3 From 0ae11080995f30cfb8362d5680e361da04fa6f79 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:14 -0700 Subject: dt-bindings: arm: aspeed: add Facebook Darwin board Document the new compatibles used on Meta/Facebook Darwin board. Signed-off-by: Tao Ren Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250728055618.61616-13-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index e06a2e75e00d..b3c9d3310d57 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -83,6 +83,7 @@ properties: - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,cloudripper-bmc + - facebook,darwin-bmc - facebook,elbert-bmc - facebook,fuji-bmc - facebook,fuji-data64-bmc -- cgit v1.2.3 From e9d84a1f8bfe85b6c406c4a088e537d4a5f83a87 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:11 +0530 Subject: dt-bindings: arm: qcom: lemans: Add bindings for Lemans Evaluation Kit (EVK) Introduce new bindings for the Lemans EVK, an IoT board without safety features. Signed-off-by: Wasim Nazir Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250803110113.401927-8-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae43b3556580..bf5f3beb320b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -969,6 +969,7 @@ properties: - items: - enum: + - qcom,lemans-evk - qcom,qcs9100-ride - qcom,qcs9100-ride-r3 - const: qcom,qcs9100 -- cgit v1.2.3 From 684339e80a9392cf8d331479d0942682ba0bb5ac Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 1 Aug 2025 15:07:27 -0500 Subject: dt-bindings: PCI: Add missing "#address-cells" to interrupt controllers An interrupt-controller node which is the parent provider for "interrupt-map" needs an "#address-cells" property. This fixes "interrupt_map" warnings in new dtc. Acked-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20250801200728.3252036-2-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml | 1 + Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml | 4 ++++ Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml | 3 +++ Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml | 4 ++++ Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 3 +++ 5 files changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml index 5434c144d2ec..18e7981241b5 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml @@ -108,6 +108,7 @@ examples: #include gic: interrupt-controller { + #address-cells = <0>; interrupt-controller; #interrupt-cells = <3>; }; diff --git a/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml b/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml index 68090b3ca419..8403c79634ed 100644 --- a/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml @@ -42,6 +42,9 @@ properties: additionalProperties: false properties: + '#address-cells': + const: 0 + interrupt-controller: true '#interrupt-cells': @@ -92,6 +95,7 @@ examples: reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; pcie_intc: interrupt-controller { + #address-cells = <0>; interrupt-controller; #interrupt-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml b/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml index 7be695320ddf..3d68bfbe6feb 100644 --- a/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml @@ -101,6 +101,9 @@ patternProperties: additionalProperties: false properties: + '#address-cells': + const: 0 + interrupt-controller: true '#interrupt-cells': diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml index 638b99db0433..c07b0ed51613 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml @@ -56,6 +56,9 @@ properties: additionalProperties: false properties: + '#address-cells': + const: 0 + interrupt-controller: true '#interrupt-cells': @@ -109,6 +112,7 @@ examples: <0 0 0 4 &pcie_intc 3>; pcie_intc: interrupt-controller { + #address-cells = <0>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 69b499c96c71..c704099f134b 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -99,6 +99,9 @@ properties: additionalProperties: false properties: + '#address-cells': + const: 0 + interrupt-controller: true '#interrupt-cells': -- cgit v1.2.3 From 62498af7b1082d76031f98e4c3d6fb2b9af47772 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Wed, 16 Jul 2025 19:51:22 +0200 Subject: dt-bindings: cpufreq: Add mediatek,mt8196-cpufreq-hw binding The MediaTek MT8196 SoC has new cpufreq hardware, with added memory register ranges to control Dynamic-Voltage-Frequency-Scaling. The DVFS hardware is controlled through a set of registers referred to as "FDVFS". They set the target frequency the DVFS hardware should aim for for each performance domain. Instead of working around the old binding and its already established meanings for the reg items, add a new binding. The FDVFS register memory region is at the beginning, which allows us to easily expand this binding for future SoCs which may have more than 3 performance domains. Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Viresh Kumar --- .../cpufreq/mediatek,mt8196-cpufreq-hw.yaml | 82 ++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml b/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml new file mode 100644 index 000000000000..5f3c7db3f3aa --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/mediatek,mt8196-cpufreq-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Hybrid CPUFreq for MT8196/MT6991 series SoCs + +maintainers: + - Nicolas Frattaroli + +description: + MT8196 uses CPUFreq management hardware that supports dynamic voltage + frequency scaling (dvfs), and can support several performance domains. + +properties: + compatible: + const: mediatek,mt8196-cpufreq-hw + + reg: + items: + - description: FDVFS control register region + - description: OPP tables and control for performance domain 0 + - description: OPP tables and control for performance domain 1 + - description: OPP tables and control for performance domain 2 + + "#performance-domain-cells": + const: 1 + +required: + - compatible + - reg + - "#performance-domain-cells" + +additionalProperties: false + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + enable-method = "psci"; + performance-domains = <&performance 0>; + reg = <0x000>; + }; + + /* ... */ + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-x4"; + enable-method = "psci"; + performance-domains = <&performance 1>; + reg = <0x600>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-x925"; + enable-method = "psci"; + performance-domains = <&performance 2>; + reg = <0x700>; + }; + }; + + /* ... */ + + soc { + #address-cells = <2>; + #size-cells = <2>; + + performance: performance-controller@c2c2034 { + compatible = "mediatek,mt8196-cpufreq-hw"; + reg = <0 0xc220400 0 0x20>, <0 0xc2c0f20 0 0x120>, + <0 0xc2c1040 0 0x120>, <0 0xc2c1160 0 0x120>; + #performance-domain-cells = <1>; + }; + }; -- cgit v1.2.3 From 187a3426a664737381a70a3fca3b8108f2300de9 Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Wed, 30 Jul 2025 10:27:30 +0300 Subject: dt-bindings: soc: samsung: usi: add samsung,exynos2200-usi compatible Add samsung,exynos2200-usi dedicated compatible for representing the USI of Samsung Exynos 2200 SoC. Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20250730072730.1882549-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index cb22637091e8..c694926e56ef 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -36,6 +36,7 @@ properties: - items: - enum: - google,gs101-usi + - samsung,exynos2200-usi - samsung,exynosautov9-usi - samsung,exynosautov920-usi - const: samsung,exynos850-usi -- cgit v1.2.3 From 0b9275edc3543d0d2d03313a7c8de5157d61b189 Mon Sep 17 00:00:00 2001 From: Sai Krishna Musham Date: Thu, 7 Aug 2025 13:10:18 +0530 Subject: dt-bindings: PCI: amd-mdb: Add example usage of reset-gpios for PCIe RP PERST# Update the device tree binding example to include usage of the `reset-gpios` property in PCIe Root Port (RP) bridge node for PERST# signal handling. Signed-off-by: Sai Krishna Musham Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250807074019.811672-2-sai.krishna.musham@amd.com --- .../bindings/pci/amd,versal2-mdb-host.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml index 43dc2585c237..421e1116ae7e 100644 --- a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml @@ -71,6 +71,17 @@ properties: - "#address-cells" - "#interrupt-cells" +patternProperties: + '^pcie@[0-2],0$': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + unevaluatedProperties: false + required: - reg - reg-names @@ -87,6 +98,7 @@ examples: - | #include #include + #include soc { #address-cells = <2>; @@ -112,6 +124,16 @@ examples: #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&tca6416_u37 7 GPIO_ACTIVE_LOW>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; -- cgit v1.2.3 From 243167e96939630b7d0d7f61be926d327e14a017 Mon Sep 17 00:00:00 2001 From: Nick Li Date: Mon, 11 Aug 2025 18:46:06 +0800 Subject: dt-bindings: vendor-prefixes: Add Shanghai FourSemi Semiconductor Co.,Ltd Add vendor prefix for Shanghai FourSemi Semiconductor Co.,Ltd Link: https://en.foursemi.com/ Signed-off-by: Nick Li Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/EA25BCF08F8BA128+20250811104610.8993-2-nick.li@foursemi.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..a92261b10c52 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -552,6 +552,8 @@ patternProperties: description: FocalTech Systems Co.,Ltd "^forlinx,.*": description: Baoding Forlinx Embedded Technology Co., Ltd. + "^foursemi,.*": + description: Shanghai FourSemi Semiconductor Co.,Ltd. "^freebox,.*": description: Freebox SAS "^freecom,.*": -- cgit v1.2.3 From fd90680da7e2d92e50ad72dfd4ea601098ab3493 Mon Sep 17 00:00:00 2001 From: Nick Li Date: Mon, 11 Aug 2025 18:46:07 +0800 Subject: ASoC: dt-bindings: Add FS2104/5S audio amplifiers Add a DT schema for describing FourSemi FS2104/5S audio amplifiers which support both I2S and I2C interface. Signed-off-by: Nick Li Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/350C011186D85903+20250811104610.8993-3-nick.li@foursemi.com Signed-off-by: Mark Brown --- .../bindings/sound/foursemi,fs2105s.yaml | 101 +++++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/foursemi,fs2105s.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/foursemi,fs2105s.yaml b/Documentation/devicetree/bindings/sound/foursemi,fs2105s.yaml new file mode 100644 index 000000000000..4da735317e0f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/foursemi,fs2105s.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/foursemi,fs2105s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FourSemi FS2104/5S Digital Audio Amplifier + +maintainers: + - Nick Li + +description: + The FS2104 is a 15W Inductor-Less, Stereo, Closed-Loop, + Digital Input Class-D Power Amplifier with Enhanced Signal Processing. + The FS2105S is a 30W Inductor-Less, Stereo, Closed-Loop, + Digital Input Class-D Power Amplifier with Enhanced Signal Processing. + +properties: + compatible: + oneOf: + - items: + - enum: + - foursemi,fs2104 + - const: foursemi,fs2105s + - enum: + - foursemi,fs2105s + + reg: + maxItems: 1 + + clocks: + items: + - description: The clock of I2S BCLK + + clock-names: + items: + - const: bclk + + interrupts: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + pvdd-supply: + description: + Regulator for power supply(PVDD in datasheet). + + dvdd-supply: + description: + Regulator for digital supply(DVDD in datasheet). + + reset-gpios: + maxItems: 1 + description: + It's the SDZ pin in datasheet, the pin is active low, + it will power down and reset the chip to shut down state. + + firmware-name: + maxItems: 1 + description: | + The firmware(*.bin) contains: + a. Register initialization settings + b. DSP effect parameters + c. Multi-scene sound effect configurations(optional) + It's gernerated by FourSemi's tuning tool. + +required: + - compatible + - reg + - '#sound-dai-cells' + - pvdd-supply + - dvdd-supply + - reset-gpios + - firmware-name + +allOf: + - $ref: dai-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + audio-codec@68 { + compatible = "foursemi,fs2105s"; + reg = <0x68>; + clocks = <&clocks 18>; + clock-names = "bclk"; + #sound-dai-cells = <0>; + pvdd-supply = <&pvdd_supply>; + dvdd-supply = <&dvdd_supply>; + reset-gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + firmware-name = "fs2105s-btl-2p0-0s.bin"; + pinctrl-names = "default"; + pinctrl-0 = <&fs210x_pins_default>; + }; + }; -- cgit v1.2.3 From a54ef14188519a0994d0264f701f5771815fa11e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 7 Aug 2025 16:44:57 -0500 Subject: regulator: dt-bindings: Clean-up active-semi,act8945a duplication The active-semi,act8945a binding is documented in multiple places. The charger child node is documented in regulator/active-semi,act8945a.yaml and power/supply/active-semi,act8945a-charger.yaml. An old text binding is in mfd/act8945a.txt. Update the regulator/active-semi,act8945a.yaml with the additional descriptions and constraints from power/supply/active-semi,act8945a-charger.yaml, and then remove it and mfd/act8945a.txt. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250807214459.4173892-1-robh@kernel.org Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/mfd/act8945a.txt | 82 ---------------------- .../power/supply/active-semi,act8945a-charger.yaml | 76 -------------------- .../bindings/regulator/active-semi,act8945a.yaml | 25 +++++-- 3 files changed, 19 insertions(+), 164 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/act8945a.txt delete mode 100644 Documentation/devicetree/bindings/power/supply/active-semi,act8945a-charger.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/act8945a.txt b/Documentation/devicetree/bindings/mfd/act8945a.txt deleted file mode 100644 index 5ca75d888b4a..000000000000 --- a/Documentation/devicetree/bindings/mfd/act8945a.txt +++ /dev/null @@ -1,82 +0,0 @@ -Device-Tree bindings for Active-semi ACT8945A MFD driver - -Required properties: - - compatible: "active-semi,act8945a". - - reg: the I2C slave address for the ACT8945A chip - -The chip exposes two subdevices: - - a regulators: see ../regulator/act8945a-regulator.txt - - a charger: see ../power/act8945a-charger.txt - -Example: - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - - active-semi,vsel-high; - - regulators { - vdd_1v35_reg: REG_DCDC1 { - regulator-name = "VDD_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd_1v2_reg: REG_DCDC2 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - vdd_3v3_reg: REG_DCDC3 { - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_fuse_reg: REG_LDO1 { - regulator-name = "VDD_FUSE"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_3v3_lp_reg: REG_LDO2 { - regulator-name = "VDD_3V3_LP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_led_reg: REG_LDO3 { - regulator-name = "VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sdhc_1v8_reg: REG_LDO4 { - regulator-name = "VDD_SDHC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - - charger { - compatible = "active-semi,act8945a-charger"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; - interrupt-parent = <&pioA>; - interrupts = <45 IRQ_TYPE_LEVEL_LOW>; - - active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/power/supply/active-semi,act8945a-charger.yaml b/Documentation/devicetree/bindings/power/supply/active-semi,act8945a-charger.yaml deleted file mode 100644 index 5220d9cb16d8..000000000000 --- a/Documentation/devicetree/bindings/power/supply/active-semi,act8945a-charger.yaml +++ /dev/null @@ -1,76 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/power/supply/active-semi,act8945a-charger.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Active-semi ACT8945A Charger Function - -maintainers: - - Sebastian Reichel - -allOf: - - $ref: power-supply.yaml# - -properties: - compatible: - const: active-semi,act8945a-charger - - interrupts: - maxItems: 1 - - active-semi,chglev-gpios: - maxItems: 1 - description: charge current level GPIO - - active-semi,lbo-gpios: - maxItems: 1 - description: low battery voltage detect GPIO - - active-semi,input-voltage-threshold-microvolt: - description: | - Specifies the charger's input over-voltage threshold value. - Despite the name, specified values are in millivolt (mV). - Defaults to 6.6 V - enum: [ 6600, 7000, 7500, 8000 ] - - active-semi,precondition-timeout: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Specifies the charger's PRECONDITION safety timer setting value in minutes. - If 0, it means to disable this timer. - Defaults to 40 minutes. - enum: [ 0, 40, 60, 80 ] - - active-semi,total-timeout: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Specifies the charger's total safety timer setting value in hours; - If 0, it means to disable this timer; - Defaults to 3 hours. - enum: [ 0, 3, 4, 5 ] - -required: - - compatible - - interrupts - - active-semi,chglev-gpios - - active-semi,lbo-gpios - -additionalProperties: false - -examples: - - | - #include - #include - pmic { - charger { - compatible = "active-semi,act8945a-charger"; - interrupt-parent = <&pioA>; - interrupts = <45 IRQ_TYPE_LEVEL_LOW>; - active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml b/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml index bdf3f7d34ef5..a8d579844dc7 100644 --- a/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml +++ b/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml @@ -91,28 +91,41 @@ properties: maxItems: 1 active-semi,chglev-gpios: - description: CGHLEV GPIO + description: charge current level GPIO maxItems: 1 active-semi,lbo-gpios: - description: LBO GPIO + description: low battery voltage detect GPIO maxItems: 1 active-semi,input-voltage-threshold-microvolt: - description: Input voltage threshold - maxItems: 1 + description: + Specifies the charger's input over-voltage threshold value. Despite + the name, specified values are in millivolt (mV). + enum: [ 6600, 7000, 7500, 8000 ] + default: 6600 active-semi,precondition-timeout: - description: Precondition timeout + description: + Specifies the charger's PRECONDITION safety timer setting value in + minutes. If 0, it means to disable this timer. + enum: [ 0, 40, 60, 80 ] + default: 40 $ref: /schemas/types.yaml#/definitions/uint32 active-semi,total-timeout: - description: Total timeout + description: + Specifies the charger's total safety timer setting value in hours; If + 0, it means to disable this timer; + enum: [ 0, 3, 4, 5 ] + default: 3 $ref: /schemas/types.yaml#/definitions/uint32 required: - compatible - interrupts + - active-semi,chglev-gpios + - active-semi,lbo-gpios additionalProperties: false -- cgit v1.2.3 From 17c66b1037aa52277d42c942db76672a1298858e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 31 Jul 2025 17:12:22 -0500 Subject: dt-bindings: fsi: Convert fsi-master-gpio to DT schema Convert the GPIO-based FSI master binding to DT schema format. Drop the "fsi-master" compatible as it has not be used consistently and doesn't represent anything. Acked-by: Eddie James Link: https://lore.kernel.org/r/20250731-dt-fsi-cleanups-v1-5-e7b695a29fc3@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/fsi/fsi-master-gpio.txt | 28 ---------- .../devicetree/bindings/fsi/fsi-master-gpio.yaml | 63 ++++++++++++++++++++++ 2 files changed, 63 insertions(+), 28 deletions(-) delete mode 100644 Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt create mode 100644 Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt b/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt deleted file mode 100644 index 1e442450747f..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-tree bindings for gpio-based FSI master driver ------------------------------------------------------ - -Required properties: - - compatible = "fsi-master-gpio"; - - clock-gpios = ; : GPIO for FSI clock - - data-gpios = ; : GPIO for FSI data signal - -Optional properties: - - enable-gpios = ; : GPIO for enable signal - - trans-gpios = ; : GPIO for voltage translator enable - - mux-gpios = ; : GPIO for pin multiplexing with other - functions (eg, external FSI masters) - - no-gpio-delays; : Don't add extra delays between GPIO - accesses. This is useful when the HW - GPIO block is running at a low enough - frequency. - -Examples: - - fsi-master { - compatible = "fsi-master-gpio", "fsi-master"; - clock-gpios = <&gpio 0>; - data-gpios = <&gpio 1>; - enable-gpios = <&gpio 2>; - trans-gpios = <&gpio 3>; - mux-gpios = <&gpio 4>; - } diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml b/Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml new file mode 100644 index 000000000000..21bfbad595b3 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/fsi-master-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: fsi-master-gpio + +maintainers: + - Eddie James + +allOf: + - $ref: /schemas/fsi/fsi-controller.yaml + +properties: + compatible: + items: + - const: fsi-master-gpio + + clock-gpios: + description: GPIO for FSI clock + maxItems: 1 + + data-gpios: + description: GPIO for FSI data signal + maxItems: 1 + + enable-gpios: + description: GPIO for enable signal + maxItems: 1 + + trans-gpios: + description: GPIO for voltage translator enable + maxItems: 1 + + mux-gpios: + description: GPIO for pin multiplexing with other functions (eg, external + FSI masters) + maxItems: 1 + + no-gpio-delays: + description: + Don't add extra delays between GPIO accesses. This is useful when the HW + GPIO block is running at a low enough frequency. + type: boolean + +required: + - compatible + - clock-gpios + - data-gpios + +unevaluatedProperties: false + +examples: + - | + fsi-master { + compatible = "fsi-master-gpio"; + clock-gpios = <&gpio 0>; + data-gpios = <&gpio 1>; + enable-gpios = <&gpio 2>; + trans-gpios = <&gpio 3>; + mux-gpios = <&gpio 4>; + }; -- cgit v1.2.3 From a678ec17f57c97e9bdcb81f67f9af73ae72b3422 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 31 Jul 2025 17:12:23 -0500 Subject: dt-bindings: fsi: Convert aspeed,ast2400-cf-fsi-master to DT schema Convert the ASpeed Coldfire offloaded GPIO FSI master. Drop the "fsi-master" compatible as it has not be used consistently and doesn't represent anything. Acked-by: Eddie James Link: https://lore.kernel.org/r/20250731-dt-fsi-cleanups-v1-6-e7b695a29fc3@kernel.org Signed-off-by: Rob Herring (Arm) --- .../bindings/fsi/aspeed,ast2400-cf-fsi-master.yaml | 81 ++++++++++++++++++++++ .../devicetree/bindings/fsi/fsi-master-ast-cf.txt | 36 ---------- 2 files changed, 81 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/fsi/aspeed,ast2400-cf-fsi-master.yaml delete mode 100644 Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/fsi/aspeed,ast2400-cf-fsi-master.yaml b/Documentation/devicetree/bindings/fsi/aspeed,ast2400-cf-fsi-master.yaml new file mode 100644 index 000000000000..690b6c936f18 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/aspeed,ast2400-cf-fsi-master.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/aspeed,ast2400-cf-fsi-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASpeed ColdFire offloaded GPIO-based FSI master + +maintainers: + - Eddie James + +allOf: + - $ref: /schemas/fsi/fsi-controller.yaml# + +properties: + compatible: + enum: + - aspeed,ast2400-cf-fsi-master + - aspeed,ast2500-cf-fsi-master + + clock-gpios: + maxItems: 1 + description: GPIO for FSI clock + + data-gpios: + maxItems: 1 + description: GPIO for FSI data signal + + enable-gpios: + maxItems: 1 + description: GPIO for enable signal + + trans-gpios: + maxItems: 1 + description: GPIO for voltage translator enable + + mux-gpios: + maxItems: 1 + description: + GPIO for pin multiplexing with other functions (eg, external FSI masters) + + memory-region: + maxItems: 1 + description: + Reference to the reserved memory for the ColdFire. Must be 2M aligned on + AST2400 and 1M aligned on AST2500. + + aspeed,cvic: + description: Reference to the CVIC node. + $ref: /schemas/types.yaml#/definitions/phandle + + aspeed,sram: + description: Reference to the SRAM node. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - clock-gpios + - data-gpios + - enable-gpios + - trans-gpios + - mux-gpios + - memory-region + - aspeed,cvic + - aspeed,sram + +unevaluatedProperties: false + +examples: + - | + fsi-master { + compatible = "aspeed,ast2500-cf-fsi-master"; + clock-gpios = <&gpio 0>; + data-gpios = <&gpio 1>; + enable-gpios = <&gpio 2>; + trans-gpios = <&gpio 3>; + mux-gpios = <&gpio 4>; + memory-region = <&coldfire_memory>; + aspeed,cvic = <&cvic>; + aspeed,sram = <&sram>; + }; diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt b/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt deleted file mode 100644 index 3dc752db748b..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt +++ /dev/null @@ -1,36 +0,0 @@ -Device-tree bindings for ColdFire offloaded gpio-based FSI master driver ------------------------------------------------------------------------- - -Required properties: - - compatible = - "aspeed,ast2400-cf-fsi-master" for an AST2400 based system - or - "aspeed,ast2500-cf-fsi-master" for an AST2500 based system - - - clock-gpios = ; : GPIO for FSI clock - - data-gpios = ; : GPIO for FSI data signal - - enable-gpios = ; : GPIO for enable signal - - trans-gpios = ; : GPIO for voltage translator enable - - mux-gpios = ; : GPIO for pin multiplexing with other - functions (eg, external FSI masters) - - memory-region = ; : Reference to the reserved memory for - the ColdFire. Must be 2M aligned on - AST2400 and 1M aligned on AST2500 - - aspeed,sram = ; : Reference to the SRAM node. - - aspeed,cvic = ; : Reference to the CVIC node. - -Examples: - - fsi-master { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; - - clock-gpios = <&gpio 0>; - data-gpios = <&gpio 1>; - enable-gpios = <&gpio 2>; - trans-gpios = <&gpio 3>; - mux-gpios = <&gpio 4>; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - } -- cgit v1.2.3 From 59304e7b80b4554fae6f1df0f518bd341a0fedc9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 6 Aug 2025 01:03:08 +0200 Subject: dt-bindings: arm: Spell out acronym When I authored these bindings I had no idea what "AEM" stood for. Now I know: it means "Architecture Envelope Model". Detail this in the bindings. Signed-off-by: Linus Walleij Acked-by: Conor Dooley Reviewed-by: Sudeep Holla Link: https://lore.kernel.org/r/20250806-aem-dt-bind-v1-1-d14676dfb027@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 8dd6b6446394..89298b39903f 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -103,8 +103,9 @@ properties: - const: arm,juno-r2 - const: arm,juno - const: arm,vexpress - - description: Arm AEMv8a Versatile Express Real-Time System Model - (VE RTSM) is a programmers view of the Versatile Express with Arm + - description: Arm AEMv8a (Architecture Envelope Model) + Versatile Express Real-Time System Model (VE RTSM) + is a programmers view of the Versatile Express with Arm v8A hardware. See ARM DUI 0575D. items: - const: arm,rtsm_ve,aemv8a -- cgit v1.2.3 From 5293e8f2a854344ef9aba2391b44c7a437889ebb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 8 Aug 2025 14:30:15 +0100 Subject: dt-bindings: pinctrl: renesas: Document RZ/T2H and RZ/N2H SoCs Document the pin and GPIO controller IP for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI header file used by both the bindings and the driver. The RZ/T2H SoC supports 729 pins, while RZ/N2H supports 576 pins. Both share the same controller architecture; separate compatible strings are added for each SoC to distinguish them. Co-developed-by: Thierry Bultel Signed-off-by: Thierry Bultel Signed-off-by: Lad Prabhakar Reviewed-by: "Rob Herring (Arm)" Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250808133017.2053637-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../pinctrl/renesas,r9a09g077-pinctrl.yaml | 172 +++++++++++++++++++++ .../pinctrl/renesas,r9a09g077-pinctrl.h | 22 +++ 2 files changed, 194 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml new file mode 100644 index 000000000000..36d665971484 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller + +maintainers: + - Lad Prabhakar + +description: + The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller. + Pin multiplexing and GPIO configuration are performed on a per-pin basis. + Each port supports up to 8 pins, each configurable for either GPIO (port mode) + or alternate function mode. Each pin supports function mode values ranging from + 0x0 to 0x2A, allowing selection from up to 43 different functions. + +properties: + compatible: + enum: + - renesas,r9a09g077-pinctrl # RZ/T2H + - renesas,r9a09g087-pinctrl # RZ/N2H + + reg: + minItems: 1 + items: + - description: Non-safety I/O Port base + - description: Safety I/O Port safety region base + - description: Safety I/O Port Non-safety region base + + reg-names: + minItems: 1 + items: + - const: nsr + - const: srs + - const: srn + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZT2H_GPIO() helper macro from + (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer + flag. Use the macros defined in include/dt-bindings/gpio/gpio.h. + + gpio-ranges: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +definitions: + renesas-rzt2h-n2h-pins-node: + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + properties: + pinmux: + description: + Values are constructed from I/O port number, pin number, and + alternate function configuration number using the RZT2H_PORT_PINMUX() + helper macro from . + pins: true + phandle: true + input: true + input-enable: true + output-enable: true + oneOf: + - required: [pinmux] + - required: [pins] + additionalProperties: false + +patternProperties: + # Grouping nodes: allow multiple "-pins" subnodes within a "-group" + '.*-group$': + type: object + description: + Pin controller client devices can organize pin configuration entries into + grouping nodes ending in "-group". These group nodes may contain multiple + child nodes each ending in "-pins" to configure distinct sets of pins. + additionalProperties: false + patternProperties: + '-pins$': + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' + + # Standalone "-pins" nodes under client devices or groups + '-pins$': + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' + + '-hog$': + type: object + description: GPIO hog node + properties: + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + line-name: true + required: + - gpio-hog + - gpios + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - clocks + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + + pinctrl@802c0000 { + compatible = "renesas,r9a09g077-pinctrl"; + reg = <0x802c0000 0x2000>, + <0x812c0000 0x2000>, + <0x802b0000 0x2000>; + reg-names = "nsr", "srs", "srn"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 288>; + power-domains = <&cpg>; + + serial0-pins { + pinmux = , /* Tx */ + ; /* Rx */ + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + i2c0-pins { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + sd0-sd-group { + ctrl-pins { + pinmux = , /* SD0_CLK */ + ; /* SD0_CMD */ + }; + + data-pins { + pinmux = , /* SD0_CLK */ + ; /* SD0_CMD */ + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h new file mode 100644 index 000000000000..f088793f23ee --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/T2H family pinctrl bindings. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ + +#define RZT2H_PINS_PER_PORT 8 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16)) + +/* Convert a port and pin label to its global pin index */ +#define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */ -- cgit v1.2.3 From c17ccefb611fdb346eef9be6bfbd0bfd04afa204 Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Mon, 11 Aug 2025 14:39:51 +0530 Subject: dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran [ Added interconnect related changes ] Reviewed-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq5424-apss-clk.yaml | 55 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,apss-ipq.h | 6 +++ include/dt-bindings/interconnect/qcom,ipq5424.h | 3 ++ 3 files changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml new file mode 100644 index 000000000000..def739fa0a8c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm APSS IPQ5424 Clock Controller + +maintainers: + - Varadarajan Narayanan + +description: + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. + The RCG and PLL have a separate register space from the GCC. + +properties: + compatible: + enum: + - qcom,ipq5424-apss-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference to the XO clock. + - description: Reference to the GPLL0 clock. + + '#clock-cells': + const: 1 + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include + + apss_clk: clock-controller@fa80000 { + compatible = "qcom,ipq5424-apss-clk"; + reg = <0x0fa80000 0x20000>; + clocks = <&xo_board>, + <&gcc GPLL0>; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h index 77b6e05492e2..0bb41e5efdef 100644 --- a/include/dt-bindings/clock/qcom,apss-ipq.h +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -8,5 +8,11 @@ #define APCS_ALIAS0_CLK_SRC 0 #define APCS_ALIAS0_CORE_CLK 1 +#define APSS_PLL_EARLY 2 +#define APSS_SILVER_CLK_SRC 3 +#define APSS_SILVER_CORE_CLK 4 +#define L3_PLL 5 +#define L3_CLK_SRC 6 +#define L3_CORE_CLK 7 #endif diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h index a770356112ee..afd7e0683a24 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -21,4 +21,7 @@ #define MASTER_CNOC_USB 16 #define SLAVE_CNOC_USB 17 +#define MASTER_CPU 0 +#define SLAVE_L3 1 + #endif /* INTERCONNECT_QCOM_IPQ5424_H */ -- cgit v1.2.3 From 3fa1095979393d5b178264cc1bdfb473e80ab774 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Fri, 2 May 2025 18:47:49 +0530 Subject: dt-bindings: sram: qcom,imem: Document IPQ5424 compatible Add compatible for Qualcomm's IPQ5424 IMEM. Acked-by: Rob Herring (Arm) Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20250502-wdt_reset_reason-v3-1-b2dc7ace38ca@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 72d35e30c439..6a627c57ae2f 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - qcom,apq8064-imem + - qcom,ipq5424-imem - qcom,msm8226-imem - qcom,msm8974-imem - qcom,msm8976-imem -- cgit v1.2.3 From 3e0252ea5d91ac21c6b606f71f42733b526646df Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 4 Jun 2025 16:40:28 +0300 Subject: dt-bindings: arm: qcom: add qcom,sm6150 fallback compatible to QCS615 QCS615 SoC is based on the earlier mobile chip SM6150. Add corresponding compatible string to follow established practice for IoT chips. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250604-qcs615-sm6150-v1-1-2f01fd46c365@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index bf5f3beb320b..1b705079c1ae 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -87,6 +87,7 @@ description: | sm6115 sm6115p sm6125 + sm6150 sm6350 sm6375 sm7125 @@ -949,6 +950,7 @@ properties: - enum: - qcom,qcs615-ride - const: qcom,qcs615 + - const: qcom,sm6150 - items: - enum: -- cgit v1.2.3 From 1a67f85c690658a35cac41c070df33e3e5a72868 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Sun, 25 May 2025 06:53:33 -0300 Subject: dt-bindings: arm: qcom: Add Dell Latitude 7455 Document the X1E80100-based Dell Latitude 7455 laptop. Signed-off-by: Val Packett Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250525095341.12462-3-val@packett.cool Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1b705079c1ae..c8a71a33d358 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1149,6 +1149,7 @@ properties: - enum: - asus,vivobook-s15 - asus,zenbook-a14-ux3407ra + - dell,latitude-7455 - dell,xps13-9345 - hp,elitebook-ultra-g1q - hp,omnibook-x14 -- cgit v1.2.3 From cb69daf085b5974fef2df9789f8c1b35e78e7913 Mon Sep 17 00:00:00 2001 From: Nick Hu Date: Fri, 1 Aug 2025 15:01:12 +0800 Subject: dt-bindings: riscv: Add SiFive vendor extensions description Add description for SiFive vendor extensions "xsfcflushdlone", "xsfpgflushdlone" and "xsfcease". This is used in the SBI implementation [1]. Link: https://lore.kernel.org/opensbi/20250708074940.10904-1-nick.hu@sifive.com/ [1] Signed-off-by: Nick Hu Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf53..5638297759df 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -663,6 +663,24 @@ properties: https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf # SiFive + - const: xsfcease + description: + SiFive CEASE Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/freedom-u740-c000-manual + + - const: xsfcflushdlone + description: + SiFive L1D Cache Flush Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/freedom-u740-c000-manual + + - const: xsfpgflushdlone + description: + SiFive PGFLUSH Instruction Extensions for the power management. The + CPU will flush the L1D and enter the cease state after executing + the instruction. + - const: xsfvqmaccdod description: SiFive Int8 Matrix Multiplication Extensions Specification. -- cgit v1.2.3 From f93e5882134a314760d47536d93b57fbd32d0da1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Jul 2025 15:24:37 +0200 Subject: dt-bindings: arm: qcom: Drop redundant free-form SoC list The schema and Devicetree specification defines how list of top-level compatibles should be created, thus first paragraph explaining this is completely redundant. The list of SoCs is redundant as well, because the schema lists them. On the other hand, Linux kernel should not be place to store marketing names of some company products, so such list is irrelevant here. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250724132436.77160-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 95 ------------------------- 1 file changed, 95 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8a71a33d358..1df00d9e6de0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -10,101 +10,6 @@ maintainers: - Bjorn Andersson description: | - For devices using the Qualcomm SoC the "compatible" properties consists of - one or several "manufacturer,model" strings, describing the device itself, - followed by one or several "qcom," strings, describing the SoC used in - the device. - - The 'SoC' element must be one of the following strings: - - apq8016 - apq8026 - apq8064 - apq8074 - apq8084 - apq8094 - apq8096 - ipq4018 - ipq4019 - ipq5018 - ipq5332 - ipq5424 - ipq6018 - ipq8064 - ipq8074 - ipq9574 - mdm9615 - msm8226 - msm8660 - msm8916 - msm8917 - msm8926 - msm8929 - msm8939 - msm8953 - msm8956 - msm8960 - msm8974 - msm8974pro - msm8976 - msm8992 - msm8994 - msm8996 - msm8996pro - msm8998 - qcs404 - qcs615 - qcs8300 - qcs8550 - qcm2290 - qcm6490 - qcs9100 - qdu1000 - qrb2210 - qrb4210 - qru1000 - sa8155p - sa8540p - sa8775p - sar2130p - sc7180 - sc7280 - sc8180x - sc8280xp - sda660 - sdm450 - sdm630 - sdm632 - sdm636 - sdm660 - sdm670 - sdm845 - sdx55 - sdx65 - sdx75 - sm4250 - sm4450 - sm6115 - sm6115p - sm6125 - sm6150 - sm6350 - sm6375 - sm7125 - sm7150 - sm7225 - sm7325 - sm8150 - sm8250 - sm8350 - sm8450 - sm8550 - sm8650 - sm8750 - x1e78100 - x1e80100 - x1p42100 - There are many devices in the list below that run the standard ChromeOS bootloader setup and use the open source depthcharge bootloader to boot the OS. These devices use the bootflow explained at -- cgit v1.2.3 From a6c4d92fcc74b4402d1ecdf6f4a7304a37a69ada Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 17 Jul 2025 08:54:46 +0200 Subject: dt-bindings: soc: qcom,rpmh-rsc: Remove double colon from description No double colon is necessary in the description. Fix it. Reported-by: Rob Herring Closes: https://lore.kernel.org/lkml/20250625150458.GA1182597-robh@kernel.org/ Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717-bindings-double-colon-v1-3-c04abc180fcd@fairphone.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index 036562eb5140..26d9bc773ec5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -28,7 +28,7 @@ description: | SLEEP - Triggered by F/W WAKE - Triggered by F/W CONTROL - Triggered by F/W - See also:: + See also: The order in which they are described in the DT, should match the hardware configuration. -- cgit v1.2.3 From 474aa14da0e160f2f3fb002b64b8363ae91f9590 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Jul 2025 18:24:13 +0200 Subject: dt-bindings: arm: qcom-soc: Document new Milos and Glymur SoCs Extend the schema enforcing correct SoC-block naming to cover Milos (compatibles already accepted by some maintainers for next release) and Glymur (posted on mailing lists [1]) SoCs. Link: https://lore.kernel.org/linux-devicetree/20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com/ [1] Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250716162412.27471-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom-soc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index a77d68dcad4e..27261039d56f 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -23,7 +23,9 @@ description: | select: properties: compatible: - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + oneOf: + - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,.*(glymur|milos).*$" required: - compatible @@ -34,6 +36,7 @@ properties: - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" + - pattern: "^qcom,(glymur|milos)-.*$" # Legacy namings - variations of existing patterns/compatibles are OK, # but do not add completely new entries to these: -- cgit v1.2.3 From bae72efa3ca6674ff99668b00290376babae10f5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jul 2025 12:16:08 +0200 Subject: dt-bindings: arm: qcom: Remove sdm845-cheza Cheza was a prototype board, used mainly by the ChromeOS folks. Almost no working devices are known to exist, and the small amount of remaining ones are not in use anymore. Remove the compatible strings reserved for it, as, quite frankly, Cheza is no more. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-2-6fa8d3261813@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 3 --- 1 file changed, 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1df00d9e6de0..b5acb0d26346 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -884,9 +884,6 @@ properties: - items: - enum: - - google,cheza - - google,cheza-rev1 - - google,cheza-rev2 - lenovo,yoga-c630 - lg,judyln - lg,judyp -- cgit v1.2.3 From 3a99873d8b9f6c1ec027987fff7b32eab9273316 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 22 Jun 2025 18:26:47 +0000 Subject: dt-bindings: arm: qcom: add Sony Xperia SP Document the Sony Xperia SP (huashan), which uses the MSM8960T SoC. The MSM8960T is a variant of the MSM8960 featuring an upgraded GPU (Adreno 320 instead of Adreno 225) and a slightly overclocked CPU (1.7GHz instead of 1.5GHz). Signed-off-by: Antony Kurniawan Soemardi Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250623-msm8960-sdcard-v2-4-340a5e8f7df0@smankusors.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae43b3556580..b9e8defc7ffe 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -203,6 +203,12 @@ properties: - samsung,expressatt - const: qcom,msm8960 + - items: + - enum: + - sony,huashan + - const: qcom,msm8960t + - const: qcom,msm8960 + - items: - enum: - lge,hammerhead -- cgit v1.2.3 From be477c3924f80809871df12f72d80d405d482ba2 Mon Sep 17 00:00:00 2001 From: Satya Priya Kakitapalli Date: Thu, 10 Jul 2025 18:30:39 +0530 Subject: dt-bindings: clock: qcom,videocc: Add sc8180x compatible The sc8180x video clock controller block is identical to that of sm8150. Add a new compatible string for sc8180x videocc and use sm8150 as fallback. Signed-off-by: Satya Priya Kakitapalli Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250710-sc8180x-videocc-dt-v4-1-07a9d9d5e0e6@quicinc.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,videocc.yaml | 23 +++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 5f7738d6835c..f4ff9acef9d5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -23,13 +23,17 @@ description: | properties: compatible: - enum: - - qcom,sc7180-videocc - - qcom,sc7280-videocc - - qcom,sdm845-videocc - - qcom,sm6350-videocc - - qcom,sm8150-videocc - - qcom,sm8250-videocc + oneOf: + - enum: + - qcom,sc7180-videocc + - qcom,sc7280-videocc + - qcom,sdm845-videocc + - qcom,sm6350-videocc + - qcom,sm8150-videocc + - qcom,sm8250-videocc + - items: + - const: qcom,sc8180x-videocc + - const: qcom,sm8150-videocc clocks: minItems: 1 @@ -110,8 +114,9 @@ allOf: - if: properties: compatible: - enum: - - qcom,sm8150-videocc + contains: + enum: + - qcom,sm8150-videocc then: properties: clocks: -- cgit v1.2.3 From e98329896b5639f8437af8ff9316f20cb50d9187 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 2 Jul 2025 14:43:09 +0530 Subject: dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS615 compatible Document compatible for cpufreq hardware on Qualcomm QCS615 platform. Signed-off-by: Taniya Das Acked-by: Krzysztof Kozlowski Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e0242bed3342..2d42fc3d8ef8 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -22,6 +22,7 @@ properties: items: - enum: - qcom,qcm2290-cpufreq-hw + - qcom,qcs615-cpufreq-hw - qcom,sc7180-cpufreq-hw - qcom,sc8180x-cpufreq-hw - qcom,sdm670-cpufreq-hw @@ -132,6 +133,7 @@ allOf: compatible: contains: enum: + - qcom,qcs615-cpufreq-hw - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss - qcom,sa8775p-cpufreq-epss -- cgit v1.2.3 From 78a474b5a31a25e0a77e50df42be925f7cb575e6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Aug 2025 15:54:04 +0200 Subject: dt-bindings: phy: fsl,imx8mq-usb: Drop 'db' suffix duplicating dtschema A common property unit suffix '-db' was added to dtschema, thus in-kernel bindings should not reference the type. Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250811-dt-bindings-db-v1-2-457301523bb5@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml index 22dd91591a09..6a47e08e0e97 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml @@ -76,7 +76,6 @@ properties: description: Adjust TX de-emphasis attenuation in dB at nominal 3.5dB point as per USB specification - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 36 -- cgit v1.2.3 From 8c02c8353460f8630313aef6810f34e134a3c1ee Mon Sep 17 00:00:00 2001 From: Mahdi Khosravi Date: Mon, 11 Aug 2025 11:09:40 +0300 Subject: ASoC: dt-bindings: realtek,alc5623: convert to DT schema Convert alc5623 audio codec binding to DT schema. Also add "realtek,alc5621" to the compatible list for existing use in kirkwood-t5325.dts. Signed-off-by: Mahdi Khosravi Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250811080940.7909-1-mmk1776@gmail.com Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/alc5623.txt | 25 ---------- .../devicetree/bindings/sound/realtek,alc5623.yaml | 54 ++++++++++++++++++++++ 2 files changed, 54 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/alc5623.txt create mode 100644 Documentation/devicetree/bindings/sound/realtek,alc5623.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/alc5623.txt b/Documentation/devicetree/bindings/sound/alc5623.txt deleted file mode 100644 index 26c86c98d671..000000000000 --- a/Documentation/devicetree/bindings/sound/alc5623.txt +++ /dev/null @@ -1,25 +0,0 @@ -ALC5621/ALC5622/ALC5623 audio Codec - -Required properties: - - - compatible: "realtek,alc5623" - - reg: the I2C address of the device. - -Optional properties: - - - add-ctrl: Default register value for Reg-40h, Additional Control - Register. If absent or has the value of 0, the - register is untouched. - - - jack-det-ctrl: Default register value for Reg-5Ah, Jack Detect - Control Register. If absent or has value 0, the - register is untouched. - -Example: - - alc5621: alc5621@1a { - compatible = "alc5621"; - reg = <0x1a>; - add-ctrl = <0x3700>; - jack-det-ctrl = <0x4810>; - }; diff --git a/Documentation/devicetree/bindings/sound/realtek,alc5623.yaml b/Documentation/devicetree/bindings/sound/realtek,alc5623.yaml new file mode 100644 index 000000000000..683c58c3ef50 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/realtek,alc5623.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/realtek,alc5623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ALC5621/ALC5623 Audio Codec + +maintainers: + - Mahdi Khosravi + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - realtek,alc5621 + - realtek,alc5623 + + reg: + maxItems: 1 + + add-ctrl: + description: + Default register value for Reg-40h, Additional Control Register. + If absent or zero, the register is left untouched. + $ref: /schemas/types.yaml#/definitions/uint32 + + jack-det-ctrl: + description: + Default register value for Reg-5Ah, Jack Detect Control Register. + If absent or zero, the register is left untouched. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + codec@1a { + compatible = "realtek,alc5623"; + reg = <0x1a>; + add-ctrl = <0x3700>; + jack-det-ctrl = <0x4810>; + }; + }; -- cgit v1.2.3 From ebfe5797ac3e6e9fb56340b6b228d2747fdec912 Mon Sep 17 00:00:00 2001 From: Eric Gonçalves Date: Sun, 15 Jun 2025 20:44:37 +0000 Subject: dt-bindings: arm: qcom: document r0q board binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds compatible for the Samsung Galaxy S22 (SM-S901E) (r0q), based on the Snapdragon 8 Gen 1 SoC. Signed-off-by: Eric Gonçalves Link: https://lore.kernel.org/r/20250615204438.1130213-1-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b5acb0d26346..fa929698229e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1002,6 +1002,7 @@ properties: - qcom,sm8450-qrd - sony,pdx223 - sony,pdx224 + - samsung,r0q - const: qcom,sm8450 - items: -- cgit v1.2.3 From f8262b8dadfa635cc8f203c40eb0b75b8625f44c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Aug 2025 16:22:36 +0200 Subject: dt-bindings: nfc: ti,trf7970a: Drop 'db' suffix duplicating dtschema A common property unit suffix '-db' was added to dtschema, thus in-kernel bindings should not reference the type. Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley Link: https://patch.msgid.link/20250811142235.170407-2-krzysztof.kozlowski@linaro.org Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml b/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml index 5f49bd9ac5e6..783a85b84893 100644 --- a/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml +++ b/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml @@ -56,7 +56,6 @@ properties: Regulator for supply voltage to VIN pin ti,rx-gain-reduction-db: - $ref: /schemas/types.yaml#/definitions/uint32 description: | Specify an RX gain reduction to reduce antenna sensitivity with 5dB per increment, with a maximum of 15dB. Supported values: [0, 5, 10, 15]. -- cgit v1.2.3 From bab4ab484a6ca170847da9bffe86f1fa90df4bbe Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 15:33:55 -0500 Subject: ASoC: dt-bindings: Convert brcm,bcm2835-i2s to DT schema Convert the Broadcom BCM2835 I2S/PCM binding to DT schema format. It's a straightforward conversion. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250812203356.735234-1-robh@kernel.org Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/brcm,bcm2835-i2s.txt | 24 ---------- .../bindings/sound/brcm,bcm2835-i2s.yaml | 51 ++++++++++++++++++++++ 2 files changed, 51 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt create mode 100644 Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt deleted file mode 100644 index 7bb0362828ec..000000000000 --- a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Broadcom BCM2835 SoC I2S/PCM module - -Required properties: -- compatible: "brcm,bcm2835-i2s" -- reg: Should contain PCM registers location and length. -- clocks: the (PCM) clock to use -- dmas: List of DMA controller phandle and DMA request line ordered pairs. -- dma-names: Identifier string for each DMA request line in the dmas property. - These strings correspond 1:1 with the ordered pairs in dmas. - - One of the DMA channels will be responsible for transmission (should be - named "tx") and one for reception (should be named "rx"). - -Example: - -bcm2835_i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x24>; - clocks = <&clocks BCM2835_CLOCK_PCM>; - - dmas = <&dma 2>, - <&dma 3>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.yaml b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.yaml new file mode 100644 index 000000000000..f3cfe92684d0 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/brcm,bcm2835-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 SoC I2S/PCM module + +maintainers: + - Florian Fainelli + +properties: + compatible: + const: brcm,bcm2835-i2s + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + dmas: + items: + - description: Transmission DMA controller phandle and request line. + - description: Reception DMA controller phandle and request line. + + dma-names: + items: + - const: tx + - const: rx + +required: + - compatible + - reg + - clocks + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include + + i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = <0x7e203000 0x24>; + clocks = <&clocks BCM2835_CLOCK_PCM>; + dmas = <&dma 2>, <&dma 3>; + dma-names = "tx", "rx"; + }; -- cgit v1.2.3 From cebd717d8f010a9897105434dbc6bdbd85693596 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Mon, 11 Aug 2025 17:31:36 +0200 Subject: dt-bindings: net: airoha: npu: Add memory regions used for wlan offload Document memory regions used by Airoha EN7581 NPU for wlan traffic offloading. The brand new added memory regions do not introduce any backward compatibility issues since they will be used just to offload traffic to/from the MT76 wireless NIC and the MT76 probing will not fail if these memory regions are not provide, it will just disable offloading via the NPU module. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Lorenzo Bianconi Link: https://patch.msgid.link/20250811-airoha-en7581-wlan-offlaod-v7-1-58823603bb4e@kernel.org Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/airoha,en7581-npu.yaml | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml index 76dd97c3fb40..c7644e6586d3 100644 --- a/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml +++ b/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml @@ -41,9 +41,21 @@ properties: - description: wlan irq line5 memory-region: - maxItems: 1 - description: - Memory used to store NPU firmware binary. + oneOf: + - items: + - description: NPU firmware binary region + - items: + - description: NPU firmware binary region + - description: NPU wlan offload RX buffers region + - description: NPU wlan offload TX buffers region + - description: NPU wlan offload TX packet identifiers region + + memory-region-names: + items: + - const: firmware + - const: pkt + - const: tx-pkt + - const: tx-bufid required: - compatible @@ -79,6 +91,8 @@ examples: , , ; - memory-region = <&npu_binary>; + memory-region = <&npu_firmware>, <&npu_pkt>, <&npu_txpkt>, + <&npu_txbufid>; + memory-region-names = "firmware", "pkt", "tx-pkt", "tx-bufid"; }; }; -- cgit v1.2.3 From 4ca28157bd52dfa6df665f8854d754cc03f45acf Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Mon, 28 Jul 2025 10:29:43 +0000 Subject: dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon Add compatible string for pipe-phy GRF found on RK3528 SoC, which controls misc settings for the integrated naneng-combphy. Signed-off-by: Yao Zi Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250728102947.38984-3-ziyao@disroot.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 1ab0b092e2a5..fe5361713167 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -16,6 +16,7 @@ properties: - enum: - rockchip,rk3288-sgrf - rockchip,rk3528-ioc-grf + - rockchip,rk3528-pipe-phy-grf - rockchip,rk3528-vo-grf - rockchip,rk3528-vpu-grf - rockchip,rk3562-ioc-grf -- cgit v1.2.3 From 43a9fade69799bd10e315e87cdc60a3f75b85414 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Mon, 28 Jul 2025 10:29:44 +0000 Subject: dt-bindings: phy: rockchip: naneng-combphy: Add power-domains property Though isn't described in existing devicetrees, most Rockchip combphys belong to a specific power-domain of the SoC. Taking RK3588 as example, combphy 0 and combphy 2 belong to the PD_BUS domain. Document the power-domains property to allow describing the information correctly in devicetree. Signed-off-by: Yao Zi Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250728102947.38984-4-ziyao@disroot.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml index 3e101c3c5ea9..db293d2fbf1a 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -45,6 +45,9 @@ properties: phy-supply: description: Single PHY regulator + power-domains: + maxItems: 1 + rockchip,enable-ssc: type: boolean description: -- cgit v1.2.3 From b6c02cba32b9902b2b51dee740f1d3af8271820a Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Mon, 28 Jul 2025 10:29:45 +0000 Subject: dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant Rockchip RK3528 ships one naneng-combphy which operates in either PCIe or USB 3 mode. Document its compatible string. Signed-off-by: Yao Zi Acked-by: Conor Dooley Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250728102947.38984-5-ziyao@disroot.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml index db293d2fbf1a..379b08bd9e97 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: enum: + - rockchip,rk3528-naneng-combphy - rockchip,rk3562-naneng-combphy - rockchip,rk3568-naneng-combphy - rockchip,rk3576-naneng-combphy @@ -108,7 +109,9 @@ allOf: properties: compatible: contains: - const: rockchip,rk3588-naneng-combphy + enum: + - rockchip,rk3528-naneng-combphy + - rockchip,rk3588-naneng-combphy then: properties: resets: -- cgit v1.2.3 From 791cfbe1c56076c9d3bcf856b5175bfbc9c5a2d4 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 9 Jul 2025 16:55:14 +0200 Subject: dt-bindings: phy: qcom,snps-eusb2-repeater: Document qcom,tune-res-fsdif Document the FS Differential TX Output Resistance Tuning value found on the eUSB2 repeater on Qualcomm PMICs. The tuning values have special meanings, being different offsets of the resistance to the default value in Ohms but the exact meaning is not relevant here, as the correct tuning is determined by hardware engineers to make sure the electrical properties are as expected. Signed-off-by: Luca Weiss Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250709-sm7635-eusb-repeater-v2-1-b6eff075c097@fairphone.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml index 27f064a71c9f..6bfd11657e29 100644 --- a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml @@ -52,6 +52,12 @@ properties: minimum: 0 maximum: 7 + qcom,tune-res-fsdif: + $ref: /schemas/types.yaml#/definitions/uint8 + description: FS Differential TX Output Resistance Tuning + minimum: 0 + maximum: 7 + required: - compatible - reg -- cgit v1.2.3 From 5edc4054655009691deb79142af1ffe5aba0a224 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 9 Jul 2025 16:55:16 +0200 Subject: dt-bindings: phy: qcom,snps-eusb2-repeater: Add compatible for PMIV0104 Add a dt-bindings compatible string for the Qualcomm's PMIV0104 PMIC. Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250709-sm7635-eusb-repeater-v2-3-b6eff075c097@fairphone.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml index 6bfd11657e29..5bf0d6c9c025 100644 --- a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-repeater.yaml @@ -22,6 +22,7 @@ properties: - const: qcom,pm8550b-eusb2-repeater - enum: - qcom,pm8550b-eusb2-repeater + - qcom,pmiv0104-eusb2-repeater - qcom,smb2360-eusb2-repeater reg: -- cgit v1.2.3 From 1aba1eab0bd896928ae20dbf1f60a175a6e1ad0f Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 29 Jul 2025 13:52:12 -0700 Subject: dt-bindings: memory: Update brcmstb-memc-ddr binding with older chips The older MIPS-based chips incorporated a memory controller with the revision A.0.0, update the binding to list that compatible. Signed-off-by: Florian Fainelli Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250729205213.3392481-2-florian.fainelli@broadcom.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml index b935894bd4fc..3328c8df8190 100644 --- a/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml @@ -42,6 +42,10 @@ properties: items: - const: brcm,brcmstb-memc-ddr-rev-b.1.x - const: brcm,brcmstb-memc-ddr + - description: Revision 0.x controllers + items: + - const: brcm,brcmstb-memc-ddr-rev-a.0.0 + - const: brcm,brcmstb-memc-ddr reg: maxItems: 1 -- cgit v1.2.3 From d0de6895095356f1cc2d5f9825df220f10d34cee Mon Sep 17 00:00:00 2001 From: Jeff Chang Date: Wed, 13 Aug 2025 10:08:50 +0800 Subject: regulator: dt-bindings: Add Richtek RT5133 Support Add bindings for Richtek RT5133 IC Controlled PMIC Signed-off-by: Jeff Chang Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250813020910.2977555-1-jeff_chang@richtek.com Signed-off-by: Mark Brown --- .../bindings/regulator/richtek,rt5133.yaml | 178 +++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/richtek,rt5133.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/richtek,rt5133.yaml b/Documentation/devicetree/bindings/regulator/richtek,rt5133.yaml new file mode 100644 index 000000000000..d2e007fee6ba --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/richtek,rt5133.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/richtek,rt5133.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT5133 PMIC Regulator + +maintainers: + - ShihChia Chang + +description: + The RT5133 is an integrated Power Management IC for portable devices, + featuring 8 LDOs and 3 GPOs. It allows programmable output voltages, + soft-start times, and protections via I2C. GPO operation depends on LDO1 + voltage. + +properties: + compatible: + enum: + - richtek,rt5133 + + reg: + maxItems: 1 + + enable-gpios: + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + richtek,oc-shutdown-all: + type: boolean + description: + Controls the behavior when any LDO (Low Dropout Regulator) enters an + Over Current state. + If set to true, all LDO channels will be shut down. + If set to false, only the affected LDO channel will shut down itself. + + richtek,pgb-shutdown-all: + type: boolean + description: + Controls the behavior when any LDO enters a Power Good Bad state. + If set to true, all LDO channels will be shut down. + If set to false, only the affected LDO channel will shut down itself. + + regulators: + type: object + additionalProperties: false + + properties: + base: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for the base regulator, which is the top-level supply for + LDO1 to LDO6. It functions merely as an on/off switch rather than + regulating voltages. If none of LDO1 to LDO6 are in use, switching + off the base will reduce the quiescent current. + + required: + - regulator-name + + patternProperties: + "^ldo([1-6])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator + + required: + - regulator-name + + "^ldo([7-8])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator + + properties: + vin-supply: true + + required: + - regulator-name + - vin-supply + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@18 { + compatible = "richtek,rt5133"; + reg = <0x18>; + wakeup-source; + interrupts-extended = <&gpio 0 IRQ_TYPE_EDGE_FALLING>; + enable-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + gpio-controller; + #gpio-cells = <2>; + richtek,oc-shutdown-all; + richtek,pgb-shutdown-all; + regulators { + base { + regulator-name = "base"; + }; + pvin78: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3199998>; + regulator-active-discharge = <1>; + }; + ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3200000>; + regulator-active-discharge = <1>; + }; + ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + regulator-active-discharge = <1>; + }; + ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + regulator-active-discharge = <1>; + }; + ldo5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + regulator-active-discharge = <1>; + }; + ldo6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + regulator-active-discharge = <1>; + }; + ldo7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-active-discharge = <1>; + vin-supply = <&pvin78>; + }; + ldo8 { + regulator-name = "ldo8"; + regulator-min-microvolt = <855000>; + regulator-max-microvolt = <1200000>; + regulator-active-discharge = <1>; + vin-supply = <&pvin78>; + }; + }; + }; + }; -- cgit v1.2.3 From 20b3c9a403ee23e57a7e6bf5370ca438c3cd2e99 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 6 Aug 2025 16:28:23 -0500 Subject: dt-bindings: arm: Convert ti,keystone to DT schema Signed-off-by: Rob Herring (Arm) Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20250806212824.1635084-1-robh@kernel.org Signed-off-by: Nishanth Menon --- .../devicetree/bindings/arm/keystone/keystone.txt | 42 ---------------------- .../devicetree/bindings/arm/ti/ti,keystone.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/keystone/keystone.txt create mode 100644 Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt deleted file mode 100644 index f310bad04483..000000000000 --- a/Documentation/devicetree/bindings/arm/keystone/keystone.txt +++ /dev/null @@ -1,42 +0,0 @@ -TI Keystone Platforms Device Tree Bindings ------------------------------------------------ - -Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the -following properties. - -Required properties: - - compatible: All TI specific devices present in Keystone SOC should be in - the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 - type UART should use the specified compatible for those devices. - -SoC families: - -- Keystone 2 generic SoC: - compatible = "ti,keystone" - -SoCs: - -- Keystone 2 Hawking/Kepler - compatible = "ti,k2hk", "ti,keystone" -- Keystone 2 Lamarr - compatible = "ti,k2l", "ti,keystone" -- Keystone 2 Edison - compatible = "ti,k2e", "ti,keystone" -- K2G - compatible = "ti,k2g", "ti,keystone" - -Boards: -- Keystone 2 Hawking/Kepler EVM - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone" - -- Keystone 2 Lamarr EVM - compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone" - -- Keystone 2 Edison EVM - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone" - -- K2G EVM - compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone" - -- K2G Industrial Communication Engine EVM - compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone" diff --git a/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml b/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml new file mode 100644 index 000000000000..20d4084f4506 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/ti,keystone.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone Platforms + +maintainers: + - Nishanth Menon + - Santosh Shilimkar + +properties: + compatible: + oneOf: + - description: K2G + items: + - enum: + - ti,k2g-evm + - ti,k2g-ice + - const: ti,k2g + - const: ti,keystone + - description: Keystone 2 Edison + items: + - enum: + - ti,k2e-evm + - const: ti,k2e + - const: ti,keystone + - description: Keystone 2 Lamarr + items: + - enum: + - ti,k2l-evm + - const: ti,k2l + - const: ti,keystone + - description: Keystone 2 Hawking/Kepler + items: + - enum: + - ti,k2hk-evm + - const: ti,k2hk + - const: ti,keystone + +additionalProperties: true -- cgit v1.2.3 From e58ebd14a5f15eccf3dd45edf4bc900b346096bf Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 5 Aug 2025 12:47:29 +0100 Subject: dt-bindings: usb: renesas,usbhs: Add RZ/T2H and RZ/N2H support Document the USBHS controller for the Renesas RZ/T2H (r9a09g077) and RZ/N2H (r9a09g087) SoCs. While the USBHS block is similar to the one found on the RZ/G2L SoC, it differs slightly in terms of interrupt configuration, clock/reset requirements, and register bit definitions. Due to these differences, a new compatible string `renesas,usbhs-r9a09g077` is introduced for the RZ/T2H SoC. The USBHS controller on the RZ/N2H (r9a09g087) SoC is identical to that on the RZ/T2H, so it uses the `renesas,usbhs-r9a09g077` compatible string as a fallback. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250805114730.2491238-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/renesas,usbhs.yaml | 28 +++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index a19816bbb1fd..0b8b90dd1951 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -59,6 +59,12 @@ properties: - renesas,usbhs-r8a77995 # R-Car D3 - const: renesas,rcar-gen3-usbhs + - const: renesas,usbhs-r9a09g077 # RZ/T2H + + - items: + - const: renesas,usbhs-r9a09g087 # RZ/N2H + - const: renesas,usbhs-r9a09g077 # RZ/T2H + reg: maxItems: 1 @@ -141,9 +147,25 @@ allOf: required: - resets else: - properties: - interrupts: - maxItems: 1 + if: + properties: + compatible: + contains: + const: renesas,usbhs-r9a09g077 + then: + properties: + resets: false + clocks: + maxItems: 1 + interrupts: + items: + - description: USB function interrupt USB_FI + - description: USB function DMA0 transmit completion interrupt USB_FDMA0 + - description: USB function DMA1 transmit completion interrupt USB_FDMA1 + else: + properties: + interrupts: + maxItems: 1 additionalProperties: false -- cgit v1.2.3 From 738812440b3c9083188191caa62ef950cf1ed9ed Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 7 Aug 2025 16:43:50 -0500 Subject: dt-bindings: usb: Drop duplicate nvidia,tegra20-ehci.txt The nvidia,tegra20-ehci binding is already documented in ci-hdrc-usb2.yaml, so drop the old text binding. Signed-off-by: "Rob Herring (Arm)" Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250807214351.4172243-1-robh@kernel.org Signed-off-by: Greg Kroah-Hartman --- .../bindings/usb/nvidia,tegra20-ehci.txt | 23 ---------------------- 1 file changed, 23 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt deleted file mode 100644 index f60785f73d3d..000000000000 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt +++ /dev/null @@ -1,23 +0,0 @@ -Tegra SOC USB controllers - -The device node for a USB controller that is part of a Tegra -SOC is as described in the document "Open Firmware Recommended -Practice : Universal Serial Bus" with the following modifications -and additions : - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-ehci". - For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain - "nvidia,-ehci" plus at least one of the above, where is - tegra114, tegra124, tegra132, or tegra210. - - nvidia,phy : phandle of the PHY that the controller is connected to. - - clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb - -Optional properties: - - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20 - USB ports, which need reset twice due to hardware issues. -- cgit v1.2.3 From d903f5c60a0ea95aa03d5158d38bb057da6eae3e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 4 Aug 2025 17:20:40 -0500 Subject: dt-bindings: clock: Convert silabs,si514/544 to DT schema Convert the Silicon Labs SI514 and SI544 bindings to DT schema format. Combine the bindings into a single schema as they are the same. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250804222042.4083656-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/silabs,si514.txt | 24 ---------- .../devicetree/bindings/clock/silabs,si544.txt | 25 ---------- .../devicetree/bindings/clock/silabs,si544.yaml | 54 ++++++++++++++++++++++ 3 files changed, 54 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si514.txt delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si544.txt create mode 100644 Documentation/devicetree/bindings/clock/silabs,si544.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/silabs,si514.txt b/Documentation/devicetree/bindings/clock/silabs,si514.txt deleted file mode 100644 index a4f28ec86f35..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si514.txt +++ /dev/null @@ -1,24 +0,0 @@ -Binding for Silicon Labs 514 programmable I2C clock generator. - -Reference -This binding uses the common clock binding[1]. Details about the device can be -found in the datasheet[2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Si514 datasheet - https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf - -Required properties: - - compatible: Shall be "silabs,si514" - - reg: I2C device address. - - #clock-cells: From common clock bindings: Shall be 0. - -Optional properties: - - clock-output-names: From common clock bindings. Recommended to be "si514". - -Example: - si514: clock-generator@55 { - reg = <0x55>; - #clock-cells = <0>; - compatible = "silabs,si514"; - }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.txt b/Documentation/devicetree/bindings/clock/silabs,si544.txt deleted file mode 100644 index b86535b80920..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si544.txt +++ /dev/null @@ -1,25 +0,0 @@ -Binding for Silicon Labs 544 programmable I2C clock generator. - -Reference -This binding uses the common clock binding[1]. Details about the device can be -found in the datasheet[2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Si544 datasheet - https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf - -Required properties: - - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according - to the speed grade of the chip. - - reg: I2C device address. - - #clock-cells: From common clock bindings: Shall be 0. - -Optional properties: - - clock-output-names: From common clock bindings. Recommended to be "si544". - -Example: - si544: clock-controller@55 { - reg = <0x55>; - #clock-cells = <0>; - compatible = "silabs,si544b"; - }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.yaml b/Documentation/devicetree/bindings/clock/silabs,si544.yaml new file mode 100644 index 000000000000..f87e71867108 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si544.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/silabs,si544.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Labs SI514/SI544 clock generator + +maintainers: + - Mike Looijmans + +description: > + Silicon Labs 514/544 programmable I2C clock generator. Details about the device + can be found in the datasheet: + + https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf + https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf + +properties: + compatible: + enum: + - silabs,si514 + - silabs,si544a + - silabs,si544b + - silabs,si544c + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@55 { + reg = <0x55>; + #clock-cells = <0>; + compatible = "silabs,si544b"; + }; + }; -- cgit v1.2.3 From b02011c8c61f1e61d6b4edf6a9e24620c965d376 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 4 Aug 2025 17:20:32 -0500 Subject: dt-bindings: clock: Convert silabs,si5341 to DT schema Convert the Silicon Labs SI5341 binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250804222034.4083410-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/silabs,si5341.txt | 175 ----------------- .../devicetree/bindings/clock/silabs,si5341.yaml | 217 +++++++++++++++++++++ 2 files changed, 217 insertions(+), 175 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si5341.txt create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5341.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/silabs,si5341.txt b/Documentation/devicetree/bindings/clock/silabs,si5341.txt deleted file mode 100644 index ce55aba0ce22..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si5341.txt +++ /dev/null @@ -1,175 +0,0 @@ -Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable -i2c clock generator. - -Reference -[1] Si5341 Data Sheet - https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf -[2] Si5341 Reference Manual - https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf -[3] Si5345 Reference Manual - https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf - -The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output -clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which -in turn can be directed to any of the 10 (or 4) outputs through a divider. -The internal structure of the clock generators can be found in [2]. -The Si5345 is similar to the Si5341 with the addition of fractional input -dividers and automatic input selection, as described in [3]. -The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs. - -The driver can be used in "as is" mode, reading the current settings from the -chip at boot, in case you have a (pre-)programmed device. If the PLL is not -configured when the driver probes, it assumes the driver must fully initialize -it. - -The device type, speed grade and revision are determined runtime by probing. - -The driver currently does not support any fancy input configurations. They can -still be programmed into the chip and the driver will leave them "as is". - -==I2C device node== - -Required properties: -- compatible: shall be one of the following: - "silabs,si5340" - Si5340 A/B/C/D - "silabs,si5341" - Si5341 A/B/C/D - "silabs,si5342" - Si5342 A/B/C/D - "silabs,si5344" - Si5344 A/B/C/D - "silabs,si5345" - Si5345 A/B/C/D -- reg: i2c device address, usually 0x74 -- #clock-cells: from common clock binding; shall be set to 2. - The first value is "0" for outputs, "1" for synthesizers. - The second value is the output or synthesizer index. -- clocks: from common clock binding; list of parent clock handles, - corresponding to inputs. Use a fixed clock for the "xtal" input. - At least one must be present. -- clock-names: One of: "xtal", "in0", "in1", "in2" - -Optional properties: -- vdd-supply: Regulator node for VDD -- vdda-supply: Regulator node for VDDA -- vdds-supply: Regulator node for VDDS -- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL - feedback divider. Must be such that the PLL output is in the valid range. For - example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only - the fraction matters, using 3500 and 12 will deliver the exact same result. - If these are not specified, and the PLL is not yet programmed when the driver - probes, the PLL will be set to 14GHz. -- silabs,reprogram: When present, the driver will always assume the device must - be initialized, and always performs the soft-reset routine. Since this will - temporarily stop all output clocks, don't do this if the chip is generating - the CPU clock for example. -- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used - in EXTCLK (external reference clock) rather than XTAL (crystal) mode. -- interrupts: Interrupt for INTRb pin. -- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V - rather than 1.8V thresholds. -- vddoX-supply (where X is an output index): Regulator node for VDDO for the - specified output. The driver selects the output VDD_SEL setting based on this - voltage. -- #address-cells: shall be set to 1. -- #size-cells: shall be set to 0. - - -== Child nodes: Outputs == - -The child nodes list the output clocks. - -Each of the clock outputs can be overwritten individually by using a child node. -If a child node for a clock output is not set, the configuration remains -unchanged. - -Required child node properties: -- reg: number of clock output. - -Optional child node properties: -- silabs,format: Output format, one of: - 1 = differential (defaults to LVDS levels) - 2 = low-power (defaults to HCSL levels) - 4 = LVCMOS -- silabs,common-mode: Manually override output common mode, see [2] for values -- silabs,amplitude: Manually override output amplitude, see [2] for values -- silabs,synth-master: boolean. If present, this output is allowed to change the - multisynth frequency dynamically. -- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH - when disabled, otherwise it's driven LOW. - -==Example== - -/* 48MHz reference crystal */ -ref48: ref48M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; -}; - -i2c-master-node { - /* Programmable clock (for logic) */ - si5341: clock-generator@74 { - reg = <0x74>; - compatible = "silabs,si5341"; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&ref48>; - clock-names = "xtal"; - - silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */ - silabs,pll-m-den = <48>; - silabs,reprogram; /* Chips are not programmed, always reset */ - - out@0 { - reg = <0>; - silabs,format = <1>; /* LVDS 3v3 */ - silabs,common-mode = <3>; - silabs,amplitude = <3>; - silabs,synth-master; - }; - - /* - * Output 6 configuration: - * LVDS 1v8 - */ - out@6 { - reg = <6>; - silabs,format = <1>; /* LVDS 1v8 */ - silabs,common-mode = <13>; - silabs,amplitude = <3>; - }; - - /* - * Output 8 configuration: - * HCSL 3v3 - */ - out@8 { - reg = <8>; - silabs,format = <2>; - silabs,common-mode = <11>; - silabs,amplitude = <3>; - }; - }; -}; - -some-video-node { - /* Standard clock bindings */ - clock-names = "pixel"; - clocks = <&si5341 0 7>; /* Output 7 */ - - /* Set output 7 to use syntesizer 3 as its parent */ - assigned-clocks = <&si5341 0 7>, <&si5341 1 3>; - assigned-clock-parents = <&si5341 1 3>; - /* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */ - assigned-clock-rates = <148500000>, <594000000>; -}; - -some-audio-node { - clock-names = "i2s-clk"; - clocks = <&si5341 0 0>; - /* - * since output 0 is a synth-master, the synth will be automatically set - * to an appropriate frequency when the audio driver requests another - * frequency. We give control over synth 2 to this output here. - */ - assigned-clocks = <&si5341 0 0>; - assigned-clock-parents = <&si5341 1 2>; -}; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5341.yaml b/Documentation/devicetree/bindings/clock/silabs,si5341.yaml new file mode 100644 index 000000000000..b4f7efdf0b7b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5341.yaml @@ -0,0 +1,217 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/silabs,si5341.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Labs Si5340/1/2/4/5 programmable i2c clock generator + +maintainers: + - Mike Looijmans + +description: > + Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable i2c clock + generator. + + Reference + [1] Si5341 Data Sheet + https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf + [2] Si5341 Reference Manual + https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf + [3] Si5345 Reference Manual + https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf + + The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output + clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which + in turn can be directed to any of the 10 (or 4) outputs through a divider. + The internal structure of the clock generators can be found in [2]. + The Si5345 is similar to the Si5341 with the addition of fractional input + dividers and automatic input selection, as described in [3]. + The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs. + + The driver can be used in "as is" mode, reading the current settings from the + chip at boot, in case you have a (pre-)programmed device. If the PLL is not + configured when the driver probes, it assumes the driver must fully initialize + it. + + The device type, speed grade and revision are determined runtime by probing. + +properties: + compatible: + enum: + - silabs,si5340 + - silabs,si5341 + - silabs,si5342 + - silabs,si5344 + - silabs,si5345 + + reg: + maxItems: 1 + + "#clock-cells": + const: 2 + description: > + The first value is "0" for outputs, "1" for synthesizers. + + The second value is the output or synthesizer index. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + items: + - const: xtal + - const: in0 + - const: in1 + - const: in2 + + interrupts: + maxItems: 1 + description: Interrupt for INTRb pin + + vdd-supply: + description: Regulator node for VDD + + vdda-supply: + description: Regulator node for VDDA + + vdds-supply: + description: Regulator node for VDDS + + silabs,pll-m-num: + description: + Numerator for PLL feedback divider. Must be such that the PLL output is in + the valid range. For example, to create 14GHz from a 48MHz xtal, use + m-num=14000 and m-den=48. Only the fraction matters, using 3500 and 12 + will deliver the exact same result. If these are not specified, and the + PLL is not yet programmed when the driver probes, the PLL will be set to + 14GHz. + $ref: /schemas/types.yaml#/definitions/uint32 + + silabs,pll-m-den: + description: Denominator for PLL feedback divider + $ref: /schemas/types.yaml#/definitions/uint32 + + silabs,reprogram: + description: Always perform soft-reset and reinitialize PLL + type: boolean + + silabs,xaxb-ext-clk: + description: Use XA/XB pins as external reference clock + type: boolean + + silabs,iovdd-33: + description: I2C lines use 3.3V thresholds + type: boolean + +patternProperties: + "^vddo[0-9]-supply$": true + + "^out@[0-9]$": + description: > + Output-specific override nodes + + Each of the clock outputs can be overwritten individually by using a child + node. If a child node for a clock output is not set, the configuration + remains unchanged. + type: object + additionalProperties: false + + properties: + reg: + description: Number of clock output + maximum: 9 + + silabs,format: + description: Output format + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4] + + silabs,common-mode: + description: Override output common mode + $ref: /schemas/types.yaml#/definitions/uint32 + + silabs,amplitude: + description: Override output amplitude + $ref: /schemas/types.yaml#/definitions/uint32 + + silabs,synth-master: + description: Allow dynamic multisynth rate control + type: boolean + + silabs,disable-high: + description: Drive output HIGH when disabled + type: boolean + + required: + - reg + +required: + - compatible + - reg + - "#clock-cells" + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@74 { + reg = <0x74>; + compatible = "silabs,si5341"; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + + silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */ + silabs,pll-m-den = <48>; + silabs,reprogram; /* Chips are not programmed, always reset */ + + out@0 { + reg = <0>; + silabs,format = <1>; /* LVDS 3v3 */ + silabs,common-mode = <3>; + silabs,amplitude = <3>; + silabs,synth-master; + }; + + /* + * Output 6 configuration: + * LVDS 1v8 + */ + out@6 { + reg = <6>; + silabs,format = <1>; /* LVDS 1v8 */ + silabs,common-mode = <13>; + silabs,amplitude = <3>; + }; + + /* + * Output 8 configuration: + * HCSL 3v3 + */ + out@8 { + reg = <8>; + silabs,format = <2>; + silabs,common-mode = <11>; + silabs,amplitude = <3>; + }; + }; + }; -- cgit v1.2.3 From 7513cc391400ef1b27c422b251c2444097ed1ce7 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 4 Aug 2025 17:20:08 -0500 Subject: dt-bindings: clock: Convert silabs,si570 to DT schema Convert the Silicon Labs SI570 binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250804222010.4082782-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/silabs,si570.txt | 41 ----------- .../devicetree/bindings/clock/silabs,si570.yaml | 80 ++++++++++++++++++++++ 2 files changed, 80 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si570.txt create mode 100644 Documentation/devicetree/bindings/clock/silabs,si570.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/silabs,si570.txt b/Documentation/devicetree/bindings/clock/silabs,si570.txt deleted file mode 100644 index 5dda17df1ac5..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si570.txt +++ /dev/null @@ -1,41 +0,0 @@ -Binding for Silicon Labs 570, 571, 598 and 599 programmable -I2C clock generators. - -Reference -This binding uses the common clock binding[1]. Details about the devices can be -found in the data sheets[2][3]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Si570/571 Data Sheet - https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf -[3] Si598/599 Data Sheet - https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf - -Required properties: - - compatible: Shall be one of "silabs,si570", "silabs,si571", - "silabs,si598", "silabs,si599" - - reg: I2C device address. - - #clock-cells: From common clock bindings: Shall be 0. - - factory-fout: Factory set default frequency. This frequency is part specific. - The correct frequency for the part used has to be provided in - order to generate the correct output frequencies. For more - details, please refer to the data sheet. - - temperature-stability: Temperature stability of the device in PPM. Should be - one of: 7, 20, 50 or 100. - -Optional properties: - - clock-output-names: From common clock bindings. Recommended to be "si570". - - clock-frequency: Output frequency to generate. This defines the output - frequency set during boot. It can be reprogrammed during - runtime through the common clock framework. - - silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely - on hardware loading of RAM from NVM at power on. - -Example: - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - }; diff --git a/Documentation/devicetree/bindings/clock/silabs,si570.yaml b/Documentation/devicetree/bindings/clock/silabs,si570.yaml new file mode 100644 index 000000000000..90e2f79e2b2a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si570.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/silabs,si570.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Labs Si570/Si571/Si598/Si599 programmable I2C clock generator + +maintainers: + - Soren Brinkmann + +description: > + Silicon Labs 570, 571, 598 and 599 programmable I2C clock generators. Details + about the devices can be found in the data sheets[1][2]. + + [1] Si570/571 Data Sheet + https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf + [2] Si598/599 Data Sheet + https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf + +properties: + compatible: + enum: + - silabs,si570 + - silabs,si571 + - silabs,si598 + - silabs,si599 + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + factory-fout: + description: Factory-set default frequency in Hz. + $ref: /schemas/types.yaml#/definitions/uint32 + + temperature-stability: + description: Temperature stability of the device in PPM. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 7 + - 20 + - 50 + - 100 + + clock-output-names: + maxItems: 1 + + clock-frequency: + description: Output frequency to generate at boot; can be reprogrammed at runtime. + + silabs,skip-recall: + description: Skip the NVM-to-RAM recall operation during boot. + type: boolean + +required: + - compatible + - reg + - '#clock-cells' + - factory-fout + - temperature-stability + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@5d { + compatible = "silabs,si570"; + reg = <0x5d>; + #clock-cells = <0>; + temperature-stability = <50>; + factory-fout = <156250000>; + }; + }; -- cgit v1.2.3 From bedeb73fb9848df572bd6e06bcac3bb374cd0e5b Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 4 Aug 2025 12:53:03 -0500 Subject: dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding The fujitsu,mb86s70-crg11 binding is unused. The driver for it was removed in 2017. It's not used for Synquacer DT either like some other mb86s70 bindings are. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250804175304.3423965-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- .../bindings/clock/fujitsu,mb86s70-crg11.txt | 26 ---------------------- 1 file changed, 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt deleted file mode 100644 index 332396265689..000000000000 --- a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt +++ /dev/null @@ -1,26 +0,0 @@ -Fujitsu CRG11 clock driver bindings ------------------------------------ - -Required properties : -- compatible : Shall contain "fujitsu,mb86s70-crg11" -- #clock-cells : Shall be 3 {cntrlr domain port} - -The consumer specifies the desired clock pointing to its phandle. - -Example: - - clock: crg11 { - compatible = "fujitsu,mb86s70-crg11"; - #clock-cells = <3>; - }; - - mhu: mhu0@2b1f0000 { - #mbox-cells = <1>; - compatible = "arm,mhu"; - reg = <0 0x2B1F0000 0x1000>; - interrupts = <0 36 4>, /* LP Non-Sec */ - <0 35 4>, /* HP Non-Sec */ - <0 37 4>; /* Secure */ - clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */ - clock-names = "clk"; - }; -- cgit v1.2.3 From 6793ca9a43c8c9262802af3e6096df0fa2dcaa6c Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 11 Aug 2025 17:17:01 -0500 Subject: dt-bindings: clock: adi,axi-clkgen: add clock-output-names property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an optional `clock-output-names` property to the ADI AXI Clock Generator binding. This is already being used in the Linux driver and real-world dtbs, so we should document it to allow for correct binding validation. Signed-off-by: David Lechner Link: https://lore.kernel.org/r/20250811-dt-bindings-clk-axi-clkgen-add-clock-output-names-property-v1-1-f02727736aa7@baylibre.com Reviewed-by: Nuno Sá Acked-by: Conor Dooley Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml index 2b2041818a0a..6eea1a41150a 100644 --- a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml @@ -42,6 +42,9 @@ properties: - const: clkin2 - const: s_axi_aclk + clock-output-names: + maxItems: 1 + '#clock-cells': const: 0 @@ -65,4 +68,5 @@ examples: reg = <0xff000000 0x1000>; clocks = <&osc 1>, <&clkc 15>; clock-names = "clkin1", "s_axi_aclk"; + clock-output-names = "spi_sclk"; }; -- cgit v1.2.3 From a341bcfbfa74a00ddb741bbfe9a7c08c63382235 Mon Sep 17 00:00:00 2001 From: Kyle Hendry Date: Tue, 15 Jul 2025 16:46:03 -0700 Subject: dt-bindings: reset: add compatible for bcm63xx ephy control Add compatible string for bcm63xx ephy control. Signed-off-by: Kyle Hendry Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250715234605.36216-3-kylehendrydev@gmail.com Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml index 00150b93fca0..b8a320bb1776 100644 --- a/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml +++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml @@ -13,7 +13,9 @@ maintainers: properties: compatible: - const: brcm,bcm6345-reset + enum: + - brcm,bcm6345-reset + - brcm,bcm63xx-ephy-ctrl reg: maxItems: 1 -- cgit v1.2.3 From f93dd842719b123cfad6385a32acf6386a3c7659 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 7 Aug 2025 16:45:07 -0500 Subject: dt-bindings: display: Drop duplicate ti,opa362 binding The "ti,opa362" binding is already supported in simple-bridge.yaml, so remove the old binding doc. Acked-by: Conor Dooley Reviewed-by: Tomi Valkeinen Link: https://lore.kernel.org/r/20250807214508.4174167-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/ti/ti,opa362.txt | 38 ---------------------- 1 file changed, 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/ti/ti,opa362.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/ti/ti,opa362.txt b/Documentation/devicetree/bindings/display/ti/ti,opa362.txt deleted file mode 100644 index f96083c0bd17..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,opa362.txt +++ /dev/null @@ -1,38 +0,0 @@ -OPA362 analog video amplifier - -Required properties: -- compatible: "ti,opa362" -- enable-gpios: enable/disable output gpio - -Required node: -- Video port 0 for opa362 input -- Video port 1 for opa362 output - -Example: - -tv_amp: opa362 { - compatible = "ti,opa362"; - enable-gpios = <&gpio1 23 0>; /* GPIO to enable video out amplifier */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - opa_in: endpoint@0 { - remote-endpoint = <&venc_out>; - }; - }; - - port@1 { - reg = <1>; - opa_out: endpoint@0 { - remote-endpoint = <&tv_connector_in>; - }; - }; - }; -}; - - - -- cgit v1.2.3 From 6b8c52b41be4b3940f38b037cc953505aeb5768c Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 6 Aug 2025 16:27:40 -0500 Subject: dt-bindings: arm: Convert cavium,thunder-88xx to DT schema Convert Cavium Thunder-88xx boards to DT schema format. There's not any defined board compatibles in this case. Link: https://lore.kernel.org/r/20250806212741.1633917-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/cavium,thunder-88xx.yaml | 19 +++++++++++++++++++ .../devicetree/bindings/arm/cavium-thunder.txt | 10 ---------- 2 files changed, 19 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cavium,thunder-88xx.yaml delete mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cavium,thunder-88xx.yaml b/Documentation/devicetree/bindings/arm/cavium,thunder-88xx.yaml new file mode 100644 index 000000000000..d7c813118c1c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium,thunder-88xx.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cavium,thunder-88xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cavium Thunder 88xx SoC + +maintainers: + - Robert Richter + +properties: + $nodename: + const: '/' + compatible: + items: + - const: cavium,thunder-88xx + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt deleted file mode 100644 index 6f63a5866902..000000000000 --- a/Documentation/devicetree/bindings/arm/cavium-thunder.txt +++ /dev/null @@ -1,10 +0,0 @@ -Cavium Thunder platform device tree bindings --------------------------------------------- - -Boards with Cavium's Thunder SoC shall have following properties. - -Root Node ---------- -Required root node properties: - - - compatible = "cavium,thunder-88xx"; -- cgit v1.2.3 From f56fbb6a1b36da1d481d7ce8245f7bedad3aa863 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 6 Aug 2025 16:28:11 -0500 Subject: dt-bindings: arm: Drop obsolete cavium-thunder2.txt The binding is already converted to schema and is located in Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.yaml. Link: https://lore.kernel.org/r/20250806212812.1634740-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 8 -------- MAINTAINERS | 2 +- 2 files changed, 1 insertion(+), 9 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt deleted file mode 100644 index dc5dd65cbce7..000000000000 --- a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt +++ /dev/null @@ -1,8 +0,0 @@ -Cavium ThunderX2 CN99XX platform tree bindings ----------------------------------------------- - -Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - -These SoC uses the "cavium,thunder2" core which will be compatible -with "brcm,vulcan". diff --git a/MAINTAINERS b/MAINTAINERS index c2cf508e6379..7969d09dff17 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5545,7 +5545,7 @@ CAVIUM THUNDERX2 ARM64 SOC M: Robert Richter L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Odd Fixes -F: Documentation/devicetree/bindings/arm/cavium-thunder2.txt +F: Documentation/devicetree/bindings/arm/bcm/brcm,vulcan-soc.yaml F: arch/arm64/boot/dts/cavium/thunder2-99xx* CBS/ETF/TAPRIO QDISCS -- cgit v1.2.3 From 5de28cf4ae21aebb6a5af09c96d1fad9eb03f2f8 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 13:14:27 -0500 Subject: dt-bindings: arm/cpus: Add missing Applied Micro CPU compatibles "apm,potenza" and "apm,strega" CPU compatibles have been in use for some time. Link: https://lore.kernel.org/r/20250812181428.69490-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5bd517befb68..bb1ab514924d 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -80,6 +80,8 @@ properties: compatible: enum: + - apm,potenza + - apm,strega - apple,avalanche - apple,blizzard - apple,cyclone -- cgit v1.2.3 From 01ce6aa56caa9dc7b240828ed40df8180df7afb7 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 15:33:25 -0500 Subject: dt-bindings: interrupt-controller: Convert hisilicon,mbigen-v2 to DT schema Convert the HiSilicon MBIGEN binding to DT schema format. It's a straight-forward conversion. Link: https://lore.kernel.org/r/20250812203327.730393-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../interrupt-controller/hisilicon,mbigen-v2.txt | 84 ---------------------- .../interrupt-controller/hisilicon,mbigen-v2.yaml | 76 ++++++++++++++++++++ 2 files changed, 76 insertions(+), 84 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt deleted file mode 100644 index a6813a071f15..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt +++ /dev/null @@ -1,84 +0,0 @@ -Hisilicon mbigen device tree bindings. -======================================= - -Mbigen means: message based interrupt generator. - -MBI is kind of msi interrupt only used on Non-PCI devices. - -To reduce the wired interrupt number connected to GIC, -Hisilicon designed mbigen to collect and generate interrupt. - - -Non-pci devices can connect to mbigen and generate the -interrupt by writing ITS register. - -The mbigen chip and devices connect to mbigen have the following properties: - -Mbigen main node required properties: -------------------------------------------- -- compatible: Should be "hisilicon,mbigen-v2" - -- reg: Specifies the base physical address and size of the Mbigen - registers. - -Mbigen sub node required properties: ------------------------------------------- -- interrupt controller: Identifies the node as an interrupt controller - -- msi-parent: Specifies the MSI controller this mbigen use. - For more detail information,please refer to the generic msi-parent binding in - Documentation/devicetree/bindings/interrupt-controller/msi.txt. - -- num-pins: the total number of pins implemented in this Mbigen - instance. - -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 2. - - The 1st cell is hardware pin number of the interrupt.This number is local to - each mbigen chip and in the range from 0 to the maximum interrupts number - of the mbigen. - - The 2nd cell is the interrupt trigger type. - The value of this cell should be: - 1: rising edge triggered - or - 4: high level triggered - -Examples: - - mbigen_chip_dsa { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_gmac:intc_gmac { - interrupt-controller; - msi-parent = <&its_dsa 0x40b1c>; - num-pins = <9>; - #interrupt-cells = <2>; - }; - - mbigen_i2c:intc_i2c { - interrupt-controller; - msi-parent = <&its_dsa 0x40b0e>; - num-pins = <2>; - #interrupt-cells = <2>; - }; - }; - -Devices connect to mbigen required properties: ----------------------------------------------------- --interrupts:Specifies the interrupt source. - For the specific information of each cell in this property,please refer to - the "interrupt-cells" description mentioned above. - -Examples: - gmac0: ethernet@c2080000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0xc2080000 0 0x20000>, - <0 0xc0000000 0 0x1000>; - interrupt-parent = <&mbigen_device_gmac>; - interrupts = <656 1>, - <657 1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.yaml b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.yaml new file mode 100644 index 000000000000..326424e6e02a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/hisilicon,mbigen-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon mbigen v2 + +maintainers: + - Wei Xu + +description: > + Mbigen means: message based interrupt generator. + + MBI is kind of msi interrupt only used on Non-PCI devices. + + To reduce the wired interrupt number connected to GIC, Hisilicon designed + mbigen to collect and generate interrupt. + + Non-pci devices can connect to mbigen and generate the interrupt by writing + ITS register. + +properties: + compatible: + const: hisilicon,mbigen-v2 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + additionalProperties: false + + properties: + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + msi-parent: + maxItems: 1 + + num-pins: + description: The total number of pins implemented in this Mbigen instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - interrupt-controller + - "#interrupt-cells" + - msi-parent + - num-pins + +examples: + - | + mbigen@c0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0xc0080000 0x10000>; + + mbigen_gmac: intc_gmac { + interrupt-controller; + #interrupt-cells = <2>; + msi-parent = <&its_dsa 0x40b1c>; + num-pins = <9>; + }; + + mbigen_i2c: intc_i2c { + interrupt-controller; + #interrupt-cells = <2>; + msi-parent = <&its_dsa 0x40b0e>; + num-pins = <2>; + }; + }; -- cgit v1.2.3 From 7fdc1d1b02e471c2ad4292705265706e003430a0 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Thu, 14 Aug 2025 14:54:19 +0000 Subject: dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Glymur SoC Document the RPMh Network-On-Chip Interconnect in Glymur platform. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Reviewed-by: "Rob Herring (Arm)" Signed-off-by: Raviteja Laggyshetty Link: https://lore.kernel.org/r/20250814-glymur-icc-v2-1-596cca6b6015@oss.qualcomm.com Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,glymur-rpmh.yaml | 172 +++++++++++++++++ .../dt-bindings/interconnect/qcom,glymur-rpmh.h | 205 +++++++++++++++++++++ 2 files changed, 377 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,glymur-rpmh.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml new file mode 100644 index 000000000000..d55a7bcf5591 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR + +maintainers: + - Raviteja Laggyshetty + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,glymur-rpmh.h + +properties: + compatible: + enum: + - qcom,glymur-aggre1-noc + - qcom,glymur-aggre2-noc + - qcom,glymur-aggre3-noc + - qcom,glymur-aggre4-noc + - qcom,glymur-clk-virt + - qcom,glymur-cnoc-cfg + - qcom,glymur-cnoc-main + - qcom,glymur-hscnoc + - qcom,glymur-lpass-ag-noc + - qcom,glymur-lpass-lpiaon-noc + - qcom,glymur-lpass-lpicx-noc + - qcom,glymur-mc-virt + - qcom,glymur-mmss-noc + - qcom,glymur-nsinoc + - qcom,glymur-nsp-noc + - qcom,glymur-oobm-ss-noc + - qcom,glymur-pcie-east-anoc + - qcom,glymur-pcie-east-slv-noc + - qcom,glymur-pcie-west-anoc + - qcom,glymur-pcie-west-slv-noc + - qcom,glymur-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-clk-virt + - qcom,glymur-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-pcie-west-anoc + then: + properties: + clocks: + items: + - description: aggre PCIE_3A WEST AXI clock + - description: aggre PCIE_3B WEST AXI clock + - description: aggre PCIE_4 WEST AXI clock + - description: aggre PCIE_6 WEST AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-pcie-east-anoc + then: + properties: + clocks: + items: + - description: aggre PCIE_5 EAST AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre USB3 TERT AXI clock + - description: aggre USB4_2 AXI clock + - description: aggre UFS PHY AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-aggre4-noc + then: + properties: + clocks: + items: + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + - description: aggre USB4_0 AXI clock + - description: aggre USB4_1 AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-pcie-west-anoc + - qcom,glymur-pcie-east-anoc + - qcom,glymur-aggre2-noc + - qcom,glymur-aggre4-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + #include + clk_virt: interconnect-0 { + compatible = "qcom,glymur-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,glymur-aggre1-noc"; + reg = <0x016e0000 0x14400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre4_noc: interconnect@1740000 { + compatible = "qcom,glymur-aggre4-noc"; + reg = <0x01740000 0x14400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; + }; diff --git a/include/dt-bindings/interconnect/qcom,glymur-rpmh.h b/include/dt-bindings/interconnect/qcom,glymur-rpmh.h new file mode 100644 index 000000000000..6a0e754345e4 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,glymur-rpmh.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_GLYMUR_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_GLYMUR_H + +#define MASTER_CRYPTO 0 +#define MASTER_SOCCP_PROC 1 +#define MASTER_QDSS_ETR 2 +#define MASTER_QDSS_ETR_1 3 +#define SLAVE_A1NOC_SNOC 4 + +#define MASTER_UFS_MEM 0 +#define MASTER_USB3_2 1 +#define MASTER_USB4_2 2 +#define SLAVE_A2NOC_SNOC 3 + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_1 2 +#define MASTER_QUP_2 3 +#define MASTER_SP 4 +#define MASTER_SDCC_2 5 +#define MASTER_SDCC_4 6 +#define MASTER_USB2 7 +#define MASTER_USB3_MP 8 +#define SLAVE_A3NOC_SNOC 9 + +#define MASTER_USB3_0 0 +#define MASTER_USB3_1 1 +#define MASTER_USB4_0 2 +#define MASTER_USB4_1 3 +#define SLAVE_A4NOC_HSCNOC 4 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define SLAVE_QUP_CORE_0 3 +#define SLAVE_QUP_CORE_1 4 +#define SLAVE_QUP_CORE_2 5 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_AHB2PHY_2 3 +#define SLAVE_AHB2PHY_3 4 +#define SLAVE_AV1_ENC_CFG 5 +#define SLAVE_CAMERA_CFG 6 +#define SLAVE_CLK_CTL 7 +#define SLAVE_CRYPTO_0_CFG 8 +#define SLAVE_DISPLAY_CFG 9 +#define SLAVE_GFX3D_CFG 10 +#define SLAVE_IMEM_CFG 11 +#define SLAVE_PCIE_0_CFG 12 +#define SLAVE_PCIE_1_CFG 13 +#define SLAVE_PCIE_2_CFG 14 +#define SLAVE_PCIE_3A_CFG 15 +#define SLAVE_PCIE_3B_CFG 16 +#define SLAVE_PCIE_4_CFG 17 +#define SLAVE_PCIE_5_CFG 18 +#define SLAVE_PCIE_6_CFG 19 +#define SLAVE_PCIE_RSCC 20 +#define SLAVE_PDM 21 +#define SLAVE_PRNG 22 +#define SLAVE_QDSS_CFG 23 +#define SLAVE_QSPI_0 24 +#define SLAVE_QUP_0 25 +#define SLAVE_QUP_1 26 +#define SLAVE_QUP_2 27 +#define SLAVE_SDCC_2 28 +#define SLAVE_SDCC_4 29 +#define SLAVE_SMMUV3_CFG 30 +#define SLAVE_TCSR 31 +#define SLAVE_TLMM 32 +#define SLAVE_UFS_MEM_CFG 33 +#define SLAVE_USB2 34 +#define SLAVE_USB3_0 35 +#define SLAVE_USB3_1 36 +#define SLAVE_USB3_2 37 +#define SLAVE_USB3_MP 38 +#define SLAVE_USB4_0 39 +#define SLAVE_USB4_1 40 +#define SLAVE_USB4_2 41 +#define SLAVE_VENUS_CFG 42 +#define SLAVE_CNOC_PCIE_SLAVE_EAST_CFG 43 +#define SLAVE_CNOC_PCIE_SLAVE_WEST_CFG 44 +#define SLAVE_LPASS_QTB_CFG 45 +#define SLAVE_CNOC_MNOC_CFG 46 +#define SLAVE_NSP_QTB_CFG 47 +#define SLAVE_PCIE_EAST_ANOC_CFG 48 +#define SLAVE_PCIE_WEST_ANOC_CFG 49 +#define SLAVE_QDSS_STM 50 +#define SLAVE_TCU 51 + +#define MASTER_HSCNOC_CNOC 0 +#define SLAVE_AOSS 1 +#define SLAVE_IPC_ROUTER_CFG 2 +#define SLAVE_SOCCP 3 +#define SLAVE_TME_CFG 4 +#define SLAVE_APPSS 5 +#define SLAVE_CNOC_CFG 6 +#define SLAVE_BOOT_IMEM 7 +#define SLAVE_IMEM 8 + +#define MASTER_GPU_TCU 0 +#define MASTER_PCIE_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_AGGRE_NOC_EAST 4 +#define MASTER_GFX3D 5 +#define MASTER_LPASS_GEM_NOC 6 +#define MASTER_MNOC_HF_MEM_NOC 7 +#define MASTER_MNOC_SF_MEM_NOC 8 +#define MASTER_COMPUTE_NOC 9 +#define MASTER_PCIE_EAST 10 +#define MASTER_PCIE_WEST 11 +#define MASTER_SNOC_SF_MEM_NOC 12 +#define MASTER_WLAN_Q6 13 +#define MASTER_GIC 14 +#define SLAVE_HSCNOC_CNOC 15 +#define SLAVE_LLCC 16 +#define SLAVE_PCIE_EAST 17 +#define SLAVE_PCIE_WEST 18 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_AV1_ENC 0 +#define MASTER_CAMNOC_HF 1 +#define MASTER_CAMNOC_ICP 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_EVA 4 +#define MASTER_MDP 5 +#define MASTER_CDSP_HCP 6 +#define MASTER_VIDEO 7 +#define MASTER_VIDEO_CV_PROC 8 +#define MASTER_VIDEO_V_PROC 9 +#define MASTER_CNOC_MNOC_CFG 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_MNOC_SF_MEM_NOC 12 +#define SLAVE_SERVICE_MNOC 13 + +#define MASTER_CPUCP 0 +#define SLAVE_NSINOC_SYSTEM_NOC 1 +#define SLAVE_SERVICE_NSINOC 2 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_NSP0_HSC_NOC 1 + +#define MASTER_OOBMSS_SP_PROC 0 +#define SLAVE_OOBMSS_SNOC 1 + +#define MASTER_PCIE_EAST_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define MASTER_PCIE_5 3 +#define SLAVE_PCIE_EAST_MEM_NOC 4 +#define SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC 5 + +#define MASTER_HSCNOC_PCIE_EAST 0 +#define MASTER_CNOC_PCIE_EAST_SLAVE_CFG 1 +#define SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG 2 +#define SLAVE_SERVICE_PCIE_EAST 3 +#define SLAVE_PCIE_0 4 +#define SLAVE_PCIE_1 5 +#define SLAVE_PCIE_5 6 + +#define MASTER_PCIE_WEST_ANOC_CFG 0 +#define MASTER_PCIE_2 1 +#define MASTER_PCIE_3A 2 +#define MASTER_PCIE_3B 3 +#define MASTER_PCIE_4 4 +#define MASTER_PCIE_6 5 +#define SLAVE_PCIE_WEST_MEM_NOC 6 +#define SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC 7 + +#define MASTER_HSCNOC_PCIE_WEST 0 +#define MASTER_CNOC_PCIE_WEST_SLAVE_CFG 1 +#define SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG 2 +#define SLAVE_SERVICE_PCIE_WEST 3 +#define SLAVE_PCIE_2 4 +#define SLAVE_PCIE_3A 5 +#define SLAVE_PCIE_3B 6 +#define SLAVE_PCIE_4 7 +#define SLAVE_PCIE_6 8 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_A3NOC_SNOC 2 +#define MASTER_NSINOC_SNOC 3 +#define MASTER_OOBMSS 4 +#define SLAVE_SNOC_GEM_NOC_SF 5 + +#endif -- cgit v1.2.3 From f10512e2c44e6ee3242314d43102acab7340e2d3 Mon Sep 17 00:00:00 2001 From: Hendrik Hamerlinck Date: Wed, 13 Aug 2025 11:22:39 +0200 Subject: dt-bindings: riscv: spacemit: Add OrangePi RV2 board Document the compatible string for the OrangePi RV2 board [1]. The board is described as using the Ky X1 SoC, which, based on available downstream sources and testing, appears to be identical or very closely related to the SpacemiT K1 SoC [2]. Link: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-RV2.html [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Signed-off-by: Hendrik Hamerlinck Reviewed-by: Yixun Lan Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250813092240.180333-2-hendrik.hamerlinck@hammernet.be Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 077b94f10dca..c56b62a6299a 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -22,6 +22,7 @@ properties: - enum: - bananapi,bpi-f3 - milkv,jupiter + - xunlong,orangepi-rv2 - const: spacemit,k1 additionalProperties: true -- cgit v1.2.3 From 7f224967aee7d5ad88b6db76ca161be622ae7b34 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 31 Jul 2025 09:15:52 +0200 Subject: scsi: ufs: qcom: dt-bindings: Split common part to qcom,ufs-common.yaml The binding for Qualcomm SoC UFS controllers grew and it will grow further. It already includes several conditionals, partially for difference in handling encryption block (ICE, either as phandle or as I/O address space) but it will further grow for MCQ. Prepare for splitting this one big binding into several ones for common group of devices by defining common part for all Qualcomm UFS schemas. This only moves code, no functional impact expected. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250731-dt-bindings-ufs-qcom-v2-1-53bb634bf95a@linaro.org Reviewed-by: Rob Herring (Arm) Signed-off-by: Martin K. Petersen --- .../devicetree/bindings/ufs/qcom,ufs-common.yaml | 67 ++++++++++++++++++++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 53 +---------------- 2 files changed, 68 insertions(+), 52 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml new file mode 100644 index 000000000000..962dffcd28b4 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs-common.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,ufs-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Universal Flash Storage (UFS) Controller Common Properties + +maintainers: + - Bjorn Andersson + +properties: + clocks: + minItems: 7 + maxItems: 9 + + clock-names: + minItems: 7 + maxItems: 9 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 2 + + interconnect-names: + items: + - const: ufs-ddr + - const: cpu-ufs + + iommus: + minItems: 1 + maxItems: 2 + + phys: + maxItems: 1 + + phy-names: + items: + - const: ufsphy + + power-domains: + maxItems: 1 + + required-opps: + maxItems: 1 + + resets: + maxItems: 1 + + '#reset-cells': + const: 1 + + reset-names: + items: + - const: rst + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the RESET pin of the UFS memory device. + +allOf: + - $ref: ufs-common.yaml + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 6c6043d9809e..fc0f7b8d1cd1 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -47,39 +47,6 @@ properties: - const: qcom,ufshc - const: jedec,ufs-2.0 - clocks: - minItems: 7 - maxItems: 9 - - clock-names: - minItems: 7 - maxItems: 9 - - dma-coherent: true - - interconnects: - minItems: 2 - maxItems: 2 - - interconnect-names: - items: - - const: ufs-ddr - - const: cpu-ufs - - iommus: - minItems: 1 - maxItems: 2 - - phys: - maxItems: 1 - - phy-names: - items: - - const: ufsphy - - power-domains: - maxItems: 1 - qcom,ice: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the Inline Crypto Engine node @@ -93,30 +60,12 @@ properties: - const: std - const: ice - required-opps: - maxItems: 1 - - resets: - maxItems: 1 - - '#reset-cells': - const: 1 - - reset-names: - items: - - const: rst - - reset-gpios: - maxItems: 1 - description: - GPIO connected to the RESET pin of the UFS memory device. - required: - compatible - reg allOf: - - $ref: ufs-common.yaml + - $ref: qcom,ufs-common.yaml - if: properties: -- cgit v1.2.3 From 655c8f511926250e0da9e8b1a9b8f1cf2c173b41 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 31 Jul 2025 09:15:53 +0200 Subject: scsi: ufs: qcom: dt-bindings: Split SC7180 and similar The binding for Qualcomm SoC UFS controllers grew and it will grow further. Split SC7180 and several other devices which: 1. Do not reference ICE as I/O address space, but as a phandle, 2. Have same order of clocks (SC7180 has one clock less than SC7280 and other variants in split binding). The split allows easier review and maintenance of the binding. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250731-dt-bindings-ufs-qcom-v2-2-53bb634bf95a@linaro.org Reviewed-by: Rob Herring (Arm) Signed-off-by: Martin K. Petersen --- .../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 167 +++++++++++++++++++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 104 +++++-------- 2 files changed, 202 insertions(+), 69 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml new file mode 100644 index 000000000000..d94ef4e6b85a --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,sc7180-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7180 and Other SoCs UFS Controllers + +maintainers: + - Bjorn Andersson + +# Select only our matches, not all jedec,ufs-2.0 +select: + properties: + compatible: + contains: + enum: + - qcom,msm8998-ufshc + - qcom,qcs8300-ufshc + - qcom,sa8775p-ufshc + - qcom,sc7180-ufshc + - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc + - qcom,sc8280xp-ufshc + - qcom,sm8250-ufshc + - qcom,sm8350-ufshc + - qcom,sm8450-ufshc + - qcom,sm8550-ufshc + required: + - compatible + +properties: + compatible: + items: + - enum: + - qcom,msm8998-ufshc + - qcom,qcs8300-ufshc + - qcom,sa8775p-ufshc + - qcom,sc7180-ufshc + - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc + - qcom,sc8280xp-ufshc + - qcom,sm8250-ufshc + - qcom,sm8350-ufshc + - qcom,sm8450-ufshc + - qcom,sm8550-ufshc + - const: qcom,ufshc + - const: jedec,ufs-2.0 + + reg: + maxItems: 1 + + reg-names: + items: + - const: std + + clocks: + minItems: 7 + maxItems: 8 + + clock-names: + minItems: 7 + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: rx_lane1_sync_clk + + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Inline Crypto Engine node + +required: + - compatible + - reg + +allOf: + - $ref: qcom,ufs-common.yaml + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-ufshc + then: + properties: + clocks: + maxItems: 7 + clock-names: + maxItems: 7 + else: + properties: + clocks: + minItems: 8 + clock-names: + minItems: 8 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ufs@1d84000 { + compatible = "qcom,sm8450-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; + + power-domains = <&gcc UFS_PHY_GDSC>; + iommus = <&apps_smmu 0xe0 0x0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + qcom,ice = <&ice>; + }; + }; diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index fc0f7b8d1cd1..191b88120d13 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -15,7 +15,17 @@ select: properties: compatible: contains: - const: qcom,ufshc + enum: + - qcom,msm8994-ufshc + - qcom,msm8996-ufshc + - qcom,qcs615-ufshc + - qcom,sdm845-ufshc + - qcom,sm6115-ufshc + - qcom,sm6125-ufshc + - qcom,sm6350-ufshc + - qcom,sm8150-ufshc + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc required: - compatible @@ -25,23 +35,12 @@ properties: - enum: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - - qcom,msm8998-ufshc - qcom,qcs615-ufshc - - qcom,qcs8300-ufshc - - qcom,sa8775p-ufshc - - qcom,sc7180-ufshc - - qcom,sc7280-ufshc - - qcom,sc8180x-ufshc - - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - - qcom,sm8250-ufshc - - qcom,sm8350-ufshc - - qcom,sm8450-ufshc - - qcom,sm8550-ufshc - qcom,sm8650-ufshc - qcom,sm8750-ufshc - const: qcom,ufshc @@ -72,41 +71,6 @@ allOf: compatible: contains: enum: - - qcom,sc7180-ufshc - then: - properties: - clocks: - minItems: 7 - maxItems: 7 - clock-names: - items: - - const: core_clk - - const: bus_aggr_clk - - const: iface_clk - - const: core_clk_unipro - - const: ref_clk - - const: tx_lane0_sync_clk - - const: rx_lane0_sync_clk - reg: - maxItems: 1 - reg-names: - maxItems: 1 - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-ufshc - - qcom,qcs8300-ufshc - - qcom,sa8775p-ufshc - - qcom,sc7280-ufshc - - qcom,sc8180x-ufshc - - qcom,sc8280xp-ufshc - - qcom,sm8250-ufshc - - qcom,sm8350-ufshc - - qcom,sm8450-ufshc - - qcom,sm8550-ufshc - qcom,sm8650-ufshc - qcom,sm8750-ufshc then: @@ -246,10 +210,10 @@ unevaluatedProperties: false examples: - | - #include + #include #include #include - #include + #include #include soc { @@ -257,9 +221,12 @@ examples: #size-cells = <2>; ufs@1d84000 { - compatible = "qcom,sm8450-ufshc", "qcom,ufshc", + compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; + reg = <0x0 0x01d84000 0x0 0x2500>, + <0x0 0x01d90000 0x0 0x8000>; + reg-names = "std", "ice"; + interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -275,19 +242,8 @@ examples: vccq-max-microamp = <1200000>; power-domains = <&gcc UFS_PHY_GDSC>; - iommus = <&apps_smmu 0xe0 0x0>; - interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; - interconnect-names = "ufs-ddr", "cpu-ufs"; + iommus = <&apps_smmu 0x300 0>; - clock-names = "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -295,15 +251,25 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = <75000000 300000000>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk", + "ice_core_clk"; + freq-table-hz = <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, <0 0>, <0 0>, - <75000000 300000000>, - <75000000 300000000>, <0 0>, <0 0>, - <0 0>; - qcom,ice = <&ice>; + <0 300000000>; }; }; -- cgit v1.2.3 From 149009f2dc6f781f490a13264eaa565281e4d490 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 31 Jul 2025 09:15:54 +0200 Subject: scsi: ufs: qcom: dt-bindings: Split SM8650 and similar The binding for Qualcomm SoC UFS controllers grew and it will grow further. Split SM8650 and SM8750 UFS controllers which: 1. Do not reference ICE as IO address space, but as phandle, 2. Have same order of clocks. 3. Have MCQ I/O address space. Document that MCQ address space as optional to maintain backwards compatibility and because Linux drivers can operate perfectly fine without it (thus without MCQ feature). Linux driver already uses "mcq" as possible name for "reg-names" property. The split allows easier review and maintenance of the binding. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250731-dt-bindings-ufs-qcom-v2-3-53bb634bf95a@linaro.org Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Signed-off-by: Martin K. Petersen --- .../devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 178 +++++++++++++++++++++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 32 ---- 2 files changed, 178 insertions(+), 32 deletions(-) create mode 100644 Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml new file mode 100644 index 000000000000..aaa0bbb5bfe1 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/qcom,sm8650-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8650 and Other SoCs UFS Controllers + +maintainers: + - Bjorn Andersson + +# Select only our matches, not all jedec,ufs-2.0 +select: + properties: + compatible: + contains: + enum: + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + required: + - compatible + +properties: + compatible: + items: + - enum: + - qcom,sm8650-ufshc + - qcom,sm8750-ufshc + - const: qcom,ufshc + - const: jedec,ufs-2.0 + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: std + - const: mcq + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: rx_lane1_sync_clk + + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the Inline Crypto Engine node + +required: + - compatible + - reg + +allOf: + - $ref: qcom,ufs-common.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ufshc@1d84000 { + compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + operating-points-v2 = <&ufs_opp_table>; + + iommus = <&apps_smmu 0x60 0>; + + lanes-per-direction = <2>; + qcom,ice = <&ice>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index 191b88120d13..1dd41f6d5258 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -24,8 +24,6 @@ select: - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc required: - compatible @@ -41,8 +39,6 @@ properties: - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 @@ -66,34 +62,6 @@ required: allOf: - $ref: qcom,ufs-common.yaml - - if: - properties: - compatible: - contains: - enum: - - qcom,sm8650-ufshc - - qcom,sm8750-ufshc - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: core_clk - - const: bus_aggr_clk - - const: iface_clk - - const: core_clk_unipro - - const: ref_clk - - const: tx_lane0_sync_clk - - const: rx_lane0_sync_clk - - const: rx_lane1_sync_clk - reg: - minItems: 1 - maxItems: 1 - reg-names: - maxItems: 1 - - if: properties: compatible: -- cgit v1.2.3 From eb0e3f301d6ee7c813556fa6ca714e436f5235b0 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 16 Jul 2025 18:06:30 -0700 Subject: dt-bindings: arm: cpus: Add edac-enabled property Some ARM Cortex CPUs including A72 have Error Detection And Correction (EDAC) support on their L1 and L2 caches. That functionality is in implementation defined registers, so using it is not safe in virtualized environments or when EL3 already uses these registers. Add a edac-enabled flag which can be explicitly set when EDAC can be used. [ bp: Massage commit message. ] Signed-off-by: Sascha Hauer Signed-off-by: Vijay Balakrishna Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/1752714390-27389-3-git-send-email-vijayb@linux.microsoft.com --- Documentation/devicetree/bindings/arm/cpus.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5bd517befb68..4accf4cbc6c7 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -353,6 +353,12 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Link to Mediatek Cache Coherent Interconnect + edac-enabled: + $ref: /schemas/types.yaml#/definitions/flag + description: + A72 CPUs support Error Detection And Correction (EDAC) on their L1 and + L2 caches. This flag marks this function as usable. + qcom,saw: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -399,6 +405,17 @@ properties: allOf: - $ref: /schemas/cpu.yaml# - $ref: /schemas/opp/opp-v1.yaml# + - if: + not: + properties: + compatible: + contains: + const: arm,cortex-a72 + then: + # Allow edac-enabled only for Cortex A72 + properties: + edac-enabled: false + - if: # If the enable-method property contains one of those values properties: -- cgit v1.2.3 From 38f9f4f5f8828e43c549fd07b70fe5bc4c2ef2f6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 6 Aug 2025 16:27:32 -0500 Subject: dt-bindings: arm: Convert marvell,berlin to DT schema Reviewed-by: Jisheng Zhang Link: https://lore.kernel.org/r/20250806212733.1633662-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/marvell,berlin.yaml | 45 +++++++++++ Documentation/devicetree/bindings/arm/syna.txt | 89 ---------------------- 2 files changed, 45 insertions(+), 89 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/marvell,berlin.yaml delete mode 100644 Documentation/devicetree/bindings/arm/syna.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.yaml b/Documentation/devicetree/bindings/arm/marvell,berlin.yaml new file mode 100644 index 000000000000..4e8442980dcb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell,berlin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synaptics/Marvell Berlin SoC + +maintainers: + - Jisheng Zhang + +description: + According to https://www.synaptics.com/company/news/conexant-marvell + Synaptics has acquired the Multimedia Solutions Business of Marvell, so + Berlin SoCs are now Synaptics' SoCs. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - sony,nsz-gs7 + - const: marvell,berlin2 + - const: marvell,berlin + - items: + - enum: + - google,chromecast + - valve,steamlink + - const: marvell,berlin2cd + - const: marvell,berlin + - items: + - enum: + - marvell,berlin2q-dmp + - const: marvell,berlin2q + - const: marvell,berlin + - items: + - enum: + - marvell,berlin4ct-dmp + - marvell,berlin4ct-stb + - const: marvell,berlin4ct + - const: marvell,berlin + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt deleted file mode 100644 index f53c430f648c..000000000000 --- a/Documentation/devicetree/bindings/arm/syna.txt +++ /dev/null @@ -1,89 +0,0 @@ -Synaptics SoC Device Tree Bindings - -According to https://www.synaptics.com/company/news/conexant-marvell -Synaptics has acquired the Multimedia Solutions Business of Marvell, so -berlin SoCs are now Synaptics' SoCs now. - ---------------------------------------------------------------- - -Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 -shall have the following properties: - -* Required root node properties: -compatible: must contain "marvell,berlin" - -In addition, the above compatible shall be extended with the specific -SoC and board used. Currently known SoC compatibles are: - "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), - "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) - "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) - "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114) - "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) - -* Example: - -/ { - model = "Sony NSZ-GS7"; - compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; - - ... -} - -* Marvell Berlin CPU control bindings - -CPU control register allows various operations on CPUs, like resetting them -independently. - -Required properties: -- compatible: should be "marvell,berlin-cpu-ctrl" -- reg: address and length of the register set - -Example: - -cpu-ctrl@f7dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xf7dd0000 0x10000>; -}; - -* Marvell Berlin2 chip control binding - -Marvell Berlin SoCs have a chip control register set providing several -individual registers dealing with pinmux, padmux, clock, reset, and secondary -CPU boot address. Unfortunately, the individual registers are spread among the -chip control registers, so there should be a single DT node only providing the -different functions which are described below. - -Required properties: -- compatible: - * the first and second values must be: - "simple-mfd", "syscon" -- reg: address and length of following register sets for - BG2/BG2CD: chip control register set - BG2Q: chip control register set and cpu pll registers - -* Marvell Berlin2 system control binding - -Marvell Berlin SoCs have a system control register set providing several -individual registers dealing with pinmux, padmux, and reset. - -Required properties: -- compatible: - * the first and second values must be: - "simple-mfd", "syscon" -- reg: address and length of the system control register set - -Example: - -chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - /* sub-device nodes */ -}; - -sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - /* sub-device nodes */ -}; -- cgit v1.2.3 From 47829efa1cf42993e5bea2b4aea7e1cfcf8bd438 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 13:14:20 -0500 Subject: dt-bindings: perf: Convert apm,xgene-pmu to DT schema Convert the Applied Micro X-Gene PMU binding to DT schema format. It is a straightforward conversion. Link: https://lore.kernel.org/r/20250812181422.68286-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/perf/apm,xgene-pmu.yaml | 142 +++++++++++++++++++++ .../devicetree/bindings/perf/apm-xgene-pmu.txt | 112 ---------------- MAINTAINERS | 2 +- 3 files changed, 143 insertions(+), 113 deletions(-) create mode 100644 Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml delete mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml b/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml new file mode 100644 index 000000000000..314048a2a134 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/apm,xgene-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC PMU + +maintainers: + - Khuong Dinh + +description: | + This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. + The following PMU devices are supported: + + L3C - L3 cache controller + IOB - IO bridge + MCB - Memory controller bridge + MC - Memory controller + +properties: + compatible: + enum: + - apm,xgene-pmu + - apm,xgene-pmu-v2 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + regmap-csw: + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-mcba: + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-mcbb: + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - regmap-csw + - regmap-mcba + - regmap-mcbb + - reg + - interrupts + +additionalProperties: + type: object + additionalProperties: false + + properties: + compatible: + enum: + - apm,xgene-pmu-l3c + - apm,xgene-pmu-iob + - apm,xgene-pmu-mcb + - apm,xgene-pmu-mc + + reg: + maxItems: 1 + + enable-bit-index: + description: + Specifies which bit enables the associated resource in MCB or MC subnodes. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 31 + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pmu@78810000 { + compatible = "apm,xgene-pmu-v2"; + reg = <0x0 0x78810000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + interrupts = <0x0 0x22 0x4>; + + pmul3c@7e610000 { + compatible = "apm,xgene-pmu-l3c"; + reg = <0x0 0x7e610000 0x0 0x1000>; + }; + + pmuiob@7e940000 { + compatible = "apm,xgene-pmu-iob"; + reg = <0x0 0x7e940000 0x0 0x1000>; + }; + + pmucmcb@7e710000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e710000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmcb@7e730000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e730000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e810000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e810000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmc@7e850000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e850000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e890000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e890000 0x0 0x1000>; + enable-bit-index = <2>; + }; + + pmucmc@7e8d0000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e8d0000 0x0 0x1000>; + enable-bit-index = <3>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt deleted file mode 100644 index afb11cf693c0..000000000000 --- a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt +++ /dev/null @@ -1,112 +0,0 @@ -* APM X-Gene SoC PMU bindings - -This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. -The following PMU devices are supported: - - L3C - L3 cache controller - IOB - IO bridge - MCB - Memory controller bridge - MC - Memory controller - -The following section describes the SoC PMU DT node binding. - -Required properties: -- compatible : Shall be "apm,xgene-pmu" for revision 1 or - "apm,xgene-pmu-v2" for revision 2. -- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. -- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. -- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. -- reg : First resource shall be the CPU bus PMU resource. -- interrupts : Interrupt-specifier for PMU IRQ. - -Required properties for L3C subnode: -- compatible : Shall be "apm,xgene-pmu-l3c". -- reg : First resource shall be the L3C PMU resource. - -Required properties for IOB subnode: -- compatible : Shall be "apm,xgene-pmu-iob". -- reg : First resource shall be the IOB PMU resource. - -Required properties for MCB subnode: -- compatible : Shall be "apm,xgene-pmu-mcb". -- reg : First resource shall be the MCB PMU resource. -- enable-bit-index : The bit indicates if the according MCB is enabled. - -Required properties for MC subnode: -- compatible : Shall be "apm,xgene-pmu-mc". -- reg : First resource shall be the MC PMU resource. -- enable-bit-index : The bit indicates if the according MC is enabled. - -Example: - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - pmu: pmu@78810000 { - compatible = "apm,xgene-pmu-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - reg = <0x0 0x78810000 0x0 0x1000>; - interrupts = <0x0 0x22 0x4>; - - pmul3c@7e610000 { - compatible = "apm,xgene-pmu-l3c"; - reg = <0x0 0x7e610000 0x0 0x1000>; - }; - - pmuiob@7e940000 { - compatible = "apm,xgene-pmu-iob"; - reg = <0x0 0x7e940000 0x0 0x1000>; - }; - - pmucmcb@7e710000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e710000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmcb@7e730000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e730000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e810000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e810000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmc@7e850000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e850000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e890000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e890000 0x0 0x1000>; - enable-bit-index = <2>; - }; - - pmucmc@7e8d0000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e8d0000 0x0 0x1000>; - enable-bit-index = <3>; - }; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 7969d09dff17..4e6fa336ff70 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1895,7 +1895,7 @@ APPLIED MICRO (APM) X-GENE SOC PMU M: Khuong Dinh S: Supported F: Documentation/admin-guide/perf/xgene-pmu.rst -F: Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt +F: Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml F: drivers/perf/xgene_pmu.c APPLIED MICRO QT2025 PHY DRIVER -- cgit v1.2.3 From 326d2519811200da0e301dce3e93389dadd197a4 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 14 Aug 2025 08:51:56 -0500 Subject: dt-bindings: powerpc: Drop duplicate fsl/mpic.txt The chrp,open-pic binding schema already supports the "fsl,mpic" compatible. Add a couple of missing properties and support for 4 "#interrupt-cells" to the chrp,open-pic binding, so fsl/mpic.txt can be removed. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250814135157.2747346-2-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../interrupt-controller/chrp,open-pic.yaml | 17 +- .../devicetree/bindings/powerpc/fsl/mpic.txt | 231 --------------------- 2 files changed, 16 insertions(+), 232 deletions(-) delete mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml index f0d9bbd7d510..642738512f3c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml @@ -36,12 +36,27 @@ properties: const: 0 '#interrupt-cells': - const: 2 + description: + A value of 4 means that interrupt specifiers contain the interrupt-type or + type-specific information cells. + enum: [ 2, 4 ] pic-no-reset: description: Indicates the PIC shall not be reset during runtime initialization. type: boolean + single-cpu-affinity: + description: + If present, non-IPI interrupts will be routed to a single CPU at a time. + type: boolean + + last-interrupt-source: + description: + Some MPICs do not correctly report the number of hardware sources in the + global feature registers. This value, if specified, overrides the value + read from MPIC_GREG_FEATURE_LAST_SRC. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt deleted file mode 100644 index dc5744636a57..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt +++ /dev/null @@ -1,231 +0,0 @@ -===================================================================== -Freescale MPIC Interrupt Controller Node -Copyright (C) 2010,2011 Freescale Semiconductor Inc. -===================================================================== - -The Freescale MPIC interrupt controller is found on all PowerQUICC -and QorIQ processors and is compatible with the Open PIC. The -notable difference from Open PIC binding is the addition of 2 -additional cells in the interrupt specifier defining interrupt type -information. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Shall include "fsl,mpic". Freescale MPIC - controllers compatible with this binding have Block - Revision Registers BRR1 and BRR2 at offset 0x0 and - 0x10 in the MPIC. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical - offset and length of the device's registers within the - CCSR address space. - - - interrupt-controller - Usage: required - Value type: - Definition: Specifies that this node is an interrupt - controller - - - #interrupt-cells - Usage: required - Value type: - Definition: Shall be 2 or 4. A value of 2 means that interrupt - specifiers do not contain the interrupt-type or type-specific - information cells. - - - #address-cells - Usage: required - Value type: - Definition: Shall be 0. - - - pic-no-reset - Usage: optional - Value type: - Definition: The presence of this property specifies that the - MPIC must not be reset by the client program, and that - the boot program has initialized all interrupt source - configuration registers to a sane state-- masked or - directed at other cores. This ensures that the client - program will not receive interrupts for sources not belonging - to the client. The presence of this property also mandates - that any initialization related to interrupt sources shall - be limited to sources explicitly referenced in the device tree. - - - big-endian - Usage: optional - Value type: - If present the MPIC will be assumed to be big-endian. Some - device-trees omit this property on MPIC nodes even when the MPIC is - in fact big-endian, so certain boards override this property. - - - single-cpu-affinity - Usage: optional - Value type: - If present the MPIC will be assumed to only be able to route - non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC). - - - last-interrupt-source - Usage: optional - Value type: - Some MPICs do not correctly report the number of hardware sources - in the global feature registers. If specified, this field will - override the value read from MPIC_GREG_FEATURE_LAST_SRC. - -INTERRUPT SPECIFIER DEFINITION - - Interrupt specifiers consists of 4 cells encoded as - follows: - - <1st-cell> interrupt-number - - Identifies the interrupt source. The meaning - depends on the type of interrupt. - - Note: If the interrupt-type cell is undefined - (i.e. #interrupt-cells = 2), this cell - should be interpreted the same as for - interrupt-type 0-- i.e. an external or - normal SoC device interrupt. - - <2nd-cell> level-sense information, encoded as follows: - 0 = low-to-high edge triggered - 1 = active low level-sensitive - 2 = active high level-sensitive - 3 = high-to-low edge triggered - - <3rd-cell> interrupt-type - - The following types are supported: - - 0 = external or normal SoC device interrupt - - The interrupt-number cell contains - the SoC device interrupt number. The - type-specific cell is undefined. The - interrupt-number is derived from the - MPIC a block of registers referred to as - the "Interrupt Source Configuration Registers". - Each source has 32-bytes of registers - (vector/priority and destination) in this - region. So interrupt 0 is at offset 0x0, - interrupt 1 is at offset 0x20, and so on. - - 1 = error interrupt - - The interrupt-number cell contains - the SoC device interrupt number for - the error interrupt. The type-specific - cell identifies the specific error - interrupt number. - - 2 = MPIC inter-processor interrupt (IPI) - - The interrupt-number cell identifies - the MPIC IPI number. The type-specific - cell is undefined. - - 3 = MPIC timer interrupt - - The interrupt-number cell identifies - the MPIC timer number. The type-specific - cell is undefined. - - <4th-cell> type-specific information - - The type-specific cell is encoded as follows: - - - For interrupt-type 1 (error interrupt), - the type-specific cell contains the - bit number of the error interrupt in the - Error Interrupt Summary Register. - -EXAMPLE 1 - /* - * mpic interrupt controller with 4 cells per specifier - */ - mpic: pic@40000 { - compatible = "fsl,mpic"; - interrupt-controller; - #interrupt-cells = <4>; - #address-cells = <0>; - reg = <0x40000 0x40000>; - }; - -EXAMPLE 2 - /* - * The MPC8544 I2C controller node has an internal - * interrupt number of 27. As per the reference manual - * this corresponds to interrupt source configuration - * registers at 0x5_0560. - * - * The interrupt source configuration registers begin - * at 0x5_0000. - * - * To compute the interrupt specifier interrupt number - * - * 0x560 >> 5 = 43 - * - * The interrupt source configuration registers begin - * at 0x5_0000, and so the i2c vector/priority registers - * are at 0x5_0560. - */ - i2c@3000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl-i2c"; - reg = <0x3000 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; - - -EXAMPLE 3 - /* - * Definition of a node defining the 4 - * MPIC IPI interrupts. Note the interrupt - * type of 2. - */ - ipi@410a0 { - compatible = "fsl,mpic-ipi"; - reg = <0x40040 0x10>; - interrupts = <0 0 2 0 - 1 0 2 0 - 2 0 2 0 - 3 0 2 0>; - }; - -EXAMPLE 4 - /* - * Definition of a node defining the MPIC - * global timers. Note the interrupt - * type of 3. - */ - timer0: timer@41100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x41100 0x100 0x41300 4>; - interrupts = <0 0 3 0 - 1 0 3 0 - 2 0 3 0 - 3 0 3 0>; - }; - -EXAMPLE 5 - /* - * Definition of an error interrupt (interrupt type 1). - * SoC interrupt number is 16 and the specific error - * interrupt bit in the error interrupt summary register - * is 23. - */ - memory-controller@8000 { - compatible = "fsl,p4080-memory-controller"; - reg = <0x8000 0x1000>; - interrupts = <16 2 1 23>; - }; -- cgit v1.2.3 From 83d76bf0360f7041d03d8f70301b0a8f96c9c872 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 23 Jul 2025 08:56:45 +0000 Subject: dt-bindings: iio: adc: rockchip-saradc: Allow use of a power-domain The SARADC controller in most Rockchip SoCs are part of power domains that are always powered on, i.e. PD_BUS or PD_PERI. These always powered on power domains have typically not been described in the device tree. Because these power domains have been left out of the device tree there has not been any real need to properly describe the power domain of the SARADC controller. On RK3528 the SARADC controller is part of the PD_VPU power domain. Add support to describe an optional power-domains for the SARADC controller in Rockchip SoCs. Signed-off-by: Jonas Karlman Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250723085654.2273324-4-jonas@kwiboo.se Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml index 41e0c56ef8e3..f776041fd08f 100644 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml @@ -47,6 +47,9 @@ properties: - const: saradc - const: apb_pclk + power-domains: + maxItems: 1 + resets: maxItems: 1 -- cgit v1.2.3 From 07306551cb76d61b02391d26a2e85c7711e92e1c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Jul 2025 13:13:46 +0200 Subject: dt-bindings: iio: Drop unused header includes in examples Drop includes of headers which example code does not use. No functional impact. Signed-off-by: Krzysztof Kozlowski Reviewed-by: David Heidelberg Acked-by: Matti Vaittinen Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250724111345.47889-5-krzysztof.kozlowski@linaro.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml | 1 - Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml | 2 -- Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml | 2 -- Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml | 2 -- Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml | 2 -- Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml | 1 - Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml | 1 - Documentation/devicetree/bindings/iio/accel/kionix,kxsd9.yaml | 1 - Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml | 1 - Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml | 1 - Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml | 1 - Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml | 1 - Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml | 1 - Documentation/devicetree/bindings/iio/adc/ti,ads1298.yaml | 1 - Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml | 1 - Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml | 2 -- Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml | 2 -- Documentation/devicetree/bindings/iio/light/st,vl6180.yaml | 1 - .../devicetree/bindings/iio/magnetometer/voltafield,af8133j.yaml | 1 - Documentation/devicetree/bindings/iio/pressure/bmp085.yaml | 1 - 20 files changed, 26 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml index 5887021cc90f..3dc973b98f81 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml @@ -37,7 +37,6 @@ unevaluatedProperties: false examples: - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml index 0c5b64cae965..3a8c69eecfde 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml @@ -57,7 +57,6 @@ unevaluatedProperties: false examples: - | - #include #include i2c { #address-cells = <1>; @@ -73,7 +72,6 @@ examples: }; }; - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index 84d949392012..a23a626bfab6 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -56,7 +56,6 @@ unevaluatedProperties: false examples: - | - #include #include i2c { #address-cells = <1>; @@ -72,7 +71,6 @@ examples: }; }; - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml index c07261c71013..f39e2912731f 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml @@ -58,7 +58,6 @@ unevaluatedProperties: false examples: - | - #include #include i2c { #address-cells = <1>; @@ -74,7 +73,6 @@ examples: }; }; - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml index 62465e36a590..88aa67bf2280 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml @@ -37,7 +37,6 @@ unevaluatedProperties: false examples: - | - #include #include i2c { #address-cells = <1>; @@ -52,7 +51,6 @@ examples: }; }; - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml index 457a709b583c..85c9537f1f02 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma255.yaml @@ -107,7 +107,6 @@ examples: }; }; - | - # include spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml index 8723a336229e..c5fedcf998f2 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml @@ -40,7 +40,6 @@ additionalProperties: false examples: - | - #include #include i2c { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/accel/kionix,kxsd9.yaml b/Documentation/devicetree/bindings/iio/accel/kionix,kxsd9.yaml index f64d99b35492..53de921768ac 100644 --- a/Documentation/devicetree/bindings/iio/accel/kionix,kxsd9.yaml +++ b/Documentation/devicetree/bindings/iio/accel/kionix,kxsd9.yaml @@ -57,7 +57,6 @@ examples: }; }; - | - # include spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml index ddec9747436c..705adbe88def 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml @@ -93,7 +93,6 @@ unevaluatedProperties: false examples: - | - #include #include i2c { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml index 21ee319d4675..62d906e24997 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml @@ -379,7 +379,6 @@ unevaluatedProperties: false examples: # Example AD7173-8 with external reference connected to REF+/REF-: - | - #include #include spi { diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index c28db0d635a0..b9dc04b0d307 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -278,7 +278,6 @@ examples: - | #include #include - #include pmic { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml b/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml index 2a8ad4fdfc6b..f0a1347ba4db 100644 --- a/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml +++ b/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml @@ -50,7 +50,6 @@ unevaluatedProperties: false examples: - | - #include spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml b/Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml index 775eee972b12..044b66a3b00c 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml @@ -44,7 +44,6 @@ unevaluatedProperties: false examples: - | - #include spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads1298.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads1298.yaml index bf5a43a81d59..71f9f9b745cb 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,ads1298.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads1298.yaml @@ -59,7 +59,6 @@ unevaluatedProperties: false examples: - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml index 4cacc9948726..3a725ece7ec4 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml @@ -44,7 +44,6 @@ unevaluatedProperties: false examples: - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml index d4d4e5c3d856..119e28a833fd 100644 --- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml @@ -74,7 +74,6 @@ unevaluatedProperties: false examples: - | - #include #include i2c { #address-cells = <1>; @@ -91,7 +90,6 @@ examples: }; }; - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml b/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml index 688100b240bc..2930b3386703 100644 --- a/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml +++ b/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml @@ -47,7 +47,6 @@ unevaluatedProperties: false examples: - | - #include #include i2c { #address-cells = <1>; @@ -63,7 +62,6 @@ examples: }; }; - | - #include #include spi { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/light/st,vl6180.yaml b/Documentation/devicetree/bindings/iio/light/st,vl6180.yaml index 27c36ab7990d..8598fb631aac 100644 --- a/Documentation/devicetree/bindings/iio/light/st,vl6180.yaml +++ b/Documentation/devicetree/bindings/iio/light/st,vl6180.yaml @@ -32,7 +32,6 @@ required: examples: - | - #include i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/voltafield,af8133j.yaml b/Documentation/devicetree/bindings/iio/magnetometer/voltafield,af8133j.yaml index b6ab01a6914a..ed42dc5afb99 100644 --- a/Documentation/devicetree/bindings/iio/magnetometer/voltafield,af8133j.yaml +++ b/Documentation/devicetree/bindings/iio/magnetometer/voltafield,af8133j.yaml @@ -44,7 +44,6 @@ additionalProperties: false examples: - | - #include #include i2c { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml index 706b7e24f182..b9ea37317b53 100644 --- a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml @@ -109,7 +109,6 @@ examples: }; - | # include - # include spi { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 1c3e87983cf0d71139afe88db440e3a42ea34ebe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Jul 2025 13:13:47 +0200 Subject: dt-bindings: iio: adc: Replace hard-coded GPIO/IRQ flag with a define For readability use known defines instead of hard-coding GPIO or interrupt flag. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Acked-by: Matti Vaittinen Link: https://patch.msgid.link/20250724111345.47889-6-krzysztof.kozlowski@linaro.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml | 2 +- Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml index ef8d51e74c08..592854766583 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml @@ -63,6 +63,6 @@ examples: vdd-supply = <&adc_vdd>; vref-supply = <&adc_vref>; spi-max-frequency = <1000000>; - shutdown-gpios = <&gpio 26 1>; + shutdown-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml b/Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml index 503285823376..4a8f127de7e3 100644 --- a/Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml +++ b/Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml @@ -81,7 +81,7 @@ examples: reg = <0x10>; interrupt-parent = <&gpio1>; - interrupts = <29 8>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&dummyreg>; iovdd-supply = <&dummyreg>; -- cgit v1.2.3 From 971255565074b160d5d05d6b0d9e6f70cbb7c4a9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Jul 2025 13:13:48 +0200 Subject: dt-bindings: iio: adc: samsung,exynos-adc: Use correct IRQ level in example The interrupt line to GIC is IRQ_TYPE_LEVEL_HIGH, so use that instead of "none". Also replace the hard-coded GIC_SPI flag. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Reviewed-by: Sam Protsenko Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250724111345.47889-7-krzysztof.kozlowski@linaro.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml index 4e40f6bed5db..8069e99ddac8 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml @@ -128,10 +128,12 @@ allOf: examples: - | + #include + adc: adc@12d10000 { compatible = "samsung,exynos-adc-v1"; reg = <0x12d10000 0x100>; - interrupts = <0 106 0>; + interrupts = ; #io-channel-cells = <1>; clocks = <&clock 303>; @@ -152,11 +154,12 @@ examples: - | #include + #include adc@126c0000 { compatible = "samsung,exynos3250-adc"; reg = <0x126c0000 0x100>; - interrupts = <0 137 0>; + interrupts = ; #io-channel-cells = <1>; clocks = <&cmu CLK_TSADC>, -- cgit v1.2.3 From 0a84f5105b405d8506707d244f225b040dfb04f4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Jul 2025 13:13:49 +0200 Subject: dt-bindings: iio: light: Simplify interrupts property in the example dynaimage,al3010 and dynaimage,al3320a are I2C devices, so their interrupts are not routed to GIC and rarely first interrupt cell is <0>. This looks like copy-paste from some SoC block, so drop it and also for readability use known defines instead of hard-coding interrupt flag. Signed-off-by: Krzysztof Kozlowski Reviewed-by: David Heidelberg Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250724111345.47889-8-krzysztof.kozlowski@linaro.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml | 2 +- Documentation/devicetree/bindings/iio/light/dynaimage,al3320a.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml b/Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml index f1048c30e73e..1472c997c16f 100644 --- a/Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml +++ b/Documentation/devicetree/bindings/iio/light/dynaimage,al3010.yaml @@ -42,6 +42,6 @@ examples: compatible = "dynaimage,al3010"; reg = <0x1c>; vdd-supply = <&vdd_reg>; - interrupts = <0 99 4>; + interrupts = <99 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/Documentation/devicetree/bindings/iio/light/dynaimage,al3320a.yaml b/Documentation/devicetree/bindings/iio/light/dynaimage,al3320a.yaml index 8249be99cff9..d06db737cd9e 100644 --- a/Documentation/devicetree/bindings/iio/light/dynaimage,al3320a.yaml +++ b/Documentation/devicetree/bindings/iio/light/dynaimage,al3320a.yaml @@ -40,6 +40,6 @@ examples: compatible = "dynaimage,al3320a"; reg = <0x1c>; vdd-supply = <&vdd_reg>; - interrupts = <0 99 4>; + interrupts = <99 IRQ_TYPE_LEVEL_HIGH>; }; }; -- cgit v1.2.3 From 73c8b83b4aedae07b3c45379fe14be5a2734cbca Mon Sep 17 00:00:00 2001 From: Rodrigo Gobbi Date: Fri, 1 Aug 2025 19:10:00 -0300 Subject: dt-bindings: iio: pressure: add invensense,icp10100 There is no txt file for it, add yaml for invensense,icp10100 which is already used in the driver. Also, document other compatibles for ICP-101xx family and add invensense,icp10100 as a fallback. Acked-by: Jean-Baptiste Maneyrol Signed-off-by: Rodrigo Gobbi Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250801221424.132305-1-rodrigo.gobbi.7@gmail.com Signed-off-by: Jonathan Cameron --- .../bindings/iio/pressure/invensense,icp10100.yaml | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/pressure/invensense,icp10100.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/pressure/invensense,icp10100.yaml b/Documentation/devicetree/bindings/iio/pressure/invensense,icp10100.yaml new file mode 100644 index 000000000000..5d980aa04bb3 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/pressure/invensense,icp10100.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/pressure/invensense,icp10100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: InvenSense ICP-101xx Barometric Pressure Sensors + +maintainers: + - Jean-Baptiste Maneyrol + +description: | + Support for ICP-101xx family: ICP-10100, ICP-10101, ICP-10110, ICP-10111. + Those devices uses a simple I2C communication bus, measuring the pressure + in a ultra-low noise at the lowest power. + Datasheet: https://product.tdk.com/system/files/dam/doc/product/sensor/pressure/capacitive-pressure/data_sheet/ds-000186-icp-101xx.pdf + +properties: + compatible: + oneOf: + - items: + - enum: + - invensense,icp10101 + - invensense,icp10110 + - invensense,icp10111 + - const: invensense,icp10100 + - const: invensense,icp10100 + + reg: + maxItems: 1 + + vdd-supply: true + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + pressure@63 { + compatible = "invensense,icp10101", "invensense,icp10100"; + reg = <0x63>; + vdd-supply = <&vdd_1v8>; + }; + }; +... -- cgit v1.2.3 From 7e2d03d00475b1a560e7e8f166b7534f4ade8fff Mon Sep 17 00:00:00 2001 From: Andreas Klinger Date: Mon, 28 Jul 2025 09:54:44 +0200 Subject: dt-bindings: iio: light: veml6046x00: add color sensor Add a new compatible for Vishay high accuracy RGBIR color sensor veml6046x00. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Andreas Klinger Link: https://patch.msgid.link/20250728075447.338725-2-ak@it-klinger.de Signed-off-by: Jonathan Cameron --- .../bindings/iio/light/vishay,veml6046x00.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/light/vishay,veml6046x00.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/light/vishay,veml6046x00.yaml b/Documentation/devicetree/bindings/iio/light/vishay,veml6046x00.yaml new file mode 100644 index 000000000000..112d448ff0bf --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/vishay,veml6046x00.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/vishay,veml6046x00.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Vishay VEML6046X00 High accuracy RGBIR color sensor + +maintainers: + - Andreas Klinger + +description: + VEML6046X00 datasheet at https://www.vishay.com/docs/80173/veml6046x00.pdf + +properties: + compatible: + enum: + - vishay,veml6046x00 + + reg: + maxItems: 1 + + vdd-supply: true + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + color-sensor@29 { + compatible = "vishay,veml6046x00"; + reg = <0x29>; + vdd-supply = <&vdd_reg>; + interrupt-parent = <&gpio2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + }; +... -- cgit v1.2.3 From 260bb98ce3df870ef3d73361f6918463bc88a5b6 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 11 Aug 2025 11:51:50 +0300 Subject: dt-bindings: iio: adc: ad7476: Drop redundant prop: true The ad7476 supports a few variants with different power-supplies and control GPIOs. The binding first unconditionally introduces all the properties, and later sets them 'true' or 'false' based on the combatible. The 'true' seems to be implied by the initial property introduction so the 'true' -branches in later conditional handling (based on the compatible) can be omitted. Drop the redundant true -branches. Signed-off-by: Matti Vaittinen Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/bee66444bf628ba9a34a02738a1842e2abc14290.1754901948.git.mazziesaccount@gmail.com Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/adi,ad7476.yaml | 54 ++++++++++------------ 1 file changed, 24 insertions(+), 30 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml index d0cb32f136e5..db2a9662bd94 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml @@ -106,19 +106,17 @@ allOf: - vcc-supply # Devices with a vref - if: - properties: - compatible: - contains: - enum: - - adi,ad7091r - - adi,ad7273 - - adi,ad7274 - - adi,ad7475 - - lltc,ltc2314-14 + not: + properties: + compatible: + contains: + enum: + - adi,ad7091r + - adi,ad7273 + - adi,ad7274 + - adi,ad7475 + - lltc,ltc2314-14 then: - properties: - vref-supply: true - else: properties: vref-supply: false # Devices with a vref where it is not optional @@ -135,29 +133,25 @@ allOf: required: - vref-supply - if: - properties: - compatible: - contains: - enum: - - adi,ad7475 - - adi,ad7495 + not: + properties: + compatible: + contains: + enum: + - adi,ad7475 + - adi,ad7495 then: - properties: - vdrive-supply: true - else: properties: vdrive-supply: false - if: - properties: - compatible: - contains: - enum: - - adi,ad7091 - - adi,ad7091r + not: + properties: + compatible: + contains: + enum: + - adi,ad7091 + - adi,ad7091r then: - properties: - adi,conversion-start-gpios: true - else: properties: adi,conversion-start-gpios: false -- cgit v1.2.3 From 261b90763fc4d51637abd44ae248a6183fc2de4d Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 11 Aug 2025 11:52:04 +0300 Subject: dt-bindings: iio: adc: ad7476: Add ROHM bd79105 The ROHM BD79105 is a simple, 16-bit, 1-channel ADC with a 'CONVSTART' pin used to start the ADC conversion. Other than the 'CONVSTART', there are 3 supply pins (one used as a reference), analog inputs, ground and communication pins. It's worth noting that the pin somewhat confusingly labeled as 'DIN', is a pin which should be used as a chip-select. The IC does not have any writable registers. The device is designed so that the output pin can, in addition to outputting the data, be used as a 'data-ready'-IRQ. There are cases where the IRQ can't be used (because it is delivered via SPI data-line). Hence, some systems may use a GPIO for polling the data readiness. Add a compatible for the bd79105 and add the data-ready GPIO to the binding. Signed-off-by: Matti Vaittinen Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/3f70f68665225be3091f8a0412e74037b6a2a88e.1754901948.git.mazziesaccount@gmail.com Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/adi,ad7476.yaml | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml index db2a9662bd94..55880191c511 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml @@ -41,6 +41,7 @@ properties: - adi,ad7910 - adi,ad7920 - adi,ad7940 + - rohm,bd79105 - ti,adc081s - ti,adc101s - ti,adc121s @@ -55,6 +56,11 @@ properties: reg: maxItems: 1 + interrupts: + description: + The data-ready interrupt. Provided via DOUT pin. + maxItems: 1 + vcc-supply: description: Main powersupply voltage for the chips, sometimes referred to as VDD on @@ -75,6 +81,10 @@ properties: description: A GPIO used to trigger the start of a conversion maxItems: 1 + rdy-gpios: + description: A GPIO for detecting the data-ready. + maxItems: 1 + required: - compatible - reg @@ -82,6 +92,20 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# +# Devices with an IRQ + - if: + properties: + compatible: + contains: + enum: + - rohm,bd79105 + then: + properties: + interrupts: true + else: + properties: + interrupts: false + # Devices where reference is vcc - if: properties: @@ -116,6 +140,7 @@ allOf: - adi,ad7274 - adi,ad7475 - lltc,ltc2314-14 + - rohm,bd79105 then: properties: vref-supply: false @@ -129,6 +154,7 @@ allOf: - adi,ad7274 - adi,ad7475 - lltc,ltc2314-14 + - rohm,bd79105 then: required: - vref-supply @@ -140,9 +166,23 @@ allOf: enum: - adi,ad7475 - adi,ad7495 + - rohm,bd79105 then: properties: vdrive-supply: false + + # Devices which support polling the data-ready via GPIO + - if: + not: + properties: + compatible: + contains: + enum: + - rohm,bd79105 + then: + properties: + rdy-gpios: false + - if: not: properties: @@ -151,10 +191,22 @@ allOf: enum: - adi,ad7091 - adi,ad7091r + - rohm,bd79105 then: properties: adi,conversion-start-gpios: false + # Devices with a convstart GPIO where it is not optional + - if: + properties: + compatible: + contains: + enum: + - rohm,bd79105 + then: + required: + - adi,conversion-start-gpios + unevaluatedProperties: false examples: -- cgit v1.2.3 From 26f0675fba4360516ee717ecc5ea099fe6819f1b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Aug 2025 15:24:46 +0200 Subject: dt-bindings: iio: Replace bouncing Analog emails MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Emails to stefan.popa@analog.com and alexandru.tachici@analog.com bounce permanently: Remote Server returned '550 5.1.10 RESOLVER.ADR.RecipientNotFound; Recipient not found by SMTP address lookup' so replace them with Marcelo Schmitt and Nuno Sá (listed alphabetically by first name) from Analog where appropriate. Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Acked-by: Nuno Sá Acked-by: Marcelo Schmitt Link: https://patch.msgid.link/20250812132445.75398-2-krzysztof.kozlowski@linaro.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml | 3 ++- Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml | 3 ++- Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml | 3 ++- Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml | 1 - Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml | 3 ++- Documentation/devicetree/bindings/iio/frequency/adf4371.yaml | 3 ++- Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml | 3 ++- 7 files changed, 12 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml index 3dc973b98f81..a92e153705f3 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ADIS16240 Programmable Impact Sensor and Recorder driver maintainers: - - Alexandru Tachici + - Marcelo Schmitt + - Nuno Sá description: | ADIS16240 Programmable Impact Sensor and Recorder driver that supports diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml index 88aa67bf2280..0ba0df46c3a9 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer maintainers: - - Stefan Popa + - Marcelo Schmitt + - Nuno Sá description: | Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer that supports diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml index 7146a654ae38..4dd5395730c1 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml @@ -8,7 +8,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AD7124 ADC device driver maintainers: - - Stefan Popa + - Marcelo Schmitt + - Nuno Sá description: | Bindings for the Analog Devices AD7124 ADC device. Datasheet can be diff --git a/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml b/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml index 5207c919abe0..eac48166fe72 100644 --- a/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml +++ b/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml @@ -9,7 +9,6 @@ title: Linear Technology / Analog Devices LTC2496 ADC maintainers: - Lars-Peter Clausen - Michael Hennerich - - Stefan Popa properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml index 82b0eed6a7b7..091cc93f1f90 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml @@ -8,7 +8,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AD5770R DAC device driver maintainers: - - Alexandru Tachici + - Marcelo Schmitt + - Nuno Sá description: | Bindings for the Analog Devices AD5770R current DAC device. Datasheet can be diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml index 53d607441612..2e1ff77fd1de 100644 --- a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml +++ b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADF4371/ADF4372 Wideband Synthesizers maintainers: - - Popa Stefan + - Marcelo Schmitt + - Nuno Sá description: | Analog Devices ADF4371/ADF4372 SPI Wideband Synthesizers diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml index 7a1a74fec281..43ecf46e9c20 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16480.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADIS16480 and similar IMUs maintainers: - - Alexandru Tachici + - Marcelo Schmitt + - Nuno Sá properties: compatible: -- cgit v1.2.3 From 0caebd1658bbb3796bec4e3449876742d29701ab Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:01:51 +0200 Subject: dt-bindings: mmc: fsl,esdhc: Add explicit reference to mmc-controller-common Even though it is referenced by mmc/mmc-controller.yaml it still raises the warning: esdhc@1560000 (fsl,ls1021a-esdhc): Unevaluated properties are not allowed ('bus-width' was unexpected) Adding an explicit reference fixes this. Signed-off-by: Alexander Stein Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250725060152.262094-1-alexander.stein@ew.tq-group.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml index 62087cf920df..f45e592901e2 100644 --- a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml @@ -90,6 +90,7 @@ required: allOf: - $ref: sdhci-common.yaml# + - $ref: mmc-controller-common.yaml# unevaluatedProperties: false -- cgit v1.2.3 From cefbc3109932d7a34040b4d87746af1d36567358 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Sun, 13 Jul 2025 15:27:28 +0200 Subject: dt-bindings: arm: sti: drop B2120 board support B2120 boards are internal boards which never were commercialised. Remove them from bindings. Signed-off-by: Raphael Gallais-Pou Acked-by: Krzysztof Kozlowski Signed-off-by: Patrice Chotard --- Documentation/devicetree/bindings/arm/sti.yaml | 4 ---- 1 file changed, 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml index 842def3e3f2b..177358895fe1 100644 --- a/Documentation/devicetree/bindings/arm/sti.yaml +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -14,12 +14,8 @@ properties: const: '/' compatible: oneOf: - - items: - - const: st,stih407-b2120 - - const: st,stih407 - items: - enum: - - st,stih410-b2120 - st,stih410-b2260 - const: st,stih410 - items: -- cgit v1.2.3 From 65fe705367efc3e06ccfa2a3a107081d8e69f70e Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Fri, 1 Aug 2025 13:18:09 +0200 Subject: dt-bindings: pinctrl: mediatek: mt8183: Allow gpio-line-names Add support for the 'gpio-line-names' property in the MT8183 pinctrl binding. This allows naming the GPIOs, which is already done in several device trees (e.g. mt8183-kukui-jacuzzi.dtsi, mt8183-kukui-kakadu.dtsi, mt8183-kukui-krane.dtsi), but was previously generating DT schema warnings. Signed-off-by: Julien Massot Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/20250801-mtk-dtb-warnings-v1-7-6ba4e432427b@collabora.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 464879274cae..3db2438fadc7 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -48,6 +48,8 @@ properties: description: GPIO valid number range. + gpio-line-names: true + interrupt-controller: true interrupts: -- cgit v1.2.3 From 126750523eac0ea79df672d9771eb483f7497b16 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Fri, 15 Aug 2025 22:53:52 +0530 Subject: ASoC: dt-bindings: qcom,wsa8830: Add reset-gpios for shared line On Qualcomm platforms such as QCS6490-RB3Gen2, the WSA883x speaker amplifiers share the SD_N GPIO line between two speakers, thus requires coordinated control when asserting the GPIO. Linux supports shared GPIO handling via the "reset-gpios" property, which can be used to specify either the powerdown or reset GPIOs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Mohammad Rafi Shaik Link: https://patch.msgid.link/20250815172353.2430981-2-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml b/Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml index 14d312f9c345..098f1df62c8c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml @@ -29,6 +29,10 @@ properties: description: GPIO spec for Powerdown/Shutdown line to use (pin SD_N) maxItems: 1 + reset-gpios: + description: Powerdown/Shutdown line to use (pin SD_N) + maxItems: 1 + vdd-supply: description: VDD Supply for the Codec @@ -50,10 +54,15 @@ required: - compatible - reg - vdd-supply - - powerdown-gpios - "#thermal-sensor-cells" - "#sound-dai-cells" +oneOf: + - required: + - powerdown-gpios + - required: + - reset-gpios + unevaluatedProperties: false examples: -- cgit v1.2.3 From f1bbfc405e3d36545f4fd1931c3e1d32396d1b63 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 18 Aug 2025 11:12:22 +0300 Subject: dt-bindings: iio: adc: Add BD7910[0,1,2,3] The ROHM BD79100, BD79101, BD79102, BD79103 are very similar ADCs as the ROHM BD79104. The BD79100 has only 1 channel. BD79101 has 2 channels and the BD79102 has 4 channels. Both BD79103 and BD79104 have 4 channels, and, based on the data sheets, they seem identical from the software point-of-view. Signed-off-by: Matti Vaittinen Acked-by: Conor Dooley Reviewed-by: David Lechner Link: https://patch.msgid.link/0874c5933cf56430b9440d19ff46f746e4897952.1755504346.git.mazziesaccount@gmail.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml b/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml index f0a1347ba4db..d5192ec58f59 100644 --- a/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml +++ b/Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml @@ -14,7 +14,15 @@ description: | properties: compatible: - const: rohm,bd79104 + oneOf: + - enum: + - rohm,bd79100 + - rohm,bd79101 + - rohm,bd79102 + - rohm,bd79104 + - items: + - const: rohm,bd79103 + - const: rohm,bd79104 reg: maxItems: 1 -- cgit v1.2.3 From a510980e740cc58be5733d4c15b22c7822e84c71 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Wed, 13 Aug 2025 12:21:19 +0100 Subject: dt-bindings: net: realtek,rtl82xx: document wakeup-source property The RTL8211F PHY has two modes for a single INTB/PMEB pin: 1. INTB mode, where it signals interrupts to the CPU, which can include wake-on-LAN events. 2. PMEB mode, where it only signals a wake-on-LAN event, which may either be a latched logic low until software manually clears the WoL state, or pulsed mode. In the case of (1), there is no way to know whether the interrupt to which the PHY is connected is capable of waking the system. In the case of (2), there would be no interrupt property in the PHY's DT description, and thus there is nothing to describe whether the pin is even wired to anything such as a power management controller. There is a "wakeup-source" property which can be applied to any device - see Documentation/devicetree/bindings/power/wakeup-source.txt Case 1 above matches example 2 in this document, and case 2 above matches example 3. Therefore, it seems reasonable to make use of this existing specification, albiet it hasn't been converted to YAML. Document the wakeup-source property in the device description, which will indicate that the PHY has been wired up in such a way that it can wake the system from a low power state. We will use this in a rewrite of the existing broken Wake-on-Lan code that was merged during the 6.16 merge window to support case 1. Case 2 can be added to the driver later without needing to further alter the DT description. To be clear, the existing Wake-on-Lan code that was recently merged has multiple functional issues. Signed-off-by: Russell King (Oracle) Acked-by: Conor Dooley Link: https://patch.msgid.link/E1um9Xj-008kBx-72@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml b/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml index d248a08a2136..2b5697bd7c5d 100644 --- a/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml @@ -45,12 +45,16 @@ properties: description: Disable CLKOUT clock, CLKOUT clock default is enabled after hardware reset. - realtek,aldps-enable: type: boolean description: Enable ALDPS mode, ALDPS mode default is disabled after hardware reset. + wakeup-source: + type: boolean + description: + Enable Wake-on-LAN support for the RTL8211F PHY. + unevaluatedProperties: false allOf: -- cgit v1.2.3 From edafd4f3fd52a614c5cee2684559367eac2286dc Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Sat, 9 Aug 2025 15:29:16 +0530 Subject: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the SM8750 QMP PCIe PHY Gen3 x2 Document the QMP PCIe PHY on the SM8750 platform. Signed-off-by: Krishna Chaitanya Chundru Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250809-pakala-v1-1-abf1c416dbaa@oss.qualcomm.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index a1ae8c7988c8..cb706cf8219d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -42,6 +42,7 @@ properties: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,sm8750-qmp-gen3x2-pcie-phy - qcom,x1e80100-qmp-gen3x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy @@ -164,6 +165,7 @@ allOf: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,sm8750-qmp-gen3x2-pcie-phy then: properties: clocks: -- cgit v1.2.3 From 91d7789fd016e0616913313b3306b83f8a608489 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Wed, 6 Aug 2025 19:41:10 +0800 Subject: dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible Add new compatible string "fsl,imx91-media-blk-ctrl" for i.MX91, which has different input clocks compared to i.MX93. Update the clock-names list and handle it in the if-else branch accordingly. Keep the same restriction for the existed compatible strings. Reviewed-by: Rob Herring (Arm) Reviewed-by: Frank Li Signed-off-by: Joy Zou Link: https://lore.kernel.org/r/20250806114119.1948624-3-joy.zou@nxp.com Signed-off-by: Ulf Hansson --- .../bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml | 59 +++++++++++++++++----- 1 file changed, 47 insertions(+), 12 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml index b3554e7f9e76..34aea58094e5 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -18,7 +18,9 @@ description: properties: compatible: items: - - const: fsl,imx93-media-blk-ctrl + - enum: + - fsl,imx91-media-blk-ctrl + - fsl,imx93-media-blk-ctrl - const: syscon reg: @@ -31,21 +33,54 @@ properties: maxItems: 1 clocks: + minItems: 8 maxItems: 10 clock-names: - items: - - const: apb - - const: axi - - const: nic - - const: disp - - const: cam - - const: pxp - - const: lcdif - - const: isi - - const: csi - - const: dsi + minItems: 8 + maxItems: 10 +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx91-media-blk-ctrl + then: + properties: + clocks: + maxItems: 8 + clock-names: + items: + - const: apb + - const: axi + - const: nic + - const: disp + - const: cam + - const: lcdif + - const: isi + - const: csi + - if: + properties: + compatible: + contains: + const: fsl,imx93-media-blk-ctrl + then: + properties: + clocks: + minItems: 10 + clock-names: + items: + - const: apb + - const: axi + - const: nic + - const: disp + - const: cam + - const: pxp + - const: lcdif + - const: isi + - const: csi + - const: dsi required: - compatible - reg -- cgit v1.2.3 From 46b4ddd2c4951c073a16bbf271221240fe2584e5 Mon Sep 17 00:00:00 2001 From: Abd-Alrhman Masalkhi Date: Thu, 17 Jul 2025 06:39:32 +0000 Subject: dt-bindings: eeprom: Add ST M24LR support Add support for STMicroelectronics M24LR RFID/NFC EEPROM chips. These devices use two I2C addresses: the primary address provides access to control and system parameter registers, while the secondary address is used for EEPROM access. Signed-off-by: Abd-Alrhman Masalkhi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717063934.5083-2-abd.masalkhi@gmail.com Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/eeprom/st,m24lr.yaml | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/eeprom/st,m24lr.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/st,m24lr.yaml b/Documentation/devicetree/bindings/eeprom/st,m24lr.yaml new file mode 100644 index 000000000000..0a0820e9d11f --- /dev/null +++ b/Documentation/devicetree/bindings/eeprom/st,m24lr.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/eeprom/st,m24lr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics M24LR NFC/RFID EEPROM + +maintainers: + - Abd-Alrhman Masalkhi + +description: + STMicroelectronics M24LR series are dual-interface (RF + I2C) + EEPROM chips. These devices support I2C-based access to both + memory and a system area that controls authentication and configuration. + They expose two I2C addresses, one for the system parameter sector and + one for the EEPROM. + +allOf: + - $ref: /schemas/nvmem/nvmem.yaml# + +properties: + compatible: + enum: + - st,m24lr04e-r + - st,m24lr16e-r + - st,m24lr64e-r + + reg: + items: + - description: I2C address used for control/system registers + - description: I2C address used for EEPROM memory access + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "st,m24lr04e-r"; + reg = <0x57>, /* primary-device */ + <0x53>; /* secondary-device */ + }; + }; +... -- cgit v1.2.3 From 15e3363af00a9e5b4f5c10b17940733a8613ef57 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Tue, 12 Aug 2025 16:24:40 -0500 Subject: dt-bindings: pinctrl: Document Tegra186 pin controllers Tegra186 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide. Reviewed-by: Rob Herring (Arm) Signed-off-by: Aaron Kling Link: https://lore.kernel.org/20250812-tegra186-pinctrl-v3-1-115714eeecb1@gmail.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/nvidia,tegra186-pinmux.yaml | 285 +++++++++++++++++++++ 1 file changed, 285 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml new file mode 100644 index 000000000000..ac764d0ac4b6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml @@ -0,0 +1,285 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra186-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + enum: + - nvidia,tegra186-pinmux + - nvidia,tegra186-pinmux-aon + + reg: + items: + - description: pinmux registers + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + unevaluatedProperties: false + properties: + nvidia,function: + enum: [ aud, can0, can1, ccla, dca, dcb, dcc, directdc, directdc1, + displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp, + dspk0, dspk1, dtv, eqos, extperiph1, extperiph2, extperiph3, + extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c7, + i2c8, i2c9, i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, iqc0, iqc1, + nv, pe, pe0, pe1, pe2, qspi, rsvd0, rsvd1, rsvd2, rsvd3, + sata, sce, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, + spi2, spi3, spi4, touch, uarta, uartb, uartc, uartd, uarte, + uartf, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, + wdt ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + + required: + - nvidia,pins + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-pinmux + then: + patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + additionalProperties: + properties: + nvidia,pins: + description: An array of strings. Each string contains the name + of a pin or group. Valid values for these names are listed + below. + items: + enum: [ pex_l0_rst_n_pa0, pex_l0_clkreq_n_pa1, + pex_wake_n_pa2, pex_l1_rst_n_pa3, + pex_l1_clkreq_n_pa4, pex_l2_rst_n_pa5, + pex_l2_clkreq_n_pa6, uart4_tx_pb0, uart4_rx_pb1, + uart4_rts_pb2, uart4_cts_pb3, gpio_wan1_pb4, + gpio_wan2_pb5, gpio_wan3_pb6, gpio_wan4_pc0, + dap2_sclk_pc1, dap2_dout_pc2, dap2_din_pc3, + dap2_fs_pc4, gen1_i2c_scl_pc5, gen1_i2c_sda_pc6, + sdmmc1_clk_pd0, sdmmc1_cmd_pd1, sdmmc1_dat0_pd2, + sdmmc1_dat1_pd3, sdmmc1_dat2_pd4, sdmmc1_dat3_pd5, + eqos_txc_pe0, eqos_td0_pe1, eqos_td1_pe2, + eqos_td2_pe3, eqos_td3_pe4, eqos_tx_ctl_pe5, + eqos_rd0_pe6, eqos_rd1_pe7, eqos_rd2_pf0, + eqos_rd3_pf1, eqos_rx_ctl_pf2, eqos_rxc_pf3, + eqos_mdio_pf4, eqos_mdc_pf5, sdmmc3_clk_pg0, + sdmmc3_cmd_pg1, sdmmc3_dat0_pg2, sdmmc3_dat1_pg3, + sdmmc3_dat2_pg4, sdmmc3_dat3_pg5, gpio_wan5_ph0, + gpio_wan6_ph1, gpio_wan7_ph2, gpio_wan8_ph3, + bcpu_pwr_req_ph4, mcpu_pwr_req_ph5, gpu_pwr_req_ph6, + gpio_pq0_pi0, gpio_pq1_pi1, gpio_pq2_pi2, + gpio_pq3_pi3, gpio_pq4_pi4, gpio_pq5_pi5, + gpio_pq6_pi6, gpio_pq7_pi7, dap1_sclk_pj0, + dap1_dout_pj1, dap1_din_pj2, dap1_fs_pj3, + aud_mclk_pj4, gpio_aud0_pj5, gpio_aud1_pj6, + gpio_aud2_pj7, gpio_aud3_pk0, gen7_i2c_scl_pl0, + gen7_i2c_sda_pl1, gen9_i2c_scl_pl2, gen9_i2c_sda_pl3, + usb_vbus_en0_pl4, usb_vbus_en1_pl5, gp_pwm6_pl6, + gp_pwm7_pl7, dmic1_dat_pm0, dmic1_clk_pm1, + dmic2_dat_pm2, dmic2_clk_pm3, dmic4_dat_pm4, + dmic4_clk_pm5, gpio_cam1_pn0, gpio_cam2_pn1, + gpio_cam3_pn2, gpio_cam4_pn3, gpio_cam6_pn5, + gpio_cam7_pn6, extperiph1_clk_po0, + extperiph2_clk_po1, cam_i2c_scl_po2, cam_i2c_sda_po3, + dp_aux_ch0_hpd_pp0, dp_aux_ch1_hpd_pp1, hdmi_cec_pp2, + gpio_edp0_pp3, gpio_edp1_pp4, gpio_edp2_pp5, + gpio_edp3_pp6, directdc1_clk_pq0, directdc1_in_pq1, + directdc1_out0_pq2, directdc1_out1_pq3, + directdc1_out2_pq4, directdc1_out3_pq5, + qspi_sck_pr0, qspi_io0_pr1, qspi_io1_pr2, + qspi_io2_pr3, qspi_io3_pr4, qspi_cs_n_pr5, + uart1_tx_pt0, uart1_rx_pt1, uart1_rts_pt2, + uart1_cts_pt3, uart2_tx_px0, uart2_rx_px1, + uart2_rts_px2, uart2_cts_px3, uart5_tx_px4, + uart5_rx_px5, uart5_rts_px6, uart5_cts_px7, + gpio_mdm1_py0, gpio_mdm2_py1, gpio_mdm3_py2, + gpio_mdm4_py3, gpio_mdm5_py4, gpio_mdm6_py5, + gpio_mdm7_py6, ufs0_ref_clk_pbb0, ufs0_rst_pbb1, + dap4_sclk_pcc0, dap4_dout_pcc1, dap4_din_pcc2, + dap4_fs_pcc3, directdc_comp, sdmmc1_comp, eqos_comp, + sdmmc3_comp, qspi_comp, + # drive groups + drive_gpio_aud3_pk0, drive_gpio_aud2_pj7, + drive_gpio_aud1_pj6, drive_gpio_aud0_pj5, + drive_aud_mclk_pj4, drive_dap1_fs_pj3, + drive_dap1_din_pj2, drive_dap1_dout_pj1, + drive_dap1_sclk_pj0, drive_dmic1_clk_pm1, + drive_dmic1_dat_pm0, drive_dmic2_dat_pm2, + drive_dmic2_clk_pm3, drive_dmic4_dat_pm4, + drive_dmic4_clk_pm5, drive_dap4_fs_pcc3, + drive_dap4_din_pcc2, drive_dap4_dout_pcc1, + drive_dap4_sclk_pcc0, drive_extperiph2_clk_po1, + drive_extperiph1_clk_po0, drive_cam_i2c_sda_po3, + drive_cam_i2c_scl_po2, drive_gpio_cam1_pn0, + drive_gpio_cam2_pn1, drive_gpio_cam3_pn2, + drive_gpio_cam4_pn3, drive_gpio_cam5_pn4, + drive_gpio_cam6_pn5, drive_gpio_cam7_pn6, + drive_dap2_din_pc3, drive_dap2_dout_pc2, + drive_dap2_fs_pc4, drive_dap2_sclk_pc1, + drive_uart4_cts_pb3, drive_uart4_rts_pb2, + drive_uart4_rx_pb1, drive_uart4_tx_pb0, + drive_gpio_wan4_pc0, drive_gpio_wan3_pb6, + drive_gpio_wan2_pb5, drive_gpio_wan1_pb4, + drive_gen1_i2c_scl_pc5, drive_gen1_i2c_sda_pc6, + drive_uart1_cts_pt3, drive_uart1_rts_pt2, + drive_uart1_rx_pt1, drive_uart1_tx_pt0, + drive_directdc1_out3_pq5, drive_directdc1_out2_pq4, + drive_directdc1_out1_pq3, drive_directdc1_out0_pq2, + drive_directdc1_in_pq1, drive_directdc1_clk_pq0, + drive_gpio_pq0_pi0, drive_gpio_pq1_pi1, + drive_gpio_pq2_pi2, drive_gpio_pq3_pi3, + drive_gpio_pq4_pi4, drive_gpio_pq5_pi5, + drive_gpio_pq6_pi6, drive_gpio_pq7_pi7, + drive_gpio_edp2_pp5, drive_gpio_edp3_pp6, + drive_gpio_edp0_pp3, drive_gpio_edp1_pp4, + drive_dp_aux_ch0_hpd_pp0, drive_dp_aux_ch1_hpd_pp1, + drive_hdmi_cec_pp2, drive_pex_l2_clkreq_n_pa6, + drive_pex_wake_n_pa2, drive_pex_l1_clkreq_n_pa4, + drive_pex_l1_rst_n_pa3, drive_pex_l0_clkreq_n_pa1, + drive_pex_l0_rst_n_pa0, drive_pex_l2_rst_n_pa5, + drive_sdmmc1_clk_pd0, drive_sdmmc1_cmd_pd1, + drive_sdmmc1_dat3_pd5, drive_sdmmc1_dat2_pd4, + drive_sdmmc1_dat1_pd3, drive_sdmmc1_dat0_pd2, + drive_eqos_td3_pe4, drive_eqos_td2_pe3, + drive_eqos_td1_pe2, drive_eqos_td0_pe1, + drive_eqos_rd3_pf1, drive_eqos_rd2_pf0, + drive_eqos_rd1_pe7, drive_eqos_mdio_pf4, + drive_eqos_rd0_pe6, drive_eqos_mdc_pf5, + drive_eqos_txc_pe0, drive_eqos_rxc_pf3, + drive_eqos_tx_ctl_pe5, drive_eqos_rx_ctl_pf2, + drive_sdmmc3_dat3_pg5, drive_sdmmc3_dat2_pg4, + drive_sdmmc3_dat1_pg3, drive_sdmmc3_dat0_pg2, + drive_sdmmc3_cmd_pg1, drive_sdmmc3_clk_pg0, + drive_qspi_io3_pr4, drive_qspi_io2_pr3, + drive_qspi_io1_pr2, drive_qspi_io0_pr1, + drive_qspi_sck_pr0, drive_qspi_cs_n_pr5, + drive_gpio_wan8_ph3, drive_gpio_wan7_ph2, + drive_gpio_wan6_ph1, drive_gpio_wan5_ph0, + drive_uart2_tx_px0, drive_uart2_rx_px1, + drive_uart2_rts_px2, drive_uart2_cts_px3, + drive_uart5_rx_px5, drive_uart5_tx_px4, + drive_uart5_rts_px6, drive_uart5_cts_px7, + drive_gpio_mdm1_py0, drive_gpio_mdm2_py1, + drive_gpio_mdm3_py2, drive_gpio_mdm4_py3, + drive_gpio_mdm5_py4, drive_gpio_mdm6_py5, + drive_gpio_mdm7_py6, drive_bcpu_pwr_req_ph4, + drive_mcpu_pwr_req_ph5, drive_gpu_pwr_req_ph6, + drive_gen7_i2c_scl_pl0, drive_gen7_i2c_sda_pl1, + drive_gen9_i2c_sda_pl3, drive_gen9_i2c_scl_pl2, + drive_usb_vbus_en0_pl4, drive_usb_vbus_en1_pl5, + drive_gp_pwm7_pl7, drive_gp_pwm6_pl6, + drive_ufs0_rst_pbb1, drive_ufs0_ref_clk_pbb0, + drive_directdc_comp, drive_sdmmc1_comp, + drive_eqos_comp, drive_sdmmc3_comp, drive_sdmmc4_clk, + drive_sdmmc4_cmd, drive_sdmmc4_dqs, + drive_sdmmc4_dat7, drive_sdmmc4_dat6, + drive_sdmmc4_dat5, drive_sdmmc4_dat4, + drive_sdmmc4_dat3, drive_sdmmc4_dat2, + drive_sdmmc4_dat1, drive_sdmmc4_dat0, + drive_qspi_comp ] + + - if: + properties: + compatible: + const: nvidia,tegra186-pinmux-aon + then: + patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + additionalProperties: + properties: + nvidia,pins: + items: + enum: [ pwr_i2c_scl_ps0, pwr_i2c_sda_ps1, batt_oc_ps2, + safe_state_ps3, vcomp_alert_ps4, gpio_dis0_pu0, + gpio_dis1_pu1, gpio_dis2_pu2, gpio_dis3_pu3, + gpio_dis4_pu4, gpio_dis5_pu5, gpio_sen0_pv0, + gpio_sen1_pv1, gpio_sen2_pv2, gpio_sen3_pv3, + gpio_sen4_pv4, gpio_sen5_pv5, gpio_sen6_pv6, + gpio_sen7_pv7, gen8_i2c_scl_pw0, gen8_i2c_sda_pw1, + uart3_tx_pw2, uart3_rx_pw3, uart3_rts_pw4, + uart3_cts_pw5, uart7_tx_pw6, uart7_rx_pw7, + can1_dout_pz0, can1_din_pz1, can0_dout_pz2, + can0_din_pz3, can_gpio0_paa0, can_gpio1_paa1, + can_gpio2_paa2, can_gpio3_paa3, can_gpio4_paa4, + can_gpio5_paa5, can_gpio6_paa6, can_gpio7_paa7, + gpio_sen8_pee0, gpio_sen9_pee1, touch_clk_pee2, + power_on_pff0, gpio_sw1_pff1, gpio_sw2_pff2, + gpio_sw3_pff3, gpio_sw4_pff4, shutdown, pmu_int, + soc_pwr_req, clk_32k_in, + # drive groups + drive_touch_clk_pee2, drive_uart3_cts_pw5, + drive_uart3_rts_pw4, drive_uart3_rx_pw3, + drive_uart3_tx_pw2, drive_gen8_i2c_sda_pw1, + drive_gen8_i2c_scl_pw0, drive_uart7_rx_pw7, + drive_uart7_tx_pw6, drive_gpio_sen0_pv0, + drive_gpio_sen1_pv1, drive_gpio_sen2_pv2, + drive_gpio_sen3_pv3, drive_gpio_sen4_pv4, + drive_gpio_sen5_pv5, drive_gpio_sen6_pv6, + drive_gpio_sen7_pv7, drive_gpio_sen8_pee0, + drive_gpio_sen9_pee1, drive_can_gpio7_paa7, + drive_can1_dout_pz0, drive_can1_din_pz1, + drive_can0_dout_pz2, drive_can0_din_pz3, + drive_can_gpio0_paa0, drive_can_gpio1_paa1, + drive_can_gpio2_paa2, drive_can_gpio3_paa3, + drive_can_gpio4_paa4, drive_can_gpio5_paa5, + drive_can_gpio6_paa6, drive_gpio_sw1_pff1, + drive_gpio_sw2_pff2, drive_gpio_sw3_pff3, + drive_gpio_sw4_pff4, drive_shutdown, drive_pmu_int, + drive_safe_state_ps3, drive_vcomp_alert_ps4, + drive_soc_pwr_req, drive_batt_oc_ps2, + drive_clk_32k_in, drive_power_on_pff0, + drive_pwr_i2c_scl_ps0, drive_pwr_i2c_sda_ps1, + drive_gpio_dis0_pu0, drive_gpio_dis1_pu1, + drive_gpio_dis2_pu2, drive_gpio_dis3_pu3, + drive_gpio_dis4_pu4, drive_gpio_dis5_pu5 ] + +required: + - compatible + - reg + +examples: + - | + #include + + pinmux@2430000 { + compatible = "nvidia,tegra186-pinmux"; + reg = <0x2430000 0x15000>; + + pinctrl-names = "jetson_io"; + pinctrl-0 = <&jetson_io_pinmux>; + + jetson_io_pinmux: pinmux { + hdr40-pin7 { + nvidia,pins = "aud_mclk_pj4"; + nvidia,function = "aud"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; +... -- cgit v1.2.3 From 29a799917947d24c55e8902ef29f5cb52195682c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 5 Aug 2025 09:47:39 +0200 Subject: dt-bindings: power: mediatek: Document access-controllers property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow specifying access-controllers in the main power controller node and deprecate the old mediatek,infracfg, mediatek,infracfg-nao and mediatek,smi properties located in the children. This is done in order to both simplify the power controller nodes and in preparation for adding support for new generation SoCs like MT8196/MT6991 and other variants, which will need to set protection on new busses. Reviewed-by: Nícolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250805074746.29457-4-angelogioacchino.delregno@collabora.com Signed-off-by: Ulf Hansson --- .../bindings/power/mediatek,power-controller.yaml | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 9c7cc632abee..500d98921581 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -44,6 +44,15 @@ properties: '#size-cells': const: 0 + access-controllers: + description: + A number of phandles to external blocks to set and clear the required + bits to enable or disable bus protection, necessary to avoid any bus + faults while enabling or disabling a power domain. + For example, this may hold phandles to INFRACFG and SMI. + minItems: 1 + maxItems: 3 + patternProperties: "^power-domain@[0-9a-f]+$": $ref: "#/$defs/power-domain-node" @@ -123,14 +132,17 @@ $defs: mediatek,infracfg: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG register range. + deprecated: true mediatek,infracfg-nao: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG-NAO register range. + deprecated: true mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register range. + deprecated: true required: - reg @@ -138,6 +150,31 @@ $defs: required: - compatible +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8183-power-controller + then: + properties: + access-controllers: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8365-power-controller + then: + properties: + access-controllers: + minItems: 3 + maxItems: 3 + additionalProperties: false examples: -- cgit v1.2.3 From 0106b6c114cf8b77d801d9e280b221f8b4d5595b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 3 Jul 2025 14:08:46 +0200 Subject: dt-bindings: PCI: mediatek-gen3: Add support for MT6991/MT8196 Add compatible strings for MT8196 and MT6991 (which are fully compatible between each other) and clock definitions. These new SoCs don't have tl_96m and tl_32k clocks, but need an AHB to APB bus clock and a low power clock. Signed-off-by: AngeloGioacchino Del Regno [mani: changed 'maxItems' to 'minItems' for reset] Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250703120847.121826-3-angelogioacchino.delregno@collabora.com --- .../bindings/pci/mediatek-pcie-gen3.yaml | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 162406e0691a..0278845701ce 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -52,7 +52,12 @@ properties: - mediatek,mt8188-pcie - mediatek,mt8195-pcie - const: mediatek,mt8192-pcie + - items: + - enum: + - mediatek,mt6991-pcie + - const: mediatek,mt8196-pcie - const: mediatek,mt8192-pcie + - const: mediatek,mt8196-pcie - const: airoha,en7581-pcie reg: @@ -212,6 +217,36 @@ allOf: mediatek,pbus-csr: false + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8196-pcie + then: + properties: + clocks: + minItems: 6 + + clock-names: + items: + - const: pl_250m + - const: tl_26m + - const: bus + - const: low_power + - const: peri_26m + - const: peri_mem + + resets: + minItems: 2 + + reset-names: + items: + - const: phy + - const: mac + + mediatek,pbus-csr: false + - if: properties: compatible: -- cgit v1.2.3 From 566c269873c642856bceced2add800d2ce8b8c94 Mon Sep 17 00:00:00 2001 From: Goran Rađenović Date: Wed, 16 Jul 2025 17:48:05 +0200 Subject: dt-bindings: arm: imx8mp: Add Ultratronik Ultra-MACH SBC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the Ultratronik Ultra-MACH SBC, based on the NXP i.MX8MP SoC. This board is manufactured by Ultratronik GmbH and uses the compatible string "ux,imx8mp-ultra-mach-sbc". Acked-by: Krzysztof Kozlowski Signed-off-by: Goran Rađenović Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a3e9f9e0735a..839f428c9f75 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1112,6 +1112,7 @@ properties: - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel + - ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8MP based board - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board - const: fsl,imx8mp -- cgit v1.2.3 From 04113322406b4763677922f80ba5ab44a8dae7bb Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Tue, 19 Aug 2025 22:13:01 +0200 Subject: ASoC: dt-bindings: ti,twl4030-audio: convert to DT schema Convert the TWL4030 audio module bindings from txt to YAML format and move them to the sound subsystem bindings directory. This patch also refines the schema by adding an enum constraint for ti,enable-vibra and updates the example to remove irrelevant I2C clock-frequency property. Signed-off-by: Jihed Chaibi Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250819201302.80712-2-jihed.chaibi.dev@gmail.com Signed-off-by: Mark Brown --- .../devicetree/bindings/mfd/twl4030-audio.txt | 46 ----------- .../bindings/sound/ti,twl4030-audio.yaml | 90 ++++++++++++++++++++++ 2 files changed, 90 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/twl4030-audio.txt create mode 100644 Documentation/devicetree/bindings/sound/ti,twl4030-audio.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt deleted file mode 100644 index 414d2ae0adf6..000000000000 --- a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt +++ /dev/null @@ -1,46 +0,0 @@ -Texas Instruments TWL family (twl4030) audio module - -The audio module inside the TWL family consist of an audio codec and a vibra -driver. - -Required properties: -- compatible : must be "ti,twl4030-audio" - -Optional properties, nodes: - -Audio functionality: -- codec { }: Need to be present if the audio functionality is used. Within this - section the following options can be used: -- ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts - from the start of the recorded sample (in ms) --ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise --ti,hs_extmute: Use external mute for HS pop reduction --ti,hs_extmute_gpio: Use external GPIO to control the external mute --ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the - valid values. - -Vibra functionality -- ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if - missing or it is 0, the vibra functionality is disabled. - -Example: -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - - ti,enable-vibra = <1>; - - codec { - ti,ramp_delay_value = <3>; - }; - - }; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/ti,twl4030-audio.yaml b/Documentation/devicetree/bindings/sound/ti,twl4030-audio.yaml new file mode 100644 index 000000000000..c9c3f7513ad4 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,twl4030-audio.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,twl4030-audio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TWL4030-family Audio Module + +maintainers: + - Peter Ujfalusi + +description: + The audio module within the TWL4030-family of companion chips consists + of an audio codec and a vibra driver. This binding describes the parent + node for these functions. + +properties: + compatible: + const: ti,twl4030-audio + + codec: + type: object + description: Node containing properties for the audio codec functionality. + + properties: + ti,digimic_delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in milliseconds after enabling digital microphones to reduce + artifacts. + + ti,ramp_delay_value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Headset ramp delay configuration to reduce pop noise. + + ti,hs_extmute: + type: boolean + description: + Enable the use of an external mute for headset pop reduction. + + ti,hs_extmute_gpio: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The GPIO specifier for the external mute control. + maxItems: 1 + + ti,offset_cncl_path: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Offset cancellation path selection. Refer to the Technical + Reference Manual for valid values. + + # The 'codec' node itself is optional, but if it exists, it can be empty. + # We don't require any of its sub-properties. + + ti,enable-vibra: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Enable or disable the vibra functionality. + +additionalProperties: false + +required: + - compatible + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + + ti,enable-vibra = <1>; + + codec { + ti,ramp_delay_value = <3>; + }; + + }; + }; + }; -- cgit v1.2.3 From c232495d28ca092d0c39b10e35d3d613bd2414ab Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Tue, 19 Aug 2025 22:13:02 +0200 Subject: ASoC: dt-bindings: omap-twl4030: convert to DT schema Convert the legacy TXT binding for the OMAP TWL4030 sound card to the modern YAML DT schema format. This adds formal validation and improves documentation. Acked-by: Mark Brown Signed-off-by: Jihed Chaibi Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250819201302.80712-3-jihed.chaibi.dev@gmail.com Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/omap-twl4030.txt | 62 -------------- .../devicetree/bindings/sound/ti,omap-twl4030.yaml | 98 ++++++++++++++++++++++ 2 files changed, 98 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/omap-twl4030.txt create mode 100644 Documentation/devicetree/bindings/sound/ti,omap-twl4030.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt deleted file mode 100644 index f6a715e4ef43..000000000000 --- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Texas Instruments SoC with twl4030 based audio setups - -Required properties: -- compatible: "ti,omap-twl4030" -- ti,model: Name of the sound card (for example "omap3beagle") -- ti,mcbsp: phandle for the McBSP node - -Optional properties: -- ti,codec: phandle for the twl4030 audio node -- ti,mcbsp-voice: phandle for the McBSP node connected to the voice port of twl -- ti, jack-det-gpio: Jack detect GPIO -- ti,audio-routing: List of connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. - If the routing is not provided all possible connection will be available - -Available audio endpoints for the audio-routing table: - -Board connectors: - * Headset Stereophone - * Earpiece Spk - * Handsfree Spk - * Ext Spk - * Main Mic - * Sub Mic - * Headset Mic - * Carkit Mic - * Digital0 Mic - * Digital1 Mic - * Line In - -twl4030 pins: - * HSOL - * HSOR - * EARPIECE - * HFL - * HFR - * PREDRIVEL - * PREDRIVER - * CARKITL - * CARKITR - * MAINMIC - * SUBMIC - * HSMIC - * DIGIMIC0 - * DIGIMIC1 - * CARKITMIC - * AUXL - * AUXR - - * Headset Mic Bias - * Mic Bias 1 /* Used for Main Mic or Digimic0 */ - * Mic Bias 2 /* Used for Sub Mic or Digimic1 */ - -Example: - -sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; -}; diff --git a/Documentation/devicetree/bindings/sound/ti,omap-twl4030.yaml b/Documentation/devicetree/bindings/sound/ti,omap-twl4030.yaml new file mode 100644 index 000000000000..27c7019bdc85 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,omap-twl4030.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,omap-twl4030.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments SoC with twl4030 based audio setups + +maintainers: + - Peter Ujfalusi + +description: + Audio setups on TI OMAP SoCs using TWL4030-family + audio codec connected via a McBSP port. + +properties: + compatible: + const: ti,omap-twl4030 + + ti,model: + $ref: /schemas/types.yaml#/definitions/string + description: Name of the sound card (for example "omap3beagle"). + + ti,mcbsp: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle for the McBSP node. + + ti,codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle for the twl4030 audio node. + + ti,mcbsp-voice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the McBSP node connected to the voice port. + + ti,jack-det-gpio: + description: GPIO specifier for jack detection. + maxItems: 1 + + ti,audio-routing: + description: | + A list of audio routing connections. Each entry is a pair of strings, + with the first being the connection's sink and the second being the + source. If not provided, all possible connections are available. + + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + items: + enum: + # Board Connectors + - Headset Stereophone + - Earpiece Spk + - Handsfree Spk + - Ext Spk + - Main Mic + - Sub Mic + - Headset Mic + - Carkit Mic + - Digital0 Mic + - Digital1 Mic + - Line In + + # CODEC Pins + - HSOL + - HSOR + - EARPIECE + - HFL + - HFR + - PREDRIVEL + - PREDRIVER + - CARKITL + - CARKITR + - MAINMIC + - SUBMIC + - HSMIC + - DIGIMIC0 + - DIGIMIC1 + - CARKITMIC + - AUXL + - AUXR + + # Headset Mic Bias + - Mic Bias 1 # Used for Main Mic or Digimic0 + - Mic Bias 2 # Used for Sub Mic or Digimic1 + +required: + - compatible + - ti,model + - ti,mcbsp + +additionalProperties: false + +examples: + - | + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + ti,mcbsp = <&mcbsp2>; + }; -- cgit v1.2.3 From 3bad7fe22796a420c6e16b591c37ed1bd6cc2a30 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 7 Aug 2025 18:33:19 +0200 Subject: dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Reference usb-switch.yaml to allow mode-switch The QMP USB3/DP Combo PHY can work in 3 modes: - DisplayPort Only - USB3 Only - USB3 + DisplayPort Combo mode In order to switch between those modes, the PHY needs to receive Type-C events, allow marking to the phy with the mode-switch property in order to allow the PHY to Type-C events. Reference usb-switch.yaml as a simpler way to allow the mode-switch property instead of duplicating the property definition. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Tested-by: Neil Armstrong # on Lenovo Thinkpad T14S Link: https://lore.kernel.org/r/20250807-topic-4ln_dp_respin-v4-1-43272d6eca92@oss.qualcomm.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 38ce04c35d94..c8bc512df08b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -73,10 +73,8 @@ properties: description: See include/dt-bindings/phy/phy-qcom-qmp.h - orientation-switch: - description: - Flag the PHY as possible handler of USB Type-C orientation switching - type: boolean + mode-switch: true + orientation-switch: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -106,6 +104,7 @@ required: - "#phy-cells" allOf: + - $ref: /schemas/usb/usb-switch.yaml# - if: properties: compatible: -- cgit v1.2.3 From ab9c8aeb2d208381a7c948ea2f753cbe8a451502 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 8 Aug 2025 22:52:05 +0100 Subject: dt-bindings: phy: renesas,usb2-phy: Add RZ/T2H and RZ/N2H support Document the USB2 PHY controller for the Renesas RZ/T2H (r9a09g077) and RZ/N2H (r9a09g087) SoCs. These SoCs share the same PHY block, which is similar to the one on RZ/G2L but differs in clocks, resets, and register bits. To account for these differences, a new compatible string `renesas,usb2-phy-r9a09g077` is introduced. The RZ/N2H SoC uses the same PHY as RZ/T2H, so it reuses the RZ/T2H compatible string as a fallback. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20250808215209.3692744-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/renesas,usb2-phy.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index f45c5f039ae8..179cb4bfc424 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -44,6 +44,12 @@ properties: - const: renesas,usb2-phy-r9a09g056 # RZ/V2N - const: renesas,usb2-phy-r9a09g057 + - const: renesas,usb2-phy-r9a09g077 # RZ/T2H + + - items: + - const: renesas,usb2-phy-r9a09g087 # RZ/N2H + - const: renesas,usb2-phy-r9a09g077 + reg: maxItems: 1 @@ -120,6 +126,17 @@ allOf: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,usb2-phy-r9a09g077 + then: + properties: + clocks: + minItems: 2 + resets: false + additionalProperties: false examples: -- cgit v1.2.3 From ce489635960a6a3fcb0abe0918994f2d8deb02ed Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Wed, 30 Jul 2025 15:27:25 +0800 Subject: dt-bindings: phy: Add eDP PHY compatible for QCS8300 Add compatible string for the supported eDP PHY on QCS8300 platform. QCS8300 have the same eDP PHY with SA8775P. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/r/20250730072725.1433360-1-quic_yongmou@quicinc.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,edp-phy.yaml | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 293fb6a9b1c3..eb97181cbb95 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -16,13 +16,18 @@ description: properties: compatible: - enum: - - qcom,sa8775p-edp-phy - - qcom,sc7280-edp-phy - - qcom,sc8180x-edp-phy - - qcom,sc8280xp-dp-phy - - qcom,sc8280xp-edp-phy - - qcom,x1e80100-dp-phy + oneOf: + - enum: + - qcom,sa8775p-edp-phy + - qcom,sc7280-edp-phy + - qcom,sc8180x-edp-phy + - qcom,sc8280xp-dp-phy + - qcom,sc8280xp-edp-phy + - qcom,x1e80100-dp-phy + - items: + - enum: + - qcom,qcs8300-edp-phy + - const: qcom,sa8775p-edp-phy reg: items: -- cgit v1.2.3 From 7a430af7d135be5042f14987bce16f6b40a3f694 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 15:33:07 -0500 Subject: dt-bindings: dma: nvidia,tegra20-apbdma: Add undocumented compatibles and "clock-names" Add the undocumented NVIDIA APBDMA compatibles and "clock-names" which are already in use. There doesn't appear to be any per compatible differences. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250812203308.727731-1-robh@kernel.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml index a2ffd5209b3b..ea40c4e27a97 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml @@ -18,10 +18,17 @@ maintainers: properties: compatible: oneOf: - - const: nvidia,tegra20-apbdma + - enum: + - nvidia,tegra114-apbdma + - nvidia,tegra20-apbdma - items: - const: nvidia,tegra30-apbdma - const: nvidia,tegra20-apbdma + - items: + - enum: + - nvidia,tegra124-apbdma + - nvidia,tegra210-apbdma + - const: nvidia,tegra148-apbdma reg: maxItems: 1 @@ -32,6 +39,9 @@ properties: clocks: maxItems: 1 + clock-names: + const: dma + interrupts: description: Should contain all of the per-channel DMA interrupts in -- cgit v1.2.3 From 411053cb6657a3cf8db50a2d004a112070ca14b2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 19 Aug 2025 09:13:44 -0300 Subject: dt-bindings: w1: imx: Add an entry for the interrupts property There is an interrupt line connected to the one-wire block on the i.MX51 and i.MX53. Add an entry for the interrupt property to avoid the following dt-schema warning: 'interrupts' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Fabio Estevam Acked-by: Conor Dooley Reviewed-by: Frank Li Link: https://lore.kernel.org/r/20250819121344.2765940-1-festevam@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/w1/fsl-imx-owire.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/w1/fsl-imx-owire.yaml b/Documentation/devicetree/bindings/w1/fsl-imx-owire.yaml index 55adea827c34..2c1bbc0eb05a 100644 --- a/Documentation/devicetree/bindings/w1/fsl-imx-owire.yaml +++ b/Documentation/devicetree/bindings/w1/fsl-imx-owire.yaml @@ -24,6 +24,9 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 1 + clocks: maxItems: 1 @@ -40,5 +43,6 @@ examples: owire@63fa4000 { compatible = "fsl,imx53-owire", "fsl,imx21-owire"; reg = <0x63fa4000 0x4000>; + interrupts = <88>; clocks = <&clks IMX5_CLK_OWIRE_GATE>; }; -- cgit v1.2.3 From 74403d260a4b5c12c15c1862c3df5b17b803549a Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 14 Jul 2025 11:13:45 -0400 Subject: dt-bindings: arm: fsl: add i.MX8ULP EVK9 board Add DT compatible string for the i.MX8ULP EVK9 board. Signed-off-by: Laurentiu Mihalcea Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 839f428c9f75..e21758546d13 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1383,6 +1383,7 @@ properties: - description: i.MX8ULP based Boards items: - enum: + - fsl,imx8ulp-9x9-evk # i.MX8ULP EVK9 Board - fsl,imx8ulp-evk # i.MX8ULP EVK Board - const: fsl,imx8ulp -- cgit v1.2.3 From 1898fc572118a65aa0d927dd5ff4b7e1a0140ddd Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Mon, 18 Aug 2025 21:14:25 +0800 Subject: dt-bindings: net: Add PPE for Qualcomm IPQ9574 SoC The PPE (packet process engine) hardware block is available in Qualcomm IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in the IPQ9574 SoC includes six Ethernet ports (6 GMAC and 6 XGMAC), which are used to connect with external PHY devices by PCS. It includes an L2 switch function for bridging packets among the 6 Ethernet ports and the CPU port. The CPU port enables packet transfer between the Ethernet ports and the ARM cores in the SoC, using the Ethernet DMA. The PPE also includes packet processing offload capabilities for various networking functions such as route and bridge flows, VLANs, different tunnel protocols and VPN. The PPE switch is modeled according to the Ethernet switch schema, with additional properties defined for the switch node for interrupts, clocks, resets, interconnects and Ethernet DMA. The switch port node is extended with additional properties for clocks and resets. Reviewed-by: Rob Herring (Arm) Signed-off-by: Luo Jie Link: https://patch.msgid.link/20250818-qcom_ipq_ppe-v8-1-1d4ff641fce9@quicinc.com Signed-off-by: Paolo Abeni --- .../devicetree/bindings/net/qcom,ipq9574-ppe.yaml | 533 +++++++++++++++++++++ 1 file changed, 533 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml new file mode 100644 index 000000000000..753f370b7605 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml @@ -0,0 +1,533 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ packet process engine (PPE) + +maintainers: + - Luo Jie + - Lei Wei + - Suruchi Agarwal + - Pavithra R + +description: | + The Ethernet functionality in the PPE (Packet Process Engine) is comprised + of three components, the switch core, port wrapper and Ethernet DMA. + + The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and + two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet + port to host CPU communication using Ethernet DMA. The other is used + communicating to the EIP engine which is used for IPsec offload. On the + IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external + Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue + Management) and SCH (Scheduler) modules for supporting the packet processing. + + The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) + supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There + are 3 UNIPHY (PCS) instances supported on the IPQ9574. + + Ethernet DMA is used to transmit and receive packets between the six Ethernet + ports and ARM host CPU. + + The follow diagram shows the PPE hardware block along with its connectivity + to the external hardware blocks such clock hardware blocks (CMNPLL, GCC, + NSS clock controller) and Ethernet PCS/PHY blocks. For depicting the PHY + connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an + example. + + +---------+ + | 48 MHZ | + +----+----+ + |(clock) + v + +----+----+ + +------| CMN PLL | + | +----+----+ + | |(clock) + | v + | +----+----+ +----+----+ (clock) +----+----+ + | +---| NSSCC | | GCC |--------->| MDIO | + | | +----+----+ +----+----+ +----+----+ + | | |(clock & reset) |(clock) + | | v v + | | +----+---------------------+--+----------+----------+---------+ + | | | +-----+ |EDMA FIFO | | EIP FIFO| + | | | | SCH | +----------+ +---------+ + | | | +-----+ | | | + | | | +------+ +------+ +-------------------+ | + | | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | | + | | | +------+ +------+ +-------------------+ | + | | | | | + | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | + | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | | + | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ | + | | | | | | | | | | + | | +-----+---------+---------+---------+---------+---------+-----+ + | | | | | | | | + | | +---+---------+---------+---------+---+ +---+---+ +---+---+ + +--+---->| PCS0 | | PCS1 | | PCS2 | + |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+ + | | | | | | | + | +---+---------+---------+---------+---+ +---+---+ +---+---+ + +------->| QCA8075 PHY | | PHY4 | | PHY5 | + (clock) +-------------------------------------+ +-------+ +-------+ + +properties: + compatible: + enum: + - qcom,ipq9574-ppe + + reg: + maxItems: 1 + + clocks: + items: + - description: PPE core clock + - description: PPE APB (Advanced Peripheral Bus) clock + - description: PPE IPE (Ingress Process Engine) clock + - description: PPE BM, QM and scheduler clock + + clock-names: + items: + - const: ppe + - const: apb + - const: ipe + - const: btq + + resets: + maxItems: 1 + description: PPE reset, which is necessary before configuring PPE hardware + + interrupts: + maxItems: 1 + description: PPE switch miscellaneous interrupt + + interconnects: + items: + - description: Bus interconnect path leading to PPE switch core function + - description: Bus interconnect path leading to PPE register access + - description: Bus interconnect path leading to QoS generation + - description: Bus interconnect path leading to timeout reference + - description: Bus interconnect path leading to NSS NOC from memory NOC + - description: Bus interconnect path leading to memory NOC from NSS NOC + - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC + + interconnect-names: + items: + - const: ppe + - const: ppe_cfg + - const: qos_gen + - const: timeout_ref + - const: nssnoc_memnoc + - const: memnoc_nssnoc + - const: memnoc_nssnoc_1 + + ethernet-dma: + type: object + additionalProperties: false + description: + EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM + host CPU. There are 32 TX descriptor rings, 32 TX completion rings, + 24 RX descriptor rings and 8 RX fill rings supported. + + properties: + clocks: + items: + - description: EDMA system clock + - description: EDMA APB (Advanced Peripheral Bus) clock + + clock-names: + items: + - const: sys + - const: apb + + resets: + maxItems: 1 + description: EDMA reset + + interrupts: + minItems: 65 + maxItems: 65 + + interrupt-names: + minItems: 65 + maxItems: 65 + items: + oneOf: + - pattern: '^txcmpl_([1-2]?[0-9]|3[01])$' + - pattern: '^rxfill_[0-7]$' + - pattern: '^rxdesc_(1?[0-9]|2[0-3])$' + - const: misc + description: + Interrupts "txcmpl_[0-31]" are the Ethernet DMA TX completion ring interrupts. + Interrupts "rxfill_[0-7]" are the Ethernet DMA RX fill ring interrupts. + Interrupts "rxdesc_[0-23]" are the Ethernet DMA RX Descriptor ring interrupts. + Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt. + + required: + - clocks + - clock-names + - resets + - interrupts + - interrupt-names + + ethernet-ports: + patternProperties: + "^ethernet-port@[1-6]+$": + type: object + unevaluatedProperties: false + $ref: ethernet-switch-port.yaml# + + properties: + reg: + minimum: 1 + maximum: 6 + description: PPE Ethernet port ID + + clocks: + items: + - description: Port MAC clock + - description: Port RX clock + - description: Port TX clock + + clock-names: + items: + - const: mac + - const: rx + - const: tx + + resets: + items: + - description: Port MAC reset + - description: Port RX reset + - description: Port TX reset + + reset-names: + items: + - const: mac + - const: rx + - const: tx + + required: + - reg + - clocks + - clock-names + - resets + - reset-names + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - interconnects + - interconnect-names + - ethernet-dma + +allOf: + - $ref: ethernet-switch.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + ethernet-switch@3a000000 { + compatible = "qcom,ipq9574-ppe"; + reg = <0x3a000000 0xbef800>; + clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>; + clock-names = "ppe", + "apb", + "ipe", + "btq"; + resets = <&nsscc PPE_FULL_RESET>; + interrupts = ; + interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>, + <&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>, + <&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>, + <&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>, + <&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>, + <&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>, + <&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>; + interconnect-names = "ppe", + "ppe_cfg", + "qos_gen", + "timeout_ref", + "nssnoc_memnoc", + "memnoc_nssnoc", + "memnoc_nssnoc_1"; + + ethernet-dma { + clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>; + clock-names = "sys", + "apb"; + resets = <&nsscc EDMA_HW_RESET>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "txcmpl_0", + "txcmpl_1", + "txcmpl_2", + "txcmpl_3", + "txcmpl_4", + "txcmpl_5", + "txcmpl_6", + "txcmpl_7", + "txcmpl_8", + "txcmpl_9", + "txcmpl_10", + "txcmpl_11", + "txcmpl_12", + "txcmpl_13", + "txcmpl_14", + "txcmpl_15", + "txcmpl_16", + "txcmpl_17", + "txcmpl_18", + "txcmpl_19", + "txcmpl_20", + "txcmpl_21", + "txcmpl_22", + "txcmpl_23", + "txcmpl_24", + "txcmpl_25", + "txcmpl_26", + "txcmpl_27", + "txcmpl_28", + "txcmpl_29", + "txcmpl_30", + "txcmpl_31", + "rxfill_0", + "rxfill_1", + "rxfill_2", + "rxfill_3", + "rxfill_4", + "rxfill_5", + "rxfill_6", + "rxfill_7", + "rxdesc_0", + "rxdesc_1", + "rxdesc_2", + "rxdesc_3", + "rxdesc_4", + "rxdesc_5", + "rxdesc_6", + "rxdesc_7", + "rxdesc_8", + "rxdesc_9", + "rxdesc_10", + "rxdesc_11", + "rxdesc_12", + "rxdesc_13", + "rxdesc_14", + "rxdesc_15", + "rxdesc_16", + "rxdesc_17", + "rxdesc_18", + "rxdesc_19", + "rxdesc_20", + "rxdesc_21", + "rxdesc_22", + "rxdesc_23", + "misc"; + }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@1 { + reg = <1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + phy-handle = <&phy0>; + pcs-handle = <&pcs0_ch0>; + clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>, + <&nsscc NSS_CC_PORT1_RX_CLK>, + <&nsscc NSS_CC_PORT1_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT1_MAC_ARES>, + <&nsscc PORT1_RX_ARES>, + <&nsscc PORT1_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@2 { + reg = <2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + phy-handle = <&phy1>; + pcs-handle = <&pcs0_ch1>; + clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>, + <&nsscc NSS_CC_PORT2_RX_CLK>, + <&nsscc NSS_CC_PORT2_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT2_MAC_ARES>, + <&nsscc PORT2_RX_ARES>, + <&nsscc PORT2_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@3 { + reg = <3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + phy-handle = <&phy2>; + pcs-handle = <&pcs0_ch2>; + clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>, + <&nsscc NSS_CC_PORT3_RX_CLK>, + <&nsscc NSS_CC_PORT3_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT3_MAC_ARES>, + <&nsscc PORT3_RX_ARES>, + <&nsscc PORT3_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@4 { + reg = <4>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + phy-handle = <&phy3>; + pcs-handle = <&pcs0_ch3>; + clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>, + <&nsscc NSS_CC_PORT4_RX_CLK>, + <&nsscc NSS_CC_PORT4_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT4_MAC_ARES>, + <&nsscc PORT4_RX_ARES>, + <&nsscc PORT4_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@5 { + reg = <5>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + phy-handle = <&phy4>; + pcs-handle = <&pcs1_ch0>; + clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>, + <&nsscc NSS_CC_PORT5_RX_CLK>, + <&nsscc NSS_CC_PORT5_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT5_MAC_ARES>, + <&nsscc PORT5_RX_ARES>, + <&nsscc PORT5_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@6 { + reg = <6>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + phy-handle = <&phy5>; + pcs-handle = <&pcs2_ch0>; + clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>, + <&nsscc NSS_CC_PORT6_RX_CLK>, + <&nsscc NSS_CC_PORT6_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT6_MAC_ARES>, + <&nsscc PORT6_RX_ARES>, + <&nsscc PORT6_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + }; + }; -- cgit v1.2.3 From ee97f1fe67c0dff62549c6d8e8a7784431e65d46 Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Tue, 12 Aug 2025 10:46:39 +0200 Subject: dt-bindings: pinctrl: rp1: Describe groups for RP1 pin controller The DT binding for RP1 pin controller currently lacks the group definitions. Add groups enumeration to the schema. Signed-off-by: Andrea della Porta Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/20250812084639.13442-1-andrea.porta@suse.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/raspberrypi,rp1-gpio.yaml | 35 +++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml index eec9a9b58542..af6fbbd4feea 100644 --- a/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml @@ -72,10 +72,36 @@ $defs: pins: description: List of gpio pins affected by the properties specified in this - subnode. + subnode (either this or "groups" must be specified). items: pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$' + groups: + description: + List of groups affected by the properties specified in this + subnode (either this or "pins" must be specified). + items: + anyOf: + - pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$' + - enum: [ uart0, uart0_ctrl, uart1, uart1_ctrl, uart2, uart2_ctrl, + uart3, uart3_ctrl, uart4, uart4_ctrl, uart5_0, + uart5_0_ctrl, uart5_1, uart5_1_ctrl, uart5_2, + uart5_2_ctrl, uart5_3, + sd0, sd1, + i2s0, i2s0_dual, i2s0_quad, i2s1, i2s1_dual, i2s1_quad, + i2s2_0, i2s2_0_dual, i2s2_1, i2s2_1_dual, + i2c4_0, i2c4_1, i2c4_2, i2c4_3, i2c6_0, i2c6_1, i2c5_0, + i2c5_1, i2c5_2, i2c5_3, i2c0_0, i2c0_1, i2c1_0, i2c1_1, + i2c2_0, i2c2_1, i2c3_0, i2c3_1, i2c3_2, + dpi_16bit, dpi_16bit_cpadhi, dpi_16bit_pad666, + dpi_18bit, dpi_18bit_cpadhi, dpi_24bit, + spi0, spi0_quad, spi1, spi2, spi3, spi4, spi5, spi6_0, + spi6_1, spi7_0, spi7_1, spi8_0, spi8_1, + aaud_0, aaud_1, aaud_2, aaud_3, aaud_4, + vbus0_0, vbus0_1, vbus1, vbus2, vbus3, + mic_0, mic_1, mic_2, mic_3, + ir ] + function: enum: [ alt0, alt1, alt2, alt3, alt4, gpio, alt6, alt7, alt8, none, aaud, dcd0, dpi, dsi0_te_ext, dsi1_te_ext, dsr0, dtr0, gpclk0, @@ -103,6 +129,13 @@ $defs: drive-strength: enum: [ 2, 4, 8, 12 ] + required: + - function + + oneOf: + - required: [ groups ] + - required: [ pins ] + additionalProperties: false allOf: -- cgit v1.2.3 From d78e48ebe04e9566f8ecbf51471e80da3adbceeb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 21 Aug 2025 10:31:01 +0200 Subject: ASoC: dt-bindings: Minor whitespace cleanup in example The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250821083100.46340-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/fsl,easrc.yaml | 2 +- Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/fsl,easrc.yaml b/Documentation/devicetree/bindings/sound/fsl,easrc.yaml index 8f1108e7e14e..d5727f8bfb0b 100644 --- a/Documentation/devicetree/bindings/sound/fsl,easrc.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,easrc.yaml @@ -104,6 +104,6 @@ examples: "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx"; firmware-name = "imx/easrc/easrc-imx8mn.bin"; - fsl,asrc-rate = <8000>; + fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; }; diff --git a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml index 85799f83e65f..c9152bac7421 100644 --- a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml @@ -176,7 +176,7 @@ examples: <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; fsl,asrc-width = <16>; port { -- cgit v1.2.3 From a4d5f63d4384533101e0308fb2e9ac16bacc446c Mon Sep 17 00:00:00 2001 From: Nikunj Kela Date: Wed, 30 Jul 2025 14:30:00 -0700 Subject: dt-bindings: firmware: arm,scmi: Allow multiple instances Enable multiple SCMI instances by appending an instance-number suffix to the 'scmi' node name. The SCMI spec assumes a single SCMI platform, but in practice its responsibilities may be split across several SCMI platform/server instances. However, only one instance can serve as the system-wide (true) SCMI platform. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Cristian Marussi Signed-off-by: Nikunj Kela Signed-off-by: Deepti Jaggi Message-Id: <20250730-8255-scmi-v6-1-a7d8ba19aded@quicinc.com> Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index abbd62f1fed0..be817fd9cc34 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -27,7 +27,7 @@ anyOf: properties: $nodename: - const: scmi + pattern: '^scmi(-[0-9]+)?$' compatible: oneOf: -- cgit v1.2.3 From fb43a9e696e1ecba8781b5ea601db07802f50a9f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 18 Aug 2025 14:38:13 -0400 Subject: dt-bindings: input: convert lpc32xx-key.txt to yaml format Convert lpc32xx-key.txt to yaml format. Additional changes: - set maximum of key-row(column) to 4. - add ref to matrix-keymap.yaml. Reviewed-by: Vladimir Zapolskiy Signed-off-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250818183814.3603308-1-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov --- .../devicetree/bindings/input/lpc32xx-key.txt | 34 ------------ .../devicetree/bindings/input/nxp,lpc3220-key.yaml | 61 ++++++++++++++++++++++ 2 files changed, 61 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/input/lpc32xx-key.txt create mode 100644 Documentation/devicetree/bindings/input/nxp,lpc3220-key.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/lpc32xx-key.txt b/Documentation/devicetree/bindings/input/lpc32xx-key.txt deleted file mode 100644 index 2b075a080d30..000000000000 --- a/Documentation/devicetree/bindings/input/lpc32xx-key.txt +++ /dev/null @@ -1,34 +0,0 @@ -NXP LPC32xx Key Scan Interface - -This binding is based on the matrix-keymap binding with the following -changes: - -Required Properties: -- compatible: Should be "nxp,lpc3220-key" -- reg: Physical base address of the controller and length of memory mapped - region. -- interrupts: The interrupt number to the cpu. -- clocks: phandle to clock controller plus clock-specifier pair -- nxp,debounce-delay-ms: Debounce delay in ms -- nxp,scan-delay-ms: Repeated scan period in ms -- linux,keymap: the key-code to be reported when the key is pressed - and released, see also - Documentation/devicetree/bindings/input/matrix-keymap.txt - -Note: keypad,num-rows and keypad,num-columns are required, and must be equal -since LPC32xx only supports square matrices - -Example: - - key@40050000 { - compatible = "nxp,lpc3220-key"; - reg = <0x40050000 0x1000>; - clocks = <&clk LPC32XX_CLK_KEY>; - interrupt-parent = <&sic1>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - }; diff --git a/Documentation/devicetree/bindings/input/nxp,lpc3220-key.yaml b/Documentation/devicetree/bindings/input/nxp,lpc3220-key.yaml new file mode 100644 index 000000000000..9e0d977bdf5c --- /dev/null +++ b/Documentation/devicetree/bindings/input/nxp,lpc3220-key.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/nxp,lpc3220-key.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC32xx Key Scan Interface + +maintainers: + - Frank Li + +properties: + compatible: + const: nxp,lpc3220-key + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + nxp,debounce-delay-ms: + description: Debounce delay in ms + + nxp,scan-delay-ms: + description: Repeated scan period in ms + +required: + - compatible + - reg + - interrupts + - clocks + - nxp,debounce-delay-ms + - nxp,scan-delay-ms + - linux,keymap + +allOf: + - $ref: matrix-keymap.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + key@40050000 { + compatible = "nxp,lpc3220-key"; + reg = <0x40050000 0x1000>; + clocks = <&clk LPC32XX_CLK_KEY>; + interrupt-parent = <&sic1>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + keypad,num-rows = <1>; + keypad,num-columns = <1>; + nxp,debounce-delay-ms = <3>; + nxp,scan-delay-ms = <34>; + linux,keymap = <0x00000002>; + }; -- cgit v1.2.3 From 255ca339320d6295d678398b54973dddc792e2d2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 25 Jul 2025 08:24:50 +0200 Subject: dt-bindings: arm: fsl: add TQMLS1012AL TQMLS1012AL is a SOM using NXP LS1012A CPU. MBLS1012AL is a carrier reference design. [1] https://www.tq-group.com/en/products/tq-embedded/qoriq-layerscape/tqmls1012al Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index e21758546d13..02431ab80aa6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1539,6 +1539,12 @@ properties: - fsl,ls1012a-qds - const: fsl,ls1012a + - description: TQ Systems TQMLS12AL SoM on MBLS1012AL board + items: + - const: tq,ls1012a-tqmls1012al-mbls1012al + - const: tq,ls1012a-tqmls1012al + - const: fsl,ls1012a + - description: LS1021A based Boards items: - enum: -- cgit v1.2.3 From 6351806e5cd3290de6914327a7359e6f4a9e9a5f Mon Sep 17 00:00:00 2001 From: Pengfei Li Date: Wed, 6 Aug 2025 19:41:09 +0800 Subject: dt-bindings: arm: fsl: add i.MX91 11x11 evk board Add the board imx91-11x11-evk in the binding document. Signed-off-by: Pengfei Li Signed-off-by: Joy Zou Acked-by: Conor Dooley Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 02431ab80aa6..ebafa6ecbcb6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1387,6 +1387,12 @@ properties: - fsl,imx8ulp-evk # i.MX8ULP EVK Board - const: fsl,imx8ulp + - description: i.MX91 based Boards + items: + - enum: + - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - const: fsl,imx91 + - description: i.MX93 based Boards items: - enum: -- cgit v1.2.3 From 5a22df198bd3f515dfd9ff064a81f41567427dfc Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Thu, 21 Aug 2025 13:20:35 +0200 Subject: dt-bindings: mmc: sdhci-pxa: add state_uhs pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the pxav3 controller, increasing the drive strength of the data pins might be required to maintain stability on fast bus clocks (above 100 MHz). Add a state_uhs pinctrl to allow this. Reviewed-by: Rob Herring (Arm) Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20250821-pxav3-uhs-v4-1-bb588314f3c3@dujemihanovic.xyz Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/sdhci-pxa.yaml | 29 +++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml index e7c06032048a..fba1cc50fdf0 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -44,12 +44,27 @@ allOf: items: - const: default - const: state_cmd_gpio - pinctrl-0: - description: - Should contain default pinctrl. + pinctrl-1: description: Should switch CMD pin to GPIO mode as a high output. + - if: + properties: + compatible: + contains: + const: mrvl,pxav3-mmc + then: + properties: + pinctrl-names: + description: + Optional for increasing stability of the controller at fast bus clocks. + items: + - const: default + - const: state_uhs + + pinctrl-1: + description: + Should switch the drive strength of the data pins to high. properties: compatible: @@ -82,6 +97,14 @@ properties: - const: io - const: core + pinctrl-names: true + + pinctrl-0: + description: + Should contain default pinctrl. + + pinctrl-1: true + mrvl,clk-delay-cycles: description: Specify a number of cycles to delay for tuning. $ref: /schemas/types.yaml#/definitions/uint32 -- cgit v1.2.3 From 480a76c64f4f6a7f8d4aa2ac86cd2178687716b9 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 22 Aug 2025 14:39:49 +0800 Subject: dt-bindings: display: simple-bridge: Add ra620 compatible RA620 is a DP to HDMI bridge converter from RADXA, which first found be used on ROCK 5 ITX. This chip can be used without involving software. Signed-off-by: Andy Yan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822063959.692098-6-andyshrk@163.com Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml index 43cf4df9811a..421f99ca42d9 100644 --- a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +++ b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml @@ -28,6 +28,7 @@ properties: - enum: - adi,adv7123 - dumb-vga-dac + - radxa,ra620 - ti,opa362 - ti,ths8134 - ti,ths8135 -- cgit v1.2.3 From 8e484ff181b177ea2e86e537fd7a5c8f9d7532ad Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Jul 2025 18:48:57 +0200 Subject: dt-bindings: vendor-prefixes: Add prefix for Shenzhen Bestar Electronic Add the prefix for Bestar, named in full both on Panelook.com and their display datasheets as Shenzhen Bestar Electronic Technology Co., Ltd. which produces at least DSI displays and maybe more. Acked-by: "Rob Herring (Arm)" Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250707164906.1445288-5-heiko@sntech.de --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..abc43c43813a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -221,6 +221,8 @@ patternProperties: description: BeagleBoard.org Foundation "^belling,.*": description: Shanghai Belling Co., Ltd. + "^bestar,.*": + description: Shenzhen Bestar Electronic Technology Co., Ltd. "^bhf,.*": description: Beckhoff Automation GmbH & Co. KG "^bigtreetech,.*": -- cgit v1.2.3 From 157ba8c6742931a617a34555c27dd10b36385cf3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Jul 2025 18:48:58 +0200 Subject: dt-bindings: display: ili9881c: Add Bestar BSD1218-A101KL68 LCD panel Document the compatible value for Bestar BSD1218-A101KL68 LCD panels that are based around the ili9881c controller. Acked-by: "Rob Herring (Arm)" Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250707164906.1445288-6-heiko@sntech.de --- Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml index a51af61d4846..434cc6af9c95 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml @@ -18,6 +18,7 @@ properties: - enum: - ampire,am8001280g - bananapi,lhr050h41 + - bestar,bsd1218-a101kl68 - feixin,k101-im2byl02 - raspberrypi,dsi-7inch - startek,kd050hdfia020 -- cgit v1.2.3 From f05530bdaf42aa0e6bb4cde76ba6a081cf473d44 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Jul 2025 18:49:01 +0200 Subject: dt-bindings: display: rockchip: Add rk3576 to RK3588 DW DSI2 controller schema The rk3576 controller is based on the same newer Synopsis IP as the one found in the rk3588. Its external setting bits in the GRF are different though, so it needs its own distinct compatible. Acked-by: "Rob Herring (Arm)" Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250707164906.1445288-9-heiko@sntech.de --- .../devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml index 53384e47b507..75cd1c13fa52 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: enum: + - rockchip,rk3576-mipi-dsi2 - rockchip,rk3588-mipi-dsi2 reg: -- cgit v1.2.3 From 0e3f3d7c7ae3dec5ff52325915e3efcbce652a82 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Jul 2025 18:49:00 +0200 Subject: dt-bindings: soc: rockchip: add rk3576 mipi dcphy syscon RK3576 CSI and DSI support requires the GRF for its DC-PHY. The "general register files" provide additional setting-bits outside the regular ip-block reg-space. Acked-by: "Rob Herring (Arm)" Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250707164906.1445288-8-heiko@sntech.de --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 1ab0b092e2a5..6a94c271a6b1 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3568-usb2phy-grf - rockchip,rk3576-bigcore-grf - rockchip,rk3576-cci-grf + - rockchip,rk3576-dcphy-grf - rockchip,rk3576-gpu-grf - rockchip,rk3576-hdptxphy-grf - rockchip,rk3576-litcore-grf -- cgit v1.2.3 From 32299eb03414cbb475ce3068b64db6d306df5b88 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 21 Aug 2025 23:56:38 +0800 Subject: dt-bindings: mailbox: apple,mailbox: Add ASC mailboxes on Apple A11 and T2 Add bindings for ASC mailboxes as found on Apple A11 and T2 SoCs. These mailboxes are used for coprocessors including Secure Enclave Processor (SEP), the NVMe coprocessor and the system management controller. Acked-by: Rob Herring (Arm) Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250821-t8015-nvme-v3-1-14a4178adf68@gmail.com Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 474c1a0f99f3..bdf58f03b848 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -33,6 +33,13 @@ properties: - apple,t6000-asc-mailbox - const: apple,asc-mailbox-v4 + - description: + An older ASC mailbox interface found on T2 and A11 that is also + used for the NVMe coprocessor and the system management + controller. + items: + - const: apple,t8015-asc-mailbox + - description: M3 mailboxes are an older variant with a slightly different MMIO interface still found on the M1. It is used for the Thunderbolt -- cgit v1.2.3 From 7d11b8c260ea68ce8f420ad467b04b21ea34b011 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 Aug 2025 18:00:06 +0800 Subject: dt-bindings: vendor-prefixes: Add HINLINK Add vendor prefix for HINLINK, which is an SBC manufacturer. Link: https://www.hinlink.cn/ Signed-off-by: Chukun Pan Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250818100009.170202-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..1305da271a68 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -646,6 +646,8 @@ patternProperties: description: HiDeep Inc. "^himax,.*": description: Himax Technologies, Inc. + "^hinlink,.*": + description: Shenzhen HINLINK Technology Co., Ltd. "^hirschmann,.*": description: Hirschmann Automation and Control GmbH "^hisi,.*": -- cgit v1.2.3 From 4bef07b79ab1ef7d963eaa2c37948030e418d538 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 Aug 2025 18:00:07 +0800 Subject: dt-bindings: arm: rockchip: Add HINLINK H66K / H68K The HINLINK H66K/H68K are 2.5GbE SBC based on the RK3568 SoC. Add devicetree binding documentation for them. Signed-off-by: Chukun Pan Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250818100009.170202-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 28db6bd6aa5b..870c318fc8d4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -683,6 +683,13 @@ properties: - const: hardkernel,odroid-m2 - const: rockchip,rk3588s + - description: HINLINK H66K / H68K + items: + - enum: + - hinlink,h66k + - hinlink,h68k + - const: rockchip,rk3568 + - description: Hugsun X99 TV Box items: - const: hugsun,x99 -- cgit v1.2.3 From 3f33d1530c2c9576b57ecd220bfa7e527184a80b Mon Sep 17 00:00:00 2001 From: Salih Erim Date: Wed, 20 Aug 2025 11:05:19 +0100 Subject: MAINTAINERS: Update xilinx-ams driver maintainers Anand left AMD/Xilinx some time ago. Salih and Connall are new maintainers of xilinx-ams driver. Signed-off-by: Salih Erim Acked-by: Rob Herring (Arm) Acked-by: Michal Simek Acked-by: O'Griofa, Conall Link: https://patch.msgid.link/20250820100519.2272509-1-salih.erim@amd.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml | 3 ++- MAINTAINERS | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml index a403392fb263..3ae1a0bab38f 100644 --- a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Ultrascale AMS controller maintainers: - - Anand Ashok Dumbre + - Salih Erim + - Conall O'Griofa description: | The AMS (Analog Monitoring System) includes an ADC as well as on-chip sensors diff --git a/MAINTAINERS b/MAINTAINERS index 76cba707a2c9..af1c8d2bfb3d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27550,7 +27550,8 @@ F: include/uapi/linux/dqblk_xfs.h F: include/uapi/linux/fsmap.h XILINX AMS DRIVER -M: Anand Ashok Dumbre +M: Salih Erim +M: Conall O'Griofa L: linux-iio@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml -- cgit v1.2.3 From d6d389646a35daae9fc1f21fe9221dcb7b3cc41f Mon Sep 17 00:00:00 2001 From: Ben Collins Date: Fri, 22 Aug 2025 09:23:50 -0400 Subject: dt-bindings: iio: mcp9600: Set default 3 for thermocouple-type As is already documented in this file, Type-K is the default, so make that explicit in the dt-bindings. Signed-off-by: Ben Collins Reviewed-by: Krzysztof Kozlowski Reviewed-by: David Lechner Link: https://patch.msgid.link/20250822-upstream-changes-v8-1-40bb1739e3e2@watter.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml b/Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml index d2cafa38a544..57b387a1accc 100644 --- a/Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml @@ -37,6 +37,7 @@ properties: thermocouple-type: $ref: /schemas/types.yaml#/definitions/uint32 + default: 3 description: Type of thermocouple (THERMOCOUPLE_TYPE_K if omitted). Use defines in dt-bindings/iio/temperature/thermocouple.h. -- cgit v1.2.3 From 894751730a0d1674e43167b187e6605371667c8b Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Thu, 21 Aug 2025 10:19:07 +0530 Subject: dt-bindings: pinctrl: qcom,sc7280-lpass-lpi-pinctrl: Document the clock property Document the clock property in sc7280 LPASS LPI pinctrl node. Clock settings required for Audioreach solution. The existing SC7280 platform only supports non-ADSP audio solutions. To enable audio functionality on ADSP with the AudioReach solution. additional core and audio hardware clocks must be configured. Without these clocks, the ADSP will crash. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20250821044914.710044-3-quic_pkumpatl@quicinc.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml index 08801cc4e476..bc7b8dda8837 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -20,6 +20,16 @@ properties: reg: maxItems: 2 + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + patternProperties: "-state$": oneOf: @@ -70,10 +80,16 @@ unevaluatedProperties: false examples: - | + #include lpass_tlmm: pinctrl@33c0000 { compatible = "qcom,sc7280-lpass-lpi-pinctrl"; reg = <0x33c0000 0x20000>, <0x3550000 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 15>; -- cgit v1.2.3 From f6a52403fd2c1b581d4f78d79def57b803f29635 Mon Sep 17 00:00:00 2001 From: Ben Collins Date: Fri, 22 Aug 2025 09:23:51 -0400 Subject: dt-bindings: iio: mcp9600: Add microchip,mcp9601 and add constraints Add microchip,mcp9601 compatible in addition to the original microchip,mcp9600 to designate support between these two chips. The current dt-binding has open-circuit and short-circuit as interrupt names, but these are only supported in mcp9601. The OC and SC detection requires that mcp9601 VSENSE be wired up, which not only enables the OC SC interrupts, but also the OC and SC status register bits. Add a microchip,vsense boolean to show the chip is wired for this support. Add constraints so this feature only applies if the mcp9601 compatible is selected. Signed-off-by: Ben Collins Reviewed-by: Krzysztof Kozlowski Reviewed-by: David Lechner Link: https://patch.msgid.link/20250822-upstream-changes-v8-2-40bb1739e3e2@watter.com Signed-off-by: Jonathan Cameron --- .../iio/temperature/microchip,mcp9600.yaml | 55 ++++++++++++++++++++-- 1 file changed, 52 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml b/Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml index 57b387a1accc..effe3bee495d 100644 --- a/Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/microchip,mcp9600.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/temperature/microchip,mcp9600.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip MCP9600 thermocouple EMF converter +title: Microchip MCP9600 and similar thermocouple EMF converters maintainers: - Andrew Hepp @@ -14,7 +14,11 @@ description: properties: compatible: - const: microchip,mcp9600 + oneOf: + - const: microchip,mcp9600 + - items: + - const: microchip,mcp9601 + - const: microchip,mcp9600 reg: maxItems: 1 @@ -43,8 +47,37 @@ properties: Use defines in dt-bindings/iio/temperature/thermocouple.h. Supported types are B, E, J, K, N, R, S, T. + microchip,vsense: + type: boolean + description: + This flag indicates that the chip has been wired with VSENSE to + enable open and short circuit detect. + vdd-supply: true +allOf: + - if: + properties: + compatible: + not: + contains: + const: microchip,mcp9601 + then: + properties: + interrupts: + minItems: 1 + maxItems: 4 + interrupt-names: + minItems: 1 + maxItems: 4 + items: + enum: + - alert1 + - alert2 + - alert3 + - alert4 + microchip,vsense: false + required: - compatible - reg @@ -64,8 +97,24 @@ examples: reg = <0x60>; interrupt-parent = <&gpio>; interrupts = <25 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "open-circuit"; + interrupt-names = "alert1"; thermocouple-type = ; vdd-supply = <&vdd>; }; }; + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@62 { + compatible = "microchip,mcp9601", "microchip,mcp9600"; + reg = <0x62>; + interrupt-parent = <&gpio>; + interrupts = <22 IRQ_TYPE_EDGE_RISING>, <23 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "open-circuit", "short-circuit"; + vdd-supply = <&vdd>; + microchip,vsense; + }; + }; -- cgit v1.2.3 From 21feb435be9b19a0be8b2c44a9efb7a5296c9a66 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 18 Aug 2025 16:00:13 -0400 Subject: dt-bindings: iio: adc: max1238: Add #io-channel-cells property Add #io-channel-cells property with a constant value of 1 because it is multi-channel ADC. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-iot.dtb: adc@35 (maxim,max1239): '#io-channel-cells' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/iio/adc/maxim,max1238.yaml# Signed-off-by: Frank Li Acked-by: Conor Dooley Link: https://patch.msgid.link/20250818200014.3700738-1-Frank.Li@nxp.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml index 60d7b34e3286..ae3c89393f1a 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml @@ -53,6 +53,9 @@ properties: reg: maxItems: 1 + "#io-channel-cells": + const: 1 + vcc-supply: true vref-supply: description: Optional external reference. If not supplied, internal -- cgit v1.2.3 From 5c2bf13c9ae951d63c97b367f4e7989d4913dcf3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 21 Aug 2025 10:31:51 +0200 Subject: dt-bindings: iio: adi,ltc2664: Minor whitespace cleanup in example The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250821083150.46554-2-krzysztof.kozlowski@linaro.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml index 1aece3392b77..4688eccfeb89 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ltc2664.yaml @@ -174,7 +174,7 @@ examples: channel@1 { reg = <1>; - output-range-microvolt= <0 10000000>; + output-range-microvolt = <0 10000000>; }; }; }; -- cgit v1.2.3 From 545908a9fb9c01e1bd7afe040f5623f561d50ea0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 17:46:26 +0200 Subject: dt-bindings: gpio-mmio: Support hogs We use hogs on some MMIO GPIO controllers so make sure the bindings support this using a pattern property. Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20250822-ixp4xx-eb-mmio-gpio-v2-1-bd2edd4a9c74@linaro.org Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/gpio/gpio-mmio.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml index 87e986386f32..ca32317dff85 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -89,6 +89,12 @@ properties: description: If this property is present, the controller cannot drive the GPIO lines. +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + required: - compatible - reg -- cgit v1.2.3 From 1f3c076063f03999c351c0725adf744ef5660733 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 17:46:27 +0200 Subject: dt-bindings: gpio-mmio: Add MMIO for IXP4xx expansion bus This expansion is a simple MMIO-mapped GPIO device but the bus has a number of additional properties that we need to bring in using a reference to the bus child node schema. Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20250822-ixp4xx-eb-mmio-gpio-v2-2-bd2edd4a9c74@linaro.org Signed-off-by: Bartosz Golaszewski --- .../devicetree/bindings/gpio/gpio-mmio.yaml | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml index ca32317dff85..b4d55bf6a285 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -22,6 +22,7 @@ properties: - brcm,bcm6345-gpio - ni,169445-nand-gpio - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller + - intel,ixp4xx-expansion-bus-mmio-gpio big-endian: true @@ -89,6 +90,14 @@ properties: description: If this property is present, the controller cannot drive the GPIO lines. +if: + properties: + compatible: + contains: + const: intel,ixp4xx-expansion-bus-mmio-gpio +then: + $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml# + patternProperties: "^.+-hog(-[0-9]+)?$": type: object @@ -102,7 +111,7 @@ required: - '#gpio-cells' - gpio-controller -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -132,3 +141,22 @@ examples: gpio-controller; #gpio-cells = <2>; }; + + bus@c4000000 { + compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; + reg = <0xc4000000 0x30>; + native-endian; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x01000000>; + dma-ranges = <0 0x0 0x50000000 0x01000000>; + gpio@1,0 { + compatible = "intel,ixp4xx-expansion-bus-mmio-gpio"; + gpio-controller; + #gpio-cells = <2>; + big-endian; + reg = <1 0x00000000 0x2>; + reg-names = "dat"; + intel,ixp4xx-eb-write-enable = <1>; + }; + }; -- cgit v1.2.3 From bc2741b032f8bbf2e46085ba9c674c094f396253 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 21 Aug 2025 10:30:39 +0200 Subject: dt-bindings: net: litex,liteeth: Correct example indentation DTS example in the bindings should be indented with 2- or 4-spaces, so correct a mixture of different styles to keep consistent 4-spaces. Signed-off-by: Krzysztof Kozlowski Acked-by: Gabriel Somlo Link: https://patch.msgid.link/20250821083038.46274-3-krzysztof.kozlowski@linaro.org Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/litex,liteeth.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml index ebf4e360f8dd..bbb71556ec9e 100644 --- a/Documentation/devicetree/bindings/net/litex,liteeth.yaml +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml @@ -86,12 +86,12 @@ examples: phy-handle = <ð_phy>; mdio { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - eth_phy: ethernet-phy@0 { - reg = <0>; - }; + eth_phy: ethernet-phy@0 { + reg = <0>; + }; }; }; ... -- cgit v1.2.3 From 7f052126ff38f497cc8721f0b0e99aa201cd5a7f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 21 Aug 2025 10:30:40 +0200 Subject: dt-bindings: net: Drop vim style annotation Bindings files should not carry markings of editor setup, so drop vim style annotation. No functional impact. Signed-off-by: Krzysztof Kozlowski Acked-by: Gabriel Somlo Link: https://patch.msgid.link/20250821083038.46274-4-krzysztof.kozlowski@linaro.org Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/litex,liteeth.yaml | 2 -- Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml | 1 - 2 files changed, 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml index bbb71556ec9e..200b198b0d9b 100644 --- a/Documentation/devicetree/bindings/net/litex,liteeth.yaml +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml @@ -95,5 +95,3 @@ examples: }; }; ... - -# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml : diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index a73fc5036905..082982c59a55 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -245,4 +245,3 @@ examples: }; ... -# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml : -- cgit v1.2.3 From 66edbb1e32eede16b261a90014451d67119fc875 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 20 Aug 2025 12:49:45 -0400 Subject: dt-bindings: gpio: Move fsl,mxs-pinctrl.txt into gpio-mxs.yaml Move mxs-pinctrl part into gpio-mxs.yaml and add pinctrl examples to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/mxs/imx28-xea.dtb: pinctrl@80018000 (fsl,imx28-pinctrl): 'auart0-2pins@0', 'auart0@0', ... 'usb1@1' do not match any of the regexes: 'gpio@[0-9]+$', 'pinctrl-[0-9]+' Signed-off-by: Frank Li Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250820164946.3782702-1-Frank.Li@nxp.com Signed-off-by: Bartosz Golaszewski --- .../devicetree/bindings/gpio/gpio-mxs.yaml | 80 ++++++++++++- .../bindings/pinctrl/fsl,mxs-pinctrl.txt | 127 --------------------- 2 files changed, 75 insertions(+), 132 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml index b58e08c8ecd8..aaf97124803f 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml @@ -18,9 +18,13 @@ description: | properties: compatible: - enum: - - fsl,imx23-pinctrl - - fsl,imx28-pinctrl + items: + - enum: + - fsl,imx23-pinctrl + - fsl,imx28-pinctrl + # Over 10 years old devices, driver use simple-bus to probe child gpio + # Devices. Keep it as it to be compatible existed dts files. + - const: simple-bus '#address-cells': const: 1 @@ -31,7 +35,65 @@ properties: maxItems: 1 patternProperties: - "gpio@[0-9]+$": + "^(?!gpio@)[^@]+@[0-9]+$": + type: object + properties: + fsl,pinmux-ids: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An integer array. Each integer in the array specify a pin + with given mux function, with bank, pin and mux packed as below. + + [15..12] : bank number + [11..4] : pin number + [3..0] : mux selection + + This integer with mux selection packed is used as an entity by both group + and config nodes to identify a pin. The mux selection in the integer takes + effects only on group node, and will get ignored by driver with config node, + since config node is only meant to set up pin configurations. + + Valid values for these integers are listed below. + + reg: + items: + - description: | + pin group index. NOTE: it is supposed wrong use reg property + here. But it is over 10 years devices. Just keep it as it. + + fsl,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + 0: MXS_DRIVE_4mA + 1: MXS_DRIVE_8mA + 2: MXS_DRIVE_12mA + 3: MXS_DRIVE_16mA + + fsl,voltage: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + 0: MXS_VOLTAGE_LOW - 1.8 V + 1: MXS_VOLTAGE_HIGH - 3.3 V + + fsl,pull-up: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + 0: MXS_PULL_DISABLE - Disable the internal pull-up + 1: MXS_PULL_ENABLE - Enable the internal pull-up + + Note that when enabling the pull-up, the internal pad keeper gets disabled. + Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up + will only disable the internal pad keeper. + + required: + - fsl,pinmux-ids + + additionalProperties: false + + "^gpio@[0-9]+$": type: object properties: compatible: @@ -80,7 +142,7 @@ examples: pinctrl@80018000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx28-pinctrl"; + compatible = "fsl,imx28-pinctrl", "simple-bus"; reg = <0x80018000 0x2000>; gpio@0 { @@ -132,4 +194,12 @@ examples: interrupt-controller; #interrupt-cells = <2>; }; + + lcdif-apx4@5 { + reg = <5>; + fsl,pinmux-ids = <0x1181 0x1191>; + fsl,drive-strength = <0>; + fsl,voltage = <0>; + fsl,pull-up = <0>; + }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt deleted file mode 100644 index 1e70a8aff260..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ /dev/null @@ -1,127 +0,0 @@ -* Freescale MXS Pin Controller - -The pins controlled by mxs pin controller are organized in banks, each bank -has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th -function is GPIO. The configuration on the pins includes drive strength, -voltage and pull-up. - -Required properties: -- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" -- reg: Should contain the register physical address and length for the - pin controller. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -The node of mxs pin controller acts as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for -a group of pins, and only affects those parameters that are explicitly listed. -In other words, a subnode that describes a drive strength parameter implies no -information about pull-up. For this reason, even seemingly boolean values are -actually tristates in this binding: unspecified, off, or on. Unspecified is -represented as an absent property, and off/on are represented as integer -values 0 and 1. - -Those subnodes under mxs pin controller node will fall into two categories. -One is to set up a group of pins for a function, both mux selection and pin -configurations, and it's called group node in the binding document. The other -one is to adjust the pin configuration for some particular pins that need a -different configuration than what is defined in group node. The binding -document calls this type of node config node. - -On mxs, there is no hardware pin group. The pin group in this binding only -means a group of pins put together for particular peripheral to work in -particular function, like SSP0 functioning as mmc0-8bit. That said, the -group node should include all the pins needed for one function rather than -having these pins defined in several group nodes. It also means each of -"pinctrl-*" phandle in client device node should only have one group node -pointed in there, while the phandle can have multiple config node referenced -there to adjust configurations for some pins in the group. - -Required subnode-properties: -- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin - with given mux function, with bank, pin and mux packed as below. - - [15..12] : bank number - [11..4] : pin number - [3..0] : mux selection - - This integer with mux selection packed is used as an entity by both group - and config nodes to identify a pin. The mux selection in the integer takes - effects only on group node, and will get ignored by driver with config node, - since config node is only meant to set up pin configurations. - - Valid values for these integers are listed below. - -- reg: Should be the index of the group nodes for same function. This property - is required only for group nodes, and should not be present in any config - nodes. - -Optional subnode-properties: -- fsl,drive-strength: Integer. - 0: MXS_DRIVE_4mA - 1: MXS_DRIVE_8mA - 2: MXS_DRIVE_12mA - 3: MXS_DRIVE_16mA -- fsl,voltage: Integer. - 0: MXS_VOLTAGE_LOW - 1.8 V - 1: MXS_VOLTAGE_HIGH - 3.3 V -- fsl,pull-up: Integer. - 0: MXS_PULL_DISABLE - Disable the internal pull-up - 1: MXS_PULL_ENABLE - Enable the internal pull-up - -Note that when enabling the pull-up, the internal pad keeper gets disabled. -Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up -will only disable the internal pad keeper. - -Examples: - -pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-pinctrl"; - reg = <0x80018000 2000>; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_DATA4__SSP0_D4 - MX28_PAD_SSP0_DATA5__SSP0_D5 - MX28_PAD_SSP0_DATA6__SSP0_D6 - MX28_PAD_SSP0_DATA7__SSP0_D7 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc_cd_cfg: mmc-cd-cfg { - fsl,pinmux-ids = ; - fsl,pull-up = ; - }; - - mmc_sck_cfg: mmc-sck-cfg { - fsl,pinmux-ids = ; - fsl,drive-strength = ; - fsl,pull-up = ; - }; -}; - -In this example, group node mmc0-8bit defines a group of pins for mxs SSP0 -to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations -applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are -adjusting the configuration for pins card-detection and clock from what group -node mmc0-8bit defines. Only the configuration properties to be adjusted need -to be listed in the config nodes. - -Valid values for i.MX28/i.MX23 pinmux-id are defined in -arch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h. -The definitions for the padconfig properties can be found in -arch/arm/boot/dts/mxs-pinfunc.h. -- cgit v1.2.3 From 604642fc148b5d98fbe5f55e4c2688f9ee0b5868 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 21 Aug 2025 10:32:14 +0200 Subject: dt-bindings: gpio: Minor whitespace cleanup in example The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Acked-by: Yixun Lan Link: https://lore.kernel.org/r/20250821083213.46642-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/gpio/maxim,max31910.yaml | 6 +++--- Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/maxim,max31910.yaml b/Documentation/devicetree/bindings/gpio/maxim,max31910.yaml index 82a190a715f9..4d200f9dffd5 100644 --- a/Documentation/devicetree/bindings/gpio/maxim,max31910.yaml +++ b/Documentation/devicetree/bindings/gpio/maxim,max31910.yaml @@ -95,9 +95,9 @@ examples: #gpio-cells = <2>; maxim,modesel-gpios = <&gpio2 23>; - maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - maxim,db0-gpios = <&gpio2 25>; - maxim,db1-gpios = <&gpio2 26>; + maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + maxim,db0-gpios = <&gpio2 25>; + maxim,db1-gpios = <&gpio2 26>; spi-max-frequency = <25000000>; }; diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml index ec0232e72c71..83e0b2d14c9f 100644 --- a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml @@ -80,7 +80,7 @@ examples: gpio@d4019000 { compatible = "spacemit,k1-gpio"; reg = <0xd4019000 0x800>; - clocks =<&ccu 9>, <&ccu 61>; + clocks = <&ccu 9>, <&ccu 61>; clock-names = "core", "bus"; gpio-controller; #gpio-cells = <3>; -- cgit v1.2.3 From 4edc575c5582550d0905f39c5e27f1f1f925fffa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 18 Aug 2025 16:21:39 +0200 Subject: dt-bindings: PCI: Correct example indentation DTS example in the bindings should be indented with 2- or 4-spaces, so correct a mixture of different styles to keep consistent 4-spaces. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250818142138.129327-2-krzysztof.kozlowski@linaro.org --- .../bindings/pci/amd,versal2-mdb-host.yaml | 2 +- .../devicetree/bindings/pci/qcom,pcie-sa8255p.yaml | 80 +++++++++++----------- 2 files changed, 41 insertions(+), 41 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml index 43dc2585c237..80b28c4212df 100644 --- a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml @@ -116,6 +116,6 @@ examples: #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; - }; + }; }; }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml index ef705a02fcd9..bdddd4f499d1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml @@ -77,46 +77,46 @@ examples: #size-cells = <2>; pci@1c00000 { - compatible = "qcom,pcie-sa8255p"; - reg = <0x4 0x00000000 0 0x10000000>; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>, - <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>; - bus-range = <0x00 0xff>; - dma-coherent; - linux,pci-domain = <0>; - power-domains = <&scmi5_pd 0>; - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; - interrupt-parent = <&intc>; - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; + compatible = "qcom,pcie-sa8255p"; + reg = <0x4 0x00000000 0 0x10000000>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>, + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + dma-coherent; + linux,pci-domain = <0>; + power-domains = <&scmi5_pd 0>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; }; }; }; -- cgit v1.2.3 From f315e030a202012a551eb648fa10cd90bd925b20 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Tue, 26 Aug 2025 13:54:27 +0200 Subject: dt-bindings: panel: lvds: Append ampire,amp19201200b5tzqw-t03 in panel-lvds List Ampire AMP19201200B5TZQW-T03 in the LVDS panel enumeration. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250826-drm-misc-next-v1-1-980d0a0592b9@foss.st.com Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml index fcb5834f799a..f8f95e772778 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml @@ -41,6 +41,8 @@ properties: - enum: # Admatec 9904379 10.1" 1024x600 LVDS panel - admatec,9904379 + # Ampire AMP19201200B5TZQW-T03 10.1" WUXGA (1920x1200) color TFT LCD panel + - ampire,amp19201200b5tzqw-t03 - auo,b101ew05 # AUO G084SN05 V9 8.4" 800x600 LVDS panel - auo,g084sn05 -- cgit v1.2.3 From 5ffa3d2f43a487f60e9f6f692aa8e22251446755 Mon Sep 17 00:00:00 2001 From: Christian Bruel Date: Wed, 20 Aug 2025 09:54:03 +0200 Subject: dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings Document the bindings for STM32MP25 PCIe Controller configured in root complex mode with one root port. Supports 4 INTx and MSI interrupts from the ARM GICv2m controller. STM32 PCIe may be in a power domain which is the case for the STM32MP25 based boards. Supports WAKE# from wake-gpios Signed-off-by: Christian Bruel Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20250820075411.1178729-4-christian.bruel@foss.st.com --- .../bindings/pci/st,stm32-pcie-common.yaml | 33 ++++++ .../bindings/pci/st,stm32-pcie-host.yaml | 112 +++++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml new file mode 100644 index 000000000000..5adbff259204 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP25 PCIe RC/EP controller + +maintainers: + - Christian Bruel + +description: + STM32MP25 PCIe RC/EP common properties + +properties: + clocks: + maxItems: 1 + description: PCIe system clock + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + access-controllers: + maxItems: 1 + +required: + - clocks + - resets + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml new file mode 100644 index 000000000000..443bfe2cdc98 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 PCIe Root Complex + +maintainers: + - Christian Bruel + +description: + PCIe root complex controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-rc + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: config + + msi-parent: + maxItems: 1 + +patternProperties: + '^pcie@[0-2],0$': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO used as WAKE# input signal + maxItems: 1 + + required: + - phys + - ranges + + unevaluatedProperties: false + +required: + - interrupt-map + - interrupt-map-mask + - ranges + - dma-ranges + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + pcie@48400000 { + compatible = "st,stm32mp25-pcie-rc"; + device_type = "pci"; + reg = <0x48400000 0x400000>, + <0x10000000 0x10000>; + reg-names = "dbi", "config"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; + dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; + clocks = <&rcc CK_BUS_PCIE>; + resets = <&rcc PCIE_R>; + msi-parent = <&v2m0>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&combophy PHY_TYPE_PCIE>; + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; -- cgit v1.2.3 From 6dd0ca9f2dfaab1bd15895bab16e5496632e53b6 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Tue, 26 Aug 2025 16:32:53 +0530 Subject: dt-bindings: PCI: qcom,pcie-sm8550: Add SM8750 compatible PCIe controller present in SM8750 SoC is backwards compatible with the controller present in SM8550 SoC. Hence, add the compatible with SM8550 fallback. Signed-off-by: Krishna Chaitanya Chundru [mani: reworded description] Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250826-pakala-v3-1-721627bd5bb0@oss.qualcomm.com --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index dbce671ba011..38b561e23c1f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -22,6 +22,7 @@ properties: - enum: - qcom,sar2130p-pcie - qcom,pcie-sm8650 + - qcom,pcie-sm8750 - const: qcom,pcie-sm8550 reg: -- cgit v1.2.3 From 40fb9751ccc6e2ad450a2b938d7c8583a34d4a56 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 26 Aug 2025 11:17:36 -0300 Subject: dt-bindings: nfc: ti,trf7970a: Restrict the ti,rx-gain-reduction-db values Instead of stating the supported values for the ti,rx-gain-reduction-db property in free text format, add an enum entry that can help validating the devicetree files. Signed-off-by: Fabio Estevam Acked-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250826141736.712827-1-festevam@gmail.com Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml b/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml index 783a85b84893..7e96a625f0cf 100644 --- a/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml +++ b/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml @@ -58,7 +58,8 @@ properties: ti,rx-gain-reduction-db: description: | Specify an RX gain reduction to reduce antenna sensitivity with 5dB per - increment, with a maximum of 15dB. Supported values: [0, 5, 10, 15]. + increment, with a maximum of 15dB. + enum: [ 0, 5, 10, 15] required: - compatible -- cgit v1.2.3 From 1e50201d3911507744adf5dafd6e25dbffee3692 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 21 Aug 2025 10:32:40 +0200 Subject: dt-bindings: ata: highbank: Minor whitespace cleanup in example The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Acked-by: Andre Przywara Signed-off-by: Damien Le Moal --- Documentation/devicetree/bindings/ata/sata_highbank.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.yaml b/Documentation/devicetree/bindings/ata/sata_highbank.yaml index f23f26a8f21c..48bdca0f5577 100644 --- a/Documentation/devicetree/bindings/ata/sata_highbank.yaml +++ b/Documentation/devicetree/bindings/ata/sata_highbank.yaml @@ -85,7 +85,7 @@ examples: dma-coherent; calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>, <&combophy0 2>, <&combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>; + calxeda,sgpio-gpio = <&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>; calxeda,led-order = <4 0 1 2 3>; calxeda,tx-atten = <0xff 22 0xff 0xff 23>; calxeda,pre-clocks = <10>; -- cgit v1.2.3 From 692173de3032b22792d21070238a986163fc29ec Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 23 Aug 2025 16:50:21 -0300 Subject: dt-bindings: ata: imx: Document 'target-supply' The 'target-supply' property is used by some i.MX devicetree files. Document it to fix the following dt-schema warning: 'target-supply' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Fabio Estevam Acked-by: Conor Dooley Signed-off-by: Damien Le Moal --- Documentation/devicetree/bindings/ata/imx-sata.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ata/imx-sata.yaml b/Documentation/devicetree/bindings/ata/imx-sata.yaml index f4eb3550a096..31c43374763a 100644 --- a/Documentation/devicetree/bindings/ata/imx-sata.yaml +++ b/Documentation/devicetree/bindings/ata/imx-sata.yaml @@ -80,6 +80,9 @@ properties: power-domains: maxItems: 1 + target-supply: + description: Power regulator for the SATA target device. + required: - compatible - reg -- cgit v1.2.3 From d939047d31ff25a49a39667417c2a996caa826f5 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 27 Aug 2025 16:44:01 -0400 Subject: dt-bindings: Remove outdated cpufreq-dt.txt The information present in this file is outdated and doesn't serve any purpose with the current design of the driver. Remove the outdated file. Signed-off-by: Frank Li [ Viresh: Rewrite commit log ] Signed-off-by: Viresh Kumar --- .../devicetree/bindings/cpufreq/cpufreq-dt.txt | 61 ---------------------- 1 file changed, 61 deletions(-) delete mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt deleted file mode 100644 index 1d7e49167666..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt +++ /dev/null @@ -1,61 +0,0 @@ -Generic cpufreq driver - -It is a generic DT based cpufreq driver for frequency management. It supports -both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share -clock and voltage across all CPUs. - -Both required and optional properties listed below must be defined -under node /cpus/cpu@0. - -Required properties: -- None - -Optional properties: -- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for - details. OPPs *must* be supplied either via DT, i.e. this property, or - populated at runtime. -- clock-latency: Specify the possible maximum transition latency for clock, - in unit of nanoseconds. -- voltage-tolerance: Specify the CPU voltage tolerance in percentage. -- #cooling-cells: - Please refer to - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. - -Examples: - -cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 1100000 - 396000 950000 - 198000 850000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; -}; -- cgit v1.2.3 From 7cb4d28e1195da9ebcdd5c2296af2fe3baad5421 Mon Sep 17 00:00:00 2001 From: Piotr Kubik Date: Tue, 26 Aug 2025 14:41:44 +0000 Subject: dt-bindings: net: pse-pd: Add bindings for Si3474 PSE controller Add the Si3474 I2C Power Sourcing Equipment controller device tree bindings documentation. Signed-off-by: Piotr Kubik Reviewed-by: Krzysztof Kozlowski Reviewed-by: Kory Maincent Link: https://patch.msgid.link/71a67c6f-6fce-49c7-96ec-554602dbd4f1@adtran.com Signed-off-by: Paolo Abeni --- .../bindings/net/pse-pd/skyworks,si3474.yaml | 144 +++++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml b/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml new file mode 100644 index 000000000000..edd36a43a387 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pse-pd/skyworks,si3474.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Skyworks Si3474 Power Sourcing Equipment controller + +maintainers: + - Piotr Kubik + +allOf: + - $ref: pse-controller.yaml# + +properties: + compatible: + enum: + - skyworks,si3474 + + reg: + maxItems: 2 + + reg-names: + items: + - const: main + - const: secondary + + channels: + description: The Si3474 is a single-chip PoE PSE controller managing + 8 physical power delivery channels. Internally, it's structured + into two logical "Quads". + Quad 0 Manages physical channels ('ports' in datasheet) 0, 1, 2, 3 + Quad 1 Manages physical channels ('ports' in datasheet) 4, 5, 6, 7. + + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + '^channel@[0-7]$': + type: object + additionalProperties: false + + properties: + reg: + maxItems: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + +required: + - compatible + - reg + - pse-pis + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-pse@26 { + compatible = "skyworks,si3474"; + reg-names = "main", "secondary"; + reg = <0x26>, <0x27>; + + channels { + #address-cells = <1>; + #size-cells = <0>; + phys0_0: channel@0 { + reg = <0>; + }; + phys0_1: channel@1 { + reg = <1>; + }; + phys0_2: channel@2 { + reg = <2>; + }; + phys0_3: channel@3 { + reg = <3>; + }; + phys0_4: channel@4 { + reg = <4>; + }; + phys0_5: channel@5 { + reg = <5>; + }; + phys0_6: channel@6 { + reg = <6>; + }; + phys0_7: channel@7 { + reg = <7>; + }; + }; + pse-pis { + #address-cells = <1>; + #size-cells = <0>; + pse_pi0: pse-pi@0 { + reg = <0>; + #pse-cells = <0>; + pairset-names = "alternative-a", "alternative-b"; + pairsets = <&phys0_0>, <&phys0_1>; + polarity-supported = "MDI-X", "S"; + vpwr-supply = <®_pse>; + }; + pse_pi1: pse-pi@1 { + reg = <1>; + #pse-cells = <0>; + pairset-names = "alternative-a", "alternative-b"; + pairsets = <&phys0_2>, <&phys0_3>; + polarity-supported = "MDI-X", "S"; + vpwr-supply = <®_pse>; + }; + pse_pi2: pse-pi@2 { + reg = <2>; + #pse-cells = <0>; + pairset-names = "alternative-a", "alternative-b"; + pairsets = <&phys0_4>, <&phys0_5>; + polarity-supported = "MDI-X", "S"; + vpwr-supply = <®_pse>; + }; + pse_pi3: pse-pi@3 { + reg = <3>; + #pse-cells = <0>; + pairset-names = "alternative-a", "alternative-b"; + pairsets = <&phys0_6>, <&phys0_7>; + polarity-supported = "MDI-X", "S"; + vpwr-supply = <®_pse>; + }; + }; + }; + }; -- cgit v1.2.3 From 2b036b13c8c2cadf7a27036f911ec99742504fce Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 22 Aug 2025 14:39:45 +0800 Subject: dt-bindings: display: rockchip: Add schema for RK3588 DPTX Controller The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller. And this DPTX controller need share a USBDP PHY with the USB 3.0 OTG controller during operation. Signed-off-by: Andy Yan Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250822063959.692098-2-andyshrk@163.com Signed-off-by: Dmitry Baryshkov --- .../bindings/display/rockchip/rockchip,dw-dp.yaml | 150 +++++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml new file mode 100644 index 000000000000..a8a008717997 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip DW DisplayPort Transmitter + +maintainers: + - Andy Yan + +description: | + The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller + which is compliant with the DisplayPort Specification Version 1.4 with the + following features: + + * DisplayPort 1.4a + * Main Link: 1/2/4 lanes + * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps + * AUX channel 1Mbps + * Single Stream Transport(SST) + * Multistream Transport (MST) + * Type-C support (alternate mode) + * HDCP 2.2, HDCP 1.3 + * Supports up to 8/10 bits per color component + * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0 + * Pixel clock up to 594MHz + * I2S, SPDIF audio interface + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3588-dp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral/APB bus clock + - description: DisplayPort AUX clock + - description: HDCP clock + - description: I2S interface clock + - description: SPDIF interfce clock + + clock-names: + items: + - const: apb + - const: aux + - const: hdcp + - const: i2s + - const: spdif + + phys: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for RGB/YUV input. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for DP output. + + required: + - port@0 + - port@1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - ports + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde50000 0x0 0x4000>; + interrupts = ; + clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, + <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, + <&cru MCLK_SPDIF2_DP0>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + assigned-clocks = <&cru CLK_AUX16M_0>; + assigned-clock-rates = <16000000>; + resets = <&cru SRST_DP0>; + phys = <&usbdp_phy0 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_dp0>; + }; + }; + + port@1 { + reg = <1>; + + dp0_out_con0: endpoint { + remote-endpoint = <&dp_con0_in>; + }; + }; + }; + }; + }; -- cgit v1.2.3 From 806d4fec0b80be6964b69947aad928a322fe77e4 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:10 +0200 Subject: dt-bindings: display: st: add two new compatibles to LTDC device The new STMicroelectronics SoC features a display controller similar to the one used in previous SoCs. Because there is additional registers, and different mandatory clocks it is incompatible with existing IPs. On STM32MP251, the device only needs two clocks while on STM32MP255 it needs four. Add the new names to the list of compatible string and handle each quirks accordingly. Acked-by: Philippe Cornu Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-1-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou --- .../devicetree/bindings/display/st,stm32-ltdc.yaml | 52 +++++++++++++++++++++- 1 file changed, 50 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index d6ea4d62a2cf..1233345a1630 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -12,7 +12,10 @@ maintainers: properties: compatible: - const: st,stm32-ltdc + enum: + - st,stm32-ltdc + - st,stm32mp251-ltdc + - st,stm32mp255-ltdc reg: maxItems: 1 @@ -24,11 +27,16 @@ properties: minItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 clock-names: items: - const: lcd + - const: bus + - const: ref + - const: lvds + minItems: 1 resets: maxItems: 1 @@ -51,6 +59,46 @@ required: - resets - port +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32-ltdc + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp251-ltdc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp255-ltdc + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + additionalProperties: false examples: -- cgit v1.2.3 From 81d678332c404384e5e83300376d9be375f6d928 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:11 +0200 Subject: dt-bindings: display: st,stm32-ltdc: add access-controllers property access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-2-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index 1233345a1630..77058a5ccf68 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -41,6 +41,9 @@ properties: resets: maxItems: 1 + access-controllers: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port description: | -- cgit v1.2.3 From 6b96ffeb81be8e43da7c4ddd0802739e22459519 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:12 +0200 Subject: dt-bindings: display: st: add new compatible to LVDS device Update the compatible to accept both "st,stm32mp255-lvds" and st,stm32mp25-lvds" respectively. Default will fall back to "st,stm32mp25-lvds". Acked-by: Krzysztof Kozlowski Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-3-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 6736f93256b5..74e61d95370c 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -31,7 +31,12 @@ description: | properties: compatible: - const: st,stm32mp25-lvds + oneOf: + - items: + - enum: + - st,stm32mp255-lvds + - const: st,stm32mp25-lvds + - const: st,stm32mp25-lvds "#clock-cells": const: 0 -- cgit v1.2.3 From 922e28eec67390686d944d03a12068df1197b393 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:13 +0200 Subject: dt-bindings: display: st,stm32mp25-lvds: add access-controllers property access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-4-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 74e61d95370c..05a73bbc246a 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -59,6 +59,9 @@ properties: resets: maxItems: 1 + access-controllers: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports -- cgit v1.2.3 From 08f6613e274f6cfe4d7d09ac5050d632dbba9342 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:14 +0200 Subject: dt-bindings: display: st,stm32mp25-lvds: add power-domains property STM32 LVDS peripheral may be in a power domain. Allow an optional single 'power-domains' entry for STM32 LVDS devices. Acked-by: Rob Herring (Arm) Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-5-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 05a73bbc246a..14e042156179 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -62,6 +62,9 @@ properties: access-controllers: maxItems: 1 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports -- cgit v1.2.3 From 1b9482f8dfce82af44e261c78777a37f32efe889 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:15 +0200 Subject: dt-bindings: arm: stm32: add required #clock-cells property On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Reviewed-by: Rob Herring (Arm) Reviewed-by: Yannick Fertre Acked-by: Christophe Roullier Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-6-9c825e28f733@foss.st.com Signed-off-by: Raphael Gallais-Pou --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 +++++++++++++++------- 1 file changed, 21 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c8492..95d2319afe23 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 + "#clock-cells": + const: 0 + required: - compatible - reg -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" additionalProperties: false -- cgit v1.2.3 From 57a48a2619c5f99d48748f9c34db510efe5ee7c9 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Mon, 28 Jul 2025 10:36:56 +0800 Subject: dt-bindings: PCI: ti,am65: Extend for use with PVU The Peripheral Virtualization Unit (PVU) on the AM65 SoC is capable of restricting DMA from PCIe devices to specific regions of host memory. Add the optional property "memory-regions" to point to such regions of memory when PVU is used. Since the PVU deals with system physical addresses, utilizing the PVU with PCIe devices also requires setting up the VMAP registers to map the Requester ID of the PCIe device to the CBA Virtual ID, which in turn is mapped to the system physical address. Hence, describe the VMAP registers which are optional unless the PVU shall be used for PCIe. Signed-off-by: Jan Kiszka Signed-off-by: Li Hua Qian [mani: Expanded PVU in description] Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250728023701.116963-3-huaqian.li@siemens.com --- .../devicetree/bindings/pci/ti,am65-pci-host.yaml | 28 +++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 0a9d10532cc8..98f6c7f1b1a6 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -20,14 +20,18 @@ properties: - ti,keystone-pcie reg: - maxItems: 4 + minItems: 4 + maxItems: 6 reg-names: + minItems: 4 items: - const: app - const: dbics - const: config - const: atu + - const: vmap_lp + - const: vmap_hp interrupts: maxItems: 1 @@ -69,6 +73,15 @@ properties: items: pattern: '^pcie-phy[0-1]$' + memory-region: + maxItems: 1 + description: | + phandle to a restricted DMA pool to be used for all devices behind + this controller. The regions should be defined according to + reserved-memory/shared-dma-pool.yaml. + Note that enforcement via the PVU will only be available to + ti,am654-pcie-rc devices. + required: - compatible - reg @@ -89,6 +102,13 @@ then: - power-domains - msi-map - num-viewport +else: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 unevaluatedProperties: false @@ -104,8 +124,10 @@ examples: reg = <0x5500000 0x1000>, <0x5501000 0x1000>, <0x10000000 0x2000>, - <0x5506000 0x1000>; - reg-names = "app", "dbics", "config", "atu"; + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; + reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; #size-cells = <2>; -- cgit v1.2.3 From 4fab69dd1fa52e28bb692afcb159fa8807d6d03f Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 27 Aug 2025 19:03:44 +0100 Subject: dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value The QiLai implementation of this cache controller uses a cache-sets of 2048, and mandates it in an if/else block - but the definition of the property only permits 1024. Add 2048 as an option, and deny its use outside of the QiLai. Fixes: 51b081cdb9237 ("dt-bindings: cache: add QiLai compatible to ax45mp") Reviewed-by: Ben Zong-You Xie Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index 4de5bb2e5f24..b135ffa4ab6b 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -47,7 +47,7 @@ properties: const: 2 cache-sets: - const: 1024 + enum: [1024, 2048] cache-size: enum: [131072, 262144, 524288, 1048576, 2097152] @@ -81,6 +81,10 @@ allOf: const: 2048 cache-size: const: 2097152 + else: + properties: + cache-sets: + const: 1024 examples: - | -- cgit v1.2.3 From 86d39a046b59583675a8c9701acc86c02768a433 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 28 Jun 2025 06:02:35 +0300 Subject: dt-bindings: display/msm/gpu: account for 7xx GPUs in clocks conditions Handle two cases for Adreno 7xx: - Adreno 702 follows A610 and A619 example and has clocks in the GPU node. - Newer 7xx GPUs use a different pattern for the compatibles and did not match currently. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio Acked-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/661351/ Link: https://lore.kernel.org/r/20250628-rework-msm-gpu-schema-v1-1-89f818c51b6a@oss.qualcomm.com --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 6ddc72fd85b0..97254f909260 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -187,6 +187,7 @@ allOf: enum: - qcom,adreno-610.0 - qcom,adreno-619.1 + - qcom,adreno-07000200 then: properties: clocks: @@ -222,7 +223,9 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' + oneOf: + - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' + - pattern: '^qcom,adreno-[0-9a-f]{8}$' then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: -- cgit v1.2.3 From cef3a60b30d1697ac796cf22f41531c916329db1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 28 Jun 2025 06:02:36 +0300 Subject: dt-bindings: display/msm/gpu: describe alwayson clock Adreno A506 and A510 have one extra clock, alwayson. Describe it in the schema. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/661352/ Link: https://lore.kernel.org/r/20250628-rework-msm-gpu-schema-v1-2-89f818c51b6a@oss.qualcomm.com --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 97254f909260..af43527188ce 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -173,6 +173,8 @@ allOf: description: GPU RBBM Timer for Adreno 5xx series - const: rbcpr description: GPU RB Core Power Reduction clock + - const: alwayson + description: GPU AON clock minItems: 2 maxItems: 7 -- cgit v1.2.3 From f3b649d7a513f71a31c451bd0825657211366d7f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 28 Jun 2025 06:02:37 +0300 Subject: dt-bindings: display/msm/gpu: describe clocks for each Adreno GPU type Rather than having a single list with all possible clocks for A3xx-A5xx define individual Adreno GPU types and corresponding clock lists. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/661348/ Link: https://lore.kernel.org/r/20250628-rework-msm-gpu-schema-v1-3-89f818c51b6a@oss.qualcomm.com --- .../devicetree/bindings/display/msm/gpu.yaml | 220 ++++++++++++++++++--- 1 file changed, 194 insertions(+), 26 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index af43527188ce..7ef80f9fac8b 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -146,41 +146,209 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' + oneOf: + - pattern: '^qcom,adreno-305\.[0-9]+$' + - pattern: '^qcom,adreno-330\.[0-9]+$' + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-306\.[0-9]+$' then: properties: clocks: - minItems: 2 - maxItems: 7 + minItems: 5 + maxItems: 6 + clock-names: + oneOf: + - items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gfx3d + description: GPU 3D engine clock + - items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gfx3d + description: GPU 3D engine clock + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-320\.[0-9]+$' + then: + properties: + clocks: + minItems: 4 + maxItems: 4 clock-names: items: - anyOf: - - const: core - description: GPU Core clock - - const: iface - description: GPU Interface clock - - const: mem - description: GPU Memory clock - - const: mem_iface - description: GPU Memory Interface clock - - const: alt_mem_iface - description: GPU Alternative Memory Interface clock - - const: gfx3d - description: GPU 3D engine clock - - const: rbbmtimer - description: GPU RBBM Timer for Adreno 5xx series - - const: rbcpr - description: GPU RB Core Power Reduction clock - - const: alwayson - description: GPU AON clock - minItems: 2 + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-405\.[0-9]+$' + then: + properties: + clocks: + minItems: 7 maxItems: 7 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gfx3d + description: GPU 3D engine clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series - required: - - clocks - - clock-names + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-506\.[0-9]+$' + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + - const: alwayson + description: GPU AON clock + + - if: + properties: + compatible: + contains: + oneOf: + - pattern: '^qcom,adreno-508\.[0-9]+$' + - pattern: '^qcom,adreno-509\.[0-9]+$' + - pattern: '^qcom,adreno-512\.[0-9]+$' + - pattern: '^qcom,adreno-540\.[0-9]+$' + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface + description: GPU Interface clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: rbcpr + description: GPU RB Core Power Reduction clock + - const: core + description: GPU Core clock + + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-510\.[0-9]+$' + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + - const: alwayson + description: GPU AON clock + + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-530\.[0-9]+$' + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock - if: properties: -- cgit v1.2.3 From 505441083afb9dde61d6b82bfa9d7cc6ad331e77 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 4 Jul 2025 19:31:53 +0300 Subject: dt-bindings: display/msm: dsi-controller-main: add SC8180X Describe the SC8180X-specific compatible for the DSI controller persent on the SoC. While the current DT for SC8180X doesn't use this compatible, all other platforms were updated to have one. This change makes SC8180X follow the lead. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/662495/ Link: https://lore.kernel.org/r/20250704-mdss-schema-v1-1-e978e4e73e14@oss.qualcomm.com --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index d4bb65c660af..4400d4cce072 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl + - qcom,sc8180x-dsi-ctrl - qcom,sdm660-dsi-ctrl - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl @@ -332,6 +333,7 @@ allOf: - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl + - qcom,sc8180x-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl -- cgit v1.2.3 From 275af16d7294e7f8a36370f274d3aa9dd01ad76a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 4 Jul 2025 19:31:54 +0300 Subject: dt-bindings: display/msm: describe DPU on SC8180X Describe the Display Processing Unit (DPU) as present on the SC8180X platform. Reported-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/662502/ Link: https://lore.kernel.org/r/20250704-mdss-schema-v1-2-e978e4e73e14@oss.qualcomm.com --- .../bindings/display/msm/qcom,sc8180x-dpu.yaml | 103 +++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sc8180x-dpu.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-dpu.yaml new file mode 100644 index 000000000000..a411126708b8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-dpu.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc8180x-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180X Display DPU + +maintainers: + - Dmitry Baryshkov + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sc8180x-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AHB clock + - description: Display HF AXI clock + - description: Display core clock + - description: Display vsync clock + - description: Display rotator clock + - description: Display LUT clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + - const: rot + - const: lut + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sc8180x-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "rot", + "lut"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... -- cgit v1.2.3 From fd5c9b3c99da614a71119fce1848e66650a6633f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 4 Jul 2025 19:31:55 +0300 Subject: dt-bindings: display/msm: describe MDSS on SC8180X Describe the Mobile Display SubSystem (MDSS) unit as present on the SC8180X platform. Reported-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/662498/ Link: https://lore.kernel.org/r/20250704-mdss-schema-v1-3-e978e4e73e14@oss.qualcomm.com --- .../bindings/display/msm/qcom,sc8180x-mdss.yaml | 359 +++++++++++++++++++++ 1 file changed, 359 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml new file mode 100644 index 000000000000..00e82bdbbcc7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml @@ -0,0 +1,359 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc8180x-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180X Display MDSS + +maintainers: + - Dmitry Baryshkov + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SC8180X target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sc8180x-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sc8180x-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + enum: + - qcom,sc8180x-dp + - qcom,sc8180x-edp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,sc8180x-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sc8180x-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>, + <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x420>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc8180x-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "rot", + "lut"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sc8180x-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sc8180x-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... -- cgit v1.2.3 From 2b0bff8c69d73cc33fc74c1e197f58ff9c7fd8c2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jul 2025 13:24:06 +0200 Subject: dt-bindings: soc: xilinx: Add support for K24, KR260 and KD240 CCs The commit 7a4c31ee877a ("arm64: zynqmp: Add support for Xilinx Kria SOM board") has added support for k26 and kv260 and the commit dbcd27526e6a ("dt-bindings: soc: xilinx: Add support for KV260 CC") has added support for KV260 and this is follow up patch for adding description for k24 SOM, KR260 (robotics platform) and KD240 (driver platform). The bootflow is the same that's why for more information please take a look at above commits. The KD240 kit is based on smaller k24 SOM with only 2GB of memory. Reviewed-by: Rob Herring (Arm) Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8ff66d0dc4e0de6f239c25d43a2a96b4224305e8.1752837842.git.michal.simek@amd.com --- .../devicetree/bindings/soc/xilinx/xilinx.yaml | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index fb5c39c79d28..c9f99e0df2b3 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -116,6 +116,36 @@ properties: - const: xlnx,zynqmp-zcu111 - const: xlnx,zynqmp + - description: Xilinx Kria SOMs K24 + minItems: 3 + items: + enum: + - xlnx,zynqmp-sm-k24-rev1 + - xlnx,zynqmp-sm-k24-revB + - xlnx,zynqmp-sm-k24-revA + - xlnx,zynqmp-sm-k24 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-sm-k24 + + - description: Xilinx Kria SOMs K24 (starter) + minItems: 3 + items: + enum: + - xlnx,zynqmp-smk-k24-rev1 + - xlnx,zynqmp-smk-k24-revB + - xlnx,zynqmp-smk-k24-revA + - xlnx,zynqmp-smk-k24 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-smk-k24 + - description: Xilinx Kria SOMs minItems: 3 items: @@ -148,6 +178,57 @@ properties: - contains: const: xlnx,zynqmp-smk-k26 + - description: Xilinx Kria SOM KD240 revA/B/1 + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kd240-rev1 + - xlnx,zynqmp-sk-kd240-revB + - xlnx,zynqmp-sk-kd240-revA + - xlnx,zynqmp-sk-kd240 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kd240-revA + - contains: + const: xlnx,zynqmp-sk-kd240 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KR260 revA/Y/Z + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kr260-revA + - xlnx,zynqmp-sk-kr260-revY + - xlnx,zynqmp-sk-kr260-revZ + - xlnx,zynqmp-sk-kr260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kr260-revA + - contains: + const: xlnx,zynqmp-sk-kr260 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KR260 rev2/1/B + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kr260-rev2 + - xlnx,zynqmp-sk-kr260-rev1 + - xlnx,zynqmp-sk-kr260-revB + - xlnx,zynqmp-sk-kr260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kr260-revB + - contains: + const: xlnx,zynqmp-sk-kr260 + - contains: + const: xlnx,zynqmp + - description: Xilinx Kria SOM KV260 revA/Y/Z minItems: 3 items: -- cgit v1.2.3 From 400915493f53b10085648b387cdbb4da5612ebfc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 19:56:14 +0200 Subject: dt-bindings: Add Actiontec vendor prefix Actiontec is a US manufacturer of telecom equipment. Acked-by: Conor Dooley Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-1-cc804884474d@linaro.org --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..a0abe9e39291 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -48,6 +48,8 @@ patternProperties: description: Acme Systems srl "^actions,.*": description: Actions Semiconductor Co., Ltd. + "^actiontec,.*": + description: Actiontec Electronics, Inc "^active-semi,.*": description: Active-Semi International Inc "^ad,.*": -- cgit v1.2.3 From 873c5c0a2baf11d7101df3fc7485a0183c8c6c29 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 19:56:15 +0200 Subject: dt-bindings: arm: ixp4xx: List actiontec devices Add two IXP4xx device families from OpenWrts backlog: Actiontec MI424WR revision A/C and revision D, both of these are IXP4xx devices. Revisions E and later use different chipsets. Acked-by: Conor Dooley Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-2-cc804884474d@linaro.org --- Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml index d60792b1d995..b7b430896596 100644 --- a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -16,6 +16,8 @@ properties: oneOf: - items: - enum: + - actiontec,mi424wr-ac + - actiontec,mi424wr-d - adieng,coyote - arcom,vulcan - dlink,dsm-g600-a -- cgit v1.2.3 From 1ea149fb5b068c1b7490451d967216ff554628af Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Mon, 11 Aug 2025 11:20:36 +0200 Subject: dt-bindings: mips: cpu: Add MIPS 34Kc Core Document MIPS 34Kc device tree bindings. It is used in the Realtek RTL930x SoC. Signed-off-by: Aleksander Jan Bajkowski Acked-by: Conor Dooley Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/cpus.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index 471373ad0cfb..d3677f53f142 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -33,6 +33,7 @@ properties: - mips,mips1004Kc - mips,mips24KEc - mips,mips24Kc + - mips,mips34Kc - mips,mips4KEc - mips,mips4Kc - mips,mips74Kc -- cgit v1.2.3 From cfbb794c62291cd8249def0d10cae922b717b53e Mon Sep 17 00:00:00 2001 From: Keguang Zhang Date: Wed, 16 Jul 2025 19:25:10 +0800 Subject: dt-bindings: mips: loongson: Add LS1B-DEMO and CQ-T300B Document two Loongson-1 boards: - loongson,ls1b-demo: a board based on Loongson-1B - loongson,cq-t300b: a board based on Loongson-1C Acked-by: Krzysztof Kozlowski Signed-off-by: Keguang Zhang Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/loongson/devices.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml index 099e40e1482d..ca66bc49c2d6 100644 --- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -40,6 +40,7 @@ properties: - description: LS1B based boards items: - enum: + - loongson,ls1b-demo - loongson,lsgz-1b-dev - const: loongson,ls1b @@ -47,6 +48,7 @@ properties: items: - enum: - loongmasses,smartloong-1c + - loongson,cq-t300b - const: loongson,ls1c additionalProperties: true -- cgit v1.2.3 From 2b31c1c7134a316a0c97da5d7bdbe15552101db3 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 15:33:34 -0500 Subject: dt-bindings: pinctrl: Convert brcm,bcm2835-gpio to DT schema Convert the Broadcom BCM2835 GPIO (and pinmux) controller binding to DT schema format. The structure of the child nodes wasn't well defined. The schema is based on the .dts users. The legacy binding is a single level of child nodes while the standard binding is 2 levels of child nodes. The "all banks" interrupt is treated as optional following actual users. Signed-off-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/20250812203337.731648-1-robh@kernel.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/brcm,bcm2835-gpio.txt | 99 ----------------- .../bindings/pinctrl/brcm,bcm2835-gpio.yaml | 120 +++++++++++++++++++++ 2 files changed, 120 insertions(+), 99 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt deleted file mode 100644 index 5682b2010e50..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ /dev/null @@ -1,99 +0,0 @@ -Broadcom BCM2835 GPIO (and pinmux) controller - -The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt -controller, and pinmux/control device. - -Required properties: -- compatible: "brcm,bcm2835-gpio" -- compatible: should be one of: - "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl - "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl - "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl - "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl -- reg: Should contain the physical address of the GPIO module's registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- interrupts : The interrupt outputs from the controller. One interrupt per - individual bank followed by the "all banks" interrupt. For BCM7211, an - additional set of per-bank interrupt line and an "all banks" wake-up - interrupt may be specified. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. - The first cell is the GPIO number. - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - -Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Each pin configuration node lists the pin(s) to which it applies, and one or -more of the mux function to select on those pin(s), and pull-up/down -configuration. Each subnode only affects those parameters that are explicitly -listed. In other words, a subnode that lists only a mux function implies no -information about any pull configuration. Similarly, a subnode that lists only -a pul parameter implies no information about the mux function. - -The BCM2835 pin configuration and multiplexing supports the generic bindings. -For details on each properties, you can refer to ./pinctrl-bindings.txt. - -Required sub-node properties: - - pins - - function - -Optional sub-node properties: - - bias-disable - - bias-pull-up - - bias-pull-down - - output-high - - output-low - -Legacy pin configuration and multiplexing binding: -*** (Its use is deprecated, use generic multiplexing and configuration -bindings instead) - -Required subnode-properties: -- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs - are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53. - -Optional subnode-properties: -- brcm,function: Integer, containing the function to mux to the pin(s): - 0: GPIO in - 1: GPIO out - 2: alt5 - 3: alt4 - 4: alt0 - 5: alt1 - 6: alt2 - 7: alt3 -- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s): - 0: none - 1: down - 2: up - -Each of brcm,function and brcm,pull may contain either a single value which -will be applied to all pins in brcm,pins, or 1 value for each entry in -brcm,pins. - -Example: - - gpio: gpio { - compatible = "brcm,bcm2835-gpio"; - reg = <0x2200000 0xb4>; - interrupts = <2 17>, <2 19>, <2 18>, <2 20>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml new file mode 100644 index 000000000000..6514f347f6bc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2835-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 GPIO (and pinmux) controller + +maintainers: + - Florian Fainelli + +description: > + The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt + controller, and pinmux/control device. + +properties: + compatible: + enum: + - brcm,bcm2835-gpio + - brcm,bcm2711-gpio + - brcm,bcm7211-gpio + + reg: + maxItems: 1 + + '#gpio-cells': + const: 2 + + gpio-controller: true + gpio-ranges: true + gpio-line-names: true + + interrupts: + description: > + Interrupt outputs: one per bank, then the combined “all banks” line. + BCM7211 may specify up to four per-bank wake-up lines and one combined + wake-up interrupt. + minItems: 4 + maxItems: 10 + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + +additionalProperties: + oneOf: + - type: object + additionalProperties: false + + patternProperties: + '^pins?-': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + pins: true + function: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + output-high: true + output-low: true + + required: + - pins + - function + + - type: object + additionalProperties: false + deprecated: true + + properties: + brcm,pins: + description: + GPIO pin numbers for legacy configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + brcm,function: + description: + Legacy mux function for the pins (0=input, 1=output, 2–7=alt functions). + $ref: /schemas/types.yaml#/definitions/uint32-array + maximum: 7 + + brcm,pull: + description: > + Legacy pull setting for the pins (0=none, 1=pull-down, 2=pull-up). + $ref: /schemas/types.yaml#/definitions/uint32-array + maximum: 2 + + required: + - brcm,pins + +allOf: + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm2835-gpio + - brcm,bcm2711-gpio + then: + properties: + interrupts: + maxItems: 5 + +examples: + - | + gpio@2200000 { + compatible = "brcm,bcm2835-gpio"; + reg = <0x2200000 0xb4>; + interrupts = <2 17>, <2 19>, <2 18>, <2 20>, <2 21>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; -- cgit v1.2.3 From 8898cf86f043468d285a474d1614e5cf1a170b16 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 15:33:47 -0500 Subject: dt-bindings: pinctrl: Convert brcm,iproc-gpio to DT schema Convert the Broadcom iProc/Cygnus GPIO/Pinconf binding to DT schema format. The child node structure is based on the example as there's not any actual .dts files with child nodes. The binding wasn't clear that "reg" can be 1 or 2 entries. The number of "reg" entries doesn't appear to be based on compatible, so no per compatible constraints for it The "brcm,iproc-stingray-gpio" could possibly be dropped. There are no .dts files using it, but the driver uses it. Signed-off-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/20250812203348.733749-1-robh@kernel.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/brcm,iproc-gpio.txt | 123 --------------------- .../bindings/pinctrl/brcm,iproc-gpio.yaml | 111 +++++++++++++++++++ 2 files changed, 111 insertions(+), 123 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt deleted file mode 100644 index a73cbeb0f309..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt +++ /dev/null @@ -1,123 +0,0 @@ -Broadcom iProc GPIO/PINCONF Controller - -Required properties: - -- compatible: - "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that - supports full-featured pinctrl and GPIO functions used in various iProc - based SoCs - - May contain an SoC-specific compatibility string to accommodate any - SoC-specific features - - "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or - "brcm,cygnus-crmu-gpio" for Cygnus SoCs - - "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support - disabled - - "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general - pinctrl support completely disabled in this IP block. In Stingray, a - different IP block is used to handle pinctrl related functions - -- reg: - Define the base and range of the I/O address space that contains SoC -GPIO/PINCONF controller registers - -- ngpios: - Total number of in-use slots in GPIO controller - -- #gpio-cells: - Must be two. The first cell is the GPIO pin number (within the -controller's pin space) and the second cell is used for the following: - bit[0]: polarity (0 for active high and 1 for active low) - -- gpio-controller: - Specifies that the node is a GPIO controller - -Optional properties: - -- interrupts: - Interrupt ID - -- interrupt-controller: - Specifies that the node is an interrupt controller - -- gpio-ranges: - Specifies the mapping between gpio controller and pin-controllers pins. - This requires 4 fields in cells defined as - - 1. Phandle of pin-controller. - 2. GPIO base pin offset. - 3 Pin-control base pin offset. - 4. number of gpio pins which are linearly mapped from pin base. - -Supported generic PINCONF properties in child nodes: - -- pins: - The list of pins (within the controller's own pin space) that properties -in the node apply to. Pin names are "gpio-" - -- bias-disable: - Disable pin bias - -- bias-pull-up: - Enable internal pull up resistor - -- bias-pull-down: - Enable internal pull down resistor - -- drive-strength: - Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) - -Example: - gpio_ccm: gpio@1800a000 { - compatible = "brcm,cygnus-ccm-gpio"; - reg = <0x1800a000 0x50>, - <0x0301d164 0x20>; - ngpios = <24>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - - touch_pins: touch_pins { - pwr: pwr { - pins = "gpio-0"; - drive-strength = <16>; - }; - - event: event { - pins = "gpio-1"; - bias-pull-up; - }; - }; - }; - - gpio_asiu: gpio@180a5000 { - compatible = "brcm,cygnus-asiu-gpio"; - reg = <0x180a5000 0x668>; - ngpios = <146>; - #gpio-cells = <2>; - gpio-controller; - interrupts = ; - interrupt-controller; - gpio-ranges = <&pinctrl 0 42 1>, - <&pinctrl 1 44 3>; - }; - - /* - * Touchscreen that uses the CCM GPIO 0 and 1 - */ - tsc { - ... - ... - gpio-pwr = <&gpio_ccm 0 0>; - gpio-event = <&gpio_ccm 1 0>; - }; - - /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ - bluetooth { - ... - ... - bcm,rfkill-bank-sel = <&gpio_asiu 5 1> - } diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml new file mode 100644 index 000000000000..a0ed308b7fc8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,iproc-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc GPIO/PINCONF Controller + +maintainers: + - Ray Jui + - Scott Branden + +properties: + compatible: + oneOf: + - enum: + - brcm,cygnus-asiu-gpio + - brcm,cygnus-ccm-gpio + - brcm,cygnus-crmu-gpio + - brcm,iproc-gpio + - brcm,iproc-stingray-gpio + - items: + - enum: + - brcm,iproc-hr2-gpio + - brcm,iproc-nsp-gpio + - const: brcm,iproc-gpio + + reg: + minItems: 1 + items: + - description: GPIO Bank registers + - description: IO Ctrl registers + + "#gpio-cells": + const: 2 + + gpio-controller: true + + gpio-ranges: true + + ngpios: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + - ngpios + +patternProperties: + '-pins$': + type: object + additionalProperties: + description: Pin configuration child nodes. + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + pins: + items: + pattern: '^gpio-' + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include + + gpio@1800a000 { + compatible = "brcm,cygnus-ccm-gpio"; + reg = <0x1800a000 0x50>, + <0x0301d164 0x20>; + ngpios = <24>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupts = ; + interrupt-controller; + + touch-pins { + pwr { + pins = "gpio-0"; + drive-strength = <16>; + }; + + event { + pins = "gpio-1"; + bias-pull-up; + }; + }; + }; -- cgit v1.2.3 From 97d37c0a4477c857f2ddf42b5fe9e4a78ab9db85 Mon Sep 17 00:00:00 2001 From: T Pratham Date: Wed, 20 Aug 2025 14:42:26 +0530 Subject: dt-bindings: crypto: Add binding for TI DTHE V2 Add DT binding for Texas Instruments DTHE V2 cryptography engine. DTHE V2 is introduced as a part of TI AM62L SoC and can currently be only found in it. Signed-off-by: T Pratham Reviewed-by: Krzysztof Kozlowski Signed-off-by: Herbert Xu --- .../bindings/crypto/ti,am62l-dthev2.yaml | 50 ++++++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/ti,am62l-dthev2.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/ti,am62l-dthev2.yaml b/Documentation/devicetree/bindings/crypto/ti,am62l-dthev2.yaml new file mode 100644 index 000000000000..5486bfeb2fe8 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/ti,am62l-dthev2.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/ti,am62l-dthev2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: K3 SoC DTHE V2 crypto module + +maintainers: + - T Pratham + +properties: + compatible: + enum: + - ti,am62l-dthev2 + + reg: + maxItems: 1 + + dmas: + items: + - description: AES Engine RX DMA Channel + - description: AES Engine TX DMA Channel + - description: SHA Engine TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx1 + - const: tx2 + +required: + - compatible + - reg + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + crypto@40800000 { + compatible = "ti,am62l-dthev2"; + reg = <0x40800000 0x10000>; + + dmas = <&main_bcdma 0 0 0x4700 0>, + <&main_bcdma 0 0 0xc701 0>, + <&main_bcdma 0 0 0xc700 0>; + dma-names = "rx", "tx1", "tx2"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..0f5bb8ad7653 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25169,6 +25169,12 @@ S: Odd Fixes F: drivers/clk/ti/ F: include/linux/clk/ti.h +TI DATA TRANSFORM AND HASHING ENGINE (DTHE) V2 CRYPTO DRIVER +M: T Pratham +L: linux-crypto@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/crypto/ti,am62l-dthev2.yaml + TI DAVINCI MACHINE SUPPORT M: Bartosz Golaszewski L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- cgit v1.2.3 From a52bdee13ed77f02dfd902baeb0eae876846672e Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 28 Aug 2025 16:54:52 -0500 Subject: dt-bindings: iio: adc: adi,ad7124: fix clocks properties Use correct clocks properties for the AD7124 family of ADCs. These ADCs have an internal clock along with an optional external clock that can be connected to the CLK pin. This pin can be wired up 3 ways: 1. Not connected - the internal clock is used. 2. Connected to an external clock (input) - the external clock is used. 3. Connected to the CLK pin on another ADC (output) - the internal clock is used on one and the other is configured for an external clock. The new bindings describe these 3 cases by picking one of the following: 1. Omit both clocks and #clock-cells properties. 2. Include only the clocks property with a phandle to the external clock. 3. Include only the #clock-cells property on the ADC providing the output. The clock-names property is now deprecated and should not be used. The MCLK signal that it refers to is an internal counter in the ADC and therefore does not make sense as a devicetree property as it can't be connected to anything external to the ADC. Since there is only one possible external clock, the clock-names property is not needed anyway. Based on the implementation of the Linux driver, it looks like the "mclk" clock was basically being used as a control to select the power mode of the ADC, which is not something that should be done in the devicetree. Reviewed-by: Rob Herring (Arm) Signed-off-by: David Lechner Link: https://patch.msgid.link/20250828-iio-adc-ad7124-proper-clock-support-v3-1-0b317b4605e5@baylibre.com Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/adi,ad7124.yaml | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml index 4dd5395730c1..2e3f84db6193 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml @@ -28,12 +28,21 @@ properties: clocks: maxItems: 1 - description: phandle to the master clock (mclk) + description: Optional external clock connected to the CLK pin. clock-names: + deprecated: true + description: + MCLK is an internal counter in the ADC. Do not use this property. items: - const: mclk + '#clock-cells': + description: + The CLK pin can be used as an output. When that is the case, include + this property. + const: 0 + interrupts: description: IRQ line for the ADC maxItems: 1 @@ -67,10 +76,14 @@ properties: required: - compatible - reg - - clocks - - clock-names - interrupts +# Can't have both clock input and output at the same time. +not: + required: + - '#clock-cells' + - clocks + patternProperties: "^channel@([0-9]|1[0-5])$": $ref: adc.yaml @@ -136,8 +149,6 @@ examples: interrupt-parent = <&gpio>; rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>; refin1-supply = <&adc_vref>; - clocks = <&ad7124_mclk>; - clock-names = "mclk"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 06cff2c4e4c35ee96532b6ddd51e78641a3b4b9d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 22 Aug 2025 03:27:30 +0300 Subject: dt-bindings: media: nxp,imx-mipi-csi2: Mark clock-frequency as deprecated Usage of the clock-frequency property, which is already optional, is discouraged in favour of using assigned-clock-rates (and assigned-clock-parents where needed). Mark the property as deprecated, and update the examples accordingly. Link: https://lore.kernel.org/r/20250822002734.23516-11-laurent.pinchart@ideasonboard.com Signed-off-by: Laurent Pinchart Reviewed-by: Frank Li Reviewed-by: Rob Herring (Arm) Signed-off-by: Hans Verkuil --- .../devicetree/bindings/media/nxp,imx-mipi-csi2.yaml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml index 03a23a26c4f3..db4889bf881e 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml @@ -66,6 +66,7 @@ properties: clock-frequency: description: The desired external clock ("wrap") frequency, in Hz default: 166000000 + deprecated: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -147,7 +148,9 @@ examples: <&clks IMX7D_MIPI_CSI_ROOT_CLK>, <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; clock-names = "pclk", "wrap", "phy"; - clock-frequency = <166000000>; + + assigned-clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>; + assigned-clock-rates = <166000000>; power-domains = <&pgc_mipi_phy>; phy-supply = <®_1p0d>; @@ -185,12 +188,16 @@ examples: compatible = "fsl,imx8mm-mipi-csi2"; reg = <0x32e30000 0x1000>; interrupts = ; - clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, <&clk IMX8MM_CLK_CSI1_ROOT>, <&clk IMX8MM_CLK_CSI1_PHY_REF>, <&clk IMX8MM_CLK_DISP_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; + + assigned-clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; + assigned-clock-rates = <250000000>; + power-domains = <&mipi_pd>; ports { -- cgit v1.2.3 From 362fc3fa78f9fa9fe9417c3c02850d282bd2c791 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 22 Aug 2025 03:27:31 +0300 Subject: dt-bindings: media: nxp,imx-mipi-csi2: Add fsl,num-channels property The CSI-2 receiver can be instantiated with up to four output channels. This is an integration-specific property, specify the number of instantiated channels through a new fsl,num-channels property. The property is optional, and defaults to 1 as only one channel is currently supported by drivers. Using the compatible string to infer the number of channels has been considered, but multiple instances of the same CSIS in the same SoC could conceptually be synthesized with a different number of channels. An explicit property is therefore more appropriate. The only known SoC to have more than one channel is the i.MX8MP. As the binding examples do not cover that SoC, don't update them. Link: https://lore.kernel.org/r/20250822002734.23516-12-laurent.pinchart@ideasonboard.com Signed-off-by: Laurent Pinchart Reviewed-by: Rob Herring (Arm) Signed-off-by: Hans Verkuil --- Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml index db4889bf881e..41ad5b84eaeb 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml @@ -68,6 +68,13 @@ properties: default: 166000000 deprecated: true + fsl,num-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of output channels + minimum: 1 + maximum: 4 + default: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports -- cgit v1.2.3 From acfaba169385bfa243a10a027f8272a974b2288a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 16 Jun 2025 04:11:10 +0300 Subject: dt-bindings: media: rkisp1: Require pclk clock on i.MX8MP variant The ISP integrated in the NXP i.MX8MP requires the pclk clock to access the HDR stitching registers. Make it mandatory in the DT binding. Link: https://lore.kernel.org/r/20250616011115.19515-2-laurent.pinchart@ideasonboard.com Signed-off-by: Laurent Pinchart Reviewed-by: Rob Herring (Arm) Signed-off-by: Hans Verkuil --- Documentation/devicetree/bindings/media/rockchip-isp1.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml index 6be00aca4181..6b360cbb42e0 100644 --- a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml +++ b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml @@ -155,6 +155,10 @@ allOf: const: fsl,imx8mp-isp then: properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 iommus: false phys: false phy-names: false -- cgit v1.2.3 From 4435a7a3fc283011a7b3e9c3b157aac8384333bd Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 16 Jun 2025 04:11:11 +0300 Subject: dt-bindings: media: rkisp1: Add second power domain on i.MX8MP In the NXP i.MX8MP, the pclk clock required by the ISP is gated by the MIPI CSI-2 power domain. Add it to the power-domains property, and require specifying power-domain-names accordingly. Link: https://lore.kernel.org/r/20250616011115.19515-3-laurent.pinchart@ideasonboard.com Signed-off-by: Laurent Pinchart Reviewed-by: Rob Herring (Arm) Signed-off-by: Hans Verkuil --- .../devicetree/bindings/media/rockchip-isp1.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml index 6b360cbb42e0..477c21417e75 100644 --- a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml +++ b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml @@ -71,7 +71,16 @@ properties: const: dphy power-domains: - maxItems: 1 + minItems: 1 + items: + - description: ISP power domain + - description: MIPI CSI-2 power domain + + power-domain-names: + minItems: 1 + items: + - const: isp + - const: csi2 ports: $ref: /schemas/graph.yaml#/properties/ports @@ -162,11 +171,19 @@ allOf: iommus: false phys: false phy-names: false + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 required: - fsl,blk-ctrl + - power-domain-names else: properties: fsl,blk-ctrl: false + power-domains: + maxItems: 1 + power-domain-names: false required: - iommus - phys -- cgit v1.2.3 From a9ee71011a5347dd77887e2c5c2f87f01acd3efb Mon Sep 17 00:00:00 2001 From: Ioana Risteiu Date: Tue, 26 Aug 2025 01:13:50 +0300 Subject: dt-bindings: iio: adc: add IIO backend support Add the generic io-backends property to the AD7779 binding to enable support for the IIO backend framework. Also add the adi,num-lanes property to set the number of lanes used by AD7779. Reviewed-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski Signed-off-by: Ioana Risteiu Link: https://patch.msgid.link/20250825221355.6214-3-Ioana.Risteiu@analog.com Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/adi,ad7779.yaml | 44 +++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7779.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7779.yaml index 044f92f39cfa..ba3f7b2bd6cf 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7779.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7779.yaml @@ -80,11 +80,36 @@ properties: reset-gpios: maxItems: 1 + io-backends: + maxItems: 1 + + adi,num-lanes: + description: + Number of lanes on which the data is sent on the output when the data + output interface is used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4] + default: 4 + required: - compatible - reg - clocks - - interrupts + +allOf: + - if: + not: + required: + - io-backends + then: + properties: + adi,num-lanes: false + +oneOf: + - required: + - interrupts + - required: + - io-backends unevaluatedProperties: false @@ -107,4 +132,21 @@ examples: clocks = <&adc_clk>; }; }; + + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7779"; + reg = <0>; + start-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio0 93 GPIO_ACTIVE_LOW>; + clocks = <&adc_clk>; + io-backends = <&iio_backend>; + adi,num-lanes = <4>; + }; + }; ... -- cgit v1.2.3 From 91f98de42310c70f9a23595b3b20aa305717d955 Mon Sep 17 00:00:00 2001 From: Hakyeong Kim Date: Mon, 25 Aug 2025 17:14:27 +0530 Subject: dt-bindings: clock: Add ARTPEC-8 clock controller Add dt-schema for Axis ARTPEC-8 SoC clock controller. The Clock Management Unit (CMU) has a top-level block CMU_CMU which generates clocks for other blocks. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS - CMU_IMEM - CMU_PERI Signed-off-by: Hakyeong Kim Signed-off-by: SeonGu Kang Reviewed-by: Rob Herring (Arm) Signed-off-by: Ravi Patel Link: https://lore.kernel.org/r/20250825114436.46882-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/axis,artpec8-clock.yaml | 213 +++++++++++++++++++++ include/dt-bindings/clock/axis,artpec8-clk.h | 169 ++++++++++++++++ 2 files changed, 382 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml new file mode 100644 index 000000000000..277af48ac841 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC-8 SoC clock controller + +maintainers: + - Jesper Nilsson + +description: | + ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit) + units, generating clocks for different domains. Those CMU units are modeled + as separate device tree nodes, and might depend on each other. + The root clock in that root tree is an external clock: OSCCLK (25 MHz). + This external clock must be defined as a fixed-rate clock in dts. + + CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_CMU. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/axis,artpec8-clk.h' header. + +properties: + compatible: + enum: + - axis,artpec8-cmu-cmu + - axis,artpec8-cmu-bus + - axis,artpec8-cmu-core + - axis,artpec8-cmu-cpucl + - axis,artpec8-cmu-fsys + - axis,artpec8-cmu-imem + - axis,artpec8-cmu-peri + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + const: axis,artpec8-cmu-cmu + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + const: axis,artpec8-cmu-bus + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_BUS BUS clock (from CMU_CMU) + - description: CMU_BUS DLP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: bus + - const: dlp + + - if: + properties: + compatible: + const: axis,artpec8-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CORE main clock (from CMU_CMU) + - description: CMU_CORE DLP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: main + - const: dlp + + - if: + properties: + compatible: + const: axis,artpec8-cmu-cpucl + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CPUCL switch clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: switch + + - if: + properties: + compatible: + const: axis,artpec8-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_FSYS SCAN0 clock (from CMU_CMU) + - description: CMU_FSYS SCAN1 clock (from CMU_CMU) + - description: CMU_FSYS BUS clock (from CMU_CMU) + - description: CMU_FSYS IP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: scan0 + - const: scan1 + - const: bus + - const: ip + + - if: + properties: + compatible: + const: axis,artpec8-cmu-imem + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_IMEM ACLK clock (from CMU_CMU) + - description: CMU_IMEM JPEG clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: aclk + - const: jpeg + + - if: + properties: + compatible: + const: axis,artpec8-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_PERI IP clock (from CMU_CMU) + - description: CMU_PERI AUDIO clock (from CMU_CMU) + - description: CMU_PERI DISP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: ip + - const: audio + - const: disp + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS + - | + #include + + cmu_fsys: clock-controller@16c10000 { + compatible = "axis,artpec8-cmu-fsys"; + reg = <0x16c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; + clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; + }; + +... diff --git a/include/dt-bindings/clock/axis,artpec8-clk.h b/include/dt-bindings/clock/axis,artpec8-clk.h new file mode 100644 index 000000000000..1e6e1409dd94 --- /dev/null +++ b/include/dt-bindings/clock/axis,artpec8-clk.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + * + * Device Tree binding constants for ARTPEC-8 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H +#define _DT_BINDINGS_CLOCK_ARTPEC8_H + +/* CMU_CMU */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_DOUT_SHARED0_DIV2 2 +#define CLK_DOUT_SHARED0_DIV3 3 +#define CLK_DOUT_SHARED0_DIV4 4 +#define CLK_FOUT_SHARED1_PLL 5 +#define CLK_DOUT_SHARED1_DIV2 6 +#define CLK_DOUT_SHARED1_DIV3 7 +#define CLK_DOUT_SHARED1_DIV4 8 +#define CLK_FOUT_AUDIO_PLL 9 +#define CLK_DOUT_CMU_BUS 10 +#define CLK_DOUT_CMU_BUS_DLP 11 +#define CLK_DOUT_CMU_CDC_CORE 12 +#define CLK_DOUT_CMU_OTP 13 +#define CLK_DOUT_CMU_CORE_MAIN 14 +#define CLK_DOUT_CMU_CORE_DLP 15 +#define CLK_DOUT_CMU_CPUCL_SWITCH 16 +#define CLK_DOUT_CMU_DLP_CORE 17 +#define CLK_DOUT_CMU_FSYS_BUS 18 +#define CLK_DOUT_CMU_FSYS_IP 19 +#define CLK_DOUT_CMU_FSYS_SCAN0 20 +#define CLK_DOUT_CMU_FSYS_SCAN1 21 +#define CLK_DOUT_CMU_GPU_3D 22 +#define CLK_DOUT_CMU_GPU_2D 23 +#define CLK_DOUT_CMU_IMEM_ACLK 24 +#define CLK_DOUT_CMU_IMEM_JPEG 25 +#define CLK_DOUT_CMU_MIF_SWITCH 26 +#define CLK_DOUT_CMU_MIF_BUSP 27 +#define CLK_DOUT_CMU_PERI_DISP 28 +#define CLK_DOUT_CMU_PERI_IP 29 +#define CLK_DOUT_CMU_PERI_AUDIO 30 +#define CLK_DOUT_CMU_RSP_CORE 31 +#define CLK_DOUT_CMU_TRFM_CORE 32 +#define CLK_DOUT_CMU_VCA_ACE 33 +#define CLK_DOUT_CMU_VCA_OD 34 +#define CLK_DOUT_CMU_VIO_CORE 35 +#define CLK_DOUT_CMU_VIO_AUDIO 36 +#define CLK_DOUT_CMU_VIP0_CORE 37 +#define CLK_DOUT_CMU_VIP1_CORE 38 +#define CLK_DOUT_CMU_VPP_CORE 39 + +/* CMU_BUS */ +#define CLK_MOUT_BUS_ACLK_USER 1 +#define CLK_MOUT_BUS_DLP_USER 2 +#define CLK_DOUT_BUS_PCLK 3 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_ACLK_USER 1 +#define CLK_MOUT_CORE_DLP_USER 2 +#define CLK_DOUT_CORE_PCLK 3 + +/* CMU_CPUCL */ +#define CLK_FOUT_CPUCL_PLL 1 +#define CLK_MOUT_CPUCL_PLL 2 +#define CLK_MOUT_CPUCL_SWITCH_USER 3 +#define CLK_DOUT_CPUCL_CPU 4 +#define CLK_DOUT_CPUCL_CLUSTER_ACLK 5 +#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG 6 +#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK 7 +#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 8 +#define CLK_DOUT_CPUCL_PCLK 9 +#define CLK_DOUT_CPUCL_CMUREF 10 +#define CLK_DOUT_CPUCL_DBG 11 +#define CLK_DOUT_CPUCL_PCLKDBG 12 +#define CLK_GOUT_CPUCL_CLUSTER_CPU 13 +#define CLK_GOUT_CPUCL_SHORTSTOP 14 +#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 15 +#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 16 + +/* CMU_FSYS */ +#define CLK_FOUT_FSYS_PLL 1 +#define CLK_MOUT_FSYS_SCAN0_USER 2 +#define CLK_MOUT_FSYS_SCAN1_USER 3 +#define CLK_MOUT_FSYS_BUS_USER 4 +#define CLK_MOUT_FSYS_MMC_USER 5 +#define CLK_DOUT_FSYS_PCIE_PIPE 6 +#define CLK_DOUT_FSYS_ADC 7 +#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL 8 +#define CLK_DOUT_FSYS_EQOS_INT125 9 +#define CLK_DOUT_FSYS_OTP_MEM 10 +#define CLK_DOUT_FSYS_SCLK_UART 11 +#define CLK_DOUT_FSYS_EQOS_25 12 +#define CLK_DOUT_FSYS_EQOS_2p5 13 +#define CLK_DOUT_FSYS_BUS300 14 +#define CLK_DOUT_FSYS_BUS_QSPI 15 +#define CLK_DOUT_FSYS_MMC_CARD0 16 +#define CLK_DOUT_FSYS_MMC_CARD1 17 +#define CLK_DOUT_SCAN_CLK_FSYS_125 18 +#define CLK_DOUT_FSYS_QSPI 19 +#define CLK_DOUT_FSYS_SFMC_NAND 20 +#define CLK_DOUT_FSYS_SCAN_CLK_MMC 21 +#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 22 +#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 23 +#define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK 24 +#define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK 25 +#define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK 26 +#define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK 27 +#define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0 28 +#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 29 +#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG 30 +#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 31 +#define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK 32 +#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I 33 +#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I 34 +#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5 35 +#define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND 36 +#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN 37 +#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK 38 +#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN 39 +#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK 40 +#define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN 41 +#define CLK_GOUT_FSYS_UART0_PCLK 42 +#define CLK_GOUT_FSYS_UART0_SCLK_UART 43 +#define CLK_GOUT_FSYS_BUS_QSPI 44 +#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK 45 +#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK 46 + +/* CMU_IMEM */ +#define CLK_MOUT_IMEM_ACLK_USER 1 +#define CLK_MOUT_IMEM_GIC_CA53 2 +#define CLK_MOUT_IMEM_GIC_CA5 3 +#define CLK_MOUT_IMEM_JPEG_USER 4 +#define CLK_GOUT_IMEM_MCT_PCLK 5 +#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 6 + +/* CMU_PERI */ +#define CLK_MOUT_PERI_IP_USER 1 +#define CLK_MOUT_PERI_AUDIO_USER 2 +#define CLK_MOUT_PERI_I2S0 3 +#define CLK_MOUT_PERI_I2S1 4 +#define CLK_MOUT_PERI_DISP_USER 5 +#define CLK_DOUT_PERI_SPI 6 +#define CLK_DOUT_PERI_UART1 7 +#define CLK_DOUT_PERI_UART2 8 +#define CLK_DOUT_PERI_PCLK 9 +#define CLK_DOUT_PERI_I2S0 10 +#define CLK_DOUT_PERI_I2S1 11 +#define CLK_DOUT_PERI_DSIM 12 +#define CLK_GOUT_PERI_UART1_PCLK 13 +#define CLK_GOUT_PERI_UART1_SCLK_UART 14 +#define CLK_GOUT_PERI_UART2_PCLK 15 +#define CLK_GOUT_PERI_UART2_SCLK_UART 16 +#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 17 +#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 18 +#define CLK_GOUT_PERI_SPI0_PCLK 19 +#define CLK_GOUT_PERI_SPI0_SCLK_SPI 20 +#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 21 +#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST 22 +#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST 23 +#define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK 24 +#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK 25 +#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK 26 +#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 27 +#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 28 + +#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */ -- cgit v1.2.3 From ea0484e4b82b3496310a94684dfad5e61421f633 Mon Sep 17 00:00:00 2001 From: Ravi Patel Date: Mon, 25 Aug 2025 17:14:32 +0530 Subject: dt-bindings: arm: Convert Axis board/soc bindings to json-schema Convert Axis SoC bindings to DT schema format using json-schema. Existing bindings supports ARTPEC-6 SoC and board. Signed-off-by: SungMin Park Signed-off-by: SeonGu Kang Reviewed-by: Rob Herring (Arm) Signed-off-by: Ravi Patel Link: https://lore.kernel.org/r/20250825114436.46882-7-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/axis.txt | 13 ----------- Documentation/devicetree/bindings/arm/axis.yaml | 29 +++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt deleted file mode 100644 index ebd33a88776f..000000000000 --- a/Documentation/devicetree/bindings/arm/axis.txt +++ /dev/null @@ -1,13 +0,0 @@ -Axis Communications AB -ARTPEC series SoC Device Tree Bindings - -ARTPEC-6 ARM SoC -================ - -Required root node properties: -- compatible = "axis,artpec6"; - -ARTPEC-6 Development board: ---------------------------- -Required root node properties: -- compatible = "axis,artpec6-dev-board", "axis,artpec6"; diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml new file mode 100644 index 000000000000..f9c218dc6883 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/axis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC platforms + +maintainers: + - Jesper Nilsson + - linux-arm-kernel@axis.com + +description: | + ARM platforms using SoCs designed by Axis branded as "ARTPEC". + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Axis ARTPEC-6 SoC board + items: + - enum: + - axis,artpec6-dev-board + - const: axis,artpec6 + +additionalProperties: true + +... -- cgit v1.2.3 From efad8eaf6f2f00460a2227c618ebb7c8e0dca201 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sat, 23 Aug 2025 11:49:47 +0200 Subject: dt-bindings: arm: apple: Add t8112 j415 compatible This adds the "apple,j415" (MacBook Air (15-inch, M2, 2023) to the apple,t8112 platform. Reviewed-by: Neal Gompa Reviewed-by: Sven Peter Signed-off-by: Janne Grunau Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250823-apple-dt-sync-6-17-v2-4-6dc0daeb4786@jannau.net Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/arm/apple.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index da60e9de1cfb..7073535b7c5b 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -92,6 +92,7 @@ description: | Devices based on the "M2" SoC: - MacBook Air (M2, 2022) + - MacBook Air (15-inch, M2, 2023) - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) @@ -279,6 +280,7 @@ properties: items: - enum: - apple,j413 # MacBook Air (M2, 2022) + - apple,j415 # MacBook Air (15-inch, M2, 2023) - apple,j473 # Mac mini (M2, 2023) - apple,j493 # MacBook Pro (13-inch, M2, 2022) - const: apple,t8112 -- cgit v1.2.3 From 03724b3496cb0272a5050a989ebf2494b1ff5a55 Mon Sep 17 00:00:00 2001 From: SeonGu Kang Date: Mon, 1 Sep 2025 10:49:21 +0530 Subject: dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC Document the compatible string for ARTPEC-8 SoC pinctrl block, which is similar to other Samsung SoC pinctrl blocks. Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250901051926.59970-2-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index de8460856141..9386dcd418c2 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -35,6 +35,7 @@ properties: compatible: enum: + - axis,artpec8-pinctrl - google,gs101-pinctrl - samsung,s3c2412-pinctrl - samsung,s3c2416-pinctrl -- cgit v1.2.3 From eef6dcbc52fa83c392a2f4a52845f347b233a584 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Sat, 23 Aug 2025 11:24:19 +0530 Subject: dt-bindings: gpio: Add Tegra256 support Extend the existing Tegra186 GPIO controller device tree bindings with support for the GPIO controller found on Tegra256. The number of pins is slightly different, but the programming model remains the same Add a new header, include/dt-bindings/gpio/tegra256-gpio.h, that defines port IDs as well as the TEGRA256_MAIN_GPIO() helper, both of which are used in conjunction to create a unique specifier for each pin. The OS can reconstruct the port ID and pin from these values to determine the register region for the corresponding GPIO. However, the OS does not use the macro definitions in this file. The symbolic names help associate these GPIO specifiers with the names used in the technical documentation available for the chip. Signed-off-by: Prathamesh Shete Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250823055420.24664-1-pshete@nvidia.com Signed-off-by: Bartosz Golaszewski --- .../bindings/gpio/nvidia,tegra186-gpio.yaml | 2 ++ include/dt-bindings/gpio/tegra256-gpio.h | 28 ++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 include/dt-bindings/gpio/tegra256-gpio.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 065f5761a93f..2bd620a1099b 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -85,6 +85,7 @@ properties: - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio - nvidia,tegra234-gpio-aon + - nvidia,tegra256-gpio reg-names: items: @@ -155,6 +156,7 @@ allOf: - nvidia,tegra186-gpio - nvidia,tegra194-gpio - nvidia,tegra234-gpio + - nvidia,tegra256-gpio then: properties: interrupts: diff --git a/include/dt-bindings/gpio/tegra256-gpio.h b/include/dt-bindings/gpio/tegra256-gpio.h new file mode 100644 index 000000000000..a0353a302aeb --- /dev/null +++ b/include/dt-bindings/gpio/tegra256-gpio.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for the nvidia,tegra256-gpio DT binding. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. + * The macros below provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA256_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA256_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA256_MAIN_GPIO_PORT_A 0 +#define TEGRA256_MAIN_GPIO_PORT_B 1 +#define TEGRA256_MAIN_GPIO_PORT_C 2 +#define TEGRA256_MAIN_GPIO_PORT_D 3 + +#define TEGRA256_MAIN_GPIO(port, offset) \ + ((TEGRA256_MAIN_GPIO_PORT_##port * 8) + (offset)) + +#endif + -- cgit v1.2.3 From 337ebfda8a4f2627bf52e200cacf6f3a2f5ccf48 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Fri, 22 Aug 2025 00:20:16 +0200 Subject: dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU support Rework the PowerVR Rogue GPU binding to use an explicit, per variant style for defining power domain properties and add support for the T-HEAD TH1520 SoC's GPU. To improve clarity and precision, the binding is refactored so that power domain items are listed explicitly for each variant [1]. The previous method relied on an implicit, positional mapping between the `power-domains` and `power-domain-names` properties. This change replaces the generic rules with self contained if/then blocks for each GPU variant, making the relationship between power domains and their names explicit and unambiguous. The generic if block for img,img-rogue, which previously required power-domains and power-domain-names for all variants, is removed. Instead, each specific GPU variant now defines its own power domain requirements within a self-contained if/then block, making the schema more explicit. This new structure is then used to add support for the `thead,th1520-gpu`. While its BXM-4-64 IP has two conceptual power domains, the TH1520 SoC integrates them behind a single power gate. The new binding models this with a specific rule that enforces a single `power-domains` entry and disallows the `power-domain-names` property. Link: https://lore.kernel.org/all/4d79c8dd-c5fb-442c-ac65-37e7176b0cdd@linaro.org/ [1] Reviewed-by: Krzysztof Kozlowski Reviewed-by: Matt Coster Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski Link: https://lore.kernel.org/r/20250822-apr_14_for_sending-v13-2-af656f7cc6c3@samsung.com Signed-off-by: Matt Coster --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 37 +++++++++++++++++----- 1 file changed, 29 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4450e2e73b3c..c87d7bece0ec 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -21,6 +21,11 @@ properties: # work with newer dts. - const: img,img-axe - const: img,img-rogue + - items: + - enum: + - thead,th1520-gpu + - const: img,img-bxm-4-64 + - const: img,img-rogue - items: - enum: - ti,j721s2-gpu @@ -77,14 +82,18 @@ required: additionalProperties: false allOf: - # Constraints added alongside the new compatible strings that would otherwise - # create an ABI break. - if: properties: compatible: contains: - const: img,img-rogue + const: img,img-axe-1-16m then: + properties: + power-domains: + items: + - description: Power domain A + power-domain-names: + maxItems: 1 required: - power-domains - power-domain-names @@ -93,13 +102,20 @@ allOf: properties: compatible: contains: - const: img,img-axe-1-16m + const: thead,th1520-gpu then: properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 power-domains: - maxItems: 1 - power-domain-names: - maxItems: 1 + items: + - description: The single, unified power domain for the GPU on the + TH1520 SoC, integrating all internal IP power domains. + power-domain-names: false + required: + - power-domains - if: properties: @@ -109,9 +125,14 @@ allOf: then: properties: power-domains: - minItems: 2 + items: + - description: Power domain A + - description: Power domain B power-domain-names: minItems: 2 + required: + - power-domains + - power-domain-names - if: properties: -- cgit v1.2.3 From 2596e9414e5f5917070a6c524d8e307234d3cc18 Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Mon, 21 Jul 2025 12:43:32 +0200 Subject: dt-bindings: display: sitronix,st7571: add optional inverted property Depending on which display that is connected to the controller, an "1" means either a black or a white pixel. The supported formats (R1/R2/XRGB8888) expects the pixels to map against (4bit): 00 => Black 01 => Dark Gray 10 => Light Gray 11 => White If this is not what the display map against, the controller has support to invert these values. Reviewed-by: Javier Martinez Canillas Signed-off-by: Marcus Folkesson Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250721-st7571-format-v2-2-159f4134098c@gmail.com Signed-off-by: Javier Martinez Canillas --- Documentation/devicetree/bindings/display/sitronix,st7571.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml index 4fea782fccd7..b83721eb4b7f 100644 --- a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml +++ b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml @@ -28,6 +28,11 @@ properties: description: Display supports 4-level grayscale. + sitronix,inverted: + type: boolean + description: + Display pixels are inverted, i.e. 0 is white and 1 is black. + reset-gpios: true width-mm: true height-mm: true -- cgit v1.2.3 From c68f78ae1d86a5eb9632b72f7b4f15912bff5b0f Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Mon, 21 Jul 2025 12:43:33 +0200 Subject: dt-bindings: display: sitronix,st7567: add optional inverted property Depending on which display that is connected to the controller, an "1" means either a black or a white pixel. The supported format (R1) expects the pixels to map against: 0 => Black 1 => White If this is not what the display map against, the controller has support to invert these values. Signed-off-by: Marcus Folkesson Reviewed-by: Rob Herring (Arm) Reviewed-by: Javier Martinez Canillas Link: https://lore.kernel.org/r/20250721-st7571-format-v2-3-159f4134098c@gmail.com Signed-off-by: Javier Martinez Canillas --- Documentation/devicetree/bindings/display/sitronix,st7567.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/sitronix,st7567.yaml b/Documentation/devicetree/bindings/display/sitronix,st7567.yaml index e8a5b8ad18fe..2eb6d00b5a25 100644 --- a/Documentation/devicetree/bindings/display/sitronix,st7567.yaml +++ b/Documentation/devicetree/bindings/display/sitronix,st7567.yaml @@ -23,6 +23,11 @@ properties: reg: maxItems: 1 + sitronix,inverted: + type: boolean + description: + Display pixels are inverted, i.e. 0 is white and 1 is black. + width-mm: true height-mm: true panel-timing: true -- cgit v1.2.3 From 3d13e378d465e8ae0be1697005342055b07eaf11 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Fri, 22 Aug 2025 11:20:05 +0200 Subject: dt-bindings: phy: ti,tcan104x-can: Document TI TCAN1051 TCAN1051-Q1 Automotive Fault Protected CAN Transceiver with CAN FD It is pretty much identical to the TCAN1042, add the compatible with fallback on the TCAN1042. Signed-off-by: Maud Spierings Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250822-can_phy3-v1-1-73b3ba1690ee@gocontroll.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml index 4a8c3829d85d..138923ffedfe 100644 --- a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml +++ b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml @@ -18,6 +18,7 @@ properties: - items: - enum: - microchip,ata6561 + - ti,tcan1051 - const: ti,tcan1042 - enum: - ti,tcan1042 -- cgit v1.2.3 From 63727c59a917b6ffdb13d51c251727a3e21d38d9 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Fri, 22 Aug 2025 08:44:10 +0200 Subject: dt-bindings: arm: qcom: Add Lenovo TB16 support Document the x1p-42-100/x1-26-100 variants of the Thinkbook 16 G7 QOY. [1]: https://psref.lenovo.com/syspool/Sys/PDF/ThinkBook/ThinkBook_16_G7_QOY/ThinkBook_16_G7_QOY_Spec.pdf Acked-by: Rob Herring (Arm) Signed-off-by: Jens Glathe Link: https://lore.kernel.org/r/20250822-tb16-dt-v12-1-bab6c2986351@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index fa929698229e..f0a6f6f7b839 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1066,6 +1066,7 @@ properties: - items: - enum: - asus,zenbook-a14-ux3407qa + - lenovo,thinkbook-16 - qcom,x1p42100-crd - const: qcom,x1p42100 -- cgit v1.2.3 From 5fa902fb5716f419915fdb11c6b7e62f5ba7d14f Mon Sep 17 00:00:00 2001 From: Eric Gonçalves Date: Fri, 15 Aug 2025 15:14:25 +0000 Subject: dt-bindings: arm: qcom: document r8q board binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add binding for the Samsung Galaxy S20 FE 4G/5G (SM-G980/SM-G981B) board, codenamed R8Q, which is based on the Qualcomm Snapdragon 865 SoC. Signed-off-by: Eric Gonçalves Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250815151426.32023-2-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f0a6f6f7b839..520e355d9cc9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -981,6 +981,7 @@ properties: - qcom,qrb5165-rb5 - qcom,sm8250-hdk - qcom,sm8250-mtp + - samsung,r8q - sony,pdx203-generic - sony,pdx206-generic - xiaomi,elish -- cgit v1.2.3 From 922e16d1770624e25e2c751a257c88690f121b1c Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Mon, 11 Aug 2025 23:08:09 +0200 Subject: dt-bindings: vendor-prefixes: Add Flipkart Add Flipkart to the vendor prefixes. Acked-by: Rob Herring (Arm) Signed-off-by: Cristian Cozzolino Link: https://lore.kernel.org/r/20250811-rimob-initial-devicetree-v4-1-b3194f14aa33@protonmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..b60957808e5f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -548,6 +548,8 @@ patternProperties: description: Foxconn Industrial Internet "^firefly,.*": description: Firefly + "^flipkart,.*": + description: Flipkart Inc. "^focaltech,.*": description: FocalTech Systems Co.,Ltd "^forlinx,.*": -- cgit v1.2.3 From ba4857cc649a7a113252e849fbf12bc282399480 Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Mon, 11 Aug 2025 23:08:10 +0200 Subject: dt-bindings: arm: qcom: Add Billion Capture+ Billion Capture+ (flipkart,rimob) is a smartphone based on Qualcomm Snapdragon 625 (MSM8953). Acked-by: Rob Herring (Arm) Signed-off-by: Cristian Cozzolino Link: https://lore.kernel.org/r/20250811-rimob-initial-devicetree-v4-2-b3194f14aa33@protonmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 520e355d9cc9..1221fb5f0665 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -187,6 +187,7 @@ properties: - items: - enum: + - flipkart,rimob - motorola,potter - xiaomi,daisy - xiaomi,mido -- cgit v1.2.3 From f116ec4e149e2b8a36579284af7b0630d7f57723 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 15 Jul 2025 21:26:57 -0300 Subject: dt-bindings: arm: qcom: Add Dell Inspiron 14 Plus 7441 Document the X1E80100-based Dell Inspiron 14 Plus 7441 laptop, codename: Thena. Signed-off-by: Bryan O'Donoghue Acked-by: Krzysztof Kozlowski Signed-off-by: Val Packett Reviewed-by: Laurentiu Tudor Tested-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250716003139.18543-2-val@packett.cool Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1221fb5f0665..1fc6319bec6b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1054,6 +1054,7 @@ properties: - enum: - asus,vivobook-s15 - asus,zenbook-a14-ux3407ra + - dell,inspiron-14-plus-7441 - dell,latitude-7455 - dell,xps13-9345 - hp,elitebook-ultra-g1q -- cgit v1.2.3 From faeb2bede83475fc74230d4ee4f4cc126eb6a444 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 28 Aug 2025 15:11:07 +0200 Subject: dt-bindings: soc: rockchip: add missing clock reference for rk3576-dcphy syscon The rk3576 mipi dcphy syscon controls a clock, so needs to allow the clock property. Add the missing entry in the list for it. Fixes: 0e3f3d7c7ae3 ("dt-bindings: soc: rockchip: add rk3576 mipi dcphy syscon") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202508271156.z3wDB6bX-lkp@intel.com/ Acked-by: Conor Dooley Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250828131107.3531769-1-heiko@sntech.de --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 6a94c271a6b1..1d0f35e26311 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -301,6 +301,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3576-dcphy-grf - rockchip,rk3576-vo1-grf - rockchip,rk3588-vo-grf - rockchip,rk3588-vo0-grf -- cgit v1.2.3 From af13e0089e98a135757ae46f6f9d5a96d33af840 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:03 +0000 Subject: dt-bindings: arm: rockchip: Add Radxa ROCK 2A/2F The ROCK 2A and ROCK 2F is a high-performance single board computer developed by Radxa, based on the Rockchip RK3528A SoC. Add devicetree binding documentation for the Radxa ROCK 2A and ROCK 2F boards. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717103720.2853031-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 870c318fc8d4..9c34630c11de 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -888,6 +888,13 @@ properties: - const: radxa,rock - const: rockchip,rk3188 + - description: Radxa ROCK 2A/2F + items: + - enum: + - radxa,rock-2a + - radxa,rock-2f + - const: rockchip,rk3528 + - description: Radxa ROCK Pi 4A/A+/B/B+/C items: - enum: -- cgit v1.2.3 From 10e6b1caacb85bb41cacb9271cdb794ae323ee52 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:05 +0000 Subject: dt-bindings: arm: rockchip: Add ArmSoM Sige1 The Sige1 is a single board computer developed by ArmSoM, based on the Rockchip RK3528A SoC. Add devicetree binding documentation for the ArmSoM Sige1 board. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717103720.2853031-4-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 9c34630c11de..ab4f0512da43 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -54,6 +54,11 @@ properties: - const: ariaboard,photonicat - const: rockchip,rk3568 + - description: ArmSoM Sige1 board + items: + - const: armsom,sige1 + - const: rockchip,rk3528 + - description: ArmSoM Sige5 board items: - const: armsom,sige5 -- cgit v1.2.3 From 11100e8f407e99adac2d311803540540b9726699 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:07 +0000 Subject: dt-bindings: arm: rockchip: Add FriendlyElec NanoPi Zero2 The NanoPi Zero2 is small single board computer developed by FriendlyElec, based on the Rockchip RK3528A SoC. Add devicetree binding documentation for the FriendlyElec NanoPi Zero2 board. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717103720.2853031-6-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ab4f0512da43..f9ee77f17ad7 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -325,6 +325,11 @@ properties: - friendlyarm,nanopi-r6s - const: rockchip,rk3588s + - description: FriendlyElec NanoPi Zero2 + items: + - const: friendlyarm,nanopi-zero2 + - const: rockchip,rk3528 + - description: FriendlyElec NanoPC T6 series boards items: - enum: -- cgit v1.2.3 From d5df661c9c76cb36d90527349ac6197a4baf2aba Mon Sep 17 00:00:00 2001 From: Abin Joseph Date: Mon, 25 Aug 2025 18:34:23 +0530 Subject: dt-bindings: dmaengine: xilinx_dma: Remove DMA client properties Remove DMA client section mentioned in the dt-bindings as it is not required to document client bindings in dmaengine bindings. Signed-off-by: Abin Joseph Signed-off-by: Radhey Shyam Pandey Acked-by: Rob Herring Signed-off-by: Abin Joseph Link: https://lore.kernel.org/r/20250825130423.5739-1-abin.joseph@amd.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 23 ---------------------- 1 file changed, 23 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 590d1948f202..b567107270cb 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -109,26 +109,3 @@ axi_vdma_0: axivdma@40030000 { xlnx,datawidth = <0x40>; } ; } ; - - -* DMA client - -Required properties: -- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, - where Channel ID is '0' for write/tx and '1' for read/rx - channel. For MCMDA, MM2S channel(write/tx) ID start from - '0' and is in [0-15] range. S2MM channel(read/rx) ID start - from '16' and is in [16-31] range. These channels ID are - fixed irrespective of IP configuration. - -- dma-names: a list of DMA channel names, one per "dmas" entry - -Example: -++++++++ - -vdmatest_0: vdmatest@0 { - compatible ="xlnx,axi-vdma-test-1.00.a"; - dmas = <&axi_vdma_0 0 - &axi_vdma_0 1>; - dma-names = "vdma0", "vdma1"; -} ; -- cgit v1.2.3 From 39ce725e621b256188550492b4b53fb02bfc872e Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:27 +0800 Subject: dt-bindings: dma: Add SpacemiT K1 PDMA controller Add device tree binding documentation for the SpacemiT K1 PDMA controller. Signed-off-by: Guodong Xu Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250822-working_dma_0701_v2-v5-1-f5c0eda734cc@riscstar.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/spacemit,k1-pdma.yaml | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml new file mode 100644 index 000000000000..ec06235baf5c --- /dev/null +++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/spacemit,k1-pdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PDMA Controller + +maintainers: + - Guodong Xu + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + const: spacemit,k1-pdma + + reg: + maxItems: 1 + + interrupts: + description: Shared interrupt for all DMA channels + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + dma-channels: + maximum: 16 + + '#dma-cells': + const: 1 + description: + The DMA request number for the peripheral device. + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - dma-channels + - '#dma-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dma-controller@d4000000 { + compatible = "spacemit,k1-pdma"; + reg = <0x0 0xd4000000 0x0 0x4000>; + interrupts = <72>; + clocks = <&syscon_apmu CLK_DMA>; + resets = <&syscon_apmu RESET_DMA>; + dma-channels = <16>; + #dma-cells = <1>; + }; + }; -- cgit v1.2.3 From cc0bacac6de7763a038550cf43cb94634d8be9cd Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Fri, 1 Aug 2025 10:48:22 +0200 Subject: dt-bindings: dma: rz-dmac: Document RZ/G3E family of SoCs The DMAC block on the RZ/G3E SoC is identical to the one found on the RZ/V2H(P) SoC. No driver changes are required, as `renesas,r9a09g057-dmac` will be used as a fallback compatible string on the RZ/G3E SoC. Signed-off-by: Tommaso Merciai Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20250801084825.471011-3-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index 92b12762c472..f891cfcc48c7 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -21,6 +21,11 @@ properties: - renesas,r9a08g045-dmac # RZ/G3S - const: renesas,rz-dmac + - items: + - enum: + - renesas,r9a09g047-dmac # RZ/G3E + - const: renesas,r9a09g057-dmac + - const: renesas,r9a09g057-dmac # RZ/V2H(P) reg: -- cgit v1.2.3 From 931c93119d7228f0fd08dc8dfc229d438aacfc11 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 10 Jul 2025 13:27:20 +0800 Subject: dt-bindings: arm: Add device Trace Network On Chip definition Add a new coresight-tnoc.yaml file to describe the bindings required to define Trace Network On Chip (TNOC) in device trees. TNOC is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace form subsystems and transfers to coresight sink. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yuanfang Zhang Reviewed-by: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20250710-trace-noc-v11-1-f849075c40b8@quicinc.com --- .../bindings/arm/qcom,coresight-tnoc.yaml | 113 +++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml new file mode 100644 index 000000000000..9d1c93a9ade3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tnoc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Trace Network On Chip - TNOC + +maintainers: + - Yuanfang Zhang + +description: > + The Trace Network On Chip (TNOC) is an integration hierarchy hardware + component that integrates the functionalities of TPDA and funnels. + + It sits in the different subsystem of SOC and aggregates the trace and + transports it to Aggregation TNOC or to coresight trace sink eventually. + TNOC embeds bridges for all the interfaces APB, ATB, TPDA and NTS (Narrow + Time Stamp). + + TNOC can take inputs from different trace sources i.e. ATB, TPDM. + + Note this binding is specifically intended for Aggregator TNOC instances. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tnoc + required: + - compatible + +properties: + $nodename: + pattern: "^tn(@[0-9a-f]+)$" + + compatible: + items: + - const: qcom,coresight-tnoc + - const: arm,primecell + + reg: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + clocks: + items: + - description: APB register access clock + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-9a-f]{1,2})?$': + description: Input connections from CoreSight Trace Bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: + Output connection to CoreSight Trace Bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + tn@109ab000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x109ab000 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tn_ag_in_tpdm_gcc: endpoint { + remote-endpoint = <&tpdm_gcc_out_tn_ag>; + }; + }; + }; + + out-ports { + port { + tn_ag_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_tn_ag>; + }; + }; + }; + }; +... -- cgit v1.2.3 From 6186e80a7440e0f9f45de6275b7f495ea11bd72c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 19:01:10 +0200 Subject: dt-bindings: mtd samsung-s3c2410: Drop S3C2410 support Samsung S3C24xx family of SoCs was removed from the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of its compatibles. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Signed-off-by: Miquel Raynal --- .../devicetree/bindings/mtd/samsung-s3c2410.txt | 56 ---------------------- 1 file changed, 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt b/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt deleted file mode 100644 index 635455350660..000000000000 --- a/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Samsung S3C2410 and compatible NAND flash controller - -Required properties: -- compatible : The possible values are: - "samsung,s3c2410-nand" - "samsung,s3c2412-nand" - "samsung,s3c2440-nand" -- reg : register's location and length. -- #address-cells, #size-cells : see nand-controller.yaml -- clocks : phandle to the nand controller clock -- clock-names : must contain "nand" - -Optional child nodes: -Child nodes representing the available nand chips. - -Optional child properties: -- nand-ecc-mode : see nand-controller.yaml -- nand-on-flash-bbt : see nand-controller.yaml - -Each child device node may optionally contain a 'partitions' sub-node, -which further contains sub-nodes describing the flash partition mapping. -See mtd.yaml for more detail. - -Example: - -nand-controller@4e000000 { - compatible = "samsung,s3c2440-nand"; - reg = <0x4e000000 0x40>; - - #address-cells = <1>; - #size-cells = <0>; - - clocks = <&clocks HCLK_NAND>; - clock-names = "nand"; - - nand { - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0 0x040000>; - }; - - partition@40000 { - label = "kernel"; - reg = <0x040000 0x500000>; - }; - }; - }; -}; -- cgit v1.2.3 From 1557c2eb023d9cdf97b4686fd206048c070d4e70 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 13:32:54 +0200 Subject: dt-bindings: arm: samsung: Drop S3C2416 Samsung S3C24xx family of SoCs was removed from the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles. Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250830113253.131974-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ------ 1 file changed, 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 26fe899badc5..f8e20e602c20 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -14,12 +14,6 @@ properties: const: '/' compatible: oneOf: - - description: S3C2416 based boards - items: - - enum: - - samsung,smdk2416 # Samsung SMDK2416 - - const: samsung,s3c2416 - - description: S3C6410 based boards items: - enum: -- cgit v1.2.3 From 19c5010e8ae23faf7b98fd738ff9970bb9066b78 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Aug 2025 15:54:03 +0200 Subject: dt-bindings: leds: issi,is31fl319x: Drop 'db' suffix duplicating dtschema A common property unit suffix '-db' was added to dtschema, thus in-kernel bindings should not reference the type. Signed-off-by: Krzysztof Kozlowski Acked-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250811-dt-bindings-db-v1-1-457301523bb5@linaro.org Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml b/Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml index 3c0431c51159..906735acfbaf 100644 --- a/Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml +++ b/Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml @@ -42,7 +42,6 @@ properties: description: GPIO attached to the SDB pin. audio-gain-db: - $ref: /schemas/types.yaml#/definitions/uint32 default: 0 description: Audio gain selection for external analog modulation input. enum: [0, 3, 6, 9, 12, 15, 18, 21] -- cgit v1.2.3 From d37db94b078197ec4be1cadebbfd7bf144e3c5e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 13:16:59 +0200 Subject: dt-bindings: pinctrl: samsung: Drop S3C2410 Samsung S3C24xx family of SoCs was removed the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles. Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250830111657.126190-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 19 +------------------ .../devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 4 ---- 2 files changed, 1 insertion(+), 22 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 0da6d69f5991..dd11c73a55da 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -30,8 +30,6 @@ properties: compatible: oneOf: - enum: - - samsung,s3c2410-wakeup-eint - - samsung,s3c2412-wakeup-eint - samsung,s3c64xx-wakeup-eint - samsung,s5pv210-wakeup-eint - samsung,exynos4210-wakeup-eint @@ -59,27 +57,12 @@ properties: description: Interrupt used by multiplexed external wake-up interrupts. minItems: 1 - maxItems: 6 + maxItems: 4 required: - compatible allOf: - - if: - properties: - compatible: - contains: - enum: - - samsung,s3c2410-wakeup-eint - - samsung,s3c2412-wakeup-eint - then: - properties: - interrupts: - minItems: 6 - maxItems: 6 - required: - - interrupts - - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 9386dcd418c2..f1094d65e846 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -37,10 +37,6 @@ properties: enum: - axis,artpec8-pinctrl - google,gs101-pinctrl - - samsung,s3c2412-pinctrl - - samsung,s3c2416-pinctrl - - samsung,s3c2440-pinctrl - - samsung,s3c2450-pinctrl - samsung,s3c64xx-pinctrl - samsung,s5pv210-pinctrl - samsung,exynos2200-pinctrl -- cgit v1.2.3 From d6900b8bd362b68c66312ea8200bc0c61c4ef542 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Fri, 29 Aug 2025 13:06:02 +0800 Subject: dt-bindings: ptp: add NETC Timer PTP clock NXP NETC (Ethernet Controller) is a multi-function PCIe Root Complex Integrated Endpoint (RCiEP), the Timer is one of its functions which provides current time with nanosecond resolution, precise periodic pulse, pulse on timeout (alarm), and time capture on external pulse support. And also supports time synchronization as required for IEEE 1588 and IEEE 802.1AS-2020. So add device tree binding doc for the PTP clock based on NETC Timer. NETC Timer has three reference clock sources, but the clock mux is inside the IP. Therefore, the driver will parse the clock name to select the desired clock source. If the clocks property is not present, NETC Timer will use the system clock of NETC IP as its reference clock. Because the Timer is a PCIe function of NETC IP, the system clock of NETC is always available to the Timer. Signed-off-by: Wei Fang Reviewed-by: Frank Li Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250829050615.1247468-2-wei.fang@nxp.com Signed-off-by: Paolo Abeni --- .../devicetree/bindings/ptp/nxp,ptp-netc.yaml | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml b/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml new file mode 100644 index 000000000000..042de9d5a92b --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/nxp,ptp-netc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP NETC V4 Timer PTP clock + +description: + NETC V4 Timer provides current time with nanosecond resolution, precise + periodic pulse, pulse on timeout (alarm), and time capture on external + pulse support. And it supports time synchronization as required for + IEEE 1588 and IEEE 802.1AS-2020. + +maintainers: + - Wei Fang + - Clark Wang + +properties: + compatible: + enum: + - pci1131,ee02 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + The reference clock of NETC Timer, can be selected between 3 different + clock sources using an integrated hardware mux TMR_CTRL[CK_SEL]. + The "ccm" means the reference clock comes from CCM of SoC. + The "ext" means the reference clock comes from external IO pins. + If not present, indicates that the system clock of NETC IP is selected + as the reference clock. + + clock-names: + enum: + - ccm + - ext + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/pci/pci-device.yaml + +unevaluatedProperties: false + +examples: + - | + pcie { + #address-cells = <3>; + #size-cells = <2>; + + ptp-timer@18,0 { + compatible = "pci1131,ee02"; + reg = <0x00c000 0 0 0 0>; + clocks = <&scmi_clk 18>; + clock-names = "ccm"; + }; + }; -- cgit v1.2.3 From db2d2de1c2a80ba2617246ca1a7b0ffd117e0783 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Fri, 29 Aug 2025 13:06:03 +0800 Subject: dt-bindings: net: move ptp-timer property to ethernet-controller.yaml For some Ethernet controllers, the PTP timer function is not integrated. Instead, the PTP timer is a separate device and provides PTP Hardware Clock (PHC) to the Ethernet controller to use, such as NXP FMan MAC, ENETC, etc. Therefore, a property is needed to indicate this hardware relationship between the Ethernet controller and the PTP timer. Since this use case is also very common, it is better to add a generic property to ethernet-controller.yaml. According to the existing binding docs, there are two good candidates, one is the "ptp-timer" defined in fsl,fman-dtsec.yaml, and the other is the "ptimer-handle" defined in fsl,fman.yaml. From the perspective of the name, the former is more straightforward, so move the "ptp-timer" from fsl,fman-dtsec.yaml to ethernet-controller.yaml. Signed-off-by: Wei Fang Reviewed-by: Vladimir Oltean Reviewed-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250829050615.1247468-3-wei.fang@nxp.com Signed-off-by: Paolo Abeni --- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 5 +++++ Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml | 4 ---- 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 66b1cfbbfe22..2c924d296a8f 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -108,6 +108,11 @@ properties: $ref: "#/properties/phy-handle" deprecated: true + ptp-timer: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Specifies a reference to a node representing an IEEE 1588 PTP device. + rx-fifo-depth: $ref: /schemas/types.yaml#/definitions/uint32 description: diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml index 60aaf30d68ed..ef1e30a48c91 100644 --- a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml @@ -81,10 +81,6 @@ properties: An array of two references: the first is the FMan RX port and the second is the TX port used by this MAC. - ptp-timer: - $ref: /schemas/types.yaml#/definitions/phandle - description: A reference to the IEEE1588 timer - phys: description: A reference to the SerDes lane(s) maxItems: 1 -- cgit v1.2.3 From 2c01536aae3e3591f27b945e85fc6b92f789580c Mon Sep 17 00:00:00 2001 From: Leo Wang Date: Wed, 13 Aug 2025 18:04:13 +0800 Subject: dt-bindings: arm: aspeed: add Meta Clemente board Document the new compatibles used on Meta Clemente. Acked-by: Conor Dooley Signed-off-by: Leo Wang Link: https://patch.msgid.link/20250813-add-support-for-meta-clemente-bmc-v11-1-8970d41f88b0@fii-foxconn.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index b3c9d3310d57..aedefca7cf4a 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -82,6 +82,7 @@ properties: - asus,x4tf-bmc - facebook,bletchley-bmc - facebook,catalina-bmc + - facebook,clemente-bmc - facebook,cloudripper-bmc - facebook,darwin-bmc - facebook,elbert-bmc -- cgit v1.2.3 From 8f48b160e1b8f0c959e25df63994e6204b3794a8 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 2 Sep 2025 15:00:40 +0100 Subject: ASoC: dt-bindings: qcom,sm8250: Add glymur sound card Document the bindings for the glymur sound card which is audioreach based architecture. Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Message-ID: <20250902140044.54508-3-srinivas.kandagatla@oss.qualcomm.com> Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/qcom,sm8250.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index 5d3dbb6cb1ae..8ac91625dce5 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -31,6 +31,7 @@ properties: - fairphone,fp4-sndcard - fairphone,fp5-sndcard - qcom,apq8096-sndcard + - qcom,glymur-sndcard - qcom,qcm6490-idp-sndcard - qcom,qcs6490-rb3gen2-sndcard - qcom,qcs8275-sndcard -- cgit v1.2.3 From 25436580f025d42bd7ccf3b960f4c405f3c91512 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 2 Sep 2025 15:00:42 +0100 Subject: ASoC: dt-bindings: qcom: Add Glymur LPASS wsa and va macro codecs Document compatibles for Qualcomm Glymur SoC macro digital codecs (VA and WSA), compatible with previous generation (SM8550 and SM8650). Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Message-ID: <20250902140044.54508-5-srinivas.kandagatla@oss.qualcomm.com> Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml | 1 + Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index dd549db6c841..2e8c26d89b00 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc8280xp-lpass-va-macro - items: - enum: + - qcom,glymur-lpass-va-macro - qcom,sm8650-lpass-va-macro - qcom,sm8750-lpass-va-macro - qcom,x1e80100-lpass-va-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml index 9082e363c709..b6f5ba5d1320 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc8280xp-lpass-wsa-macro - items: - enum: + - qcom,glymur-lpass-wsa-macro - qcom,sm8650-lpass-wsa-macro - qcom,sm8750-lpass-wsa-macro - qcom,x1e80100-lpass-wsa-macro -- cgit v1.2.3 From 72243ced3d861f99368ad2edcdce4d71c7108d16 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Sat, 30 Aug 2025 10:53:26 +0200 Subject: dt-bindings: input: tsc2007: use comma in filename Use comma between vendor-prefix and chip name as it is common. Signed-off-by: Andreas Kemnade Fixes: 45601c66b5dd ("dt-bindings: input: touchscreen: convert tsc2007.txt to yaml format") Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250830085326.36120-1-akemnade@kernel.org Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/ti,tsc2007.yaml | 75 ++++++++++++++++++++++ .../bindings/input/touchscreen/ti.tsc2007.yaml | 75 ---------------------- 2 files changed, 75 insertions(+), 75 deletions(-) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/ti.tsc2007.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml b/Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml new file mode 100644 index 000000000000..a73d110272fa --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/ti,tsc2007.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments tsc2007 touchscreen controller + +maintainers: + - Frank Li + +properties: + compatible: + const: ti,tsc2007 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ti,x-plate-ohms: + description: X-plate resistance in ohms. + + gpios: true + + pendown-gpio: true + + ti,max-rt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: maximum pressure. + + ti,fuzzx: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + specifies the absolute input fuzz x value. + If set, it will permit noise in the data up to +- the value given to the fuzz + parameter, that is used to filter noise from the event stream. + + ti,fuzzy: + $ref: /schemas/types.yaml#/definitions/uint32 + description: specifies the absolute input fuzz y value. + + ti,fuzzz: + $ref: /schemas/types.yaml#/definitions/uint32 + description: specifies the absolute input fuzz z value. + + ti,poll-period: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + how much time to wait (in milliseconds) before reading again the + values from the tsc2007. + +required: + - compatible + - reg + - ti,x-plate-ohms + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touch@49 { + compatible = "ti,tsc2007"; + reg = <0x49>; + interrupt-parent = <&gpio4>; + interrupts = <0x0 0x8>; + gpios = <&gpio4 0 0>; + ti,x-plate-ohms = <180>; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti.tsc2007.yaml b/Documentation/devicetree/bindings/input/touchscreen/ti.tsc2007.yaml deleted file mode 100644 index 8bb4bc7df4fa..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/ti.tsc2007.yaml +++ /dev/null @@ -1,75 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/input/touchscreen/ti.tsc2007.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Texas Instruments tsc2007 touchscreen controller - -maintainers: - - Frank Li - -properties: - compatible: - const: ti,tsc2007 - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - ti,x-plate-ohms: - description: X-plate resistance in ohms. - - gpios: true - - pendown-gpio: true - - ti,max-rt: - $ref: /schemas/types.yaml#/definitions/uint32 - description: maximum pressure. - - ti,fuzzx: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - specifies the absolute input fuzz x value. - If set, it will permit noise in the data up to +- the value given to the fuzz - parameter, that is used to filter noise from the event stream. - - ti,fuzzy: - $ref: /schemas/types.yaml#/definitions/uint32 - description: specifies the absolute input fuzz y value. - - ti,fuzzz: - $ref: /schemas/types.yaml#/definitions/uint32 - description: specifies the absolute input fuzz z value. - - ti,poll-period: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - how much time to wait (in milliseconds) before reading again the - values from the tsc2007. - -required: - - compatible - - reg - - ti,x-plate-ohms - -additionalProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - touch@49 { - compatible = "ti,tsc2007"; - reg = <0x49>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 0x8>; - gpios = <&gpio4 0 0>; - ti,x-plate-ohms = <180>; - }; - }; -- cgit v1.2.3 From c1b52451b604b7700419a48cf2f146ebacd9af57 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 22 Aug 2025 18:32:45 -0300 Subject: dt-bindings: input: touchscreen: tsc2007: Document 'wakeup-source' The 'wakeup-source' property is used by many devicetree files and is also supported by the tsc2007_core driver. Document it to avoid the following dt-schema warning: 'wakeup-source' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Fabio Estevam Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250822213245.125901-1-festevam@gmail.com Signed-off-by: Dmitry Torokhov --- Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml b/Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml index a73d110272fa..a595df3ea802 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/ti,tsc2007.yaml @@ -26,6 +26,8 @@ properties: pendown-gpio: true + wakeup-source: true + ti,max-rt: $ref: /schemas/types.yaml#/definitions/uint32 description: maximum pressure. -- cgit v1.2.3 From 835bdddd028ff57afaee28eb5e4b260f714fd555 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 19 Aug 2025 12:53:16 -0400 Subject: dt-bindings: soc: add vf610 reboot syscon controller Add vf610 reboot controller, which used to reboot whole system. Fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/vf/vf610-bk4.dtb: /soc/bus@40000000/src@4006e000: failed to match any schema with compatible: ['fsl,vf610-src', 'syscon'] IC reference manual calls it as system reset controller(SRC), but it is not module as reset controller, which used to reset individual device. SRC works as reboot controller, which reboots whole system. It provides a syscon interface to syscon-reboot. Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250819165317.3739366-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/soc/fsl/fsl,vf610-src.yaml | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/fsl,vf610-src.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,vf610-src.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,vf610-src.yaml new file mode 100644 index 000000000000..6fb93e8be929 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,vf610-src.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,vf610-src.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale vf610 System Reset Controller (SRC) + +maintainers: + - Frank Li + +description: + IC reference manual calls it as SRC, but it is not module as reset + controller, which used to reset individual device. SRC works as reboot + controller, which reboots whole system. It provides a syscon interface to + syscon-reboot. + +properties: + compatible: + items: + - enum: + - fsl,vf610-src + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + syscon@4006e000 { + compatible = "fsl,vf610-src", "syscon"; + reg = <0x4006e000 0x1000>; + interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; + }; + -- cgit v1.2.3 From 81bb4d07edd72a56180e2c8414ead0e63c379502 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 18 Aug 2025 15:25:35 +0200 Subject: docs: dt: writing-bindings: Document node name ABI and simple-mfd Document established Devicetree bindings maintainers review practice: 1. Device node names should not be treated as an ABI, unless for children of a device when documented. There were many patches posted using of_find_node_by_name() or of_node_name_eq() for accessing siblings or completely different nodes. These cases were introducing undocumented ABI, so they are discouraged. 2. 'simple-mfd' means children do not depend on parent device resources. 'simple-bus' is so simple, that even 'reg' properties are not applicable. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250818132534.120217-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/writing-bindings.rst | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index f8e0293a7c06..667816dd7d50 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -31,10 +31,19 @@ Overall design devices only need child nodes when the child nodes have their own DT resources. A single node can be multiple providers (e.g. clocks and resets). +- DON'T treat device node names as a stable ABI, but instead use phandles or + compatibles to find sibling devices. Exception: sub-nodes of given device + could be treated as ABI, if explicitly documented in the bindings. + - DON'T use 'syscon' alone without a specific compatible string. A 'syscon' hardware block should have a compatible string unique enough to infer the register layout of the entire block (at a minimum). +- DON'T use 'simple-mfd' compatible for non-trivial devices, where children + depend on some resources from the parent. Similarly, 'simple-bus' should not + be used for complex buses and even 'regs' property means device is not + a simple bus. + Properties ========== -- cgit v1.2.3 From 75592f9e178915867829b7ec6eb20125924a4814 Mon Sep 17 00:00:00 2001 From: Santosh Mahto Date: Wed, 20 Aug 2025 23:40:13 +0530 Subject: docs: devicetree: fix typo in writing-schema.rst MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes a spelling mistake in writing-schema.rst: "interpretted" → "interpreted" Signed-off-by: Santosh Mahto Link: https://lore.kernel.org/r/20250820181013.17817-1-eisantosh95@gmail.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/writing-schema.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index 470d1521fa17..fcd4726f8df4 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -53,7 +53,7 @@ description The default without any indicators is flowed, plain scalar style where single line breaks and leading whitespace are stripped. Paragraphs are delimited by blank lines (i.e. double line break). This style cannot contain ": " in it as - it will be interpretted as a key. Any " #" sequence will be interpretted as + it will be interpreted as a key. Any " #" sequence will be interpreted as a comment. There's other restrictions on characters as well. Most restrictions are on what the first character can be. -- cgit v1.2.3 From a6dcff26eb4dcb9178917c8c49b10265ee5f749c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 26 Apr 2024 14:54:37 -0500 Subject: yamllint: Drop excluding quoted values with ',' from checks Strings with commas were excluded from checks because yamllint had false positives for flow style maps and sequences which need quotes when values contain commas. This issue has been fixed as of the 1.34 release, so drop the work-around. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20240426195438.2771968-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/.yamllint | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/.yamllint b/Documentation/devicetree/bindings/.yamllint index fea5231e1320..532799501800 100644 --- a/Documentation/devicetree/bindings/.yamllint +++ b/Documentation/devicetree/bindings/.yamllint @@ -4,7 +4,7 @@ rules: quoted-strings: required: only-when-needed extra-allowed: - - '[$^,[]' + - '[$^[]' - '^/$' line-length: # 80 chars should be enough, but don't fail if a line is longer -- cgit v1.2.3 From 955212b1e4ac3f299c411ccd68cc702e55c4762d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 20 Aug 2025 16:17:36 +0200 Subject: dt-bindings: display: ingenic,jz4780-hdmi: Add missing clock-names The binding references synopsys,dw-hdmi.yaml schema which defines both 'clocks' and 'clock-names' with variable length, therefore we need here also same constraint for 'clock-names' as for 'clocks'. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250820-dt-bindings-display-v2-1-91e2ccba3d4e@linaro.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml index 0b27df429bdc..84df3cf239d5 100644 --- a/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml @@ -26,6 +26,9 @@ properties: clocks: maxItems: 2 + clock-names: + maxItems: 2 + ports: $ref: /schemas/graph.yaml#/properties/ports -- cgit v1.2.3 From 0387040b31aa6606cd9ef726ce4b11c5fa6079db Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 20 Aug 2025 16:17:37 +0200 Subject: dt-bindings: display: ti,tdp158: Add missing reg constraint Device can be used over I2C bus, so it documents 'reg' property, however it misses to constrain it to actual I2C address. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250820-dt-bindings-display-v2-2-91e2ccba3d4e@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml b/Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml index 1c522f72c4ba..721da44054e1 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml @@ -17,6 +17,7 @@ properties: # The reg property is required if and only if the device is connected # to an I2C bus. In pin strap mode, reg must not be specified. reg: + maxItems: 1 description: I2C address of the device # Pin 36 = Operation Enable / Reset Pin -- cgit v1.2.3 From 0e44780b423afed8c35005b31536a7bb3c52f70f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 20 Aug 2025 16:17:38 +0200 Subject: dt-bindings: display: rockchip,dw-mipi-dsi: Narrow clocks for rockchip,rk3288-mipi-dsi The binding allows in top-level from one to four clocks and each variant narrows the choice, but rockchip,rk3288-mipi-dsi missed the minItems. Reviewed-by: Heiko Stuebner Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250820-dt-bindings-display-v2-3-91e2ccba3d4e@linaro.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index 0881e82deb11..c59df3c1a3f7 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -97,9 +97,11 @@ allOf: then: properties: clocks: + minItems: 2 maxItems: 2 clock-names: + minItems: 2 maxItems: 2 - if: -- cgit v1.2.3 From 4ed46073274a5b23baf0b992c459762e28faf549 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 21 Aug 2025 17:21:33 -0500 Subject: dt-bindings: vendor-prefixes: Add undocumented vendor prefixes Add various vendor prefixes which are in use in compatible strings already. These were found by modifying vendor-prefixes.yaml into a schema to check compatible strings. The added prefixes doesn't include various duplicate prefixes in use such as "lge". Link: https://lore.kernel.org/r/20250821222136.1027269-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/vendor-prefixes.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..0f5273123650 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -86,6 +86,8 @@ patternProperties: description: Allegro DVT "^allegromicro,.*": description: Allegro MicroSystems, Inc. + "^alliedtelesis,.*": + description: Allied Telesis, Inc. "^alliedvision,.*": description: Allied Vision Technologies GmbH "^allo,.*": @@ -229,6 +231,8 @@ patternProperties: description: Bitmain Technologies "^blaize,.*": description: Blaize, Inc. + "^bluegiga,.*": + description: Bluegiga Technologies Ltd. "^blutek,.*": description: BluTek Power "^boe,.*": @@ -247,6 +251,8 @@ patternProperties: description: Bticino International "^buffalo,.*": description: Buffalo, Inc. + "^buglabs,.*": + description: Bug Labs, Inc. "^bur,.*": description: B&R Industrial Automation GmbH "^bytedance,.*": @@ -325,6 +331,8 @@ patternProperties: description: Conexant Systems, Inc. "^colorfly,.*": description: Colorful GRP, Shenzhen Xueyushi Technology Ltd. + "^compal,.*": + description: Compal Electronics, Inc. "^compulab,.*": description: CompuLab Ltd. "^comvetia,.*": @@ -353,6 +361,8 @@ patternProperties: description: Guangzhou China Star Optoelectronics Technology Co., Ltd "^csq,.*": description: Shenzen Chuangsiqi Technology Co.,Ltd. + "^csr,.*": + description: Cambridge Silicon Radio "^ctera,.*": description: CTERA Networks Intl. "^ctu,.*": @@ -455,6 +465,8 @@ patternProperties: description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc + "^egnite,.*": + description: egnite GmbH "^einfochips,.*": description: Einfochips "^eink,.*": @@ -485,8 +497,12 @@ patternProperties: description: Empire Electronix "^emtrion,.*": description: emtrion GmbH + "^enbw,.*": + description: Energie Baden-Württemberg AG "^enclustra,.*": description: Enclustra GmbH + "^endian,.*": + description: Endian SRL "^endless,.*": description: Endless Mobile, Inc. "^ene,.*": @@ -552,6 +568,8 @@ patternProperties: description: FocalTech Systems Co.,Ltd "^forlinx,.*": description: Baoding Forlinx Embedded Technology Co., Ltd. + "^foxlink,.*": + description: Foxlink Group "^freebox,.*": description: Freebox SAS "^freecom,.*": @@ -640,6 +658,10 @@ patternProperties: description: Haoyu Microelectronic Co. Ltd. "^hardkernel,.*": description: Hardkernel Co., Ltd + "^hce,.*": + description: HCE Engineering SRL + "^headacoustics,.*": + description: HEAD acoustics "^hechuang,.*": description: Shenzhen Hechuang Intelligent Co. "^hideep,.*": @@ -723,6 +745,8 @@ patternProperties: description: Shenzhen INANBO Electronic Technology Co., Ltd. "^incircuit,.*": description: In-Circuit GmbH + "^incostartec,.*": + description: INCOstartec GmbH "^indiedroid,.*": description: Indiedroid "^inet-tek,.*": @@ -931,6 +955,8 @@ patternProperties: description: Maxim Integrated Products "^maxlinear,.*": description: MaxLinear Inc. + "^maxtor,.*": + description: Maxtor Corporation "^mbvl,.*": description: Mobiveil Inc. "^mcube,.*": @@ -1094,6 +1120,8 @@ patternProperties: description: Nordic Semiconductor "^nothing,.*": description: Nothing Technology Limited + "^novatech,.*": + description: NovaTech Automation "^novatek,.*": description: Novatek "^novtech,.*": @@ -1189,6 +1217,8 @@ patternProperties: description: Pervasive Displays, Inc. "^phicomm,.*": description: PHICOMM Co., Ltd. + "^phontech,.*": + description: Phontech "^phytec,.*": description: PHYTEC Messtechnik GmbH "^picochip,.*": @@ -1273,6 +1303,8 @@ patternProperties: description: Ramtron International "^raspberrypi,.*": description: Raspberry Pi Foundation + "^raumfeld,.*": + description: Raumfeld GmbH "^raydium,.*": description: Raydium Semiconductor Corp. "^rda,.*": @@ -1311,6 +1343,8 @@ patternProperties: description: ROHM Semiconductor Co., Ltd "^ronbo,.*": description: Ronbo Electronics + "^ronetix,.*": + description: Ronetix GmbH "^roofull,.*": description: Shenzhen Roofull Technology Co, Ltd "^roseapplepi,.*": @@ -1337,8 +1371,12 @@ patternProperties: description: Schindler "^schneider,.*": description: Schneider Electric + "^schulercontrol,.*": + description: Schuler Group "^sciosense,.*": description: ScioSense B.V. + "^sdmc,.*": + description: SDMC Technology Co., Ltd "^seagate,.*": description: Seagate Technology PLC "^seeed,.*": @@ -1377,6 +1415,8 @@ patternProperties: description: Si-En Technology Ltd. "^si-linux,.*": description: Silicon Linux Corporation + "^sielaff,.*": + description: Sielaff GmbH & Co. "^siemens,.*": description: Siemens AG "^sifive,.*": @@ -1445,6 +1485,8 @@ patternProperties: description: SolidRun "^solomon,.*": description: Solomon Systech Limited + "^somfy,.*": + description: Somfy Systems Inc. "^sony,.*": description: Sony Corporation "^sophgo,.*": @@ -1515,6 +1557,8 @@ patternProperties: "^synopsys,.*": description: Synopsys, Inc. (deprecated, use snps) deprecated: true + "^taos,.*": + description: Texas Advanced Optoelectronic Solutions Inc. "^tbs,.*": description: TBS Technologies "^tbs-biometrics,.*": @@ -1545,6 +1589,8 @@ patternProperties: description: Teltonika Networks "^tempo,.*": description: Tempo Semiconductor + "^tenda,.*": + description: Shenzhen Tenda Technology Co., Ltd. "^terasic,.*": description: Terasic Inc. "^tesla,.*": @@ -1648,6 +1694,8 @@ patternProperties: description: V3 Semiconductor "^vaisala,.*": description: Vaisala + "^valve,.*": + description: Valve Corporation "^vamrs,.*": description: Vamrs Ltd. "^variscite,.*": @@ -1748,6 +1796,8 @@ patternProperties: description: Extreme Engineering Solutions (X-ES) "^xiaomi,.*": description: Xiaomi Technology Co., Ltd. + "^xicor,.*": + description: Xicor Inc. "^xillybus,.*": description: Xillybus Ltd. "^xingbangda,.*": -- cgit v1.2.3 From 8a72549c5b276849def80057a4b4789dbdb87ea6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 23 Aug 2025 18:32:59 +0200 Subject: dt-bindings: interrupt-controller: marvell,cp110-icu: Document address-cells The CP110 ICU children are interrupt controllers and can be referenced in interrupt-map properties (e.g. in arch/arm64/boot/dts/marvell/armada-cp11x.dtsi), thus the nodes should have address-cells property. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Miquel Raynal Link: https://lore.kernel.org/r/20250823163258.49648-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml index 9d4f06f45372..ddfce217e119 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml @@ -49,6 +49,9 @@ patternProperties: reg: maxItems: 1 + '#address-cells': + const: 0 + '#interrupt-cells': const: 2 -- cgit v1.2.3 From f0aed6ffb3548a03dab9e608b2bd8ce07af4be9f Mon Sep 17 00:00:00 2001 From: Harikrishna Shenoy Date: Wed, 27 Aug 2025 16:55:39 +0530 Subject: dt-bindings: display: dsi-controller: add bridge to patternProperties Extend the DSI controller schema to allow bridge child nodes. This makes it possible to describe external bridge devices directly connected as DSI peripherals. Signed-off-by: Harikrishna Shenoy Link: https://lore.kernel.org/r/20250827112539.4001513-1-h-shenoy@ti.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/dsi-controller.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/dsi-controller.yaml b/Documentation/devicetree/bindings/display/dsi-controller.yaml index 67ce10307ee0..bb4d6e9e7d0c 100644 --- a/Documentation/devicetree/bindings/display/dsi-controller.yaml +++ b/Documentation/devicetree/bindings/display/dsi-controller.yaml @@ -46,7 +46,7 @@ properties: const: 0 patternProperties: - "^panel@[0-3]$": + "^(panel|bridge)@[0-3]$": description: Panels connected to the DSI link type: object -- cgit v1.2.3 From 8b57a0aeccb1d31b82210384b1f2a3226145635f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 27 Aug 2025 17:09:11 -0400 Subject: dt-bindings: arm: cpus: Allow fsl,soc-operating-points for i.MX6 The old i.MX6 (over 10 years) chip use fsl,soc-operating-points to get SoC's voltage and frequency information when cpu change frequency. Set fsl,soc-operating-points deprecated. Allow soc-supply property and set it deprecated. Fix bunch of CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('fsl,soc-operating-points', 'soc-supply' were unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250827210912.92029-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index bb1ab514924d..78cc920e83d4 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -347,10 +347,23 @@ properties: deprecated: true description: Use 'cpu-supply' instead + soc-supply: + deprecated: true + description: Only for i.MX6/7 Soc. + sram-supply: deprecated: true description: Use 'mem-supply' instead + fsl,soc-operating-points: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: FSL i.MX6 Soc operation-points when change cpu frequency + deprecated: true + items: + items: + - description: Frequency in kHz + - description: Voltage for OPP in uV + mediatek,cci: $ref: /schemas/types.yaml#/definitions/phandle description: Link to Mediatek Cache Coherent Interconnect -- cgit v1.2.3 From 0f356eb097c314710060dde9c4fae4fd516bc63a Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 21 Aug 2025 13:06:40 -0500 Subject: dt-bindings: arm: Add Cortex-A320/A520AE/A720AE cores and PMU Add the recently introduced Cortex-A320/A520AE/A720AE core and PMU compatible strings. Link: https://lore.kernel.org/all/20250821190722.417639-1-robh@kernel.org/ Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 3 +++ Documentation/devicetree/bindings/arm/pmu.yaml | 3 +++ 2 files changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 78cc920e83d4..b1c6943e7d78 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -145,11 +145,14 @@ properties: - arm,cortex-a78 - arm,cortex-a78ae - arm,cortex-a78c + - arm,cortex-a320 - arm,cortex-a510 - arm,cortex-a520 + - arm,cortex-a520ae - arm,cortex-a710 - arm,cortex-a715 - arm,cortex-a720 + - arm,cortex-a720ae - arm,cortex-a725 - arm,cortex-m0 - arm,cortex-m0+ diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 295963a3cae7..9bb109e947dd 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -48,11 +48,14 @@ properties: - arm,cortex-a76-pmu - arm,cortex-a77-pmu - arm,cortex-a78-pmu + - arm,cortex-a320-pmu - arm,cortex-a510-pmu - arm,cortex-a520-pmu + - arm,cortex-a520ae-pmu - arm,cortex-a710-pmu - arm,cortex-a715-pmu - arm,cortex-a720-pmu + - arm,cortex-a720ae-pmu - arm,cortex-a725-pmu - arm,cortex-x1-pmu - arm,cortex-x2-pmu -- cgit v1.2.3 From 8e322143c30483a646f6e09434ebf0e33b315a4f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 13:32:39 +0200 Subject: dt-bindings: display: samsung: Drop S3C2410 Samsung S3C24xx family of SoCs was removed from Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250830113238.131006-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml index 075231716b2f..ff685031bb2c 100644 --- a/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml +++ b/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml @@ -15,7 +15,6 @@ maintainers: properties: compatible: enum: - - samsung,s3c2443-fimd - samsung,s3c6400-fimd - samsung,s5pv210-fimd - samsung,exynos3250-fimd -- cgit v1.2.3 From 93674298bede84898742f4f8836666a2bfd0ece4 Mon Sep 17 00:00:00 2001 From: Masaharu Noguchi Date: Tue, 2 Sep 2025 00:48:12 +0900 Subject: Documentation: fix typo 'Andorid' -> 'Android' in goldfish pipe binding This patch fixes a small typo in the goldfish pipe binding documentation: 'Andorid' -> 'Android'. Signed-off-by: Masaharu Noguchi Link: https://lore.kernel.org/r/20250901154812.570319-1-nogunix@gmail.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/goldfish/pipe.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/goldfish/pipe.txt b/Documentation/devicetree/bindings/goldfish/pipe.txt index e417a31a1ee3..5637ce701788 100644 --- a/Documentation/devicetree/bindings/goldfish/pipe.txt +++ b/Documentation/devicetree/bindings/goldfish/pipe.txt @@ -1,6 +1,6 @@ Android Goldfish QEMU Pipe -Andorid pipe virtual device generated by android emulator. +Android pipe virtual device generated by android emulator. Required properties: -- cgit v1.2.3 From 279ea197d9bd56d2a4d0058a55fd0eb88626ad6a Mon Sep 17 00:00:00 2001 From: Taishi Shimizu Date: Sun, 13 Jul 2025 16:18:24 +0900 Subject: dt-bindings: arm: bcm: Add support for Buffalo WXR-1750DHP Add Buffalo WXR-1750DHP under BCM4708 based boards. Signed-off-by: Taishi Shimizu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250713071826.726682-2-s.taishi14142@gmail.com Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index d925e7a3b5ef..f47d74a5b0b6 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -25,6 +25,7 @@ properties: - enum: - asus,rt-ac56u - asus,rt-ac68u + - buffalo,wxr-1750dhp - buffalo,wzr-1166dhp - buffalo,wzr-1166dhp2 - buffalo,wzr-1750dhp -- cgit v1.2.3 From a4c2ff6e507ebb47761865289772494e717d035a Mon Sep 17 00:00:00 2001 From: Ranganath V N Date: Wed, 3 Sep 2025 01:08:22 +0530 Subject: Documentation: Fix spelling mistakes Corrected a few spelling mistakes to improve the readability. Signed-off-by: Ranganath V N Acked-by: Rob Herring (Arm) Reviewed-by: Randy Dunlap Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20250902193822.6349-1-vnranganath.20@gmail.com --- Documentation/devicetree/bindings/submitting-patches.rst | 2 +- Documentation/filesystems/iomap/operations.rst | 2 +- Documentation/virt/kvm/review-checklist.rst | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/submitting-patches.rst b/Documentation/devicetree/bindings/submitting-patches.rst index 46d0b036c97e..191085b0d5e8 100644 --- a/Documentation/devicetree/bindings/submitting-patches.rst +++ b/Documentation/devicetree/bindings/submitting-patches.rst @@ -66,7 +66,7 @@ I. For patch submitters any DTS patches, regardless whether using existing or new bindings, should be placed at the end of patchset to indicate no dependency of drivers on the DTS. DTS will be anyway applied through separate tree or branch, so - different order would indicate the serie is non-bisectable. + different order would indicate the series is non-bisectable. If a driver subsystem maintainer prefers to apply entire set, instead of their relevant portion of patchset, please split the DTS patches into diff --git a/Documentation/filesystems/iomap/operations.rst b/Documentation/filesystems/iomap/operations.rst index 067ed8e14ef3..387fd9cc72ca 100644 --- a/Documentation/filesystems/iomap/operations.rst +++ b/Documentation/filesystems/iomap/operations.rst @@ -321,7 +321,7 @@ The fields are as follows: - ``writeback_submit``: Submit the previous built writeback context. Block based file systems should use the iomap_ioend_writeback_submit helper, other file system can implement their own. - File systems can optionall to hook into writeback bio submission. + File systems can optionally hook into writeback bio submission. This might include pre-write space accounting updates, or installing a custom ``->bi_end_io`` function for internal purposes, such as deferring the ioend completion to a workqueue to run metadata update diff --git a/Documentation/virt/kvm/review-checklist.rst b/Documentation/virt/kvm/review-checklist.rst index debac54e14e7..053f00c50d66 100644 --- a/Documentation/virt/kvm/review-checklist.rst +++ b/Documentation/virt/kvm/review-checklist.rst @@ -98,7 +98,7 @@ New APIs It is important to demonstrate your use case. This can be as simple as explaining that the feature is already in use on bare metal, or it can be a proof-of-concept implementation in userspace. The latter need not be - open source, though that is of course preferrable for easier testing. + open source, though that is of course preferable for easier testing. Selftests should test corner cases of the APIs, and should also cover basic host and guest operation if no open source VMM uses the feature. -- cgit v1.2.3 From 781c118c3ece2b546c6c41f617cccb36cb9534f1 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 29 Aug 2025 13:28:03 +0530 Subject: dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC Add the device tree bindings for the display clock controller which are required on Qualcomm Glymur SoC. Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250829-glymur-disp-clock-controllers-v1-1-0ce6fabd837c@oss.qualcomm.com [bjorn: Dropped unnecessary include in DT example] Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,glymur-dispcc.yaml | 98 ++++++++++++++++++ include/dt-bindings/clock/qcom,glymur-dispcc.h | 114 +++++++++++++++++++++ 2 files changed, 212 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml create mode 100644 include/dt-bindings/clock/qcom,glymur-dispcc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml new file mode 100644 index 000000000000..45f027c70e03 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on GLYMUR + +maintainers: + - Taniya Das + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains for the MDSS instances on GLYMUR SoC. + + See also: + include/dt-bindings/clock/qcom,dispcc-glymur.h + +properties: + compatible: + enum: + - qcom,glymur-dispcc + + clocks: + items: + - description: Board CXO clock + - description: Board sleep clock + - description: DisplayPort 0 link clock + - description: DisplayPort 0 VCO div clock + - description: DisplayPort 1 link clock + - description: DisplayPort 1 VCO div clock + - description: DisplayPort 2 link clock + - description: DisplayPort 2 VCO div clock + - description: DisplayPort 3 link clock + - description: DisplayPort 3 VCO div clock + - description: DSI 0 PLL byte clock + - description: DSI 0 PLL DSI clock + - description: DSI 1 PLL byte clock + - description: DSI 1 PLL DSI clock + - description: Standalone PHY 0 PLL link clock + - description: Standalone PHY 0 VCO div clock + - description: Standalone PHY 1 PLL link clock + - description: Standalone PHY 1 VCO div clock + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clock-controller@af00000 { + compatible = "qcom,glymur-dispcc"; + reg = <0x0af00000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&mdss_dp_phy0 0>, + <&mdss_dp_phy0 1>, + <&mdss_dp_phy1 0>, + <&mdss_dp_phy1 1>, + <&mdss_dp_phy2 0>, + <&mdss_dp_phy2 1>, + <&mdss_dp_phy3 0>, + <&mdss_dp_phy3 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_phy0_link 0>, + <&mdss_phy0_vco_div 0>, + <&mdss_phy1_link 1>, + <&mdss_phy1_vco_div 1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,glymur-dispcc.h b/include/dt-bindings/clock/qcom,glymur-dispcc.h new file mode 100644 index 000000000000..a845d76defe2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-dispcc.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H + +/* DISP_CC clocks */ +#define DISP_CC_ESYNC0_CLK 0 +#define DISP_CC_ESYNC0_CLK_SRC 1 +#define DISP_CC_ESYNC1_CLK 2 +#define DISP_CC_ESYNC1_CLK_SRC 3 +#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4 +#define DISP_CC_MDSS_AHB1_CLK 5 +#define DISP_CC_MDSS_AHB_CLK 6 +#define DISP_CC_MDSS_AHB_CLK_SRC 7 +#define DISP_CC_MDSS_BYTE0_CLK 8 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 11 +#define DISP_CC_MDSS_BYTE1_CLK 12 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 13 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 15 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 16 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 18 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 19 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 20 +#define DISP_CC_MDSS_DPTX0_LINK_DPIN_CLK 21 +#define DISP_CC_MDSS_DPTX0_LINK_DPIN_DIV_CLK_SRC 22 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 23 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 24 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 25 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 26 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 27 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 28 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 29 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 30 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 31 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33 +#define DISP_CC_MDSS_DPTX1_LINK_DPIN_CLK 34 +#define DISP_CC_MDSS_DPTX1_LINK_DPIN_DIV_CLK_SRC 35 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 36 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 37 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 38 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 39 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 40 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 41 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 42 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 43 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 44 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 45 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 46 +#define DISP_CC_MDSS_DPTX2_LINK_DPIN_CLK 47 +#define DISP_CC_MDSS_DPTX2_LINK_DPIN_DIV_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 49 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 50 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 51 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 52 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 53 +#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 54 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 55 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 56 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 57 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 58 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 59 +#define DISP_CC_MDSS_DPTX3_LINK_DPIN_CLK 60 +#define DISP_CC_MDSS_DPTX3_LINK_DPIN_DIV_CLK_SRC 61 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 62 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 63 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 64 +#define DISP_CC_MDSS_ESC0_CLK 65 +#define DISP_CC_MDSS_ESC0_CLK_SRC 66 +#define DISP_CC_MDSS_ESC1_CLK 67 +#define DISP_CC_MDSS_ESC1_CLK_SRC 68 +#define DISP_CC_MDSS_MDP1_CLK 69 +#define DISP_CC_MDSS_MDP_CLK 70 +#define DISP_CC_MDSS_MDP_CLK_SRC 71 +#define DISP_CC_MDSS_MDP_LUT1_CLK 72 +#define DISP_CC_MDSS_MDP_LUT_CLK 73 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 74 +#define DISP_CC_MDSS_PCLK0_CLK 75 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 76 +#define DISP_CC_MDSS_PCLK1_CLK 77 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 78 +#define DISP_CC_MDSS_PCLK2_CLK 79 +#define DISP_CC_MDSS_PCLK2_CLK_SRC 80 +#define DISP_CC_MDSS_RSCC_AHB_CLK 81 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 82 +#define DISP_CC_MDSS_VSYNC1_CLK 83 +#define DISP_CC_MDSS_VSYNC_CLK 84 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 85 +#define DISP_CC_OSC_CLK 86 +#define DISP_CC_OSC_CLK_SRC 87 +#define DISP_CC_PLL0 88 +#define DISP_CC_PLL1 89 +#define DISP_CC_SLEEP_CLK 90 +#define DISP_CC_SLEEP_CLK_SRC 91 +#define DISP_CC_XO_CLK 92 +#define DISP_CC_XO_CLK_SRC 93 + +/* DISP_CC power domains */ +#define DISP_CC_MDSS_CORE_GDSC 0 +#define DISP_CC_MDSS_CORE_INT2_GDSC 1 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +#endif -- cgit v1.2.3 From f672fcd8e6c411144a06dd07252f24805f229834 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Sep 2025 17:40:52 +0200 Subject: dt-bindings: net: altr,socfpga-stmmac: Constrain interrupts STMMAC on SoCFPGA uses exactly one interrupt in in-kernel DTS and common snps,dwmac.yaml binding is flexible, so define precise constraint for this device. Signed-off-by: Krzysztof Kozlowski Acked-by: Matthew Gerlach Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250902154051.263156-3-krzysztof.kozlowski@linaro.org Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index 3a22d35db778..fc445ad5a1f1 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -62,6 +62,13 @@ properties: - const: stmmaceth - const: ptp_ref + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: macirq + iommus: minItems: 1 maxItems: 2 -- cgit v1.2.3 From 69cd99350740a5acc81f46aa5def37808d8d6e78 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Sep 2025 17:40:53 +0200 Subject: dt-bindings: net: renesas,rzn1-gmac: Constrain interrupts Renesas RZN1 GMAC uses three interrupts in in-kernel DTS and common snps,dwmac.yaml binding is flexible, so define precise constraint for this device. Reviewed-by: Lad Prabhakar Signed-off-by: Krzysztof Kozlowski Reviewed-by: Romain Gantois Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250902154051.263156-4-krzysztof.kozlowski@linaro.org Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml index d9a8d586e260..16dd7a2631ab 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml @@ -30,6 +30,15 @@ properties: - const: renesas,rzn1-gmac - const: snps,dwmac + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + pcs-handle: description: phandle pointing to a PCS sub-node compatible with -- cgit v1.2.3 From f9b007a96a89567372a77cbddd24d5ca4be71523 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 25 Aug 2025 23:49:08 +0530 Subject: dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs Add bindings and update documentation compatible for RPMh clock controller on Glymur SoC. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-1-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index a4414ba0b287..78fa05726685 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - qcom,glymur-rpmh-clk - qcom,milos-rpmh-clk - qcom,qcs615-rpmh-clk - qcom,qdu1000-rpmh-clk -- cgit v1.2.3 From ae5b84788e5a7876a67f64761b7265529cb5a39a Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 25 Aug 2025 23:49:09 +0530 Subject: dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe and USB. Add this to the TCSR clock controller binding together with identifiers for the clocks. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-2-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 3 +++ include/dt-bindings/clock/qcom,glymur-tcsr.h | 24 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,glymur-tcsr.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 2ed7d59722fc..2c992b3437f2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550 maintainers: - Bjorn Andersson + - Taniya Das description: | Qualcomm TCSR clock control module provides the clocks, resets and power domains on SM8550 See also: + - include/dt-bindings/clock/qcom,glymur-tcsr.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h - include/dt-bindings/clock/qcom,sm8750-tcsr.h @@ -22,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,glymur-tcsr - qcom,milos-tcsr - qcom,sar2130p-tcsr - qcom,sm8550-tcsr diff --git a/include/dt-bindings/clock/qcom,glymur-tcsr.h b/include/dt-bindings/clock/qcom,glymur-tcsr.h new file mode 100644 index 000000000000..72614226b113 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-tcsr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H + +/* TCSR_CC clocks */ +#define TCSR_EDP_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_PCIE_2_CLKREF_EN 2 +#define TCSR_PCIE_3_CLKREF_EN 3 +#define TCSR_PCIE_4_CLKREF_EN 4 +#define TCSR_USB2_1_CLKREF_EN 5 +#define TCSR_USB2_2_CLKREF_EN 6 +#define TCSR_USB2_3_CLKREF_EN 7 +#define TCSR_USB2_4_CLKREF_EN 8 +#define TCSR_USB3_0_CLKREF_EN 9 +#define TCSR_USB3_1_CLKREF_EN 10 +#define TCSR_USB4_1_CLKREF_EN 11 +#define TCSR_USB4_2_CLKREF_EN 12 + +#endif -- cgit v1.2.3 From ee2d967030fee156ceb2de80ef63ddeb80d60779 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 25 Aug 2025 23:49:13 +0530 Subject: dt-bindings: clock: qcom: document the Glymur Global Clock Controller Add device tree bindings for global clock controller on Glymur SoC. Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,glymur-gcc.yaml | 121 +++++ include/dt-bindings/clock/qcom,glymur-gcc.h | 578 +++++++++++++++++++++ 2 files changed, 699 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,glymur-gcc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml new file mode 100644 index 000000000000..b05b0e6c4483 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on Glymur SoC + +maintainers: + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on Glymur SoC. + + See also: include/dt-bindings/clock/qcom,glymur-gcc.h + +properties: + compatible: + const: qcom,glymur-gcc + + clocks: + items: + - description: Board XO source + - description: Board XO_A source + - description: Sleep clock source + - description: USB 0 Phy DP0 GMUX clock source + - description: USB 0 Phy DP1 GMUX clock source + - description: USB 0 Phy PCIE PIPEGMUX clock source + - description: USB 0 Phy PIPEGMUX clock source + - description: USB 0 Phy SYS PCIE PIPEGMUX clock source + - description: USB 1 Phy DP0 GMUX 2 clock source + - description: USB 1 Phy DP1 GMUX 2 clock source + - description: USB 1 Phy PCIE PIPEGMUX clock source + - description: USB 1 Phy PIPEGMUX clock source + - description: USB 1 Phy SYS PCIE PIPEGMUX clock source + - description: USB 2 Phy DP0 GMUX 2 clock source + - description: USB 2 Phy DP1 GMUX 2 clock source + - description: USB 2 Phy PCIE PIPEGMUX clock source + - description: USB 2 Phy PIPEGMUX clock source + - description: USB 2 Phy SYS PCIE PIPEGMUX clock source + - description: PCIe 3a pipe clock + - description: PCIe 3b pipe clock + - description: PCIe 4 pipe clock + - description: PCIe 5 pipe clock + - description: PCIe 6 pipe clock + - description: QUSB4 0 PHY RX 0 clock source + - description: QUSB4 0 PHY RX 1 clock source + - description: QUSB4 1 PHY RX 0 clock source + - description: QUSB4 1 PHY RX 1 clock source + - description: QUSB4 2 PHY RX 0 clock source + - description: QUSB4 2 PHY RX 1 clock source + - description: UFS PHY RX Symbol 0 clock source + - description: UFS PHY RX Symbol 1 clock source + - description: UFS PHY TX Symbol 0 clock source + - description: USB3 PHY 0 pipe clock source + - description: USB3 PHY 1 pipe clock source + - description: USB3 PHY 2 pipe clock source + - description: USB3 UNI PHY pipe 0 clock source + - description: USB3 UNI PHY pipe 1 clock source + - description: USB4 PHY 0 pcie pipe clock source + - description: USB4 PHY 0 Max pipe clock source + - description: USB4 PHY 1 pcie pipe clock source + - description: USB4 PHY 1 Max pipe clock source + - description: USB4 PHY 2 pcie pipe clock source + - description: USB4 PHY 2 Max pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,glymur-gcc"; + reg = <0x100000 0x1f9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&usb_0_phy_dp0_gmux>, + <&usb_0_phy_dp1_gmux>, + <&usb_0_phy_pcie_pipegmux>, + <&usb_0_phy_pipegmux>, + <&usb_0_phy_sys_pcie_pipegmux>, + <&usb_1_phy_dp0_gmux_2>, + <&usb_1_phy_dp1_gmux_2>, + <&usb_1_phy_pcie_pipegmux>, + <&usb_1_phy_pipegmux>, + <&usb_1_phy_sys_pcie_pipegmux>, + <&usb_2_phy_dp0_gmux 2>, + <&usb_2_phy_dp1_gmux 2>, + <&usb_2_phy_pcie_pipegmux>, + <&usb_2_phy_pipegmux>, + <&usb_2_phy_sys_pcie_pipegmux>, + <&pcie_3a_pipe>, <&pcie_3b_pipe>, + <&pcie_4_pipe>, <&pcie_5_pipe>, + <&pcie_6_pipe>, + <&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>, + <&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>, + <&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>, + <&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>, + <&ufs_phy_tx_symbol_0>, + <&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>, + <&usb3_phy_2_pipe>, + <&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>, + <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>, + <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>, + <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindings/clock/qcom,glymur-gcc.h new file mode 100644 index 000000000000..10c12b8c51c3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-gcc.h @@ -0,0 +1,578 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL14 3 +#define GCC_GPLL14_OUT_EVEN 4 +#define GCC_GPLL4 5 +#define GCC_GPLL5 6 +#define GCC_GPLL7 7 +#define GCC_GPLL8 8 +#define GCC_GPLL9 9 +#define GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK 10 +#define GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK 11 +#define GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK 12 +#define GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK 13 +#define GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK 14 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 15 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 16 +#define GCC_AGGRE_USB2_PRIM_AXI_CLK 17 +#define GCC_AGGRE_USB3_MP_AXI_CLK 18 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 19 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 20 +#define GCC_AGGRE_USB3_TERT_AXI_CLK 21 +#define GCC_AGGRE_USB4_0_AXI_CLK 22 +#define GCC_AGGRE_USB4_1_AXI_CLK 23 +#define GCC_AGGRE_USB4_2_AXI_CLK 24 +#define GCC_AV1E_AHB_CLK 25 +#define GCC_AV1E_AXI_CLK 26 +#define GCC_AV1E_XO_CLK 27 +#define GCC_BOOT_ROM_AHB_CLK 28 +#define GCC_CAMERA_AHB_CLK 29 +#define GCC_CAMERA_HF_AXI_CLK 30 +#define GCC_CAMERA_SF_AXI_CLK 31 +#define GCC_CAMERA_XO_CLK 32 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 33 +#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 34 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 35 +#define GCC_CFG_NOC_USB3_MP_AXI_CLK 36 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 37 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 38 +#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 39 +#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 40 +#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 41 +#define GCC_DISP_AHB_CLK 42 +#define GCC_DISP_HF_AXI_CLK 43 +#define GCC_EVA_AHB_CLK 44 +#define GCC_EVA_AXI0_CLK 45 +#define GCC_EVA_AXI0C_CLK 46 +#define GCC_EVA_XO_CLK 47 +#define GCC_GP1_CLK 48 +#define GCC_GP1_CLK_SRC 49 +#define GCC_GP2_CLK 50 +#define GCC_GP2_CLK_SRC 51 +#define GCC_GP3_CLK 52 +#define GCC_GP3_CLK_SRC 53 +#define GCC_GPU_CFG_AHB_CLK 54 +#define GCC_GPU_GEMNOC_GFX_CLK 55 +#define GCC_GPU_GPLL0_CLK_SRC 56 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 57 +#define GCC_PCIE_0_AUX_CLK 58 +#define GCC_PCIE_0_AUX_CLK_SRC 59 +#define GCC_PCIE_0_CFG_AHB_CLK 60 +#define GCC_PCIE_0_MSTR_AXI_CLK 61 +#define GCC_PCIE_0_PHY_RCHNG_CLK 62 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 63 +#define GCC_PCIE_0_PIPE_CLK 64 +#define GCC_PCIE_0_SLV_AXI_CLK 65 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 66 +#define GCC_PCIE_1_AUX_CLK 67 +#define GCC_PCIE_1_AUX_CLK_SRC 68 +#define GCC_PCIE_1_CFG_AHB_CLK 69 +#define GCC_PCIE_1_MSTR_AXI_CLK 70 +#define GCC_PCIE_1_PHY_RCHNG_CLK 71 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72 +#define GCC_PCIE_1_PIPE_CLK 73 +#define GCC_PCIE_1_SLV_AXI_CLK 74 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75 +#define GCC_PCIE_2_AUX_CLK 76 +#define GCC_PCIE_2_AUX_CLK_SRC 77 +#define GCC_PCIE_2_CFG_AHB_CLK 78 +#define GCC_PCIE_2_MSTR_AXI_CLK 79 +#define GCC_PCIE_2_PHY_RCHNG_CLK 80 +#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 81 +#define GCC_PCIE_2_PIPE_CLK 82 +#define GCC_PCIE_2_SLV_AXI_CLK 83 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 84 +#define GCC_PCIE_3A_AUX_CLK 85 +#define GCC_PCIE_3A_AUX_CLK_SRC 86 +#define GCC_PCIE_3A_CFG_AHB_CLK 87 +#define GCC_PCIE_3A_MSTR_AXI_CLK 88 +#define GCC_PCIE_3A_PHY_RCHNG_CLK 89 +#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 90 +#define GCC_PCIE_3A_PIPE_CLK 91 +#define GCC_PCIE_3A_PIPE_CLK_SRC 92 +#define GCC_PCIE_3A_SLV_AXI_CLK 93 +#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 94 +#define GCC_PCIE_3B_AUX_CLK 95 +#define GCC_PCIE_3B_AUX_CLK_SRC 96 +#define GCC_PCIE_3B_CFG_AHB_CLK 97 +#define GCC_PCIE_3B_MSTR_AXI_CLK 98 +#define GCC_PCIE_3B_PHY_RCHNG_CLK 99 +#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 100 +#define GCC_PCIE_3B_PIPE_CLK 101 +#define GCC_PCIE_3B_PIPE_CLK_SRC 102 +#define GCC_PCIE_3B_PIPE_DIV2_CLK 103 +#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 104 +#define GCC_PCIE_3B_SLV_AXI_CLK 105 +#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 106 +#define GCC_PCIE_4_AUX_CLK 107 +#define GCC_PCIE_4_AUX_CLK_SRC 108 +#define GCC_PCIE_4_CFG_AHB_CLK 109 +#define GCC_PCIE_4_MSTR_AXI_CLK 110 +#define GCC_PCIE_4_PHY_RCHNG_CLK 111 +#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 112 +#define GCC_PCIE_4_PIPE_CLK 113 +#define GCC_PCIE_4_PIPE_CLK_SRC 114 +#define GCC_PCIE_4_PIPE_DIV2_CLK 115 +#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 116 +#define GCC_PCIE_4_SLV_AXI_CLK 117 +#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 118 +#define GCC_PCIE_5_AUX_CLK 119 +#define GCC_PCIE_5_AUX_CLK_SRC 120 +#define GCC_PCIE_5_CFG_AHB_CLK 121 +#define GCC_PCIE_5_MSTR_AXI_CLK 122 +#define GCC_PCIE_5_PHY_RCHNG_CLK 123 +#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 124 +#define GCC_PCIE_5_PIPE_CLK 125 +#define GCC_PCIE_5_PIPE_CLK_SRC 126 +#define GCC_PCIE_5_PIPE_DIV2_CLK 127 +#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 128 +#define GCC_PCIE_5_SLV_AXI_CLK 129 +#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 130 +#define GCC_PCIE_6_AUX_CLK 131 +#define GCC_PCIE_6_AUX_CLK_SRC 132 +#define GCC_PCIE_6_CFG_AHB_CLK 133 +#define GCC_PCIE_6_MSTR_AXI_CLK 134 +#define GCC_PCIE_6_PHY_RCHNG_CLK 135 +#define GCC_PCIE_6_PHY_RCHNG_CLK_SRC 136 +#define GCC_PCIE_6_PIPE_CLK 137 +#define GCC_PCIE_6_PIPE_CLK_SRC 138 +#define GCC_PCIE_6_PIPE_DIV2_CLK 139 +#define GCC_PCIE_6_PIPE_DIV_CLK_SRC 140 +#define GCC_PCIE_6_SLV_AXI_CLK 141 +#define GCC_PCIE_6_SLV_Q2A_AXI_CLK 142 +#define GCC_PCIE_NOC_PWRCTL_CLK 143 +#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 144 +#define GCC_PCIE_NOC_SF_CENTER_CLK 145 +#define GCC_PCIE_NOC_SLAVE_SF_EAST_CLK 146 +#define GCC_PCIE_NOC_SLAVE_SF_WEST_CLK 147 +#define GCC_PCIE_NOC_TSCTR_CLK 148 +#define GCC_PCIE_PHY_3A_AUX_CLK 149 +#define GCC_PCIE_PHY_3A_AUX_CLK_SRC 150 +#define GCC_PCIE_PHY_3B_AUX_CLK 151 +#define GCC_PCIE_PHY_3B_AUX_CLK_SRC 152 +#define GCC_PCIE_PHY_4_AUX_CLK 153 +#define GCC_PCIE_PHY_4_AUX_CLK_SRC 154 +#define GCC_PCIE_PHY_5_AUX_CLK 155 +#define GCC_PCIE_PHY_5_AUX_CLK_SRC 156 +#define GCC_PCIE_PHY_6_AUX_CLK 157 +#define GCC_PCIE_PHY_6_AUX_CLK_SRC 158 +#define GCC_PCIE_RSCC_CFG_AHB_CLK 159 +#define GCC_PCIE_RSCC_XO_CLK 160 +#define GCC_PDM2_CLK 161 +#define GCC_PDM2_CLK_SRC 162 +#define GCC_PDM_AHB_CLK 163 +#define GCC_PDM_XO4_CLK 164 +#define GCC_QMIP_AV1E_AHB_CLK 165 +#define GCC_QMIP_CAMERA_CMD_AHB_CLK 166 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 167 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 168 +#define GCC_QMIP_GPU_AHB_CLK 169 +#define GCC_QMIP_PCIE_3A_AHB_CLK 170 +#define GCC_QMIP_PCIE_3B_AHB_CLK 171 +#define GCC_QMIP_PCIE_4_AHB_CLK 172 +#define GCC_QMIP_PCIE_5_AHB_CLK 173 +#define GCC_QMIP_PCIE_6_AHB_CLK 174 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 175 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 177 +#define GCC_QMIP_VIDEO_VCODEC1_AHB_CLK 178 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 179 +#define GCC_QUPV3_OOB_CORE_2X_CLK 180 +#define GCC_QUPV3_OOB_CORE_CLK 181 +#define GCC_QUPV3_OOB_M_AHB_CLK 182 +#define GCC_QUPV3_OOB_QSPI_S0_CLK 183 +#define GCC_QUPV3_OOB_QSPI_S0_CLK_SRC 184 +#define GCC_QUPV3_OOB_QSPI_S1_CLK 185 +#define GCC_QUPV3_OOB_QSPI_S1_CLK_SRC 186 +#define GCC_QUPV3_OOB_S0_CLK 187 +#define GCC_QUPV3_OOB_S0_CLK_SRC 188 +#define GCC_QUPV3_OOB_S1_CLK 189 +#define GCC_QUPV3_OOB_S1_CLK_SRC 190 +#define GCC_QUPV3_OOB_S_AHB_CLK 191 +#define GCC_QUPV3_OOB_TCXO_CLK 192 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 193 +#define GCC_QUPV3_WRAP0_CORE_CLK 194 +#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 195 +#define GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC 196 +#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 197 +#define GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC 198 +#define GCC_QUPV3_WRAP0_QSPI_S6_CLK 199 +#define GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC 200 +#define GCC_QUPV3_WRAP0_S0_CLK 201 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 202 +#define GCC_QUPV3_WRAP0_S1_CLK 203 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 204 +#define GCC_QUPV3_WRAP0_S2_CLK 205 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 206 +#define GCC_QUPV3_WRAP0_S3_CLK 207 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 208 +#define GCC_QUPV3_WRAP0_S4_CLK 209 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 210 +#define GCC_QUPV3_WRAP0_S5_CLK 211 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 212 +#define GCC_QUPV3_WRAP0_S6_CLK 213 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 214 +#define GCC_QUPV3_WRAP0_S7_CLK 215 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 216 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 217 +#define GCC_QUPV3_WRAP1_CORE_CLK 218 +#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 219 +#define GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC 220 +#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 221 +#define GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC 222 +#define GCC_QUPV3_WRAP1_QSPI_S6_CLK 223 +#define GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC 224 +#define GCC_QUPV3_WRAP1_S0_CLK 225 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 226 +#define GCC_QUPV3_WRAP1_S1_CLK 227 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 228 +#define GCC_QUPV3_WRAP1_S2_CLK 229 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 230 +#define GCC_QUPV3_WRAP1_S3_CLK 231 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 232 +#define GCC_QUPV3_WRAP1_S4_CLK 233 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 234 +#define GCC_QUPV3_WRAP1_S5_CLK 235 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 236 +#define GCC_QUPV3_WRAP1_S6_CLK 237 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 238 +#define GCC_QUPV3_WRAP1_S7_CLK 239 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 240 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 241 +#define GCC_QUPV3_WRAP2_CORE_CLK 242 +#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 243 +#define GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC 244 +#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 245 +#define GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC 246 +#define GCC_QUPV3_WRAP2_QSPI_S6_CLK 247 +#define GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC 248 +#define GCC_QUPV3_WRAP2_S0_CLK 249 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 250 +#define GCC_QUPV3_WRAP2_S1_CLK 251 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 252 +#define GCC_QUPV3_WRAP2_S2_CLK 253 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 254 +#define GCC_QUPV3_WRAP2_S3_CLK 255 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 256 +#define GCC_QUPV3_WRAP2_S4_CLK 257 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 258 +#define GCC_QUPV3_WRAP2_S5_CLK 259 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 260 +#define GCC_QUPV3_WRAP2_S6_CLK 261 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 262 +#define GCC_QUPV3_WRAP2_S7_CLK 263 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 264 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 265 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 266 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 267 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 268 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 269 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 270 +#define GCC_SDCC2_AHB_CLK 271 +#define GCC_SDCC2_APPS_CLK 272 +#define GCC_SDCC2_APPS_CLK_SRC 273 +#define GCC_SDCC4_AHB_CLK 274 +#define GCC_SDCC4_APPS_CLK 275 +#define GCC_SDCC4_APPS_CLK_SRC 276 +#define GCC_UFS_PHY_AHB_CLK 277 +#define GCC_UFS_PHY_AXI_CLK 278 +#define GCC_UFS_PHY_AXI_CLK_SRC 279 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 280 +#define GCC_UFS_PHY_ICE_CORE_CLK 281 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 282 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 283 +#define GCC_UFS_PHY_PHY_AUX_CLK 284 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 285 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 286 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 287 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 288 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 289 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 290 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 291 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 292 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 293 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 294 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 295 +#define GCC_USB20_MASTER_CLK 296 +#define GCC_USB20_MASTER_CLK_SRC 297 +#define GCC_USB20_MOCK_UTMI_CLK 298 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 299 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 300 +#define GCC_USB20_SLEEP_CLK 301 +#define GCC_USB30_MP_MASTER_CLK 302 +#define GCC_USB30_MP_MASTER_CLK_SRC 303 +#define GCC_USB30_MP_MOCK_UTMI_CLK 304 +#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 305 +#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 306 +#define GCC_USB30_MP_SLEEP_CLK 307 +#define GCC_USB30_PRIM_MASTER_CLK 308 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 309 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 310 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 311 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 312 +#define GCC_USB30_PRIM_SLEEP_CLK 313 +#define GCC_USB30_SEC_MASTER_CLK 314 +#define GCC_USB30_SEC_MASTER_CLK_SRC 315 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 316 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 317 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 318 +#define GCC_USB30_SEC_SLEEP_CLK 319 +#define GCC_USB30_TERT_MASTER_CLK 320 +#define GCC_USB30_TERT_MASTER_CLK_SRC 321 +#define GCC_USB30_TERT_MOCK_UTMI_CLK 322 +#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 323 +#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 324 +#define GCC_USB30_TERT_SLEEP_CLK 325 +#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 326 +#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 327 +#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 328 +#define GCC_USB3_MP_PHY_AUX_CLK 329 +#define GCC_USB3_MP_PHY_AUX_CLK_SRC 330 +#define GCC_USB3_MP_PHY_COM_AUX_CLK 331 +#define GCC_USB3_MP_PHY_PIPE_0_CLK 332 +#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 333 +#define GCC_USB3_MP_PHY_PIPE_1_CLK 334 +#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 335 +#define GCC_USB3_PRIM_PHY_AUX_CLK 336 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 337 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 338 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 339 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 340 +#define GCC_USB3_SEC_PHY_AUX_CLK 341 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 342 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 343 +#define GCC_USB3_SEC_PHY_PIPE_CLK 344 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 345 +#define GCC_USB3_TERT_PHY_AUX_CLK 346 +#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 347 +#define GCC_USB3_TERT_PHY_COM_AUX_CLK 348 +#define GCC_USB3_TERT_PHY_PIPE_CLK 349 +#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 350 +#define GCC_USB4_0_CFG_AHB_CLK 351 +#define GCC_USB4_0_DP0_CLK 352 +#define GCC_USB4_0_DP1_CLK 353 +#define GCC_USB4_0_MASTER_CLK 354 +#define GCC_USB4_0_MASTER_CLK_SRC 355 +#define GCC_USB4_0_PHY_DP0_CLK_SRC 356 +#define GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC 357 +#define GCC_USB4_0_PHY_DP1_CLK_SRC 358 +#define GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC 359 +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 360 +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361 +#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 362 +#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 363 +#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 364 +#define GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC 365 +#define GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC 366 +#define GCC_USB4_0_PHY_RX0_CLK 367 +#define GCC_USB4_0_PHY_RX0_CLK_SRC 368 +#define GCC_USB4_0_PHY_RX1_CLK 369 +#define GCC_USB4_0_PHY_RX1_CLK_SRC 370 +#define GCC_USB4_0_PHY_SYS_CLK_SRC 371 +#define GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC 372 +#define GCC_USB4_0_PHY_USB_PIPE_CLK 373 +#define GCC_USB4_0_SB_IF_CLK 374 +#define GCC_USB4_0_SB_IF_CLK_SRC 375 +#define GCC_USB4_0_SYS_CLK 376 +#define GCC_USB4_0_TMU_CLK 377 +#define GCC_USB4_0_TMU_CLK_SRC 378 +#define GCC_USB4_0_UC_HRR_CLK 379 +#define GCC_USB4_1_CFG_AHB_CLK 380 +#define GCC_USB4_1_DP0_CLK 381 +#define GCC_USB4_1_DP1_CLK 382 +#define GCC_USB4_1_MASTER_CLK 383 +#define GCC_USB4_1_MASTER_CLK_SRC 384 +#define GCC_USB4_1_PHY_DP0_CLK_SRC 385 +#define GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC 386 +#define GCC_USB4_1_PHY_DP1_CLK_SRC 387 +#define GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC 388 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 389 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 390 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 391 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 392 +#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 393 +#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 394 +#define GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC 395 +#define GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC 396 +#define GCC_USB4_1_PHY_RX0_CLK 397 +#define GCC_USB4_1_PHY_RX0_CLK_SRC 398 +#define GCC_USB4_1_PHY_RX1_CLK 399 +#define GCC_USB4_1_PHY_RX1_CLK_SRC 400 +#define GCC_USB4_1_PHY_SYS_CLK_SRC 401 +#define GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC 402 +#define GCC_USB4_1_PHY_USB_PIPE_CLK 403 +#define GCC_USB4_1_SB_IF_CLK 404 +#define GCC_USB4_1_SB_IF_CLK_SRC 405 +#define GCC_USB4_1_SYS_CLK 406 +#define GCC_USB4_1_TMU_CLK 407 +#define GCC_USB4_1_TMU_CLK_SRC 408 +#define GCC_USB4_1_UC_HRR_CLK 409 +#define GCC_USB4_2_CFG_AHB_CLK 410 +#define GCC_USB4_2_DP0_CLK 411 +#define GCC_USB4_2_DP1_CLK 412 +#define GCC_USB4_2_MASTER_CLK 413 +#define GCC_USB4_2_MASTER_CLK_SRC 414 +#define GCC_USB4_2_PHY_DP0_CLK_SRC 415 +#define GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC 416 +#define GCC_USB4_2_PHY_DP1_CLK_SRC 417 +#define GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC 418 +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 419 +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 420 +#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 421 +#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 422 +#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 423 +#define GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC 424 +#define GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC 425 +#define GCC_USB4_2_PHY_RX0_CLK 426 +#define GCC_USB4_2_PHY_RX0_CLK_SRC 427 +#define GCC_USB4_2_PHY_RX1_CLK 428 +#define GCC_USB4_2_PHY_RX1_CLK_SRC 429 +#define GCC_USB4_2_PHY_SYS_CLK_SRC 430 +#define GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC 431 +#define GCC_USB4_2_PHY_USB_PIPE_CLK 432 +#define GCC_USB4_2_SB_IF_CLK 433 +#define GCC_USB4_2_SB_IF_CLK_SRC 434 +#define GCC_USB4_2_SYS_CLK 435 +#define GCC_USB4_2_TMU_CLK 436 +#define GCC_USB4_2_TMU_CLK_SRC 437 +#define GCC_USB4_2_UC_HRR_CLK 438 +#define GCC_VIDEO_AHB_CLK 439 +#define GCC_VIDEO_AXI0_CLK 440 +#define GCC_VIDEO_AXI0C_CLK 441 +#define GCC_VIDEO_AXI1_CLK 442 +#define GCC_VIDEO_XO_CLK 443 + +/* GCC power domains */ +#define GCC_PCIE_0_TUNNEL_GDSC 0 +#define GCC_PCIE_1_TUNNEL_GDSC 1 +#define GCC_PCIE_2_TUNNEL_GDSC 2 +#define GCC_PCIE_3A_GDSC 3 +#define GCC_PCIE_3A_PHY_GDSC 4 +#define GCC_PCIE_3B_GDSC 5 +#define GCC_PCIE_3B_PHY_GDSC 6 +#define GCC_PCIE_4_GDSC 7 +#define GCC_PCIE_4_PHY_GDSC 8 +#define GCC_PCIE_5_GDSC 9 +#define GCC_PCIE_5_PHY_GDSC 10 +#define GCC_PCIE_6_GDSC 11 +#define GCC_PCIE_6_PHY_GDSC 12 +#define GCC_UFS_PHY_GDSC 13 +#define GCC_USB20_PRIM_GDSC 14 +#define GCC_USB30_MP_GDSC 15 +#define GCC_USB30_PRIM_GDSC 16 +#define GCC_USB30_SEC_GDSC 17 +#define GCC_USB30_TERT_GDSC 18 +#define GCC_USB3_MP_SS0_PHY_GDSC 19 +#define GCC_USB3_MP_SS1_PHY_GDSC 20 +#define GCC_USB4_0_GDSC 21 +#define GCC_USB4_1_GDSC 22 +#define GCC_USB4_2_GDSC 23 +#define GCC_USB_0_PHY_GDSC 24 +#define GCC_USB_1_PHY_GDSC 25 +#define GCC_USB_2_PHY_GDSC 26 + +/* GCC resets */ +#define GCC_AV1E_BCR 0 +#define GCC_CAMERA_BCR 1 +#define GCC_DISPLAY_BCR 2 +#define GCC_EVA_BCR 3 +#define GCC_GPU_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_0_TUNNEL_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_1_TUNNEL_BCR 14 +#define GCC_PCIE_2_LINK_DOWN_BCR 15 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_2_PHY_BCR 17 +#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18 +#define GCC_PCIE_2_TUNNEL_BCR 19 +#define GCC_PCIE_3A_BCR 20 +#define GCC_PCIE_3A_LINK_DOWN_BCR 21 +#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 22 +#define GCC_PCIE_3A_PHY_BCR 23 +#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 24 +#define GCC_PCIE_3B_BCR 25 +#define GCC_PCIE_3B_LINK_DOWN_BCR 26 +#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 27 +#define GCC_PCIE_3B_PHY_BCR 28 +#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 29 +#define GCC_PCIE_4_BCR 30 +#define GCC_PCIE_4_LINK_DOWN_BCR 31 +#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 32 +#define GCC_PCIE_4_PHY_BCR 33 +#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 34 +#define GCC_PCIE_5_BCR 35 +#define GCC_PCIE_5_LINK_DOWN_BCR 36 +#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 37 +#define GCC_PCIE_5_PHY_BCR 38 +#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 39 +#define GCC_PCIE_6_BCR 40 +#define GCC_PCIE_6_LINK_DOWN_BCR 41 +#define GCC_PCIE_6_NOCSR_COM_PHY_BCR 42 +#define GCC_PCIE_6_PHY_BCR 43 +#define GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR 44 +#define GCC_PCIE_NOC_BCR 45 +#define GCC_PCIE_PHY_BCR 46 +#define GCC_PCIE_PHY_CFG_AHB_BCR 47 +#define GCC_PCIE_PHY_COM_BCR 48 +#define GCC_PCIE_RSCC_BCR 49 +#define GCC_PDM_BCR 50 +#define GCC_QUPV3_WRAPPER_0_BCR 51 +#define GCC_QUPV3_WRAPPER_1_BCR 52 +#define GCC_QUPV3_WRAPPER_2_BCR 53 +#define GCC_QUPV3_WRAPPER_OOB_BCR 54 +#define GCC_QUSB2PHY_HS0_MP_BCR 55 +#define GCC_QUSB2PHY_HS1_MP_BCR 56 +#define GCC_QUSB2PHY_PRIM_BCR 57 +#define GCC_QUSB2PHY_SEC_BCR 58 +#define GCC_QUSB2PHY_TERT_BCR 59 +#define GCC_QUSB2PHY_USB20_HS_BCR 60 +#define GCC_SDCC2_BCR 61 +#define GCC_SDCC4_BCR 62 +#define GCC_TCSR_PCIE_BCR 63 +#define GCC_UFS_PHY_BCR 64 +#define GCC_USB20_PRIM_BCR 65 +#define GCC_USB30_MP_BCR 66 +#define GCC_USB30_PRIM_BCR 67 +#define GCC_USB30_SEC_BCR 68 +#define GCC_USB30_TERT_BCR 69 +#define GCC_USB3_MP_SS0_PHY_BCR 70 +#define GCC_USB3_MP_SS1_PHY_BCR 71 +#define GCC_USB3_PHY_PRIM_BCR 72 +#define GCC_USB3_PHY_SEC_BCR 73 +#define GCC_USB3_PHY_TERT_BCR 74 +#define GCC_USB3_UNIPHY_MP0_BCR 75 +#define GCC_USB3_UNIPHY_MP1_BCR 76 +#define GCC_USB3PHY_PHY_PRIM_BCR 77 +#define GCC_USB3PHY_PHY_SEC_BCR 78 +#define GCC_USB3PHY_PHY_TERT_BCR 79 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 80 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 81 +#define GCC_USB4_0_BCR 82 +#define GCC_USB4_0_DP0_PHY_PRIM_BCR 83 +#define GCC_USB4_1_BCR 84 +#define GCC_USB4_2_BCR 85 +#define GCC_USB_0_PHY_BCR 86 +#define GCC_USB_1_PHY_BCR 87 +#define GCC_USB_2_PHY_BCR 88 +#define GCC_VIDEO_AXI0_CLK_ARES 89 +#define GCC_VIDEO_AXI1_CLK_ARES 90 +#define GCC_VIDEO_BCR 91 + +#endif -- cgit v1.2.3 From ac77c8f12edd894e8d3fe732d2b1c6c3de09c1aa Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 3 Sep 2025 14:58:12 +0300 Subject: dt-bindings: display/msm: dp-controller: allow eDP for SA8775P On Qualcomm SA8775P the DP controller might be driving either a DisplayPort or a eDP sink (depending on the PHY that is tied to the controller). Reflect that in the schema. Acked-by: Rob Herring (Arm) Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/672569/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-1-7526f0311eaa@oss.qualcomm.com --- .../bindings/display/msm/dp-controller.yaml | 25 ++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 9923b065323b..aed3bafa67e3 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -174,12 +174,25 @@ allOf: properties: "#sound-dai-cells": false else: - properties: - aux-bus: false - reg: - minItems: 5 - required: - - "#sound-dai-cells" + if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + then: + oneOf: + - required: + - aux-bus + - required: + - "#sound-dai-cells" + else: + properties: + aux-bus: false + reg: + minItems: 5 + required: + - "#sound-dai-cells" additionalProperties: false -- cgit v1.2.3 From 5484265fd685d752bb75dd8b34f617dd9991ba5c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 3 Sep 2025 14:58:13 +0300 Subject: dt-bindings: display/msm: dp-controller: fix fallback for SM6350 Currently SM6350 uses qcom,sm8350-dp as a fallback compatible entry. This works, but adding DP MST support will reveal that this SoC is not fully compatible with SM8350 platform: the former one doesn't provide MST support, while the latter one will get it. DT schema for SM8350 is going to demand MST-related clocks which SM6350 doesn't provide. Add new entry for SM6350 with fallback to SC7180 (which belongs to the same generation and also doesn't have MST support). SC7180 has been supported by the Linux kernel long ago (and long before SM8350 support was added). Fixes: 39086151593a ("dt-bindings: display: msm: dp-controller: document SM6350 compatible") Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/672571/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-2-7526f0311eaa@oss.qualcomm.com --- .../devicetree/bindings/display/msm/dp-controller.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index aed3bafa67e3..0f814aa6f514 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -31,13 +31,25 @@ properties: - qcom,sm8650-dp - items: - enum: - - qcom,sar2130p-dp - qcom,sm6350-dp + - const: qcom,sc7180-dp + + # deprecated entry for compatibility with old DT + - items: + - enum: + - qcom,sm6350-dp + - const: qcom,sm8350-dp + deprecated: true + + - items: + - enum: + - qcom,sar2130p-dp - qcom,sm8150-dp - qcom,sm8250-dp - qcom,sm8450-dp - qcom,sm8550-dp - const: qcom,sm8350-dp + - items: - enum: - qcom,sm8750-dp -- cgit v1.2.3 From afc9e583c0b28f885ef6aa5ef6ea098204c263ed Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 3 Sep 2025 14:58:14 +0300 Subject: dt-bindings: display/msm: dp-controller: document DP on SM7150 The qcom,sm7150-dp compatible is documented in schema. Mark DisplayPort controller as compatible with SM8350. Fixes: 726eded12dd7 ("dt-bindings: display/msm: Add SM7150 MDSS") Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/672572/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-3-7526f0311eaa@oss.qualcomm.com --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 0f814aa6f514..a18183f7ec21 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -44,6 +44,7 @@ properties: - items: - enum: - qcom,sar2130p-dp + - qcom,sm7150-dp - qcom,sm8150-dp - qcom,sm8250-dp - qcom,sm8450-dp diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml index 13c5d5ffabde..c5d209019124 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml @@ -61,7 +61,8 @@ patternProperties: additionalProperties: true properties: compatible: - const: qcom,sm7150-dp + contains: + const: qcom,sm7150-dp "^dsi@[0-9a-f]+$": type: object @@ -378,7 +379,8 @@ examples: }; displayport-controller@ae90000 { - compatible = "qcom,sm7150-dp"; + compatible = "qcom,sm7150-dp", + "qcom,sm8350-dp"; reg = <0xae90000 0x200>, <0xae90200 0x200>, <0xae90400 0xc00>, -- cgit v1.2.3 From 2c97ee44d29e90e0e1687c15bca4f1aa8eff3d78 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Wed, 3 Sep 2025 14:58:15 +0300 Subject: dt-bindings: display/msm: qcom,x1e80100-mdss: correct DP addresses Fix c&p error and correct example to use 32-bit addressing (as the rest of the example DT does) instead of 64-bit (as the platform does). It got unnoticed before since DP controller node wasn't validated against DT schema because of the missing compatible. Fixes: 81de267367d4 ("dt-bindings: display/msm: Document MDSS on X1E80100") Signed-off-by: Abhinav Kumar Reviewed-by: Rob Herring (Arm) Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/672574/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-4-7526f0311eaa@oss.qualcomm.com --- .../devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml index 3b01a0e47333..e35230a86437 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -170,11 +170,11 @@ examples: displayport-controller@ae90000 { compatible = "qcom,x1e80100-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0x600>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0x600>, + <0xae91000 0x400>, + <0xae91400 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; -- cgit v1.2.3 From 3259ffe5b14d977c52e3e56f31cf07ca21fb314d Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Wed, 3 Sep 2025 14:58:16 +0300 Subject: dt-bindings: display/msm: dp-controller: add X1E80100 Add X1E80100 to the dp-controller bindings, it has DisplayPort controller similar to other platforms, but it uses its own compatible string. Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang Acked-by: Rob Herring (Arm) Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/672578/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-5-7526f0311eaa@oss.qualcomm.com --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index a18183f7ec21..6316c929fd66 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -29,6 +29,8 @@ properties: - qcom,sdm845-dp - qcom,sm8350-dp - qcom,sm8650-dp + - qcom,x1e80100-dp + - items: - enum: - qcom,sm6350-dp @@ -193,6 +195,7 @@ allOf: contains: enum: - qcom,sa8775p-dp + - qcom,x1e80100-dp then: oneOf: - required: -- cgit v1.2.3 From 0253f5ef8da491e8e694763c4aa2ac2f48ede932 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Wed, 3 Sep 2025 14:58:17 +0300 Subject: dt-bindings: display/msm: drop assigned-clock-parents for dp controller DP controller schema documents assigned-clocks and assigned-clock-parents. However these assignments should not be a part of the ABI: there are no actual requirements on the order of the assignments, MST cases require different number of clocks to be assigned, etc. Instead of fixing up the documentation, drop the assigned-clock-parents and assigned-clocks from the bindings. The generic clock/clock.yaml already covers these properties. Suggested-by: Krzysztof Kozlowski Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang Acked-by: Rob Herring (Arm) Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/672586/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-6-7526f0311eaa@oss.qualcomm.com --- .../devicetree/bindings/display/msm/dp-controller.yaml | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 6316c929fd66..afe01332d66c 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -86,16 +86,6 @@ properties: - const: ctrl_link_iface - const: stream_pixel - assigned-clocks: - items: - - description: link clock source - - description: pixel clock source - - assigned-clock-parents: - items: - - description: phy 0 parent - - description: phy 1 parent - phys: maxItems: 1 -- cgit v1.2.3 From 9be5c47908e669db4934ef9c129b28bbc879a8be Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Wed, 3 Sep 2025 14:58:18 +0300 Subject: dt-bindings: display/msm: expand to support MST On a vast majority of Qualcomm chipsets DisplayPort controller can support several MST streams (up to 4x). To support MST these chipsets use up to 4 stream pixel clocks for the DisplayPort controller and several extra register regions. Expand corresponding region and clock bindings for these platforms and fix example schema files to follow updated bindings. Note: On chipsets that support MST, the number of streams supported can vary between controllers. For example, SA8775P supports 4 MST streams on mdss_dp0 but only 2 streams on mdss_dp1. Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring (Arm) Patchwork: https://patchwork.freedesktop.org/patch/672585/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-7-7526f0311eaa@oss.qualcomm.com --- .../bindings/display/msm/dp-controller.yaml | 103 ++++++++++++++++++++- .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 26 +++++- .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 10 +- .../bindings/display/msm/qcom,sc7280-mdss.yaml | 3 +- .../bindings/display/msm/qcom,sm7150-mdss.yaml | 10 +- .../bindings/display/msm/qcom,sm8750-mdss.yaml | 10 +- .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 10 +- 7 files changed, 150 insertions(+), 22 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index afe01332d66c..aeb4e4f36044 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -66,25 +66,37 @@ properties: - description: link register block - description: p0 register block - description: p1 register block + - description: p2 register block + - description: p3 register block + - description: mst2link register block + - description: mst3link register block interrupts: maxItems: 1 clocks: + minItems: 5 items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock + - description: Display Port stream 1 Pixel clock + - description: Display Port stream 2 Pixel clock + - description: Display Port stream 3 Pixel clock clock-names: + minItems: 5 items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel + - const: stream_1_pixel + - const: stream_2_pixel + - const: stream_3_pixel phys: maxItems: 1 @@ -166,7 +178,6 @@ required: allOf: # AUX BUS does not exist on DP controllers # Audio output also is present only on DP output - # p1 regions is present on DP, but not on eDP - if: properties: compatible: @@ -195,11 +206,95 @@ allOf: else: properties: aux-bus: false - reg: - minItems: 5 required: - "#sound-dai-cells" + - if: + properties: + compatible: + contains: + enum: + # these platforms support SST only + - qcom,sc7180-dp + - qcom,sc7280-dp + - qcom,sc7280-edp + - qcom,sc8180x-edp + - qcom,sc8280xp-edp + then: + properties: + reg: + minItems: 5 + maxItems: 5 + clocks: + minItems: 5 + maxItems: 5 + clocks-names: + minItems: 5 + maxItems: 5 + + - if: + properties: + compatible: + contains: + enum: + # these platforms support 2 streams MST on some interfaces, + # others are SST only + - qcom,sc8280xp-dp + - qcom,x1e80100-dp + then: + properties: + reg: + minItems: 5 + maxItems: 5 + clocks: + minItems: 5 + maxItems: 6 + clocks-names: + minItems: 5 + maxItems: 6 + + - if: + properties: + compatible: + contains: + # 2 streams MST + enum: + - qcom,sc8180x-dp + - qcom,sdm845-dp + - qcom,sm8350-dp + - qcom,sm8650-dp + then: + properties: + reg: + minItems: 5 + maxItems: 5 + clocks: + minItems: 6 + maxItems: 6 + clocks-names: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + # these platforms support 4 stream MST on first DP, + # 2 streams MST on the second one. + - qcom,sa8775p-dp + then: + properties: + reg: + minItems: 9 + maxItems: 9 + clocks: + minItems: 6 + maxItems: 8 + clocks-names: + minItems: 6 + maxItems: 8 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index 1053b3bc4908..e2730a2f25cf 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -375,7 +375,11 @@ examples: <0xaf54200 0x0c0>, <0xaf55000 0x770>, <0xaf56000 0x09c>, - <0xaf57000 0x09c>; + <0xaf57000 0x09c>, + <0xaf58000 0x09c>, + <0xaf59000 0x09c>, + <0xaf5a000 0x23c>, + <0xaf5b000 0x23c>; interrupt-parent = <&mdss0>; interrupts = <12>; @@ -384,16 +388,28 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>, + <&dispcc_dptx0_pixel2_clk>, + <&dispcc_dptx0_pixel3_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, - <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + <&dispcc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>, + <&dispcc_mdss_dptx0_pixel2_clk_src>, + <&dispcc_mdss_dptx0_pixel3_clk_src>; + assigned-clock-parents = <&mdss0_dp0_phy 0>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>; phys = <&mdss0_dp0_phy>; phy-names = "dp"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml index 870144b53cec..44c1bb9e4109 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -207,16 +207,20 @@ examples: <&dispcc_disp_cc_mdss_dptx0_aux_clk>, <&dispcc_disp_cc_mdss_dptx0_link_clk>, <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>, + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index 2947f27e0585..b643d3adf669 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -281,7 +281,8 @@ examples: reg = <0xaea0000 0x200>, <0xaea0200 0x200>, <0xaea0400 0xc00>, - <0xaea1000 0x400>; + <0xaea1000 0x400>, + <0xaea1400 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml index c5d209019124..9b0621d88d50 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml @@ -394,16 +394,20 @@ examples: <&dispcc_mdss_dp_aux_clk>, <&dispcc_mdss_dp_link_clk>, <&dispcc_mdss_dp_link_intf_clk>, - <&dispcc_mdss_dp_pixel_clk>; + <&dispcc_mdss_dp_pixel_clk>, + <&dispcc_mdss_dp_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc_mdss_dp_link_clk_src>, - <&dispcc_mdss_dp_pixel_clk_src>; + <&dispcc_mdss_dp_pixel_clk_src>, + <&dispcc_mdss_dp_pixel1_clk_src>; assigned-clock-parents = <&dp_phy 0>, + <&dp_phy 1>, <&dp_phy 1>; operating-points-v2 = <&dp_opp_table>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml index 72c70edc1fb0..4151f475f3bc 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -401,16 +401,20 @@ examples: <&disp_cc_mdss_dptx0_aux_clk>, <&disp_cc_mdss_dptx0_link_clk>, <&disp_cc_mdss_dptx0_link_intf_clk>, - <&disp_cc_mdss_dptx0_pixel0_clk>; + <&disp_cc_mdss_dptx0_pixel0_clk>, + <&disp_cc_mdss_dptx0_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>, - <&disp_cc_mdss_dptx0_pixel0_clk_src>; + <&disp_cc_mdss_dptx0_pixel0_clk_src>, + <&disp_cc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&dp_opp_table>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml index e35230a86437..8d698a2e055a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -183,15 +183,19 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, - <&dispcc_mdss_dptx0_pixel0_clk_src>; + <&dispcc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp0_opp_table>; -- cgit v1.2.3 From 9428fff44f0c5823fde733b64a344d7a6eda3873 Mon Sep 17 00:00:00 2001 From: "hongyu.chen1" Date: Fri, 22 Aug 2025 13:39:55 +0800 Subject: dt-bindings: power: add Amlogic S6 S7 S7D power domains Add devicetree binding document and related header file for Amlogic S6 S7 S7D secure power domains. Signed-off-by: hongyu.chen1 Signed-off-by: Xianwei Zhao Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250822-pm-s6-s7-s7d-v1-1-82e3f3aff327@amlogic.com Signed-off-by: Ulf Hansson --- .../bindings/power/amlogic,meson-sec-pwrc.yaml | 3 +++ include/dt-bindings/power/amlogic,s6-pwrc.h | 29 ++++++++++++++++++++++ include/dt-bindings/power/amlogic,s7-pwrc.h | 20 +++++++++++++++ include/dt-bindings/power/amlogic,s7d-pwrc.h | 27 ++++++++++++++++++++ 4 files changed, 79 insertions(+) create mode 100644 include/dt-bindings/power/amlogic,s6-pwrc.h create mode 100644 include/dt-bindings/power/amlogic,s7-pwrc.h create mode 100644 include/dt-bindings/power/amlogic,s7d-pwrc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml index 15d74138baa3..12b71688dd34 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -24,6 +24,9 @@ properties: - amlogic,a5-pwrc - amlogic,c3-pwrc - amlogic,t7-pwrc + - amlogic,s6-pwrc + - amlogic,s7-pwrc + - amlogic,s7d-pwrc "#power-domain-cells": const: 1 diff --git a/include/dt-bindings/power/amlogic,s6-pwrc.h b/include/dt-bindings/power/amlogic,s6-pwrc.h new file mode 100644 index 000000000000..2c005864ae73 --- /dev/null +++ b/include/dt-bindings/power/amlogic,s6-pwrc.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Amlogic, Inc. All rights reserved + */ +#ifndef _DT_BINDINGS_AMLOGIC_S6_POWER_H +#define _DT_BINDINGS_AMLOGIC_S6_POWER_H + +#define PWRC_S6_DSPA_ID 0 +#define PWRC_S6_DOS_HEVC_ID 1 +#define PWRC_S6_DOS_VDEC_ID 2 +#define PWRC_S6_VPU_HDMI_ID 3 +#define PWRC_S6_U2DRD_ID 4 +#define PWRC_S6_U3DRD_ID 5 +#define PWRC_S6_SD_EMMC_C_ID 6 +#define PWRC_S6_GE2D_ID 7 +#define PWRC_S6_AMFC_ID 8 +#define PWRC_S6_VC9000E_ID 9 +#define PWRC_S6_DEWARP_ID 10 +#define PWRC_S6_VICP_ID 11 +#define PWRC_S6_SD_EMMC_A_ID 12 +#define PWRC_S6_SD_EMMC_B_ID 13 +#define PWRC_S6_ETH_ID 14 +#define PWRC_S6_PCIE_ID 15 +#define PWRC_S6_NNA_4T_ID 16 +#define PWRC_S6_AUDIO_ID 17 +#define PWRC_S6_AUCPU_ID 18 +#define PWRC_S6_ADAPT_ID 19 + +#endif diff --git a/include/dt-bindings/power/amlogic,s7-pwrc.h b/include/dt-bindings/power/amlogic,s7-pwrc.h new file mode 100644 index 000000000000..3f21d095f784 --- /dev/null +++ b/include/dt-bindings/power/amlogic,s7-pwrc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Amlogic, Inc. All rights reserved + */ +#ifndef _DT_BINDINGS_AMLOGIC_S7_POWER_H +#define _DT_BINDINGS_AMLOGIC_S7_POWER_H + +#define PWRC_S7_DOS_HEVC_ID 0 +#define PWRC_S7_DOS_VDEC_ID 1 +#define PWRC_S7_VPU_HDMI_ID 2 +#define PWRC_S7_USB_COMB_ID 3 +#define PWRC_S7_SD_EMMC_C_ID 4 +#define PWRC_S7_GE2D_ID 5 +#define PWRC_S7_SD_EMMC_A_ID 6 +#define PWRC_S7_SD_EMMC_B_ID 7 +#define PWRC_S7_ETH_ID 8 +#define PWRC_S7_AUCPU_ID 9 +#define PWRC_S7_AUDIO_ID 10 + +#endif diff --git a/include/dt-bindings/power/amlogic,s7d-pwrc.h b/include/dt-bindings/power/amlogic,s7d-pwrc.h new file mode 100644 index 000000000000..c6998553670a --- /dev/null +++ b/include/dt-bindings/power/amlogic,s7d-pwrc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Amlogic, Inc. All rights reserved + */ +#ifndef _DT_BINDINGS_AMLOGIC_S7D_POWER_H +#define _DT_BINDINGS_AMLOGIC_S7D_POWER_H + +#define PWRC_S7D_DOS_HCODEC_ID 0 +#define PWRC_S7D_DOS_HEVC_ID 1 +#define PWRC_S7D_DOS_VDEC_ID 2 +#define PWRC_S7D_VPU_HDMI_ID 3 +#define PWRC_S7D_USB_U2DRD_ID 4 +#define PWRC_S7D_USB_U2H_ID 5 +#define PWRC_S7D_SSD_EMMC_C_ID 6 +#define PWRC_S7D_GE2D_ID 7 +#define PWRC_S7D_AMFC_ID 8 +#define PWRC_S7D_EMMC_A_ID 9 +#define PWRC_S7D_EMMC_B_ID 10 +#define PWRC_S7D_ETH_ID 11 +#define PWRC_S7D_AUCPU_ID 12 +#define PWRC_S7D_AUDIO_ID 13 +#define PWRC_S7D_SRAMA_ID 14 +#define PWRC_S7D_DMC0_ID 15 +#define PWRC_S7D_DMC1_ID 16 +#define PWRC_S7D_DDR_ID 17 + +#endif -- cgit v1.2.3 From acd2fa47aac568052bd8321586be64958e3e93b2 Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Wed, 3 Sep 2025 18:01:17 +0200 Subject: ASoC: dt-bindings: everest,es8316: Document routing strings Add a list of the es8316 pin names to the binding's description to make it self-contained and improve the user experience for board developers. Signed-off-by: Jihed Chaibi Acked-by: Rob Herring (Arm) Message-ID: <20250903160119.83625-2-jihed.chaibi.dev@gmail.com> Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/everest,es8316.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/everest,es8316.yaml b/Documentation/devicetree/bindings/sound/everest,es8316.yaml index e4b2eb5fae2f..81a0215050e0 100644 --- a/Documentation/devicetree/bindings/sound/everest,es8316.yaml +++ b/Documentation/devicetree/bindings/sound/everest,es8316.yaml @@ -12,6 +12,22 @@ maintainers: - Matteo Martelli - Binbin Zhou +description: | + Everest ES8311, ES8316 and ES8323 audio CODECs + + Pins on the device (for linking into audio routes): + + Outputs: + * LOUT: Left Analog Output + * ROUT: Right Analog Output + * MICBIAS: Microphone Bias + + Inputs: + * MIC1P: Microphone 1 Positive Analog Input + * MIC1N: Microphone 1 Negative Analog Input + * MIC2P: Microphone 2 Positive Analog Input + * MIC2N: Microphone 2 Negative Analog Input + allOf: - $ref: dai-common.yaml# -- cgit v1.2.3 From 118ddab8bb4a06fd5e13446d11d69e301044087d Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Wed, 3 Sep 2025 18:01:18 +0200 Subject: ASoC: dt-bindings: nuvoton,nau8825: Document routing strings Add a list of the nau8825 pin names to the binding's description to make it self-contained and improve the user experience for board developers. Signed-off-by: Jihed Chaibi Acked-by: Rob Herring (Arm) Message-ID: <20250903160119.83625-3-jihed.chaibi.dev@gmail.com> Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/nuvoton,nau8825.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/nuvoton,nau8825.yaml b/Documentation/devicetree/bindings/sound/nuvoton,nau8825.yaml index a54f194a0b49..4ebbcb4e6056 100644 --- a/Documentation/devicetree/bindings/sound/nuvoton,nau8825.yaml +++ b/Documentation/devicetree/bindings/sound/nuvoton,nau8825.yaml @@ -9,6 +9,20 @@ title: NAU8825 audio CODEC maintainers: - John Hsu +description: | + NAU8825 audio CODEC + + Pins on the device (for linking into audio routes): + + Outputs: + * HPOL : Headphone Left Output + * HPOR : Headphone Right Output + * MICBIAS : Microphone Bias Output + + Inputs: + * MICP : Analog Microphone Positive Input + * MICN : Analog Microphone Negative Input + allOf: - $ref: dai-common.yaml# -- cgit v1.2.3 From 0ccc1eeda155c947d88ef053e0b54e434e218ee2 Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Wed, 3 Sep 2025 18:01:19 +0200 Subject: ASoC: dt-bindings: wlf,wm8960: Document routing strings (pin names) Add a list of the wm8960 pin names to the binding's description to make it self-contained and improve the user experience for board developers. Signed-off-by: Jihed Chaibi Reviewed-by: Charles Keepax Acked-by: Rob Herring (Arm) Message-ID: <20250903160119.83625-4-jihed.chaibi.dev@gmail.com> Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/wlf,wm8960.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml b/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml index 3c2b9790ffcf..c8c786cb6c4b 100644 --- a/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml +++ b/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml @@ -9,6 +9,28 @@ title: Wolfson WM8960 audio codec maintainers: - patches@opensource.cirrus.com +description: | + Wolfson WM8960 audio codec + + Pins on the device (for linking into audio routes): + + Outputs: + * HP_L : Left Headphone/Line Output + * HP_R : Right Headphone/Line Output + * SPK_LP : Left Speaker Output (Positive) + * SPK_LN : Left Speaker Output (Negative) + * SPK_RP : Right Speaker Output (Positive) + * SPK_RN : Right Speaker Output (Negative) + * OUT3 : Mono, Left, Right or buffered midrail output for capless mode + + Inputs: + * LINPUT1 : Left single-ended or negative differential microphone input + * RINPUT1 : Right single-ended or negative differential microphone input + * LINPUT2 : Left line input or positive differential microphone input + * RINPUT2 : Right line input or positive differential microphone input + * LINPUT3 : Left line input, positive differential microphone, or Jack Detect 2 + * RINPUT3 : Right line input, positive differential microphone, or Jack Detect 3 + properties: compatible: const: wlf,wm8960 -- cgit v1.2.3 From 7748328c2fd82efed24257b2bfd796eb1fa1d09b Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Wed, 3 Sep 2025 20:43:30 +0530 Subject: ASoC: dt-bindings: qcom,lpass-va-macro: Update bindings for clocks to support ADSP Manage clock settings for ADSP solution. On Existing ADSP bypass solutions, the macro and dcodec GDSCs are enabled using power domains in lpass-va-macro which is not applicable for ADSP based platform. Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Krzysztof Kozlowski Message-ID: <20250903151337.1037246-2-mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Mark Brown --- .../bindings/sound/qcom,lpass-va-macro.yaml | 23 +++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index 2e8c26d89b00..1c0d78af3c05 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -80,12 +80,25 @@ allOf: compatible: contains: const: qcom,sc7280-lpass-va-macro + then: - properties: - clocks: - maxItems: 1 - clock-names: - maxItems: 1 + if: + required: + - power-domains + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + else: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + minItems: 3 + maxItems: 3 - if: properties: -- cgit v1.2.3 From 4d32c1f66a768dd281edadbd244dce1c63c0899d Mon Sep 17 00:00:00 2001 From: Barnabás Czémán Date: Wed, 3 Sep 2025 23:08:21 +0200 Subject: dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device tree bindings for the global clock controller on Qualcomm MSM8937 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20250903-msm8937-v9-1-a097c91c5801@mainlining.org Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 11 ++++++++--- include/dt-bindings/clock/qcom,gcc-msm8917.h | 19 +++++++++++++++++++ 2 files changed, 27 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml index fe1f5f3ed992..f2e37f439d28 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml @@ -9,16 +9,21 @@ title: Qualcomm Global Clock & Reset Controller on MSM8953 maintainers: - Adam Skladowski - Sireesh Kodali + - Barnabas Czeman description: | Qualcomm global clock control module provides the clocks, resets and power - domains on MSM8953. + domains on MSM8937 or MSM8953. - See also: include/dt-bindings/clock/qcom,gcc-msm8953.h + See also:: + include/dt-bindings/clock/qcom,gcc-msm8917.h + include/dt-bindings/clock/qcom,gcc-msm8953.h properties: compatible: - const: qcom,gcc-msm8953 + enum: + - qcom,gcc-msm8937 + - qcom,gcc-msm8953 clocks: items: diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h index 4b421e7414b5..4e3897b3669d 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8917.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -170,6 +170,23 @@ #define VFE1_CLK_SRC 163 #define VSYNC_CLK_SRC 164 #define GPLL0_SLEEP_CLK_SRC 165 +/* Addtional MSM8937-specific clocks */ +#define MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC 166 +#define MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC 167 +#define MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC 168 +#define MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC 169 +#define MSM8937_BYTE1_CLK_SRC 170 +#define MSM8937_ESC1_CLK_SRC 171 +#define MSM8937_PCLK1_CLK_SRC 172 +#define MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK 173 +#define MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK 174 +#define MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK 175 +#define MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK 176 +#define MSM8937_GCC_MDSS_BYTE1_CLK 177 +#define MSM8937_GCC_MDSS_ESC1_CLK 178 +#define MSM8937_GCC_MDSS_PCLK1_CLK 179 +#define MSM8937_GCC_OXILI_AON_CLK 180 +#define MSM8937_GCC_OXILI_TIMER_CLK 181 /* GCC block resets */ #define GCC_CAMSS_MICRO_BCR 0 @@ -187,5 +204,7 @@ #define VENUS_GDSC 5 #define VFE0_GDSC 6 #define VFE1_GDSC 7 +/* Additional MSM8937-specific GDSCs */ +#define MSM8937_OXILI_CX_GDSC 8 #endif -- cgit v1.2.3 From cf13bed78c90b2c0fc65774e86d564c868fa2a23 Mon Sep 17 00:00:00 2001 From: Barnabás Czémán Date: Wed, 3 Sep 2025 23:08:23 +0200 Subject: dt-bindings: firmware: qcom,scm: Add MSM8937 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add compatible for MSM8937. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20250903-msm8937-v9-3-a097c91c5801@mainlining.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index b913192219e4..ef97faac7e47 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -36,6 +36,7 @@ properties: - qcom,scm-msm8226 - qcom,scm-msm8660 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -134,6 +135,7 @@ allOf: - qcom,scm-msm8226 - qcom,scm-msm8660 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -177,6 +179,7 @@ allOf: - qcom,scm-mdm9607 - qcom,scm-msm8226 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8974 - qcom,scm-msm8976 -- cgit v1.2.3 From 604a932fa924e7b15be47c6208a305f289cfa309 Mon Sep 17 00:00:00 2001 From: SungMin Park Date: Mon, 1 Sep 2025 10:49:23 +0530 Subject: dt-bindings: arm: axis: Add ARTPEC-8 grizzly board Document the Axis ARTPEC-8 SoC binding and the grizzly board which uses ARTPEC-8 SoC. Signed-off-by: SungMin Park Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250901051926.59970-4-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/axis.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml index f9c218dc6883..63e9aca85db7 100644 --- a/Documentation/devicetree/bindings/arm/axis.yaml +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -8,6 +8,7 @@ title: Axis ARTPEC platforms maintainers: - Jesper Nilsson + - Lars Persson - linux-arm-kernel@axis.com description: | @@ -24,6 +25,12 @@ properties: - axis,artpec6-dev-board - const: axis,artpec6 + - description: Axis ARTPEC-8 SoC board + items: + - enum: + - axis,artpec8-grizzly + - const: axis,artpec8 + additionalProperties: true ... -- cgit v1.2.3 From 3cd4c4f3955bd97470cc8728c28327cffb09f71e Mon Sep 17 00:00:00 2001 From: Conley Lee Date: Wed, 3 Sep 2025 16:22:38 +0800 Subject: dt-bindings: net: sun4i-emac: add dma support The sun4i EMAC supports DMA for data transmission, so it is necessary to add DMA options to the device tree bindings. Signed-off-by: Conley Lee Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/tencent_4E434174E9D516431365413D1B8047C6BB06@qq.com Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml index eb26623dab51..d4d8f3a7918e 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml @@ -33,6 +33,15 @@ properties: - items: - description: phandle to SRAM - description: register value for device + dmas: + items: + - description: RX DMA Channel + - description: TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx required: - compatible -- cgit v1.2.3 From 0fec357ad073e555e7553dbc0d32278b0aaa2179 Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Sun, 24 Aug 2025 18:12:05 +0200 Subject: dt-bindings: input: touchscreen: imagis: add missing minItems MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding currently expects exactly 5 keycodes, which matches the chip's theoretical maximum but probably not the number of touch keys on any phone using the IST3032C. Add a minItems value of 2 to prevent dt-validate complaints. Also add another example to make sure the linux,keycodes property is checked. Signed-off-by: Duje Mihanović Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250824-imagis-minitems-v1-1-cea9db55e87f@dujemihanovic.xyz Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/imagis,ist3038c.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml b/Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml index bd8ede3a4ad8..0ef79343bf9a 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/imagis,ist3038c.yaml @@ -35,6 +35,7 @@ properties: linux,keycodes: description: Keycodes for the touch keys + minItems: 2 maxItems: 5 touchscreen-size-x: true @@ -87,5 +88,22 @@ examples: touchscreen-inverted-y; }; }; + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + touchscreen@50 { + compatible = "imagis,ist3032c"; + reg = <0x50>; + interrupt-parent = <&gpio>; + interrupts = <72 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ldo2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + linux,keycodes = , ; + }; + }; ... -- cgit v1.2.3 From f5e36ecc9e4a2a4bcd942ad1e9947e018ffd15b5 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 23 Aug 2025 03:01:41 -0700 Subject: dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC Describe JH7110 SoC DDR external memory interface. Signed-off-by: E Shattow Reviewed-by: Krzysztof Kozlowski Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- .../memory-controllers/starfive,jh7110-dmc.yaml | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file mode 100644 index 000000000000..d65313b33a3e --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 DMC + +maintainers: + - E Shattow + +description: + JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at + 2133Mbps (up to 2800Mbps). + +properties: + compatible: + items: + - const: starfive,jh7110-dmc + + reg: + items: + - description: controller registers + - description: phy registers + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pll + + resets: + items: + - description: axi + - description: osc + - description: apb + + reset-names: + items: + - const: axi + - const: osc + - const: apb + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + }; -- cgit v1.2.3 From cce65107897d699c78373b88f3fe94602f194d0e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 29 Aug 2025 18:04:40 -0500 Subject: dt-bindings: gpu: Convert aspeed,ast2400-gfx to DT schema Convert the ASpeed GFX Display Controller binding to DT schema format. There was a duplicate, incomplete binding in mfd which can be dropped. Add the missing 'aspeed,ast2600-gfx' compatible and 'syscon' property. Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20250829230442.1495926-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../bindings/gpu/aspeed,ast2400-gfx.yaml | 63 ++++++++++++++++++++++ .../devicetree/bindings/gpu/aspeed-gfx.txt | 41 -------------- .../devicetree/bindings/mfd/aspeed-gfx.txt | 17 ------ MAINTAINERS | 2 +- 4 files changed, 64 insertions(+), 59 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml delete mode 100644 Documentation/devicetree/bindings/gpu/aspeed-gfx.txt delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml b/Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml new file mode 100644 index 000000000000..20a4e00086ee --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/aspeed,ast2400-gfx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED GFX Display Controller + +maintainers: + - Joel Stanley + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-gfx + - aspeed,ast2500-gfx + - aspeed,ast2600-gfx + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + description: + a reserved-memory region to use for the framebuffer. + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to SCU + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - memory-region + +additionalProperties: false + +examples: + - | + #include + + display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + memory-region = <&gfx_memory>; + }; diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt deleted file mode 100644 index 958bdf962339..000000000000 --- a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt +++ /dev/null @@ -1,41 +0,0 @@ -Device tree configuration for the GFX display device on the ASPEED SoCs - -Required properties: - - compatible - * Must be one of the following: - + aspeed,ast2500-gfx - + aspeed,ast2400-gfx - * In addition, the ASPEED pinctrl bindings require the 'syscon' property to - be present - - - reg: Physical base address and length of the GFX registers - - - interrupts: interrupt number for the GFX device - - - clocks: clock number used to generate the pixel clock - - - resets: reset line that must be released to use the GFX device - - - memory-region: - Phandle to a memory region to allocate from, as defined in - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - - -Example: - -gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; - resets = <&syscon ASPEED_RESET_CRT1>; - interrupts = <0x19>; - memory-region = <&gfx_memory>; -}; - -gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; -}; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt deleted file mode 100644 index aea5370efd97..000000000000 --- a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Device tree bindings for Aspeed SoC Display Controller (GFX) - -The Aspeed SoC Display Controller primarily does as its name suggests, but also -participates in pinmux requests on the g5 SoCs. It is therefore considered a -syscon device. - -Required properties: -- compatible: "aspeed,ast2500-gfx", "syscon" -- reg: contains offset/length value of the GFX memory - region. - -Example: - -gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; -}; diff --git a/MAINTAINERS b/MAINTAINERS index 4e6fa336ff70..f3dcc2f64bc7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7543,7 +7543,7 @@ M: Joel Stanley L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) S: Supported T: git https://gitlab.freedesktop.org/drm/misc/kernel.git -F: Documentation/devicetree/bindings/gpu/aspeed-gfx.txt +F: Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml F: drivers/gpu/drm/aspeed/ DRM DRIVER FOR AST SERVER GRAPHICS CHIPS -- cgit v1.2.3 From 725386ca1949a570d8b73b179518998d399031bf Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Thu, 28 Aug 2025 15:17:10 +0200 Subject: dt-bindings: mmc: Add support for capabilities to Broadcom SDHCI controller The Broadcom BRCMSTB SDHCI Controller device supports Common properties in terms of Capabilities. Reference sdhci-common schema instead of mmc-controller in order for capabilities to be specified in DT nodes avoiding warnings from the DT compiler. Signed-off-by: Andrea della Porta Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/181cc905566f2d9b2e5076295cd285230f81ed07.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index eee6be7a7867..493655a38b37 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -61,7 +61,7 @@ properties: description: Specifies that controller should use auto CMD12 allOf: - - $ref: mmc-controller.yaml# + - $ref: sdhci-common.yaml# - if: properties: clock-names: -- cgit v1.2.3 From d9c74e6f8125ef43d0282c12cb788ae4c5290c27 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Fri, 22 Aug 2025 12:34:37 +0300 Subject: dt-bindings: net: cdns,macb: Add compatible for Raspberry Pi RP1 The Raspberry Pi RP1 chip has the Cadence GEM ethernet controller, so add a compatible string for it. Signed-off-by: Dave Stevenson Signed-off-by: Stanimir Varbanov Reviewed-by: Andrew Lunn Acked-by: Conor Dooley Reviewed-by: Nicolas Ferre Reviewed-by: Claudiu Beznea Link: https://patch.msgid.link/20250822093440.53941-3-svarbanov@suse.de Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index 559d0f733e7e..0591da97d434 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -54,6 +54,7 @@ properties: - cdns,np4-macb # NP4 SoC devices - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface + - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface - sifive,fu540-c000-gem # SiFive FU540-C000 SoC - cdns,emac # Generic - cdns,gem # Generic -- cgit v1.2.3 From f4c45db8a10b270bdd4a1644f545576c03ead523 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 29 Aug 2025 11:13:25 +0200 Subject: dt-bindings: panel: lvds: Append edt,etml0700z8dha in panel-lvds List EDT ETML0700Z8DHA in the LVDS panel enumeration. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250829-drm-misc-next-v1-1-fedb48cf50dd@foss.st.com Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml index f8f95e772778..4388d5375851 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml @@ -48,6 +48,8 @@ properties: - auo,g084sn05 # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel - chunghwa,claa070wp03xg + # EDT ETML0700Z8DHA 7.0" Full HD (1920x1080) color TFT LCD LVDS panel + - edt,etml0700z8dha # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel - edt,etml0700z9ndha # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel -- cgit v1.2.3 From 09b26dce32f0d3065e6cfbc1095fc21fd5159921 Mon Sep 17 00:00:00 2001 From: Wig Cheng Date: Tue, 2 Sep 2025 14:53:18 +0800 Subject: dt-bindings: vendor-prefixes: Add Mayqueen name Mayqueen is a Taiwan-based company primarily focused on the development of arm64 development boards and e-paper displays. Signed-off-by: Wig Cheng Acked-by: Rob Herring (Arm) Acked-by: Krzysztof Kozlowski Signed-off-by: Thomas Zimmermann Link: https://lore.kernel.org/r/20250902-drm-v5-1-d77c678c4ae3@gmail.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index abc43c43813a..7d74ecfee675 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -933,6 +933,8 @@ patternProperties: description: Maxim Integrated Products "^maxlinear,.*": description: MaxLinear Inc. + "^mayqueen,.*": + description: Mayqueen Technologies Ltd. "^mbvl,.*": description: Mobiveil Inc. "^mcube,.*": -- cgit v1.2.3 From d309c5fdf4a795e587f1852e2caf7f205c1bdffc Mon Sep 17 00:00:00 2001 From: LiangCheng Wang Date: Tue, 2 Sep 2025 14:53:19 +0800 Subject: dt-bindings: display: Add Mayqueen Pixpaper e-ink panel The binding is for the Mayqueen Pixpaper e-ink display panel, controlled via an SPI interface. Signed-off-by: LiangCheng Wang Reviewed-by: Rob Herring (Arm) Signed-off-by: Thomas Zimmermann Link: https://lore.kernel.org/r/20250902-drm-v5-2-d77c678c4ae3@gmail.com --- .../bindings/display/mayqueen,pixpaper.yaml | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mayqueen,pixpaper.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/mayqueen,pixpaper.yaml b/Documentation/devicetree/bindings/display/mayqueen,pixpaper.yaml new file mode 100644 index 000000000000..cd27f8ba5ae1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mayqueen,pixpaper.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mayqueen,pixpaper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mayqueen Pixpaper e-ink display panel + +maintainers: + - LiangCheng Wang + +description: + The Pixpaper is an e-ink display panel controlled via an SPI interface. + The panel has a resolution of 122x250 pixels and requires GPIO pins for + reset, busy, and data/command control. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: mayqueen,pixpaper + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 1000000 + default: 1000000 + + reset-gpios: + maxItems: 1 + + busy-gpios: + maxItems: 1 + + dc-gpios: + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + - busy-gpios + - dc-gpios + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + display@0 { + compatible = "mayqueen,pixpaper"; + reg = <0>; + spi-max-frequency = <1000000>; + reset-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + busy-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + dc-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + }; + }; -- cgit v1.2.3 From f5d15ff664a32593e0152d21ea747fb77e32ce7e Mon Sep 17 00:00:00 2001 From: Woodrow Douglass Date: Fri, 5 Sep 2025 08:39:42 -0400 Subject: regulator: dt-bindings: nxp,pf530x: Add NXP PF5300/PF5301/PF5302 PMICs Bindings for the pf530x series of voltage regulators Signed-off-by: Woodrow Douglass Reviewed-by: Krzysztof Kozlowski Message-ID: <20250902-pf530x-v7-1-10eb2542f944@carnegierobotics.com> Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/nxp,pf5300.yaml | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/nxp,pf5300.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/nxp,pf5300.yaml b/Documentation/devicetree/bindings/regulator/nxp,pf5300.yaml new file mode 100644 index 000000000000..5b9d5d4e48d0 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/nxp,pf5300.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/nxp,pf5300.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PF5300/PF5301/PF5302 PMIC regulators + +maintainers: + - Woodrow Douglass + +description: | + The PF5300, PF5301, and PF5302 integrate high-performance buck converters, + 12 A, 8 A, and 15 A, respectively, to power high-end automotive and industrial + processors. With adaptive voltage positioning and a high-bandwidth loop, they + offer transient regulation to minimize capacitor requirements. + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + oneOf: + - const: nxp,pf5300 + - items: + - enum: + - nxp,pf5301 + - nxp,pf5302 + - const: nxp,pf5300 + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@28 { + compatible = "nxp,pf5302", "nxp,pf5300"; + reg = <0x28>; + + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <500000>; + }; + }; -- cgit v1.2.3 From 9de9040ffc6a3c616a0b4c13c7d4d1c2778cb6ee Mon Sep 17 00:00:00 2001 From: Mounika Botcha Date: Mon, 25 Aug 2025 12:46:58 +0530 Subject: dt-bindings: crypto: Add node for True Random Number Generator Add TRNG node compatible string and reg properities. Signed-off-by: Mounika Botcha Signed-off-by: Harsh Jain Reviewed-by: Krzysztof Kozlowski Signed-off-by: Herbert Xu --- .../bindings/crypto/xlnx,versal-trng.yaml | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,versal-trng.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/xlnx,versal-trng.yaml b/Documentation/devicetree/bindings/crypto/xlnx,versal-trng.yaml new file mode 100644 index 000000000000..9dfb0b0ab5c8 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/xlnx,versal-trng.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/xlnx,versal-trng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal True Random Number Generator Hardware Accelerator + +maintainers: + - Harsh Jain + - Mounika Botcha + +description: + The Versal True Random Number Generator consists of Ring Oscillators as + entropy source and a deterministic CTR_DRBG random bit generator (DRBG). + +properties: + compatible: + const: xlnx,versal-trng + + reg: + maxItems: 1 + +required: + - reg + +additionalProperties: false + +examples: + - | + rng@f1230000 { + compatible = "xlnx,versal-trng"; + reg = <0xf1230000 0x1000>; + }; +... -- cgit v1.2.3 From 940ce882f75b66fe4f0af6da970566ef441de441 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 21 Aug 2025 23:56:40 +0800 Subject: dt-bindings: iommu: apple,sart: Add Apple A11 Add apple,t8015-sart for SARTv0 found on the Apple A11 SoC, which uses a different MMIO layout and is thus incompatible with the previously described versions Reviewed-by: Sven Peter Acked-by: Rob Herring (Arm) Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250821-t8015-nvme-v3-3-14a4178adf68@gmail.com [sven: adjusted commit message] Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/iommu/apple,sart.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/apple,sart.yaml b/Documentation/devicetree/bindings/iommu/apple,sart.yaml index e87c1520fea6..c8c62f329882 100644 --- a/Documentation/devicetree/bindings/iommu/apple,sart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,sart.yaml @@ -34,6 +34,7 @@ properties: - const: apple,t6000-sart - enum: - apple,t6000-sart + - apple,t8015-sart - apple,t8103-sart reg: -- cgit v1.2.3 From 1dd8daf1cd49b9a97544826670163d6083ad32cc Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 26 Aug 2025 20:09:12 +0800 Subject: dt-bindings: nvme: apple,nvme-ans: Add Apple A11 Add ANS2 NVMe bindings for Apple A11 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250826-t8015-nvme-v5-1-caee6ab00144@gmail.com Signed-off-by: Sven Peter --- .../devicetree/bindings/nvme/apple,nvme-ans.yaml | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml index fc6555724e18..4127d7b0a0f0 100644 --- a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml +++ b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml @@ -11,12 +11,14 @@ maintainers: properties: compatible: - items: - - enum: - - apple,t8103-nvme-ans2 - - apple,t8112-nvme-ans2 - - apple,t6000-nvme-ans2 - - const: apple,nvme-ans2 + oneOf: + - const: apple,t8015-nvme-ans2 + - items: + - enum: + - apple,t8103-nvme-ans2 + - apple,t8112-nvme-ans2 + - apple,t6000-nvme-ans2 + - const: apple,nvme-ans2 reg: items: @@ -67,6 +69,7 @@ if: compatible: contains: enum: + - apple,t8015-nvme-ans2 - apple,t8103-nvme-ans2 - apple,t8112-nvme-ans2 then: -- cgit v1.2.3 From c79bf528738c0e98e0744f7a63c27fab35c93b43 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 20 Aug 2025 14:11:01 +0200 Subject: dt-bindings: usb: IXP4xx UDC bindings This adds device tree bindings for the IXP4xx USB Device Controller (UDC). Signed-off-by: Linus Walleij Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250820-ixp4xx-udc-bindings-v1-1-640f29140164@linaro.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/intel,ixp4xx-udc.yaml | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/intel,ixp4xx-udc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/intel,ixp4xx-udc.yaml b/Documentation/devicetree/bindings/usb/intel,ixp4xx-udc.yaml new file mode 100644 index 000000000000..4ed602746897 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/intel,ixp4xx-udc.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,ixp4xx-udc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx SoC USB Device Controller (UDC) + +description: The IXP4xx SoCs has a full-speed USB Device + Controller with 16 endpoints and a built-in transceiver. + +maintainers: + - Linus Walleij + +properties: + compatible: + const: intel,ixp4xx-udc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + usb@c800b000 { + compatible = "intel,ixp4xx-udc"; + reg = <0xc800b000 0x1000>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + }; -- cgit v1.2.3 From 7d3f780122bee082f035aeb6a3cf073dc77dbd1f Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Sun, 24 Aug 2025 13:23:37 +0200 Subject: usb: dt-bindings: ti,twl4030-usb: convert to DT schema Convert the legacy TXT binding for the TWL4030 USB module to the modern YAML DT schema format. This adds formal validation and improves documentation using a conditional schema. Remove the twl4030 section from the obsolete .txt binding file Signed-off-by: Jihed Chaibi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250824112338.64953-2-jihed.chaibi.dev@gmail.com Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/ti,twl4030-usb.yaml | 74 ++++++++++++++++++++++ .../devicetree/bindings/usb/twlxxxx-usb.txt | 22 ------- 2 files changed, 74 insertions(+), 22 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/ti,twl4030-usb.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/ti,twl4030-usb.yaml b/Documentation/devicetree/bindings/usb/ti,twl4030-usb.yaml new file mode 100644 index 000000000000..6ef337507425 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,twl4030-usb.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,twl4030-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TWL4030 USB PHY and Comparator + +maintainers: + - Peter Ujfalusi + +description: + Bindings for the USB PHY and comparator module found within the + TWL4030 family of companion chips. If a sibling node is compatible with + "ti,twl4030-bci", the driver for that node will query this device for + USB power status. + +properties: + compatible: + const: ti,twl4030-usb + + interrupts: + minItems: 1 + items: + - description: OTG interrupt number for ID events. + - description: USB interrupt number for VBUS events. + + usb1v5-supply: + description: Phandle to the vusb1v5 regulator. + + usb1v8-supply: + description: Phandle to the vusb1v8 regulator. + + usb3v1-supply: + description: Phandle to the vusb3v1 regulator. + + usb_mode: + description: | + The mode used by the PHY to connect to the controller: + 1: ULPI mode + 2: CEA2011_3PIN mode + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + '#phy-cells': + const: 0 + +required: + - compatible + - interrupts + - usb1v5-supply + - usb1v8-supply + - usb3v1-supply + - usb_mode + +additionalProperties: false + +examples: + - | + #include + + usb-phy { + compatible = "ti,twl4030-usb"; + + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + + usb1v5-supply = <®_vusb1v5>; + usb1v8-supply = <®_vusb1v8>; + usb3v1-supply = <®_vusb3v1>; + usb_mode = <1>; + + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt index 17327a296110..7194c9504b28 100644 --- a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt +++ b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt @@ -19,25 +19,3 @@ Board specific device node entry &twl6030-usb { usb-supply = <&vusb>; }; - -TWL4030 USB PHY AND COMPARATOR - - compatible : Should be "ti,twl4030-usb" - - interrupts : The interrupt numbers to the cpu should be specified. First - interrupt number is the otg interrupt number that raises ID interrupts - and VBUS interrupts. The second interrupt number is optional. - - -supply : phandle to the regulator device tree node. - should be vusb1v5, vusb1v8 and vusb3v1 - - usb_mode : The mode used by the phy to connect to the controller. "1" - specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode. - -If a sibling node is compatible "ti,twl4030-bci", then it will find -this device and query it for USB power status. - -twl4030-usb { - compatible = "ti,twl4030-usb"; - interrupts = < 10 4 >; - usb1v5-supply = <&vusb1v5>; - usb1v8-supply = <&vusb1v8>; - usb3v1-supply = <&vusb3v1>; - usb_mode = <1>; -}; -- cgit v1.2.3 From 1daa7f57b85038eb3a4e6220a9623557a759758c Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Sun, 24 Aug 2025 13:23:38 +0200 Subject: usb: dt-bindings: ti,twl6030-usb: convert to DT schema Convert the legacy TXT binding for the TWL6030 USB module to the modern YAML DT schema format. This adds formal validation and improves documentation using a conditional schema. The legacy twlxxxx-usb.txt file is no longer needed and is removed. Signed-off-by: Jihed Chaibi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250824112338.64953-3-jihed.chaibi.dev@gmail.com Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/ti,twl6030-usb.yaml | 48 ++++++++++++++++++++++ .../devicetree/bindings/usb/twlxxxx-usb.txt | 21 ---------- 2 files changed, 48 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/ti,twl6030-usb.yaml delete mode 100644 Documentation/devicetree/bindings/usb/twlxxxx-usb.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/ti,twl6030-usb.yaml b/Documentation/devicetree/bindings/usb/ti,twl6030-usb.yaml new file mode 100644 index 000000000000..33b6da50660a --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,twl6030-usb.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,twl6030-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TWL6030 USB Comparator + +maintainers: + - Peter Ujfalusi + +description: + Bindings for the USB comparator module found within the TWL6030 + family of companion chips. + +properties: + compatible: + const: ti,twl6030-usb + + interrupts: + items: + - description: OTG for ID events in host mode + - description: USB device mode for VBUS events + + usb-supply: + description: + Phandle to the VUSB regulator. For TWL6030, this should be the 'vusb' + regulator. For TWL6032 subclass, it should be the 'ldousb' regulator. + +required: + - compatible + - interrupts + - usb-supply + +additionalProperties: false + +examples: + - | + #include + + usb { + compatible = "ti,twl6030-usb"; + + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + + usb-supply = <®_vusb>; + }; diff --git a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt deleted file mode 100644 index 7194c9504b28..000000000000 --- a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt +++ /dev/null @@ -1,21 +0,0 @@ -USB COMPARATOR OF TWL CHIPS - -TWL6030 USB COMPARATOR - - compatible : Should be "ti,twl6030-usb" - - interrupts : Two interrupt numbers to the cpu should be specified. First - interrupt number is the otg interrupt number that raises ID interrupts when - the controller has to act as host and the second interrupt number is the - usb interrupt number that raises VBUS interrupts when the controller has to - act as device - - usb-supply : phandle to the regulator device tree node. It should be vusb - if it is twl6030 or ldousb if it is twl6032 subclass. - -twl6030-usb { - compatible = "ti,twl6030-usb"; - interrupts = < 4 10 >; -}; - -Board specific device node entry -&twl6030-usb { - usb-supply = <&vusb>; -}; -- cgit v1.2.3 From 771713aeaca19b4dfb47595bea514859f55747b9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 31 Aug 2025 14:22:24 +0200 Subject: dt-bindings: usb: s3c2410-usb: Drop entirely S3C2410 Samsung S3C24xx family of SoCs was removed the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250831122222.50332-4-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/usb/s3c2410-usb.txt | 22 ---------------------- 1 file changed, 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/s3c2410-usb.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/s3c2410-usb.txt b/Documentation/devicetree/bindings/usb/s3c2410-usb.txt deleted file mode 100644 index 26c85afd0b53..000000000000 --- a/Documentation/devicetree/bindings/usb/s3c2410-usb.txt +++ /dev/null @@ -1,22 +0,0 @@ -Samsung S3C2410 and compatible SoC USB controller - -OHCI - -Required properties: - - compatible: should be "samsung,s3c2410-ohci" for USB host controller - - reg: address and length of the controller memory mapped region - - interrupts: interrupt number for the USB OHCI controller - - clocks: Should reference the bus and host clocks - - clock-names: Should contain two strings - "usb-bus-host" for the USB bus clock - "usb-host" for the USB host clock - -Example: - -usb0: ohci@49000000 { - compatible = "samsung,s3c2410-ohci"; - reg = <0x49000000 0x100>; - interrupts = <0 0 26 3>; - clocks = <&clocks UCLK>, <&clocks HCLK_USBH>; - clock-names = "usb-bus-host", "usb-host"; -}; -- cgit v1.2.3 From ea32cd911368e32eb770c9078158467845c82b9a Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 26 Aug 2025 07:45:07 +0800 Subject: dt-bindings: usb: usb251xb: support usage case without I2C control Currently, the usb251xb assumes i2c control, but from HW point of view, the hub supports usage case without any i2c control, I.E we only want the gpio controls, for example the following dt node: usb-hub { compatible = "microchip,usb2512b"; reset-gpios = <&porta 8 GPIO_ACTIVE_LOW>; }; Modify the dt-binding of usb2512b to support this usage case, and add the usage example to the examples section. Signed-off-by: Jisheng Zhang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250825234509.1041-2-jszhang@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/usb251xb.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb251xb.yaml b/Documentation/devicetree/bindings/usb/usb251xb.yaml index ac5b99710332..0329a6aaaa92 100644 --- a/Documentation/devicetree/bindings/usb/usb251xb.yaml +++ b/Documentation/devicetree/bindings/usb/usb251xb.yaml @@ -240,7 +240,6 @@ additionalProperties: false required: - compatible - - reg examples: - | @@ -269,3 +268,11 @@ examples: swap-dx-lanes = <1 2>; }; }; + + - | + #include + usb-hub { + /* I2C is not connected */ + compatible = "microchip,usb2512b"; + reset-gpios = <&porta 8 GPIO_ACTIVE_LOW>; + }; -- cgit v1.2.3 From 534c702c3c234665ca2fe426a9fbb12281e55d55 Mon Sep 17 00:00:00 2001 From: Markus Heidelberg Date: Fri, 15 Aug 2025 11:58:36 +0200 Subject: dt-bindings: eeprom: at25: use "size" for FRAMs without device ID Not all FRAM chips have a device ID and implement the corresponding read command. Thus the memory size, which is contained in the device ID, cannot be detected and has to be set manually as it is done for EEPROMs. Link: https://lore.kernel.org/all/20250401133148.38330-1-m.heidelberg@cab.de/ Signed-off-by: Markus Heidelberg Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250815095839.4219-2-m.heidelberg@cab.de Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/eeprom/at25.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/at25.yaml b/Documentation/devicetree/bindings/eeprom/at25.yaml index c31e5e719525..00e0f07b44f8 100644 --- a/Documentation/devicetree/bindings/eeprom/at25.yaml +++ b/Documentation/devicetree/bindings/eeprom/at25.yaml @@ -56,6 +56,7 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: Total eeprom size in bytes. + Also used for FRAMs without device ID where the size cannot be detected. address-width: $ref: /schemas/types.yaml#/definitions/uint32 @@ -146,4 +147,11 @@ examples: reg = <1>; spi-max-frequency = <40000000>; }; + + fram@2 { + compatible = "cypress,fm25", "atmel,at25"; + reg = <2>; + spi-max-frequency = <20000000>; + size = <2048>; + }; }; -- cgit v1.2.3 From 618f571af67a876ce23a1dc4eb08e152fcf0d709 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 4 Sep 2025 13:15:41 -0400 Subject: dt-bindings: input: exc3000: move eeti,egalax_ts from egalax-ts.txt to eeti,exc3000.yaml Remove legacy binding egalax-ts.txt file. And add compatible string eeti,egalax_ts and wakeup-gpios to eeti,exc3000.yaml. "eeti,egalax_ts" is general compatible string, which is not preferred. But it is compatible with old devices (older than 10 years) and existing driver in drivers/input/touchscreen/egalax_ts.c. Allow address 0x4 for eeti,egalax_ts. Don't require touchscreen-size-x(y) for eeti,egalax_ts. Keep the same restriction for existing compatible string. Fix below DTB_CHECKS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dtb: /soc/bus@2100000/i2c@21a8000/egalax_ts@4: failed to match any schema with compatible: ['eeti,egalax_ts'] Signed-off-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250904171543.517650-1-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/eeti,exc3000.yaml | 30 +++++++++++++++++----- .../bindings/input/touchscreen/egalax-ts.txt | 18 ------------- 2 files changed, 24 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/eeti,exc3000.yaml b/Documentation/devicetree/bindings/input/touchscreen/eeti,exc3000.yaml index 1c7ae05a8c15..d19b07d4cfd4 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/eeti,exc3000.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/eeti,exc3000.yaml @@ -9,25 +9,25 @@ title: EETI EXC3000 series touchscreen controller maintainers: - Dmitry Torokhov -allOf: - - $ref: touchscreen.yaml# - properties: compatible: oneOf: - const: eeti,exc3000 - const: eeti,exc80h60 - const: eeti,exc80h84 + - const: eeti,egalax_ts # Do NOT use for new binding - items: - enum: - eeti,exc81w32 - const: eeti,exc80h84 reg: - const: 0x2a + enum: [0x4, 0x2a] interrupts: maxItems: 1 reset-gpios: maxItems: 1 + wakeup-gpios: + maxItems: 1 vdd-supply: description: Power supply regulator for the chip touchscreen-size-x: true @@ -40,11 +40,29 @@ required: - compatible - reg - interrupts - - touchscreen-size-x - - touchscreen-size-y additionalProperties: false +allOf: + - $ref: touchscreen.yaml# + + - if: + properties: + compatible: + not: + contains: + const: eeti,egalax_ts + then: + properties: + reg: + const: 0x2a + + wakeup-gpios: false + + required: + - touchscreen-size-x + - touchscreen-size-y + examples: - | #include "dt-bindings/interrupt-controller/irq.h" diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt deleted file mode 100644 index ebbe93810574..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt +++ /dev/null @@ -1,18 +0,0 @@ -* EETI eGalax Multiple Touch Controller - -Required properties: -- compatible: must be "eeti,egalax_ts" -- reg: i2c slave address -- interrupts: touch controller interrupt -- wakeup-gpios: the gpio pin to be used for waking up the controller - and also used as irq pin - -Example: - - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; -- cgit v1.2.3 From 3cc08f9181156585baff92b1a3bba76fb4b14f4b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 4 Sep 2025 15:17:28 -0400 Subject: dt-bindings: input: convert semtech,sx8654 to yaml format Convert sx8654.txt to yaml format. Signed-off-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250904191731.528145-1-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/semtech,sx8654.yaml | 52 ++++++++++++++++++++++ .../bindings/input/touchscreen/sx8654.txt | 23 ---------- 2 files changed, 52 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/semtech,sx8654.yaml delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/sx8654.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/semtech,sx8654.yaml b/Documentation/devicetree/bindings/input/touchscreen/semtech,sx8654.yaml new file mode 100644 index 000000000000..b2554064b688 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/semtech,sx8654.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/semtech,sx8654.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Semtech SX8654 I2C Touchscreen Controller + +maintainers: + - Frank Li + +properties: + compatible: + enum: + - semtech,sx8650 + - semtech,sx8654 + - semtech,sx8655 + - semtech,sx8656 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@48 { + compatible = "semtech,sx8654"; + reg = <0x48>; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/sx8654.txt b/Documentation/devicetree/bindings/input/touchscreen/sx8654.txt deleted file mode 100644 index 0ebe6dd043c7..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/sx8654.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Semtech SX8654 I2C Touchscreen Controller - -Required properties: -- compatible: must be one of the following, depending on the model: - "semtech,sx8650" - "semtech,sx8654" - "semtech,sx8655" - "semtech,sx8656" -- reg: i2c slave address -- interrupts: touch controller interrupt - -Optional properties: - - reset-gpios: GPIO specification for the NRST input - -Example: - - sx8654@48 { - compatible = "semtech,sx8654"; - reg = <0x48>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - }; -- cgit v1.2.3 From 7328815c5fb0b5bc39dc5c981b18c0008786ab82 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 4 Sep 2025 16:06:37 -0400 Subject: dt-bindings: input: convert max11801-ts to yaml format Convert max11801-ts to yaml format. Signed-off-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250904200641.531897-1-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/max11801-ts.txt | 17 -------- .../bindings/input/touchscreen/maxim,max11801.yaml | 46 ++++++++++++++++++++++ 2 files changed, 46 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/max11801-ts.txt create mode 100644 Documentation/devicetree/bindings/input/touchscreen/maxim,max11801.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/max11801-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/max11801-ts.txt deleted file mode 100644 index 05e982c3454e..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/max11801-ts.txt +++ /dev/null @@ -1,17 +0,0 @@ -* MAXI MAX11801 Resistive touch screen controller with i2c interface - -Required properties: -- compatible: must be "maxim,max11801" -- reg: i2c slave address -- interrupts: touch controller interrupt - -Example: - -&i2c1 { - max11801: touchscreen@48 { - compatible = "maxim,max11801"; - reg = <0x48>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/maxim,max11801.yaml b/Documentation/devicetree/bindings/input/touchscreen/maxim,max11801.yaml new file mode 100644 index 000000000000..4f528d220199 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/maxim,max11801.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/maxim,max11801.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MAXI MAX11801 Resistive touch screen controller with i2c interface + +maintainers: + - Frank Li + +properties: + compatible: + const: maxim,max11801 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +allOf: + - $ref: touchscreen.yaml + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; + }; -- cgit v1.2.3 From c2cc1e60c1afff4f23c22561b57a5d5157dde20d Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Wed, 3 Sep 2025 12:49:52 +0530 Subject: dt-bindings: display/msm/gmu: Update Adreno 623 bindings Update Adreno 623's dt-binding to remove smmu_clk which is not required for this GMU. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Krzysztof Kozlowski Patchwork: https://patchwork.freedesktop.org/patch/672455/ Signed-off-by: Rob Clark --- .../devicetree/bindings/display/msm/gmu.yaml | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 4392aa7a4ffe..afc187935744 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -124,6 +124,40 @@ allOf: contains: enum: - qcom,adreno-gmu-623.0 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GPU AHB clock + - description: GPU HUB CX clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: ahb + - const: hub + + - if: + properties: + compatible: + contains: + enum: - qcom,adreno-gmu-635.0 - qcom,adreno-gmu-660.1 - qcom,adreno-gmu-663.0 -- cgit v1.2.3 From f3ebb77fce24b5573e7accc2ba593ae55bded1d9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 4 Sep 2025 21:57:04 +0200 Subject: dt-bindings: input: touchscreen: goodix: Drop 'interrupts' requirement Since commit 409fe0cea366 ("Input: goodix - add support for polling mode") the interrupts property is optional, since at least the Linux kernel driver supports also polling mode. Signed-off-by: Marek Vasut Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20250904195727.168152-1-marek.vasut+renesas@mailbox.org Signed-off-by: Dmitry Torokhov --- Documentation/devicetree/bindings/input/touchscreen/goodix.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml index eb4992f708b7..a96137c6f063 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -62,7 +62,6 @@ additionalProperties: false required: - compatible - reg - - interrupts examples: - | -- cgit v1.2.3 From c2cf36221021090e7b4757774f4e4c563f959fdb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 4 Sep 2025 10:38:17 +0200 Subject: dt-bindings: display: bridge: Reference DAI common schema Several display bridges (e.g. LVDS to HDMI converters) are used as sound Digital Audio Interface (DAI) and have '#sound-dai-cells', thus they should reference dai-common.yaml schema to allow common properties, like DAI name. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250904083816.48076-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml | 1 + Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml | 5 ++++- Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml | 5 ++++- Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml | 5 ++++- Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml | 5 ++++- 5 files changed, 17 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml index 0a10e10d80ff..b98d942bbe19 100644 --- a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml @@ -28,6 +28,7 @@ description: | allOf: - $ref: /schemas/display/lvds-dual-ports.yaml# + - $ref: /schemas/sound/dai-common.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml index a7eb2603691f..ba644c30dcf4 100644 --- a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml @@ -84,7 +84,10 @@ required: - interrupts - ports -additionalProperties: false +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml index 5b9d36f7af30..655db8cfdc25 100644 --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml @@ -69,7 +69,10 @@ required: - vcc-supply - ports -additionalProperties: false +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml b/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml index b8e9cf6ce4e6..3fce9e698ea1 100644 --- a/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml +++ b/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml @@ -81,7 +81,10 @@ oneOf: - required: - ports -additionalProperties: false +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml b/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml index 1509c4535e53..17ea06719b56 100644 --- a/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml +++ b/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml @@ -109,7 +109,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +unevaluatedProperties: false examples: - | -- cgit v1.2.3 From 714380b03d38e1ca8c5d42f2da6292fae082a769 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 5 Sep 2025 12:41:57 -0400 Subject: bindings: siox: convert eckelmann,siox-gpio.txt to yaml format Convert eckelmann,siox-gpio.txt to yaml format. Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20250905164200.599448-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) --- .../bindings/siox/eckelmann,siox-gpio.txt | 19 --------- .../bindings/siox/eckelmann,siox-gpio.yaml | 48 ++++++++++++++++++++++ 2 files changed, 48 insertions(+), 19 deletions(-) delete mode 100644 Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt create mode 100644 Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt b/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt deleted file mode 100644 index 55259cf39c25..000000000000 --- a/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt +++ /dev/null @@ -1,19 +0,0 @@ -Eckelmann SIOX GPIO bus - -Required properties: -- compatible : "eckelmann,siox-gpio" -- din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the - corresponding bus signals. - -Examples: - - siox { - compatible = "eckelmann,siox-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_siox>; - - din-gpios = <&gpio6 11 0>; - dout-gpios = <&gpio6 8 0>; - dclk-gpios = <&gpio6 9 0>; - dld-gpios = <&gpio6 10 0>; - }; diff --git a/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.yaml b/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.yaml new file mode 100644 index 000000000000..2ff204109b93 --- /dev/null +++ b/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/siox/eckelmann,siox-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eckelmann SIOX GPIO bus + +maintainers: + - Frank Li + +properties: + compatible: + const: eckelmann,siox-gpio + + din-gpios: + maxItems: 1 + + dout-gpios: + maxItems: 1 + + dclk-gpios: + maxItems: 1 + + dld-gpios: + maxItems: 1 + +required: + - compatible + - din-gpios + - dout-gpios + - dclk-gpios + - dld-gpios + +additionalProperties: false + +examples: + - | + siox { + compatible = "eckelmann,siox-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_siox>; + + din-gpios = <&gpio6 11 0>; + dout-gpios = <&gpio6 8 0>; + dclk-gpios = <&gpio6 9 0>; + dld-gpios = <&gpio6 10 0>; + }; -- cgit v1.2.3 From 43bd82eb33b2ac33232724a8ddb9e07cde492328 Mon Sep 17 00:00:00 2001 From: Denzeel Oliva Date: Thu, 4 Sep 2025 14:07:11 +0000 Subject: dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units Add clock management unit bindings for PERIC0 and PERIC1 blocks which provide clocks for USI, I2C and UART peripherals. Signed-off-by: Denzeel Oliva Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/samsung,exynos990-clock.yaml | 24 +++ include/dt-bindings/clock/samsung,exynos990.h | 176 +++++++++++++++++++++ 2 files changed, 200 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml index c15cc1752b02..5cd2d80b8ed6 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml @@ -30,6 +30,8 @@ description: | properties: compatible: enum: + - samsung,exynos990-cmu-peric1 + - samsung,exynos990-cmu-peric0 - samsung,exynos990-cmu-hsi0 - samsung,exynos990-cmu-peris - samsung,exynos990-cmu-top @@ -56,6 +58,28 @@ required: - reg allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos990-cmu-peric1 + - samsung,exynos990-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index c60f15503d5b..47540307cb52 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -238,6 +238,182 @@ #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 #define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK 23 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_UART_DBG 2 +#define CLK_MOUT_PERIC0_USI00_USI_USER 3 +#define CLK_MOUT_PERIC0_USI01_USI_USER 4 +#define CLK_MOUT_PERIC0_USI02_USI_USER 5 +#define CLK_MOUT_PERIC0_USI03_USI_USER 6 +#define CLK_MOUT_PERIC0_USI04_USI_USER 7 +#define CLK_MOUT_PERIC0_USI05_USI_USER 8 +#define CLK_MOUT_PERIC0_USI13_USI_USER 9 +#define CLK_MOUT_PERIC0_USI14_USI_USER 10 +#define CLK_MOUT_PERIC0_USI15_USI_USER 11 +#define CLK_MOUT_PERIC0_USI_I2C_USER 12 +#define CLK_DOUT_PERIC0_UART_DBG 13 +#define CLK_DOUT_PERIC0_USI00_USI 14 +#define CLK_DOUT_PERIC0_USI01_USI 15 +#define CLK_DOUT_PERIC0_USI02_USI 16 +#define CLK_DOUT_PERIC0_USI03_USI 17 +#define CLK_DOUT_PERIC0_USI04_USI 18 +#define CLK_DOUT_PERIC0_USI05_USI 19 +#define CLK_DOUT_PERIC0_USI13_USI 20 +#define CLK_DOUT_PERIC0_USI14_USI 21 +#define CLK_DOUT_PERIC0_USI15_USI 22 +#define CLK_DOUT_PERIC0_USI_I2C 23 +#define CLK_GOUT_PERIC0_CMU_PCLK 24 +#define CLK_GOUT_PERIC0_OSCCLK_CLK 25 +#define CLK_GOUT_PERIC0_D_TZPC_PCLK 26 +#define CLK_GOUT_PERIC0_GPIO_PCLK 27 +#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 28 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 29 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 30 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 31 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 32 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 33 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 34 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 35 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 36 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 37 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 38 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 39 +#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 40 +#define CLK_GOUT_PERIC0_TOP0_PCLK_10 41 +#define CLK_GOUT_PERIC0_TOP0_PCLK_11 42 +#define CLK_GOUT_PERIC0_TOP0_PCLK_12 43 +#define CLK_GOUT_PERIC0_TOP0_PCLK_13 44 +#define CLK_GOUT_PERIC0_TOP0_PCLK_14 45 +#define CLK_GOUT_PERIC0_TOP0_PCLK_15 46 +#define CLK_GOUT_PERIC0_TOP0_PCLK_4 47 +#define CLK_GOUT_PERIC0_TOP0_PCLK_5 48 +#define CLK_GOUT_PERIC0_TOP0_PCLK_6 49 +#define CLK_GOUT_PERIC0_TOP0_PCLK_7 50 +#define CLK_GOUT_PERIC0_TOP0_PCLK_8 51 +#define CLK_GOUT_PERIC0_TOP0_PCLK_9 52 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 53 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 54 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 55 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 56 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 57 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 58 +#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 59 +#define CLK_GOUT_PERIC0_TOP1_PCLK_0 60 +#define CLK_GOUT_PERIC0_TOP1_PCLK_15 61 +#define CLK_GOUT_PERIC0_TOP1_PCLK_3 62 +#define CLK_GOUT_PERIC0_TOP1_PCLK_4 63 +#define CLK_GOUT_PERIC0_TOP1_PCLK_5 64 +#define CLK_GOUT_PERIC0_TOP1_PCLK_6 65 +#define CLK_GOUT_PERIC0_TOP1_PCLK_7 66 +#define CLK_GOUT_PERIC0_TOP1_PCLK_8 67 +#define CLK_GOUT_PERIC0_BUSP_CLK 68 +#define CLK_GOUT_PERIC0_UART_DBG_CLK 69 +#define CLK_GOUT_PERIC0_USI00_USI_CLK 70 +#define CLK_GOUT_PERIC0_USI01_USI_CLK 71 +#define CLK_GOUT_PERIC0_USI02_USI_CLK 72 +#define CLK_GOUT_PERIC0_USI03_USI_CLK 73 +#define CLK_GOUT_PERIC0_USI04_USI_CLK 74 +#define CLK_GOUT_PERIC0_USI05_USI_CLK 75 +#define CLK_GOUT_PERIC0_USI13_USI_CLK 76 +#define CLK_GOUT_PERIC0_USI14_USI_CLK 77 +#define CLK_GOUT_PERIC0_USI15_USI_CLK 78 +#define CLK_GOUT_PERIC0_USI_I2C_CLK 79 +#define CLK_GOUT_PERIC0_SYSREG_PCLK 80 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_UART_BT_USER 2 +#define CLK_MOUT_PERIC1_USI06_USI_USER 3 +#define CLK_MOUT_PERIC1_USI07_USI_USER 4 +#define CLK_MOUT_PERIC1_USI08_USI_USER 5 +#define CLK_MOUT_PERIC1_USI09_USI_USER 6 +#define CLK_MOUT_PERIC1_USI10_USI_USER 7 +#define CLK_MOUT_PERIC1_USI11_USI_USER 8 +#define CLK_MOUT_PERIC1_USI12_USI_USER 9 +#define CLK_MOUT_PERIC1_USI18_USI_USER 10 +#define CLK_MOUT_PERIC1_USI16_USI_USER 11 +#define CLK_MOUT_PERIC1_USI17_USI_USER 12 +#define CLK_MOUT_PERIC1_USI_I2C_USER 13 +#define CLK_DOUT_PERIC1_UART_BT 14 +#define CLK_DOUT_PERIC1_USI06_USI 15 +#define CLK_DOUT_PERIC1_USI07_USI 16 +#define CLK_DOUT_PERIC1_USI08_USI 17 +#define CLK_DOUT_PERIC1_USI18_USI 18 +#define CLK_DOUT_PERIC1_USI12_USI 19 +#define CLK_DOUT_PERIC1_USI09_USI 20 +#define CLK_DOUT_PERIC1_USI10_USI 21 +#define CLK_DOUT_PERIC1_USI11_USI 22 +#define CLK_DOUT_PERIC1_USI16_USI 23 +#define CLK_DOUT_PERIC1_USI17_USI 24 +#define CLK_DOUT_PERIC1_USI_I2C 25 +#define CLK_GOUT_PERIC1_CMU_PCLK 26 +#define CLK_GOUT_PERIC1_UART_BT_CLK 27 +#define CLK_GOUT_PERIC1_USI12_USI_CLK 28 +#define CLK_GOUT_PERIC1_USI18_USI_CLK 29 +#define CLK_GOUT_PERIC1_D_TZPC_PCLK 30 +#define CLK_GOUT_PERIC1_GPIO_PCLK 31 +#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 32 +#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 33 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 34 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 35 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 36 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 37 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 38 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 39 +#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 40 +#define CLK_GOUT_PERIC1_TOP0_PCLK_10 41 +#define CLK_GOUT_PERIC1_TOP0_PCLK_11 42 +#define CLK_GOUT_PERIC1_TOP0_PCLK_12 43 +#define CLK_GOUT_PERIC1_TOP0_PCLK_13 44 +#define CLK_GOUT_PERIC1_TOP0_PCLK_14 45 +#define CLK_GOUT_PERIC1_TOP0_PCLK_15 46 +#define CLK_GOUT_PERIC1_TOP0_PCLK_4 47 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 48 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 49 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 50 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 51 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 52 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 53 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 54 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 55 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 56 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 57 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 58 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 59 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 60 +#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 61 +#define CLK_GOUT_PERIC1_TOP1_PCLK_0 62 +#define CLK_GOUT_PERIC1_TOP1_PCLK_1 63 +#define CLK_GOUT_PERIC1_TOP1_PCLK_10 64 +#define CLK_GOUT_PERIC1_TOP1_PCLK_12 65 +#define CLK_GOUT_PERIC1_TOP1_PCLK_13 66 +#define CLK_GOUT_PERIC1_TOP1_PCLK_14 67 +#define CLK_GOUT_PERIC1_TOP1_PCLK_15 68 +#define CLK_GOUT_PERIC1_TOP1_PCLK_2 69 +#define CLK_GOUT_PERIC1_TOP1_PCLK_3 70 +#define CLK_GOUT_PERIC1_TOP1_PCLK_4 71 +#define CLK_GOUT_PERIC1_TOP1_PCLK_5 72 +#define CLK_GOUT_PERIC1_TOP1_PCLK_6 73 +#define CLK_GOUT_PERIC1_TOP1_PCLK_7 74 +#define CLK_GOUT_PERIC1_TOP1_PCLK_9 75 +#define CLK_GOUT_PERIC1_BUSP_CLK 76 +#define CLK_GOUT_PERIC1_OSCCLK_CLK 77 +#define CLK_GOUT_PERIC1_USI06_USI_CLK 78 +#define CLK_GOUT_PERIC1_USI07_USI_CLK 79 +#define CLK_GOUT_PERIC1_USI08_USI_CLK 80 +#define CLK_GOUT_PERIC1_USI09_USI_CLK 81 +#define CLK_GOUT_PERIC1_USI10_USI_CLK 82 +#define CLK_GOUT_PERIC1_USI11_USI_CLK 83 +#define CLK_GOUT_PERIC1_USI16_USI_CLK 84 +#define CLK_GOUT_PERIC1_USI17_USI_CLK 85 +#define CLK_GOUT_PERIC1_USI_I2C_CLK 86 +#define CLK_GOUT_PERIC1_SYSREG_PCLK 87 +#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 88 +#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 89 +#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 90 +#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91 +#define CLK_GOUT_PERIC1_XIU_P_ACLK 92 + /* CMU_PERIS */ #define CLK_MOUT_PERIS_BUS_USER 1 #define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 -- cgit v1.2.3 From 6a9b2fb8411e1bc9345f048c8061cfa96f45151f Mon Sep 17 00:00:00 2001 From: Lakshay Piplani Date: Mon, 28 Jul 2025 09:49:12 +0530 Subject: dt-bindings: hwmon: (lm75) Add binding for NXP P3T1750 Add "nxp,p3t1750" to the lm75 compatible list. Signed-off-by: Lakshay Piplani Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250728041913.3754236-1-lakshay.piplani@nxp.com Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/lm75.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/lm75.yaml b/Documentation/devicetree/bindings/hwmon/lm75.yaml index c38255243f57..ecdd09a032e5 100644 --- a/Documentation/devicetree/bindings/hwmon/lm75.yaml +++ b/Documentation/devicetree/bindings/hwmon/lm75.yaml @@ -28,6 +28,7 @@ properties: - maxim,max31725 - maxim,max31726 - maxim,mcp980x + - nxp,p3t1750 - nxp,p3t1755 - nxp,pct2075 - st,stds75 -- cgit v1.2.3 From 3331e5469219d92ea8e9a85fe4fbf679b6aac672 Mon Sep 17 00:00:00 2001 From: ChiShih Tsai Date: Thu, 7 Aug 2025 06:37:23 +0800 Subject: dt-bindings: hwmon: adm1275: add sq24905c support Add support for sq24905c Hot-Swap Controller and Digital Power Monitor. Acked-by: Krzysztof Kozlowski Signed-off-by: ChiShih Tsai Link: https://lore.kernel.org/r/20250806223724.1207-2-tomtsai764@gmail.com Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml index ddb72857c846..d6a7517f2a50 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml @@ -18,6 +18,13 @@ description: | Datasheets: https://www.analog.com/en/products/adm1294.html + The SQ24905C is also a Hot-swap controller compatibility to the ADM1278, + the PMBUS_MFR_MODEL is MC09C + + Datasheets: + https://www.silergy.com/ + download/downloadFile?id=5669&type=product&ftype=note + properties: compatible: enum: @@ -30,6 +37,7 @@ properties: - adi,adm1281 - adi,adm1293 - adi,adm1294 + - silergy,mc09c reg: maxItems: 1 @@ -96,6 +104,7 @@ allOf: - adi,adm1281 - adi,adm1293 - adi,adm1294 + - silergy,mc09c then: properties: adi,volt-curr-sample-average: -- cgit v1.2.3 From fd1a9a68e64fc41bffd8bfbf987a11c53dda4cf2 Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Thu, 14 Aug 2025 10:04:41 +0200 Subject: dt-bindings: hwmon: convert lantiq-cputemp to yaml Convert the Lantiq cpu temperature sensor bindings to yaml format. Signed-off-by: Aleksander Jan Bajkowski Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250814080708.3054732-1-olek2@wp.pl Signed-off-by: Guenter Roeck --- .../devicetree/bindings/hwmon/lantiq,cputemp.yaml | 30 ++++++++++++++++++++++ .../devicetree/bindings/hwmon/ltq-cputemp.txt | 10 -------- 2 files changed, 30 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/hwmon/lantiq,cputemp.yaml delete mode 100644 Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/lantiq,cputemp.yaml b/Documentation/devicetree/bindings/hwmon/lantiq,cputemp.yaml new file mode 100644 index 000000000000..9419b481ff35 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/lantiq,cputemp.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/lantiq,cputemp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq cpu temperature sensor + +maintainers: + - Florian Eckert + +properties: + compatible: + const: lantiq,cputemp + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cputemp@103040 { + compatible = "lantiq,cputemp"; + reg = <0x103040 0x4>; + }; diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt deleted file mode 100644 index 473b34c876dd..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt +++ /dev/null @@ -1,10 +0,0 @@ -Lantiq cpu temperature sensor - -Requires node properties: -- compatible value : - "lantiq,cputemp" - -Example: - cputemp@0 { - compatible = "lantiq,cputemp"; - }; -- cgit v1.2.3 From 5473fccb809a4cb6777572d420c03446d96101b0 Mon Sep 17 00:00:00 2001 From: Grant Peltier Date: Wed, 27 Aug 2025 17:44:19 -0500 Subject: dt-bindings: hwmon: (pmbus/isl68137) add RAA228244 and RAA228246 support Add device type support for raa228244 and raa228246. Signed-off-by: Grant Peltier Acked-by: Conor Dooley Link: https://lore.kernel.org/r/c0c6e99e51b6fd4c5dbab02e02e4d81abe31f085.1756331945.git.grantpeltier93@gmail.com Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml index 3dc7f15484d2..ae23a05375cb 100644 --- a/Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml +++ b/Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml @@ -54,6 +54,8 @@ properties: - renesas,raa228004 - renesas,raa228006 - renesas,raa228228 + - renesas,raa228244 + - renesas,raa228246 - renesas,raa229001 - renesas,raa229004 - renesas,raa229621 -- cgit v1.2.3 From fa1ab48bfe97c86278ddf7fb535bc597e64fd210 Mon Sep 17 00:00:00 2001 From: Flaviu Nistor Date: Mon, 25 Aug 2025 21:02:43 +0300 Subject: dt-bindings: hwmon: tmp102: Add label property Add support for an optional label property similar to other hwmon devices. This allows, in case of boards with multiple TMP102 sensors, to assign distinct names to each instance. Signed-off-by: Flaviu Nistor Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250825180248.1943607-1-flaviu.nistor@gmail.com [groeck: Dropped unnecessary "|" after "description:"] Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml index 4c89448eba0d..96b2e4969f78 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml @@ -20,6 +20,10 @@ properties: reg: maxItems: 1 + label: + description: + A descriptive name for this channel, like "ambient" or "psu". + "#thermal-sensor-cells": const: 1 @@ -45,6 +49,7 @@ examples: reg = <0x48>; interrupt-parent = <&gpio7>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + label = "somelabel"; vcc-supply = <&supply>; #thermal-sensor-cells = <1>; }; -- cgit v1.2.3 From 58639dfde0c29434e902a0efe213b35ede35604e Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 29 Aug 2025 15:05:09 +1200 Subject: dt-bindings: hwmon: ti,ina2xx: Add INA780 device Add a compatible string for the INA780 device. Signed-off-by: Chris Packham Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250829030512.1179998-2-chris.packham@alliedtelesis.co.nz Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index fa68b99ef2e2..980ecba6d811 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -32,6 +32,7 @@ properties: - ti,ina237 - ti,ina238 - ti,ina260 + - ti,ina780 reg: maxItems: 1 -- cgit v1.2.3 From f19617d1478aa595b5e2439847d34f3ac414c836 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Mon, 1 Sep 2025 08:59:02 -0700 Subject: dt-bindings: hwmon: ti,ina2xx: Update details for various chips ti,maximum-expected-current-microamp, ti,shunt-gain, and shunt-resistor properties are not supported on all chips described in this bindings file. Update the bindings accordingly. Cc: Chris Packham Signed-off-by: Guenter Roeck Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250901155902.2667063-1-linux@roeck-us.net Signed-off-by: Guenter Roeck --- .../devicetree/bindings/hwmon/ti,ina2xx.yaml | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index 980ecba6d811..8b491be9c49d 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -115,10 +115,39 @@ allOf: - ti,ina237 - ti,ina238 - ti,ina260 + - ti,ina780 then: properties: ti,maximum-expected-current-microamp: false + - if: + properties: + compatible: + contains: + enum: + - silergy,sy24655 + - ti,ina209 + - ti,ina219 + - ti,ina220 + - ti,ina226 + - ti,ina230 + - ti,ina231 + - ti,ina260 + - ti,ina780 + then: + properties: + ti,shunt-gain: false + + - if: + properties: + compatible: + contains: + enum: + - ti,ina780 + then: + properties: + shunt-resistor: false + unevaluatedProperties: false examples: -- cgit v1.2.3 From bd48b5a4e8d3e1ac2c1ba1e18ba1350ea2c9eb10 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 4 Sep 2025 22:21:09 +0200 Subject: dt-bindings: hwmon: pwm-fan: Document after shutdown fan settings Document fan-shutdown-percent property, used to describe fan RPM in percent set during shutdown. This is used to keep the fan running at fixed RPM after the kernel shut down, which is useful on hardware that does keep heating itself even after the kernel did shut down, for example from some sort of management core. Signed-off-by: Marek Vasut Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250904202157.170600-1-marek.vasut+renesas@mailbox.org Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/pwm-fan.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml b/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml index 8b4ed5ee962f..a84cc3a4cfdc 100644 --- a/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml +++ b/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml @@ -31,6 +31,15 @@ properties: it must be self resetting edge interrupts. maxItems: 1 + fan-shutdown-percent: + description: + Fan RPM in percent set during shutdown. This is used to keep the fan + running at fixed RPM after the kernel shut down, which is useful on + hardware that does keep heating itself even after the kernel did shut + down, for example from some sort of management core. + minimum: 0 + maximum: 100 + fan-stop-to-start-percent: description: Minimum fan RPM in percent to start when stopped. -- cgit v1.2.3 From 7942ca9a475115b9668e53c2d9cfb57a51d62e04 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Mon, 1 Sep 2025 09:02:07 -0700 Subject: dt-bindings: hwmon: ti,ina2xx: Add INA700 Add a compatible string for INA700. The chip is register compatible with INA780 but implements different ADC ranges and thus needs a separate compatible entry. Cc: Christian Kahr Reviewed-by: Chris Packham Tested-by: Chris Packham # INA780 Reviewed-by: Krzysztof Kozlowski Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index 8b491be9c49d..d3cde8936686 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -32,6 +32,7 @@ properties: - ti,ina237 - ti,ina238 - ti,ina260 + - ti,ina700 - ti,ina780 reg: @@ -115,6 +116,7 @@ allOf: - ti,ina237 - ti,ina238 - ti,ina260 + - ti,ina700 - ti,ina780 then: properties: @@ -133,6 +135,7 @@ allOf: - ti,ina230 - ti,ina231 - ti,ina260 + - ti,ina700 - ti,ina780 then: properties: @@ -143,6 +146,7 @@ allOf: compatible: contains: enum: + - ti,ina700 - ti,ina780 then: properties: -- cgit v1.2.3 From c97c66e04c2294d59827835e6fd46e0e4a5e2c06 Mon Sep 17 00:00:00 2001 From: Wensheng Wang Date: Tue, 5 Aug 2025 18:20:18 +0800 Subject: dt-bindings: hwmon: Add MPS mp2869,mp29608,mp29612,mp29816 and mp29502 Add support for MPS mp2869/mp2869a,mp29608/mp29608a,mp29612/mp29612a, mp29816/mp29816a/mp29816b/mp29816c and mp29502 controller. Acked-by: Rob Herring (Arm) Signed-off-by: Wensheng Wang Link: https://lore.kernel.org/r/20250805102020.749850-1-wenswang@yeah.net Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/trivial-devices.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index f3dd18681aa6..0e6ba6e12a63 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -293,10 +293,20 @@ properties: - mps,mp2856 # Monolithic Power Systems Inc. multi-phase controller mp2857 - mps,mp2857 + # Monolithic Power Systems Inc. multi-phase controller mp2869 + - mps,mp2869 # Monolithic Power Systems Inc. multi-phase controller mp2888 - mps,mp2888 # Monolithic Power Systems Inc. multi-phase controller mp2891 - mps,mp2891 + # Monolithic Power Systems Inc. multi-phase controller mp29502 + - mps,mp29502 + # Monolithic Power Systems Inc. multi-phase controller mp29608 + - mps,mp29608 + # Monolithic Power Systems Inc. multi-phase controller mp29612 + - mps,mp29612 + # Monolithic Power Systems Inc. multi-phase controller mp29816 + - mps,mp29816 # Monolithic Power Systems Inc. multi-phase controller mp2993 - mps,mp2993 # Monolithic Power Systems Inc. hot-swap protection device -- cgit v1.2.3 From de33ea612a36f8415579298899fd0b6c28a45c80 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 6 May 2025 10:32:15 +0300 Subject: dt-bindings: extcon: Document Maxim MAX14526 MUIC Add bindings for Maxim MAX14526 MicroUSB Integrated Circuit. Link: https://lore.kernel.org/lkml/20250506073216.43059-2-clamor95@gmail.com/ Signed-off-by: Svyatoslav Ryhel Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chanwoo Choi --- .../devicetree/bindings/extcon/maxim,max14526.yaml | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/extcon/maxim,max14526.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/extcon/maxim,max14526.yaml b/Documentation/devicetree/bindings/extcon/maxim,max14526.yaml new file mode 100644 index 000000000000..7eb5918df1c2 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/maxim,max14526.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/maxim,max14526.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX14526 MicroUSB Integrated Circuit (MUIC) + +maintainers: + - Svyatoslav Ryhel + +properties: + compatible: + const: maxim,max14526 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + connector: + $ref: /schemas/connector/usb-connector.yaml# + + port: + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - interrupts + - connector + - port + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + muic@44 { + compatible = "maxim,max14526"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = <72 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + + muic_to_charger: endpoint@0 { + reg = <0>; + remote-endpoint = <&charger_input>; + }; + + muic_to_usb: endpoint@1 { + reg = <1>; + remote-endpoint = <&usb_input>; + }; + + muic_to_mhl: endpoint@2 { + reg = <2>; + remote-endpoint = <&mhl_input>; + }; + }; + }; + }; +... -- cgit v1.2.3 From 958bb5a2794b2090593bd7a064e0c2f53dfa20cf Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Sun, 17 Aug 2025 10:52:04 +0200 Subject: dt-bindings: extcon: rt8973a: Convert DT bindings to YAML Convert the device tree bindings for Richtek RT8973A MUIC to the YAML format. No functional changes. Signed-off-by: Artur Weber Reviewed-by: Rob Herring (Arm) Signed-off-by: Chanwoo Choi Link: https://lore.kernel.org/lkml/20250817-rt8973a-dt-bindings-yaml-v1-1-150eb4599dc9@gmail.com/ --- .../devicetree/bindings/extcon/extcon-rt8973a.txt | 23 ---------- .../bindings/extcon/richtek,rt8973a-muic.yaml | 49 ++++++++++++++++++++++ 2 files changed, 49 insertions(+), 23 deletions(-) delete mode 100644 Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt create mode 100644 Documentation/devicetree/bindings/extcon/richtek,rt8973a-muic.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt b/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt deleted file mode 100644 index cfcf455ad4de..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt +++ /dev/null @@ -1,23 +0,0 @@ - -* Richtek RT8973A - Micro USB Switch device - -The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A -is a USB port accessory detector and switch that is optimized to protect low -voltage system from abnormal high input voltage (up to 28V) and supports high -speed USB operation. Also, RT8973A support 'auto-configuration' mode. -If auto-configuration mode is enabled, RT8973A would control internal h/w patch -for USB D-/D+ switching. - -Required properties: -- compatible: Should be "richtek,rt8973a-muic" -- reg: Specifies the I2C slave address of the MUIC block. It should be 0x14 -- interrupts: Interrupt specifiers for detection interrupt sources. - -Example: - - rt8973a@14 { - compatible = "richtek,rt8973a-muic"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - reg = <0x14>; - }; diff --git a/Documentation/devicetree/bindings/extcon/richtek,rt8973a-muic.yaml b/Documentation/devicetree/bindings/extcon/richtek,rt8973a-muic.yaml new file mode 100644 index 000000000000..f9e0d816c025 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/richtek,rt8973a-muic.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/richtek,rt8973a-muic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT8973A MUIC + +maintainers: + - Chanwoo Choi + +description: + The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A + is a USB port accessory detector and switch that is optimized to protect low + voltage system from abnormal high input voltage (up to 28V) and supports high + speed USB operation. Also, RT8973A support 'auto-configuration' mode. + If auto-configuration mode is enabled, RT8973A would control internal h/w patch + for USB D-/D+ switching. + +properties: + compatible: + const: richtek,rt8973a-muic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + usb-switch@14 { + compatible = "richtek,rt8973a-muic"; + reg = <0x14>; + interrupt-parent = <&gpio>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + }; -- cgit v1.2.3 From 94d885eb8ffe15b3eb4abe92e03d852fce8ba81f Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Thu, 4 Sep 2025 22:41:44 +0200 Subject: dt-bindings: extcon: linux,extcon-usb-gpio: GPIO must be provided Without providing either ID or VBUS GPIO the driver is not able to operate. Original text binding says: "Either one of id-gpio or vbus-gpio must be present." Fixes: 79a31ce03f41 ("dt-bindings: extcon: convert extcon-usb-gpio.txt to yaml format") Acked-by: Conor Dooley Signed-off-by: David Heidelberg Signed-off-by: Chanwoo Choi Link: https://lore.kernel.org/lkml/20250904-yaml-extcon-usb-gpio-v2-1-a5c4afa496c3@ixit.cz/ --- Documentation/devicetree/bindings/extcon/linux,extcon-usb-gpio.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/extcon/linux,extcon-usb-gpio.yaml b/Documentation/devicetree/bindings/extcon/linux,extcon-usb-gpio.yaml index 8856107bdd33..8f29d333602b 100644 --- a/Documentation/devicetree/bindings/extcon/linux,extcon-usb-gpio.yaml +++ b/Documentation/devicetree/bindings/extcon/linux,extcon-usb-gpio.yaml @@ -25,6 +25,12 @@ properties: required: - compatible +anyOf: + - required: + - id-gpios + - required: + - vbus-gpios + additionalProperties: false examples: -- cgit v1.2.3 From 084d01a173f5f41afd326b1dfe73085972530ca7 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 4 Sep 2025 01:34:36 +0000 Subject: dt-bindings: gpio: loongson: Document GPIO controller of LS2K0300 SoC Loongson-2K0300 ships a GPIO controller whose input/output control logic is similar to previous generation of SoCs. Additionally, it acts as an interrupt-controller supporting both level and edge interrupts and has a distinct reset signal. Describe its compatible in devicetree. We enlarge the maximum value of ngpios to 128, since the controller technically supports at most 128 pins, although only 106 are routed out of the package. Properties for interrupt-controllers and resets are introduced and limited as LS2K0300 only. Signed-off-by: Yao Zi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Huacai Chen Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20250904013438.2405-2-ziyao@disroot.org Signed-off-by: Bartosz Golaszewski --- .../devicetree/bindings/gpio/loongson,ls-gpio.yaml | 28 +++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml index b68159600e2b..69852444df23 100644 --- a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - loongson,ls2k-gpio + - loongson,ls2k0300-gpio - loongson,ls2k0500-gpio0 - loongson,ls2k0500-gpio1 - loongson,ls2k2000-gpio0 @@ -36,7 +37,7 @@ properties: ngpios: minimum: 1 - maximum: 64 + maximum: 128 "#gpio-cells": const: 2 @@ -49,6 +50,14 @@ properties: minItems: 1 maxItems: 64 + "#interrupt-cells": + const: 2 + + interrupt-controller: true + + resets: + maxItems: 1 + required: - compatible - reg @@ -58,6 +67,23 @@ required: - gpio-ranges - interrupts +allOf: + - if: + properties: + compatible: + contains: + const: loongson,ls2k0300-gpio + then: + required: + - "#interrupt-cells" + - interrupt-controller + - resets + else: + properties: + "#interrupts-cells": false + interrupt-controller: false + resets: false + additionalProperties: false examples: -- cgit v1.2.3 From 07333899650a5d4c785d3257ee4cd278006b1070 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 28 Aug 2025 14:47:38 +0200 Subject: dt-bindings: pinctrl: Add support for Broadcom STB pin controller The STB pin controller represents a family whose silicon instances are found e.g. on BCM2712 SoC. In particular, on RaspberryPi 5, there are two separate instantiations of the same IP block which differ in the number of pins that are associated and the pinmux functions for each of those pins. The -aon- variant stands for 'Always On'. Depending on the revision of the BCM2712 (CO or D0), the pin controller instance has slight differences in the register layout. Signed-off-by: Ivan T. Ivanov Signed-off-by: Andrea della Porta Reviewed-by: Rob Herring (Arm) [linusw: Dropped extranous label and fixed whitespace] Signed-off-by: Linus Walleij --- .../bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml | 137 +++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml new file mode 100644 index 000000000000..ae6c13a746b9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2712c0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB family pin controller + +maintainers: + - Ivan T. Ivanov + - A. della Porta + +description: > + Broadcom's STB family of memory-mapped pin controllers. + + This includes the pin controllers inside the BCM2712 SoC which + are instances of the STB family and has two silicon variants, + C0 and D0, which differs slightly in terms of registers layout. + + The -aon- (Always On) variant is the same IP block but differs + in the number of pins that are associated and the pinmux functions + for each of those pins. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - brcm,bcm2712c0-pinctrl + - brcm,bcm2712c0-aon-pinctrl + - brcm,bcm2712d0-pinctrl + - brcm,bcm2712d0-aon-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-state$': + oneOf: + - $ref: '#/$defs/brcmstb-pinctrl-state' + - patternProperties: + '-pins$': + $ref: '#/$defs/brcmstb-pinctrl-state' + additionalProperties: false + +$defs: + brcmstb-pinctrl-state: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: > + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode (either this or "groups" must be specified). + items: + pattern: '^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$' + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8, + aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm, + arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2, + bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii, + ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c, + hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out, + ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0, + sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e, + sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0, + te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0, + vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1, + vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3, + vc_uart4 ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + required: + - pins + + if: + properties: + pins: + not: + contains: + pattern: "^emmc_(clk|cmd|dat[0-7]|ds)$" + then: + required: + - function + else: + properties: + function: false + + additionalProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@7d504100 { + compatible = "brcm,bcm2712c0-pinctrl"; + reg = <0x7d504100 0x30>; + + bt-shutdown-default-state { + function = "gpio"; + pins = "gpio29"; + }; + + uarta-default-state { + rts-tx-pins { + function = "uart0"; + pins = "gpio24", "gpio26"; + bias-disable; + }; + + cts-rx-pins { + function = "uart0"; + pins = "gpio25", "gpio27"; + bias-pull-up; + }; + }; + }; -- cgit v1.2.3 From ebe397530638859853738ac1fcd082e1a0fdacdc Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Fri, 5 Sep 2025 20:40:19 +0530 Subject: dt-bindings: pinctrl: qcom: Add Glymur pinctrl Add DeviceTree binding for Glymur SoC TLMM block Reviewed-by: Krzysztof Kozlowski Signed-off-by: Pankaj Patil Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,glymur-tlmm.yaml | 133 +++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml new file mode 100644 index 000000000000..d2b0cfeffb50 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,glymur-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Glymur TLMM block + +maintainers: + - Bjorn Andersson + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,glymur-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 125 + + gpio-line-names: + maxItems: 250 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-glymur-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-glymur-tlmm-state" + additionalProperties: false + +$defs: + qcom-glymur-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-4][0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, resout_gpio_n, aoss_cti, asc_cci, atest_char, atest_usb, + audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, cam_asc_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, cri_trng, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi, + edp0_hot, edp0_lcd, edp1_lcd, egpio, eusb0_ac_en, eusb1_ac_en, + eusb2_ac_en, eusb3_ac_en, eusb5_ac_en, eusb6_ac_en, gcc_gp1, + gcc_gp2, gcc_gp3, host2wlan_sol, i2c0_s_scl, i2c0_s_sda, + i2s0_data, i2s0_sck, i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws, + ibi_i3c, jitter_bist, mdp_vsync_out, mdp_vsync_e, mdp_vsync_p, + mdp_vsync_s, pcie3a_clk, pcie3a_rst_n, pcie3b_clk, + pcie4_clk_req_n, pcie5_clk_req_n, pcie6_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, pmc_oca_n, pmc_uva_n, prng_rosc, + qdss_cti, qdss_gpio, qspi, qup0_se0, qup0_se1, qup0_se2, + qup0_se3_l0, qup0_se3, qup0_se4, qup0_se5, qup0_se6, qup0_se7, + qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, + qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, + qup2_se4, qup2_se5, qup2_se6, qup2_se7, qup3_se0, qup3_se1, + sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, smb_acok_n, + sys_throttle, tb_trig_sdc2, tb_trig_sdc4, tmess_prng, + tsense_pwm, tsense_therm, usb0_dp, usb0_phy_ps, usb0_sbrx, + usb0_sbtx, usb0_tmu, usb1_dbg, usb1_dp, usb1_phy_ps, usb1_sbrx, + usb1_sbtx, usb1_tmu, usb2_dp, usb2_phy_ps, usb2_sbrx, usb2_sbtx, + usb2_tmu, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + tlmm: pinctrl@f100000 { + compatible = "qcom,glymur-tlmm"; + reg = <0x0f100000 0xf00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 249>; + wakeup-parent = <&pdc>; + gpio-reserved-ranges = <4 4>, <10 2>, <33 3>, <44 4>; + qup_uart21_default: qup-uart21-default-state { + tx-pins { + pins = "gpio86"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +... -- cgit v1.2.3 From f1f514d730f62fffd8fc160e9fb6df719c7425a7 Mon Sep 17 00:00:00 2001 From: Barnabás Czémán Date: Wed, 3 Sep 2025 23:08:24 +0200 Subject: dt-bindings: display/msm/gpu: describe A505 clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Descirbe A505 clocks it is using same clocks like A506. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnabás Czémán Patchwork: https://patchwork.freedesktop.org/patch/672751/ Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 7ef80f9fac8b..3696b083e353 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -252,7 +252,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-506\.[0-9]+$' + pattern: '^qcom,adreno-50[56]\.[0-9]+$' then: properties: clocks: -- cgit v1.2.3 From 49e55bdbcbe0abf04d7c8c882d69755ecf43d878 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Sat, 6 Sep 2025 00:53:47 +0530 Subject: dt-bindings: arm: qcom: Add Monaco EVK support Introduce new bindings for the Monaco Evaluation Kit (EVK), an IoT board based on the QCS8300 SoC. Signed-off-by: Umang Chheda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250905192350.1223812-2-umang.chheda@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1fc6319bec6b..2698ba87cd93 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -849,6 +849,7 @@ properties: - items: - enum: + - qcom,monaco-evk - qcom,qcs8300-ride - const: qcom,qcs8300 -- cgit v1.2.3 From 121f4a7e474393502cd71d63f71df7997cbc2f90 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 7 Aug 2025 08:28:51 -0500 Subject: dt-bindings: ipmi: aspeed,ast2400-kcs-bmc: Add missing "clocks" property The ASpeed kcs-bmc nodes have a "clocks" property which isn't documented. It looks like all the LPC child devices have the same clock source and some of the drivers manage their clock. Perhaps it is the parent device that should have the clock, but it's too late for that. Signed-off-by: Rob Herring (Arm) Message-ID: <20250807132852.3291305-1-robh@kernel.org> Signed-off-by: Corey Minyard --- Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml index 129e32c4c774..610c79863208 100644 --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml @@ -40,6 +40,9 @@ properties: - description: ODR register - description: STR register + clocks: + maxItems: 1 + aspeed,lpc-io-reg: $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 -- cgit v1.2.3 From 5bad16482c2a7e788c042d98f3e97d3b2bbc8cc5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 5 Sep 2025 21:16:30 +0200 Subject: regulator: dt-bindings: rpi-panel: Split 7" Raspberry Pi 720x1280 v2 binding The 5" and 7" Raspberry Pi 720x1280 Display 2 MCU is a bit more complex than the original Display 1 ATTINY88 and the binding is also a bit more demanding. Split the binding into separate file and fill in required gpio-controller, #gpio-cells and #pwm-cells which must be present for the V2 MCU. Include mention of the 5" panel in the description of Display 2, as the 5" panel uses the same MCU. Fixes: 6d09c6e474bd ("regulator: dt-bindings: rpi-panel: Add regulator for 7" Raspberry Pi 720x1280") Signed-off-by: Marek Vasut Acked-by: Conor Dooley Message-ID: <20250905191637.147141-1-marek.vasut+renesas@mailbox.org> Signed-off-by: Mark Brown --- ...rrypi,7inch-touchscreen-panel-regulator-v2.yaml | 61 ++++++++++++++++++++++ ...pberrypi,7inch-touchscreen-panel-regulator.yaml | 7 +-- 2 files changed, 63 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml b/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml new file mode 100644 index 000000000000..37b9ed371b67 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RaspberryPi 5" and 7" display V2 MCU-based regulator/backlight controller + +maintainers: + - Marek Vasut + +description: | + The RaspberryPi 5" and 7" display 2 has an MCU-based regulator, PWM + backlight and GPIO controller on the PCB, which is used to turn the + display unit on/off and control the backlight. + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + const: raspberrypi,touchscreen-panel-regulator-v2 + + reg: + maxItems: 1 + + gpio-controller: true + "#gpio-cells": + const: 2 + description: + The first cell is the pin number, and the second cell is used to + specify the gpio polarity (GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW). + + "#pwm-cells": + const: 3 + description: See ../../pwm/pwm.yaml for description of the cell formats. + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - "#pwm-cells" + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + regulator@45 { + compatible = "raspberrypi,touchscreen-panel-regulator-v2"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <3>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml b/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml index 18944d39d08f..41678400e63f 100644 --- a/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml @@ -12,17 +12,14 @@ maintainers: description: | The RaspberryPi 7" display has an ATTINY88-based regulator/backlight controller on the PCB, which is used to turn the display unit on/off - and control the backlight. The V2 supports 5" and 7" panels and also - offers PWM backlight control. + and control the backlight. allOf: - $ref: regulator.yaml# properties: compatible: - enum: - - raspberrypi,7inch-touchscreen-panel-regulator - - raspberrypi,touchscreen-panel-regulator-v2 + const: raspberrypi,7inch-touchscreen-panel-regulator reg: maxItems: 1 -- cgit v1.2.3 From 2c4f536c75217476baabbd557a44e8d4c3a2a23a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 8 Sep 2025 15:04:18 +0200 Subject: dt-bindings: display: bridge: simple: document the Realtek RTD2171 DP-to-HDMI bridge The Realtek RTD2171 chipset is a transparent DisplayPort 1.4 to HDMI 2.0 bridge. This chipset is usually found in USB-C To HDMI Adapters and Docks, or laptops to provide HDMI display output. Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250908-topic-x1e80100-hdmi-v3-1-c53b0f2bc2fb@linaro.org Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml index 421f99ca42d9..9ef587d46506 100644 --- a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +++ b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml @@ -29,6 +29,7 @@ properties: - adi,adv7123 - dumb-vga-dac - radxa,ra620 + - realtek,rtd2171 - ti,opa362 - ti,ths8134 - ti,ths8135 -- cgit v1.2.3 From bc3f7d0340f7cf32b53e40aeed25ac0c6a0e77e7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 7 Sep 2025 12:25:13 -0300 Subject: dt-bindings: arm: cpus: Document pu-supply The i.MX6Q Reference Manual describes the three digital LDO regulators as follows: "10.4.1.1.1 Digital LDO Regulators The integrated PMU includes three digital LDO regulators: LDO_ARM, LDO_PU, and LDO_SOC. These regulators provide power to the ARM_Core power domain, the combined VPU, IPU and GPU power domain, and the rest of the SoC logic (except always-ON SNVS domain)." imx6dl.dtsi uses the correct names to describe these supplies: arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; 'arm-supply' and 'soc-supply' are already documented, but 'pu-supply' is not. Document the 'pu-supply' property and set it to deprecated. This fixes the following dt-schema warning: cpu@1 (arm,cortex-a9): Unevaluated properties are not allowed ('pu-supply' was unexpected) Signed-off-by: Fabio Estevam Reviewed-by: Frank Li Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250907152513.590218-1-festevam@gmail.com Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index b1c6943e7d78..41ad4ed0e74c 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -350,6 +350,10 @@ properties: deprecated: true description: Use 'cpu-supply' instead + pu-supply: + deprecated: true + description: Only for i.MX6Q/DL/SL SoCs. + soc-supply: deprecated: true description: Only for i.MX6/7 Soc. -- cgit v1.2.3 From 7095d688de38de197c408f8904cf1c1d8b257dae Mon Sep 17 00:00:00 2001 From: Baojun Xu Date: Sat, 30 Aug 2025 14:14:59 +0800 Subject: ASoC: tas2781: Add tas2118, tas2x20, tas5825 support Update ti,tas2781.yaml for adding tas2118, tas2x20, tas257x and tas582x. Signed-off-by: Baojun Xu Reviewed-by: Rob Herring (Arm) Signed-off-by: Takashi Iwai --- .../devicetree/bindings/sound/ti,tas2781.yaml | 96 +++++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ti,tas2781.yaml b/Documentation/devicetree/bindings/sound/ti,tas2781.yaml index 5ea1cdc593b5..011211112be4 100644 --- a/Documentation/devicetree/bindings/sound/ti,tas2781.yaml +++ b/Documentation/devicetree/bindings/sound/ti,tas2781.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright (C) 2022 - 2023 Texas Instruments Incorporated +# Copyright (C) 2022 - 2025 Texas Instruments Incorporated %YAML 1.2 --- $id: http://devicetree.org/schemas/sound/ti,tas2781.yaml# @@ -11,30 +11,77 @@ maintainers: - Shenghao Ding description: | + The TAS2118/TAS2X20/TAS257x is mono, digital input Class-D audio + amplifier optimized for efficiently driving high peak power into + small loudspeakers. + Integrated speaker voltage and current sense provides for + real time monitoring of loudspeaker behavior. The TAS2563/TAS2781 is a mono, digital input Class-D audio amplifier optimized for efficiently driving high peak power into small loudspeakers. An integrated on-chip DSP supports Texas Instruments Smart Amp speaker protection algorithm. The integrated speaker voltage and current sense provides for real time monitoring of loudspeaker behavior. + The TAS5825/TAS5827 is a stereo, digital input Class-D audio + amplifier optimized for efficiently driving high peak power into + small loudspeakers. An integrated on-chip DSP supports Texas + Instruments Smart Amp speaker protection algorithm. The + integrated speaker voltage and current sense provides for real time + monitoring of loudspeaker behavior. Specifications about the audio amplifier can be found at: + https://www.ti.com/lit/gpn/tas2120 + https://www.ti.com/lit/gpn/tas2320 https://www.ti.com/lit/gpn/tas2563 + https://www.ti.com/lit/gpn/tas2572 https://www.ti.com/lit/gpn/tas2781 + https://www.ti.com/lit/gpn/tas5825m + https://www.ti.com/lit/gpn/tas5827 properties: compatible: description: | + ti,tas2020: 3.2-W Mono Digital Input Class-D Speaker Amp with 5.5V PVDD + Support. + + ti,tas2118: 5-W Mono Digital Input Class-D Speaker Amp with Integrated + 8.4-V Class-H Boost. + + ti,tas2120: 8.2-W Mono Digital Input Class-D Speaker Amp with + Integrated 14.75V Class-H Boost. + + ti,tas2320: 15-W Mono Digital Input Class-D Speaker Amp with 15V Support. + ti,tas2563: 6.1-W Boosted Class-D Audio Amplifier With Integrated DSP and IV Sense, 16/20/24/32bit stereo I2S or multichannel TDM. + ti,tas2570: 5.8-W Digital Input smart amp with I/V sense and integrated + 11-V Class-H Boost + + ti,tas2572: 6.6-W Digital Input smart amp with I/V sense and integrated + 13-V Class-H Boost + ti,tas2781: 24-V Class-D Amplifier with Real Time Integrated Speaker Protection and Audio Processing, 16/20/24/32bit stereo I2S or multichannel TDM. + + ti,tas5825: 38-W Stereo, Inductor-Less, Digital Input, Closed-Loop 4.5V + to 26.4V Class-D Audio Amplifier with 192-kHz Extended Audio Processing. + + ti,tas5827: 47-W Stereo, Digital Input, High Efficiency Closed-Loop Class-D + Amplifier with Class-H Algorithm oneOf: - items: - enum: + - ti,tas2020 + - ti,tas2118 + - ti,tas2120 + - ti,tas2320 - ti,tas2563 + - ti,tas2570 + - ti,tas2572 + - ti,tas5825 + - ti,tas5827 - const: ti,tas2781 - enum: - ti,tas2781 @@ -61,6 +108,23 @@ required: allOf: - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - ti,tas2020 + - ti,tas2118 + - ti,tas2120 + - ti,tas2320 + then: + properties: + reg: + maxItems: 4 + items: + minimum: 0x48 + maximum: 0x4b + - if: properties: compatible: @@ -79,6 +143,21 @@ allOf: minimum: 0x4c maximum: 0x4f + - if: + properties: + compatible: + contains: + enum: + - ti,tas2570 + - ti,tas2572 + then: + properties: + reg: + maxItems: 4 + items: + minimum: 0x48 + maximum: 0x4b + - if: properties: compatible: @@ -97,6 +176,21 @@ allOf: minimum: 0x38 maximum: 0x3f + - if: + properties: + compatible: + contains: + enum: + - ti,tas5825 + - ti,tas5827 + then: + properties: + reg: + maxItems: 4 + items: + minimum: 0x4c + maximum: 0x4f + additionalProperties: false examples: -- cgit v1.2.3 From 23fc2a41a2c67d622d242b670a10ce8f76a7b68e Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Mon, 8 Sep 2025 09:18:10 +0800 Subject: dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles Add SCU interrupt controller compatible strings for the AST2700 SoC: scu-ic0 to 3. This extends the MFD binding to support AST2700-based platforms. Signed-off-by: Ryan Chen Signed-off-by: Thomas Gleixner Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/all/20250908011812.1033858-3-ryan_chen@aspeedtech.com --- Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index 5eccd10d95ce..67be6d095fe4 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -75,6 +75,10 @@ patternProperties: - aspeed,ast2500-scu-ic - aspeed,ast2600-scu-ic0 - aspeed,ast2600-scu-ic1 + - aspeed,ast2700-scu-ic0 + - aspeed,ast2700-scu-ic1 + - aspeed,ast2700-scu-ic2 + - aspeed,ast2700-scu-ic3 '^silicon-id@[0-9a-f]+$': description: Unique hardware silicon identifiers within the SoC -- cgit v1.2.3 From ed7240444e82aaaa2245a3cc9b040e4db894a665 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Mon, 8 Sep 2025 09:18:11 +0800 Subject: dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles Add compatible strings for the four SCU interrupt controller instances on the AST2700 SoC (scu-ic0 to 3), following the multi-instance model used on AST2600. Also define interrupt indices in the binding header. Signed-off-by: Ryan Chen Signed-off-by: Thomas Gleixner Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/all/20250908011812.1033858-4-ryan_chen@aspeedtech.com --- .../interrupt-controller/aspeed,ast2500-scu-ic.yaml | 6 +++++- include/dt-bindings/interrupt-controller/aspeed-scu-ic.h | 14 ++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml index d5287a2bf866..d998a9d69b91 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2500-scu-ic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Aspeed AST25XX and AST26XX SCU Interrupt Controller +title: Aspeed AST25XX, AST26XX, AST27XX SCU Interrupt Controller maintainers: - Eddie James @@ -16,6 +16,10 @@ properties: - aspeed,ast2500-scu-ic - aspeed,ast2600-scu-ic0 - aspeed,ast2600-scu-ic1 + - aspeed,ast2700-scu-ic0 + - aspeed,ast2700-scu-ic1 + - aspeed,ast2700-scu-ic2 + - aspeed,ast2700-scu-ic3 reg: maxItems: 1 diff --git a/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h b/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h index f315d5a7f5ee..7dd04424afcc 100644 --- a/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h +++ b/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h @@ -20,4 +20,18 @@ #define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0 #define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1 +#define ASPEED_AST2700_SCU_IC0_PCIE_PERST_LO_TO_HI 3 +#define ASPEED_AST2700_SCU_IC0_PCIE_PERST_HI_TO_LO 2 + +#define ASPEED_AST2700_SCU_IC1_PCIE_RCRST_LO_TO_HI 3 +#define ASPEED_AST2700_SCU_IC1_PCIE_RCRST_HI_TO_LO 2 + +#define ASPEED_AST2700_SCU_IC2_PCIE_PERST_LO_TO_HI 3 +#define ASPEED_AST2700_SCU_IC2_PCIE_PERST_HI_TO_LO 2 +#define ASPEED_AST2700_SCU_IC2_LPC_RESET_LO_TO_HI 1 +#define ASPEED_AST2700_SCU_IC2_LPC_RESET_HI_TO_LO 0 + +#define ASPEED_AST2700_SCU_IC3_LPC_RESET_LO_TO_HI 1 +#define ASPEED_AST2700_SCU_IC3_LPC_RESET_HI_TO_LO 0 + #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */ -- cgit v1.2.3 From 7e5969a4d3e794993c9ca8d4026cf31a34b32b30 Mon Sep 17 00:00:00 2001 From: Kurt Borja Date: Mon, 8 Sep 2025 10:54:51 -0500 Subject: dt-bindings: trivial-devices: Add sht2x sensors Add sensirion,sht2x trivial sensors. Signed-off-by: Kurt Borja Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250908-sht2x-v4-3-bc15f68af7de@gmail.com Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/trivial-devices.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 0e6ba6e12a63..edaba5cd8434 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -372,6 +372,9 @@ properties: # Sensirion low power multi-pixel gas sensor with I2C interface - sensirion,sgpc3 # Sensirion temperature & humidity sensor with I2C interface + - sensirion,sht20 + - sensirion,sht21 + - sensirion,sht25 - sensirion,sht4x # Sensortek 3 axis accelerometer - sensortek,stk8312 -- cgit v1.2.3 From 1dd41ad7565940af6e96828230b6b11a8267437a Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 24 Jun 2025 08:34:03 +0200 Subject: Documentation: media: update Hans Verkuil's email address Replace hverkuil-cisco@xs4all.nl by hverkuil@kernel.org. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/ABI/testing/debugfs-cec-error-inj | 2 +- Documentation/devicetree/bindings/media/cec/cec-gpio.yaml | 2 +- Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml | 2 +- Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml | 2 +- Documentation/userspace-api/media/cec/cec-api.rst | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/ABI/testing/debugfs-cec-error-inj b/Documentation/ABI/testing/debugfs-cec-error-inj index 8debcb08a3b5..c512f71bba8e 100644 --- a/Documentation/ABI/testing/debugfs-cec-error-inj +++ b/Documentation/ABI/testing/debugfs-cec-error-inj @@ -1,6 +1,6 @@ What: /sys/kernel/debug/cec/*/error-inj Date: March 2018 -Contact: Hans Verkuil +Contact: Hans Verkuil Description: The CEC Framework allows for CEC error injection commands through diff --git a/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml b/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml index 64d7ec057672..582c6c9cae48 100644 --- a/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml +++ b/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: HDMI CEC GPIO maintainers: - - Hans Verkuil + - Hans Verkuil description: | The HDMI CEC GPIO module supports CEC implementations where the CEC line is diff --git a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml index 4b46aa755ccd..6ef545b1d622 100644 --- a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra HDMI CEC maintainers: - - Hans Verkuil + - Hans Verkuil allOf: - $ref: cec-common.yaml# diff --git a/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml index 6c403003cdda..2dc2829d42a0 100644 --- a/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADV7604/10/11/12 video decoder with HDMI receiver maintainers: - - Hans Verkuil + - Hans Verkuil description: The ADV7604 and ADV7610/11/12 are multiformat video decoders with diff --git a/Documentation/userspace-api/media/cec/cec-api.rst b/Documentation/userspace-api/media/cec/cec-api.rst index 578303d484f3..594f0ec420a2 100644 --- a/Documentation/userspace-api/media/cec/cec-api.rst +++ b/Documentation/userspace-api/media/cec/cec-api.rst @@ -26,7 +26,7 @@ Revision and Copyright ********************** Authors: -- Verkuil, Hans +- Verkuil, Hans - Initial version. -- cgit v1.2.3 From 9bff72cb99b10ead19ab1e36d240cc54bc4954b1 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Tue, 24 Jun 2025 08:39:35 +0200 Subject: Documentation: update Hans Verkuil's email address Replace hverkuil@xs4all.nl by hverkuil@kernel.org. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/admin-guide/bug-hunting.rst | 2 +- Documentation/admin-guide/media/ivtv.rst | 2 +- Documentation/devicetree/bindings/media/cec/cec-common.yaml | 2 +- Documentation/devicetree/bindings/media/silabs,si470x.yaml | 2 +- Documentation/driver-api/media/maintainer-entry-profile.rst | 4 ++-- Documentation/translations/zh_CN/admin-guide/bug-hunting.rst | 2 +- Documentation/translations/zh_TW/admin-guide/bug-hunting.rst | 2 +- Documentation/userspace-api/media/drivers/cx2341x-uapi.rst | 2 +- Documentation/userspace-api/media/v4l/v4l2.rst | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/admin-guide/bug-hunting.rst b/Documentation/admin-guide/bug-hunting.rst index 30858757c9f2..7da0504388ec 100644 --- a/Documentation/admin-guide/bug-hunting.rst +++ b/Documentation/admin-guide/bug-hunting.rst @@ -252,7 +252,7 @@ For example, if you find a bug at the gspca's sonixj.c file, you can get its maintainers with:: $ ./scripts/get_maintainer.pl --bug -f drivers/media/usb/gspca/sonixj.c - Hans Verkuil (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) + Hans Verkuil (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) Mauro Carvalho Chehab (maintainer:MEDIA INPUT INFRASTRUCTURE (V4L/DVB),commit_signer:1/1=100%) Tejun Heo (commit_signer:1/1=100%) Bhaktipriya Shridhar (commit_signer:1/1=100%,authored:1/1=100%,added_lines:4/4=100%,removed_lines:9/9=100%) diff --git a/Documentation/admin-guide/media/ivtv.rst b/Documentation/admin-guide/media/ivtv.rst index 101f16d0263e..8b65ac3f5321 100644 --- a/Documentation/admin-guide/media/ivtv.rst +++ b/Documentation/admin-guide/media/ivtv.rst @@ -3,7 +3,7 @@ The ivtv driver =============== -Author: Hans Verkuil +Author: Hans Verkuil This is a v4l2 device driver for the Conexant cx23415/6 MPEG encoder/decoder. The cx23415 can do both encoding and decoding, the cx23416 can only do MPEG diff --git a/Documentation/devicetree/bindings/media/cec/cec-common.yaml b/Documentation/devicetree/bindings/media/cec/cec-common.yaml index af6ee5f1c73f..6d5017d9bf55 100644 --- a/Documentation/devicetree/bindings/media/cec/cec-common.yaml +++ b/Documentation/devicetree/bindings/media/cec/cec-common.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: HDMI CEC Adapters Common Properties maintainers: - - Hans Verkuil + - Hans Verkuil properties: $nodename: diff --git a/Documentation/devicetree/bindings/media/silabs,si470x.yaml b/Documentation/devicetree/bindings/media/silabs,si470x.yaml index a3d19c562ca3..db22b88fc5bb 100644 --- a/Documentation/devicetree/bindings/media/silabs,si470x.yaml +++ b/Documentation/devicetree/bindings/media/silabs,si470x.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Silicon Labs Si470x FM Radio Receiver maintainers: - - Hans Verkuil + - Hans Verkuil - Paweł Chmiel properties: diff --git a/Documentation/driver-api/media/maintainer-entry-profile.rst b/Documentation/driver-api/media/maintainer-entry-profile.rst index ad96a89ee916..2127e5b15e8f 100644 --- a/Documentation/driver-api/media/maintainer-entry-profile.rst +++ b/Documentation/driver-api/media/maintainer-entry-profile.rst @@ -75,7 +75,7 @@ The media maintainers that work on specific areas of the subsystem are: Sean Young - HDMI CEC: - Hans Verkuil + Hans Verkuil - Media controller drivers: Laurent Pinchart @@ -84,7 +84,7 @@ The media maintainers that work on specific areas of the subsystem are: Sakari Ailus - V4L2 drivers and core V4L2 frameworks: - Hans Verkuil + Hans Verkuil The subsystem maintainer is: Mauro Carvalho Chehab diff --git a/Documentation/translations/zh_CN/admin-guide/bug-hunting.rst b/Documentation/translations/zh_CN/admin-guide/bug-hunting.rst index 4b3432753eb9..f20bf5be4cf9 100644 --- a/Documentation/translations/zh_CN/admin-guide/bug-hunting.rst +++ b/Documentation/translations/zh_CN/admin-guide/bug-hunting.rst @@ -239,7 +239,7 @@ objdump 例如，您在gspca的sonixj.c文件中发现一个缺陷，则可以通过以下方法找到它的维护者:: $ ./scripts/get_maintainer.pl -f drivers/media/usb/gspca/sonixj.c - Hans Verkuil (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) + Hans Verkuil (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) Mauro Carvalho Chehab (maintainer:MEDIA INPUT INFRASTRUCTURE (V4L/DVB),commit_signer:1/1=100%) Tejun Heo (commit_signer:1/1=100%) Bhaktipriya Shridhar (commit_signer:1/1=100%,authored:1/1=100%,added_lines:4/4=100%,removed_lines:9/9=100%) diff --git a/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst b/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst index 80ea5677ee52..c677dff826f5 100644 --- a/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst +++ b/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst @@ -242,7 +242,7 @@ objdump 例如，您在gspca的sonixj.c文件中發現一個缺陷，則可以通過以下方法找到它的維護者:: $ ./scripts/get_maintainer.pl -f drivers/media/usb/gspca/sonixj.c - Hans Verkuil (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) + Hans Verkuil (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) Mauro Carvalho Chehab (maintainer:MEDIA INPUT INFRASTRUCTURE (V4L/DVB),commit_signer:1/1=100%) Tejun Heo (commit_signer:1/1=100%) Bhaktipriya Shridhar (commit_signer:1/1=100%,authored:1/1=100%,added_lines:4/4=100%,removed_lines:9/9=100%) diff --git a/Documentation/userspace-api/media/drivers/cx2341x-uapi.rst b/Documentation/userspace-api/media/drivers/cx2341x-uapi.rst index debde65fb8cd..b617c988b915 100644 --- a/Documentation/userspace-api/media/drivers/cx2341x-uapi.rst +++ b/Documentation/userspace-api/media/drivers/cx2341x-uapi.rst @@ -130,7 +130,7 @@ Raw format c example Format of embedded V4L2_MPEG_STREAM_VBI_FMT_IVTV VBI data --------------------------------------------------------- -Author: Hans Verkuil +Author: Hans Verkuil This section describes the V4L2_MPEG_STREAM_VBI_FMT_IVTV format of the VBI data diff --git a/Documentation/userspace-api/media/v4l/v4l2.rst b/Documentation/userspace-api/media/v4l/v4l2.rst index cf8ae56a008c..64fb264fb6c4 100644 --- a/Documentation/userspace-api/media/v4l/v4l2.rst +++ b/Documentation/userspace-api/media/v4l/v4l2.rst @@ -86,7 +86,7 @@ Authors, in alphabetical order: - Documented the fielded V4L2_MPEG_STREAM_VBI_FMT_IVTV MPEG stream embedded, sliced VBI data format in this specification. -- Verkuil, Hans +- Verkuil, Hans - Designed and documented the VIDIOC_LOG_STATUS ioctl, the extended control ioctls, major parts of the sliced VBI API, the MPEG encoder and decoder APIs and the DV Timings API. -- cgit v1.2.3 From c329055587ee5248390e53fd2625438919928e2a Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 14 Aug 2025 10:52:41 +0200 Subject: media: dt-bindings: venus: Add qcm2290 dt schema Add a schema for the venus video encoder/decoder on the qcm2290. The order of the IOMMU list is strict: the first two entries correspond to non-secure IOMMUs, and the remaining three to secure IOMMUs. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil --- .../bindings/media/qcom,qcm2290-venus.yaml | 130 +++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml new file mode 100644 index 000000000000..3f3ee82fc878 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcm2290-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCM2290 Venus video encode and decode accelerators + +maintainers: + - Jorge Ramirez-Ortiz + +description: + The Venus AR50_LITE IP is a video encode and decode accelerator present + on Qualcomm platforms. + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + const: qcom,qcm2290-venus + + power-domains: + maxItems: 3 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: cx + + clocks: + maxItems: 6 + + clock-names: + items: + - const: core + - const: iface + - const: bus + - const: throttle + - const: vcodec0_core + - const: vcodec0_bus + + iommus: + maxItems: 5 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: video-mem + - const: cpu-cfg + + operating-points-v2: true + opp-table: + type: object + +required: + - compatible + - power-domain-names + - iommus + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + venus: video-codec@5a00000 { + compatible = "qcom,qcm2290-venus"; + reg = <0x5a00000 0xf0000>; + + interrupts = ; + + power-domains = <&gcc GCC_VENUS_GDSC>, + <&gcc GCC_VCODEC0_GDSC>, + <&rpmpd QCM2290_VDDCX>; + power-domain-names = "venus", + "vcodec0", + "cx"; + + operating-points-v2 = <&venus_opp_table>; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>; + clock-names = "core", + "iface", + "bus", + "throttle", + "vcodec0_core", + "vcodec0_bus"; + + memory-region = <&pil_video_mem>; + + iommus = <&apps_smmu 0x860 0x0>, + <&apps_smmu 0x880 0x0>, + <&apps_smmu 0x861 0x04>, + <&apps_smmu 0x863 0x0>, + <&apps_smmu 0x804 0xe0>; + + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; + interconnect-names = "video-mem", + "cpu-cfg"; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133333333 { + opp-hz = /bits/ 64 <133333333>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + }; -- cgit v1.2.3 From 9364790e91fbfb34aa4751e5cafe716079e26b70 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 29 Aug 2025 17:42:31 +0300 Subject: dt-bindings: media: i2c: Add OmniVision OV6211 image sensor Add device tree bindings documentation for OmniVision OV6211 image sensor. Reviewed-by: Rob Herring (Arm) Signed-off-by: Vladimir Zapolskiy Signed-off-by: Sakari Ailus Signed-off-by: Hans Verkuil --- .../devicetree/bindings/media/i2c/ovti,ov6211.yaml | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/ovti,ov6211.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov6211.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov6211.yaml new file mode 100644 index 000000000000..5a857fa2f371 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov6211.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov6211.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV6211 Image Sensor + +description: + OmniVision OV6211 image sensor is a high performance monochrome image + sensor. The sensor is controlled over a serial camera control bus + protocol (SCCB), the widest supported output image frame size is 400x400 + at 120 frames per second rate, data output format is 8/10-bit RAW + transferred over one-lane MIPI D-PHY interface. + +maintainers: + - Vladimir Zapolskiy + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: ovti,ov6211 + + reg: + maxItems: 1 + + clocks: + description: XVCLK supply clock, 6MHz to 27MHz frequency. + maxItems: 1 + + reset-gpios: + description: Active low GPIO connected to XSHUTDOWN pad of the sensor. + maxItems: 1 + + strobe-gpios: + description: Input GPIO connected to strobe pad of the sensor. + maxItems: 1 + + avdd-supply: + description: Analogue voltage supply, 2.6 to 3.0 volts. + + dovdd-supply: + description: Digital I/O voltage supply, 1.8 volts. + + dvdd-supply: + description: Digital core voltage supply. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - link-frequencies + +required: + - compatible + - reg + - port + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@60 { + compatible = "ovti,ov6211"; + reg = <0x60>; + clocks = <&camera_clk 0>; + assigned-clocks = <&camera_clk 0>; + assigned-clock-rates = <24000000>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + avdd-supply = <&vreg_2p8>; + dovdd-supply = <&vreg_1p8>; + dvdd-supply = <&vreg_1p2>; + + port { + endpoint { + link-frequencies = /bits/ 64 <480000000>; + remote-endpoint = <&mipi_csi2_ep>; + }; + }; + }; + }; +... -- cgit v1.2.3 From 9acb06945fabc3f8a392674e4c4604bf7657dd29 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 29 Aug 2025 17:42:41 +0300 Subject: dt-bindings: media: i2c: Add OmniVision OG0VE1B camera sensor Add device tree bindings documentation for OmniVision OG0VE1B camera sensor. Reviewed-by: Rob Herring (Arm) Signed-off-by: Vladimir Zapolskiy Signed-off-by: Sakari Ailus Signed-off-by: Hans Verkuil --- .../bindings/media/i2c/ovti,og0ve1b.yaml | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml new file mode 100644 index 000000000000..bd2f1ae23e65 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,og0ve1b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OG0VE1B Image Sensor + +description: + OmniVision OG0VE1B image sensor is a low power consuming monochrome + image sensor. The sensor is controlled over a serial camera control + bus protocol (SCCB), the widest supported image size is 640x480 at + 120 frames per second rate, data output format is 8/10-bit RAW + transferred over one-lane MIPI D-PHY at up to 800 Mbps. + +maintainers: + - Vladimir Zapolskiy + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: ovti,og0ve1b + + reg: + maxItems: 1 + + clocks: + description: XVCLK supply clock, 6MHz to 27MHz frequency. + maxItems: 1 + + reset-gpios: + description: Active low GPIO connected to XSHUTDOWN pad of the sensor. + maxItems: 1 + + strobe-gpios: + description: Input GPIO connected to strobe pad of the sensor. + maxItems: 1 + + avdd-supply: + description: Analog voltage supply, 2.6 to 3.0 volts. + + dovdd-supply: + description: Digital I/O voltage supply, 1.7 to 3.0 volts. + + dvdd-supply: + description: Digital core voltage supply. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - link-frequencies + +required: + - compatible + - reg + - port + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@3e { + compatible = "ovti,og0ve1b"; + reg = <0x3e>; + clocks = <&camera_clk 0>; + assigned-clocks = <&camera_clk 0>; + assigned-clock-rates = <24000000>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + avdd-supply = <&vreg_2p8>; + dovdd-supply = <&vreg_1p8>; + dvdd-supply = <&vreg_1p2>; + + port { + endpoint { + link-frequencies = /bits/ 64 <500000000>; + remote-endpoint = <&mipi_csi2_ep>; + }; + }; + }; + }; + +... -- cgit v1.2.3 From 773bb3066e6debf5b66ce598ec6a989911864d61 Mon Sep 17 00:00:00 2001 From: Himanshu Bhavani Date: Fri, 29 Aug 2025 14:39:50 +0530 Subject: dt-bindings: media: i2c: Add ov2735 sensor Add bindings for Omnivision OV2735 sensor. Add MAINTAINERS entry for Omnivision OV2735 binding documentation Signed-off-by: Himanshu Bhavani Signed-off-by: Hardevsinh Palaniya Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sakari Ailus Signed-off-by: Hans Verkuil --- .../devicetree/bindings/media/i2c/ovti,ov2735.yaml | 108 +++++++++++++++++++++ MAINTAINERS | 7 ++ 2 files changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/ovti,ov2735.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov2735.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov2735.yaml new file mode 100644 index 000000000000..bb34f21519c8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov2735.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov2735.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV2735 Image Sensor + +maintainers: + - Himanshu Bhavani + +description: + The OmniVision OV2735 is a 2MP (1920x1080) color CMOS image sensor controlled + through an I2C-compatible SCCB bus. it outputs RAW10 format and uses a 1/2.7" + optical format. + +properties: + compatible: + const: ovti,ov2735 + + reg: + maxItems: 1 + + clocks: + items: + - description: XVCLK clock + + avdd-supply: + description: Analog Domain Power Supply + + dovdd-supply: + description: I/O Domain Power Supply + + dvdd-supply: + description: Digital Domain Power Supply + + reset-gpios: + maxItems: 1 + description: Reset Pin GPIO Control (active low) + + enable-gpios: + maxItems: 1 + description: + Active-low enable pin. Labeled as 'PWDN' in the datasheet, but acts as + an enable signal. During power rail ramp-up, the device remains powered + down. Once power rails are stable, pulling this pin low powers on the + device. + + port: + description: MIPI CSI-2 transmitter port + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + items: + - const: 1 + - const: 2 + + required: + - data-lanes + - link-frequencies + +required: + - compatible + - reg + - clocks + - avdd-supply + - dovdd-supply + - dvdd-supply + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@3c { + compatible = "ovti,ov2735"; + reg = <0x3c>; + clocks = <&ov2735_clk>; + + avdd-supply = <&ov2735_avdd>; + dovdd-supply = <&ov2735_dovdd>; + dvdd-supply = <&ov2735_dvdd>; + + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + + port { + cam_out: endpoint { + remote-endpoint = <&mipi_in_cam>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <420000000>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f1b9b0f2dac8..076929bd4ff0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18671,6 +18671,13 @@ T: git git://linuxtv.org/media.git F: Documentation/devicetree/bindings/media/i2c/ovti,ov2685.yaml F: drivers/media/i2c/ov2685.c +OMNIVISION OV2735 SENSOR DRIVER +M: Hardevsinh Palaniya +M: Himanshu Bhavani +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/i2c/ovti,ov2735.yaml + OMNIVISION OV2740 SENSOR DRIVER M: Tianshu Qiu R: Sakari Ailus -- cgit v1.2.3 From aa1826696a55cb0cbf706b41d7cb5f4e22084206 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Aug 2025 12:49:23 +0300 Subject: dt-bindings: media: Deprecate clock-frequency property for camera sensors Usage of the clock-frequency property for camera sensors is discouraged in favour of using assigned-clock-rates (and assigned-clock-parents where needed). Mark the property as deprecated. Update the examples accordingly. In DT examples where the sensor input clock appears to come from a programmable clock generator, replace clock-frequency by the assigned-clocks and assigned-clock-rates properties. Otherwise, just drop clock-frequency. Signed-off-by: Laurent Pinchart Reviewed-by: Rob Herring (Arm) Signed-off-by: Sakari Ailus Reviewed-by: Mehdi Djait Signed-off-by: Hans Verkuil --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 6 ++++-- Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml | 7 +++++-- Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml | 3 +-- Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml | 6 +++++- Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml | 6 +++++- Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml | 3 +-- Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml | 6 +++++- Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml | 6 +++++- Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml | 5 +++-- .../devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml | 3 ++- Documentation/devicetree/bindings/media/samsung,fimc.yaml | 3 ++- 11 files changed, 38 insertions(+), 16 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 73144473b9b2..1687b069e032 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -292,7 +292,8 @@ examples: clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; clock-names = "xvclk"; - clock-frequency = <19200000>; + assigned-clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + assigned-clock-rates = <19200000>; dovdd-supply = <&vreg_lvs1a_1p8>; avdd-supply = <&cam0_avdd_2v8>; @@ -324,7 +325,8 @@ examples: clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; clock-names = "xclk"; - clock-frequency = <24000000>; + assigned-clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; vdddo-supply = <&vreg_lvs1a_1p8>; vdda-supply = <&cam3_avdd_2v8>; diff --git a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml index bc664a016396..217b08c8cbbd 100644 --- a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml +++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml @@ -55,6 +55,7 @@ properties: clock-frequency: description: Frequency of the external clock to the sensor in Hz. + deprecated: true reset-gpios: description: Reset GPIO. Also commonly called XSHUTDOWN in hardware @@ -93,7 +94,6 @@ properties: required: - compatible - reg - - clock-frequency - clocks additionalProperties: false @@ -114,8 +114,11 @@ examples: reg = <0x10>; reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; vana-supply = <&vaux3>; + clocks = <&omap3_isp 0>; - clock-frequency = <9600000>; + assigned-clocks = <&omap3_isp 0>; + assigned-clock-rates = <9600000>; + port { ccs_ep: endpoint { data-lanes = <1 2>; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml index 67c1c291327b..0e1d9c390180 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml @@ -39,6 +39,7 @@ properties: clock-frequency: description: Frequency of the eclk clock in Hz. + deprecated: true dovdd-supply: description: @@ -100,7 +101,6 @@ required: - reg - clocks - clock-names - - clock-frequency - dovdd-supply - avdd-supply - dvdd-supply @@ -127,7 +127,6 @@ examples: clocks = <&ov02a10_clk>; clock-names = "eclk"; - clock-frequency = <24000000>; rotation = <180>; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml index bc9b27afe3ea..a583714b1ac7 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml @@ -21,6 +21,7 @@ properties: clock-frequency: description: Frequency of the xclk clock in Hz. + deprecated: true vdda-supply: description: Analog voltage supply, 2.8 volts @@ -83,8 +84,11 @@ examples: camera@3c { compatible = "ovti,ov5645"; reg = <0x3c>; + clocks = <&clks 1>; - clock-frequency = <24000000>; + assigned-clocks = <&clks 1>; + assigned-clock-rates = <24000000>; + vdddo-supply = <&ov5645_vdddo_1v8>; vdda-supply = <&ov5645_vdda_2v8>; vddd-supply = <&ov5645_vddd_1v5>; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml index 2e5187acbbb8..922996da59b2 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml @@ -29,6 +29,7 @@ properties: clock-frequency: description: Frequency of the xclk clock in Hz. + deprecated: true vdda-supply: description: Analog voltage supply, 2.8 volts @@ -89,8 +90,11 @@ examples: camera@3c { compatible = "ovti,ov7251"; reg = <0x3c>; + clocks = <&clks 1>; - clock-frequency = <24000000>; + assigned-clocks = <&clks 1>; + assigned-clock-rates = <24000000>; + vdddo-supply = <&ov7251_vdddo_1v8>; vdda-supply = <&ov7251_vdda_2v8>; vddd-supply = <&ov7251_vddd_1v5>; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml index 3f6f72c35485..fa71f24823f2 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml @@ -37,6 +37,7 @@ properties: clock-frequency: description: Frequency of the xvclk clock in Hertz. + deprecated: true dovdd-supply: description: @@ -87,7 +88,6 @@ required: - reg - clocks - clock-names - - clock-frequency - dovdd-supply - avdd-supply - dvdd-supply @@ -114,7 +114,6 @@ examples: clocks = <&cam_osc>; clock-names = "xvclk"; - clock-frequency = <19200000>; avdd-supply = <&mt6358_vcama2_reg>; dvdd-supply = <&mt6358_vcamd_reg>; diff --git a/Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml b/Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml index c8f2955e0825..ebd95a8d9b2f 100644 --- a/Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml +++ b/Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml @@ -26,6 +26,7 @@ properties: clock-frequency: default: 24000000 description: mclk clock frequency + deprecated: true rstn-gpios: maxItems: 1 @@ -82,9 +83,12 @@ examples: sensor@2d { compatible = "samsung,s5k5baf"; reg = <0x2d>; + clocks = <&camera 0>; + assigned-clocks = <&camera 0>; + assigned-clock-rates = <24000000>; + clock-names = "mclk"; - clock-frequency = <24000000>; rstn-gpios = <&gpl2 1 GPIO_ACTIVE_LOW>; stbyn-gpios = <&gpl2 0 GPIO_ACTIVE_LOW>; vdda-supply = <&cam_io_en_reg>; diff --git a/Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml b/Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml index 7e83a94124b5..e563e35920c4 100644 --- a/Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml +++ b/Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml @@ -30,6 +30,7 @@ properties: clock-frequency: default: 24000000 description: extclk clock frequency + deprecated: true gpios: maxItems: 1 @@ -80,8 +81,11 @@ examples: sensor@10 { compatible = "samsung,s5k6a3"; reg = <0x10>; - clock-frequency = <24000000>; + clocks = <&camera 1>; + assigned-clocks = <&camera 1>; + assigned-clock-rates = <24000000>; + clock-names = "extclk"; gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; afvdd-supply = <&ldo19_reg>; diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml index 990acf89af8f..484039671cd1 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml @@ -51,6 +51,7 @@ properties: clock-frequency: description: Frequency of the xclk clock in Hz + deprecated: true vdda-supply: description: Analog power supply (2.9V) @@ -100,7 +101,6 @@ required: - reg - clocks - clock-names - - clock-frequency - vdda-supply - vddd-supply - vdddo-supply @@ -125,7 +125,8 @@ examples: clocks = <&gcc 90>; clock-names = "xclk"; - clock-frequency = <37125000>; + assigned-clocks = <&clks 1>; + assigned-clock-rates = <37125000>; vdddo-supply = <&camera_vdddo_1v8>; vdda-supply = <&camera_vdda_2v8>; diff --git a/Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml b/Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml index 3a5ff3f47060..71d63bb9abb5 100644 --- a/Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml +++ b/Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml @@ -209,9 +209,10 @@ examples: svdda-supply = <&cam_io_reg>; svddio-supply = <&ldo19_reg>; afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; clocks = <&camera 1>; clock-names = "extclk"; + assigned-clocks = <&camera 1>; + assigned-clock-rates = <24000000>; gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; port { diff --git a/Documentation/devicetree/bindings/media/samsung,fimc.yaml b/Documentation/devicetree/bindings/media/samsung,fimc.yaml index 7808d61f1fa3..2a54379d9509 100644 --- a/Documentation/devicetree/bindings/media/samsung,fimc.yaml +++ b/Documentation/devicetree/bindings/media/samsung,fimc.yaml @@ -259,10 +259,11 @@ examples: svdda-supply = <&cam_io_reg>; svddio-supply = <&ldo19_reg>; afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; /* CAM_B_CLKOUT */ clocks = <&camera 1>; clock-names = "extclk"; + assigned-clocks = <&camera 1>; + assigned-clock-rates = <24000000>; gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; port { -- cgit v1.2.3 From c7d54dba555aa282d9d1abf8a808621ae20cc6c7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Aug 2025 00:45:10 +0300 Subject: dt-bindings: media: et8ek8: Deprecate clock-frequency property Usage of the clock-frequency property for camera sensors is discouraged in favour of using assigned-clock-rates (and assigned-clock-parents where needed). Drop the property, and update the example accordingly. Signed-off-by: Laurent Pinchart Acked-by: Rob Herring (Arm) Signed-off-by: Sakari Ailus Reviewed-by: Mehdi Djait Signed-off-by: Hans Verkuil --- Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt b/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt index e80d5891b7ed..8d8e40c56872 100644 --- a/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt +++ b/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt @@ -13,9 +13,6 @@ Mandatory properties - reg: I2C address (0x3e, or an alternative address) - vana-supply: Analogue voltage supply (VANA), 2.8 volts - clocks: External clock to the sensor -- clock-frequency: Frequency of the external clock to the sensor. Camera - driver will set this frequency on the external clock. The clock frequency is - a pre-determined frequency known to be suitable to the board. - reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor is in hardware standby mode when the signal is in the low state. @@ -43,8 +40,11 @@ Example compatible = "toshiba,et8ek8"; reg = <0x3e>; vana-supply = <&vaux4>; + clocks = <&isp 0>; - clock-frequency = <9600000>; + assigned-clocks = <&isp 0>; + assigned-clock-rates = <9600000>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ port { csi_cam1: endpoint { -- cgit v1.2.3 From ea501438dcd321b058be91eadee1c67b5bec3c8d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Aug 2025 00:45:11 +0300 Subject: dt-bindings: media: imx258: Make clocks property required The sensor requires an external clock, and drivers need to access the clock to retrieve its frequency in order to configure the sensor. This makes usage of the clocks property mandatory for a system to work properly. Mark the property as required. Signed-off-by: Laurent Pinchart Acked-by: Rob Herring (Arm) Signed-off-by: Sakari Ailus Reviewed-by: Mehdi Djait Signed-off-by: Hans Verkuil --- Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml index 421b935b52bc..d105bd357dbb 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml @@ -81,6 +81,7 @@ properties: required: - compatible - reg + - clocks - port unevaluatedProperties: false -- cgit v1.2.3 From 4e181beb68a67453dadbac89e7440c4a291236dc Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 13 Aug 2025 00:45:12 +0300 Subject: dt-bindings: media: imx274: Make clocks property required The sensor requires an external clock, and drivers need to access the clock to retrieve its frequency in order to configure the sensor. This makes usage of the clocks property mandatory for a system to work properly. Mark the clocks and clock-names properties as required, and update the example accordingly. Signed-off-by: Laurent Pinchart Reviewed-by: Rob Herring (Arm) Signed-off-by: Sakari Ailus Reviewed-by: Mehdi Djait Signed-off-by: Hans Verkuil --- Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml | 4 ++++ Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml | 3 +++ 2 files changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml index b397a730ee94..b06a6e75ba97 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml @@ -46,6 +46,8 @@ properties: required: - compatible - reg + - clocks + - clock-names - port additionalProperties: false @@ -59,6 +61,8 @@ examples: imx274: camera-sensor@1a { compatible = "sony,imx274"; reg = <0x1a>; + clocks = <&imx274_clk>; + clock-names = "inck"; reset-gpios = <&gpio_sensor 0 0>; port { diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml index 4dcbd2b039a5..0539d52de422 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -361,6 +361,9 @@ examples: compatible = "sony,imx274"; reg = <0x1a>; + clocks = <&serializer>; + clock-names = "inck"; + reset-gpios = <&serializer1 0 GPIO_ACTIVE_LOW>; port { -- cgit v1.2.3 From 907cef174cd81053beb54003e79b92f89bcd5d67 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Mon, 1 Sep 2025 13:03:29 +0530 Subject: dt-bindings: media: qcom,sm8550-iris: Update Dikshita Agarwal's email address Replace quic_dikshita@quicinc.com by dikshita.agarwal@oss.qualcomm.com. Signed-off-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue [bod: Fixed patch title] Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil --- Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index c79bf2101812..0d630e620b09 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -8,7 +8,7 @@ title: Qualcomm iris video encode and decode accelerators maintainers: - Vikash Garodia - - Dikshita Agarwal + - Dikshita Agarwal description: The iris video processing unit is a video encode and decode accelerator -- cgit v1.2.3 From 088ee3df91ba7058394e92d6daf9bab40c418387 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 4 Jul 2025 15:38:41 +0200 Subject: dt-bindings: media: qcom,sm8550-iris: Add X1E80100 compatible Iris in X1E80100 is pretty much identical to SM8550. We can use the same firmware image and the same definitions in the driver, so just add qcom,x1e80100-iris to the existing list with qcom,sm8550-iris as fallback compatible. Signed-off-by: Stephan Gerhold Reviewed-by: Vikash Garodia Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil --- Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index 0d630e620b09..170eeb5a4222 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -20,6 +20,7 @@ properties: - items: - enum: - qcom,sa8775p-iris + - qcom,x1e80100-iris - const: qcom,sm8550-iris - enum: - qcom,qcs8300-iris -- cgit v1.2.3 From 49b5feb5214d1fcd79c44ec3c7be17dd48b761e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Aug 2025 15:37:38 +0200 Subject: dt-bindings: media: qcom,sm8550-iris: Add SM8750 video codec Add binding for Qualcom SM8750 Iris video codec, which comes with significantly different powering up sequence than previous SM8650, thus different clocks and resets. For consistency keep existing clock and clock-names naming, so the list shares common part. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski [bod: re-ordered patch title to dt-bindings: media] Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil --- .../bindings/media/qcom,sm8750-iris.yaml | 186 +++++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml new file mode 100644 index 000000000000..c9a0fcafe53f --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8750-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 SoC Iris video encoder and decoder + +maintainers: + - Krzysztof Kozlowski + +description: + The Iris video processing unit on Qualcomm SM8750 SoC is a video encode and + decode accelerator. + +properties: + compatible: + enum: + - qcom,sm8750-iris + + clocks: + maxItems: 6 + + clock-names: + items: + - const: iface # AXI0 + - const: core + - const: vcodec0_core + - const: iface1 # AXI1 + - const: core_freerun + - const: vcodec0_core_freerun + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + iommus: + maxItems: 2 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 4 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + + resets: + maxItems: 4 + + reset-names: + items: + - const: bus0 + - const: bus1 + - const: core + - const: vcodec0_core + +required: + - compatible + - dma-coherent + - interconnects + - interconnect-names + - iommus + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + video-codec@aa00000 { + compatible = "qcom,sm8750-iris"; + reg = <0x0aa00000 0xf0000>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc_mvs0c_clk>, + <&videocc_mvs0_clk>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc_mvs0c_freerun_clk>, + <&videocc_mvs0_freerun_clk>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun"; + + dma-coherent; + iommus = <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = ; + + operating-points-v2 = <&iris_opp_table>; + + memory-region = <&video_mem>; + + power-domains = <&videocc_mvs0c_gdsc>, + <&videocc_mvs0_gdsc>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc_mvs0c_freerun_clk_ares>, + <&videocc_mvs0_freerun_clk_ares>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; -- cgit v1.2.3 From 6d3926a237b68e3bfd3068553e6c3fa3fed1ea1b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 23 Aug 2025 17:53:50 +0200 Subject: dt-bindings: media: qcom,sm8550-iris: Do not reference legacy venus properties The Qualcomm SoC Iris video codec is an evolution of previous Venus and it comes with its own Iris Linux drivers. These new drivers were accepted under condition they actually improve state of afairs, instead of duplicating old, legacy solutions. Unfortunately binding still references common parts of Venus without actual need and benefit. For example Iris does not use fake "video-firmware" device node (fake because there is no actual device underlying it and it was added only to work around some Linux issues with IOMMU mappings). Stop referencing venus-common schema in the new Qualcomm Iris bindings and move all necessary properties, except unused "video-firmware" (no driver usage, no DTS). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring (Arm) Reviewed-by: Vikash Garodia Reviewed-by: Bryan O'Donoghue [bod: Changed title order to dt-bindings: media] Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil --- .../devicetree/bindings/media/qcom,sm8550-iris.yaml | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index 170eeb5a4222..9c4b760508b5 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -27,6 +27,9 @@ properties: - qcom,sm8550-iris - qcom,sm8650-iris + reg: + maxItems: 1 + power-domains: maxItems: 4 @@ -46,6 +49,12 @@ properties: - const: core - const: vcodec0_core + firmware-name: + maxItems: 1 + + interrupts: + maxItems: 1 + interconnects: maxItems: 2 @@ -70,6 +79,9 @@ properties: dma-coherent: true + memory-region: + maxItems: 1 + operating-points-v2: true opp-table: @@ -86,7 +98,6 @@ required: - dma-coherent allOf: - - $ref: qcom,venus-common.yaml# - if: properties: compatible: -- cgit v1.2.3 From cba308979b012664c7fe7c5baa818fcb68e86363 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 8 Jul 2025 10:32:21 +0200 Subject: dt-bindings: media: Add qcom,qcm2290-camss Add bindings for qcom,qcm2290-camss in order to support the camera subsystem found in the Qualcomm Robotics RB1 Platform (QRB2210). Signed-off-by: Loic Poulain Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski [bod: reordered patch title to dt-bindings: media] Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil --- .../bindings/media/qcom,qcm2290-camss.yaml | 243 +++++++++++++++++++++ 1 file changed, 243 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml new file mode 100644 index 000000000000..391d0f6f67ef --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml @@ -0,0 +1,243 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcm2290-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCM2290 Camera Subsystem (CAMSS) + +maintainers: + - Loic Poulain + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,qcm2290-camss + + reg: + maxItems: 9 + + reg-names: + items: + - const: top + - const: csid0 + - const: csid1 + - const: csiphy0 + - const: csiphy1 + - const: csitpg0 + - const: csitpg1 + - const: vfe0 + - const: vfe1 + + clocks: + maxItems: 15 + + clock-names: + items: + - const: ahb + - const: axi + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: csi0 + - const: csi1 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: top_ahb + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe1 + - const: vfe1_cphy_rx + + interrupts: + maxItems: 8 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csiphy0 + - const: csiphy1 + - const: csitpg0 + - const: csitpg1 + - const: vfe0 + - const: vfe1 + + interconnects: + maxItems: 3 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + + iommus: + maxItems: 4 + + power-domains: + items: + - description: GDSC CAMSS Block, Global Distributed Switch Controller. + + vdd-csiphy-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSI PHYs. + + vdd-csiphy-1p8-supply: + description: + Phandle to 1.8V regulator supply to CSI PHYs pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - vdd-csiphy-1p2-supply + - vdd-csiphy-1p8-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@5c6e000 { + compatible = "qcom,qcm2290-camss"; + + reg = <0x0 0x5c11000 0x0 0x1000>, + <0x0 0x5c6e000 0x0 0x1000>, + <0x0 0x5c75000 0x0 0x1000>, + <0x0 0x5c52000 0x0 0x1000>, + <0x0 0x5c53000 0x0 0x1000>, + <0x0 0x5c66000 0x0 0x400>, + <0x0 0x5c68000 0x0 0x400>, + <0x0 0x5c6f000 0x0 0x4000>, + <0x0 0x5c76000 0x0 0x4000>; + reg-names = "top", + "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; + clock-names = "ahb", + "axi", + "camnoc_nrt_axi", + "camnoc_rt_axi", + "csi0", + "csi1", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "top_ahb", + "vfe0", + "vfe0_cphy_rx", + "vfe1", + "vfe1_cphy_rx"; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, + <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc"; + + iommus = <&apps_smmu 0x400 0x0>, + <&apps_smmu 0x800 0x0>, + <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>; + + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + + vdd-csiphy-1p2-supply = <&pm4125_l5>; + vdd-csiphy-1p8-supply = <&pm4125_l13>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; -- cgit v1.2.3 From 8dd22e90331d64bd15adc598a8d41fee2ccf93da Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Thu, 14 Aug 2025 15:46:09 +0530 Subject: media: dt-bindings: Add qcom,sa8775p-camss compatible Add the compatible string "qcom,sa8775p-camss" to support the Camera Subsystem (CAMSS) on the Qualcomm lemans platform. The Lemans(SA8775P) platform provides: - 2 x VFE (version 690), each with 3 RDI - 5 x VFE Lite (version 690), each with 6 RDI - 2 x CSID (version 690) - 5 x CSID Lite (version 690) - 4 x CSIPHY (version 690) - 3 x TPG Lemans is the first Qualcomm SoC to introduce a CSIPHY-based Test Pattern Generator (TPG). Co-developed-by: Wenmeng Liu Signed-off-by: Wenmeng Liu Signed-off-by: Vikram Sharma Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil --- .../bindings/media/qcom,sa8775p-camss.yaml | 361 +++++++++++++++++++++ 1 file changed, 361 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml new file mode 100644 index 000000000000..019caa2b09c3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml @@ -0,0 +1,361 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sa8775p-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8775P CAMSS ISP + +maintainers: + - Vikram Sharma + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sa8775p-camss + + reg: + maxItems: 22 + + reg-names: + items: + - const: csid_wrapper + - const: csid0 + - const: csid1 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_lite2 + - const: csid_lite3 + - const: csid_lite4 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: tpg0 + - const: tpg1 + - const: tpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe_lite2 + - const: vfe_lite3 + - const: vfe_lite4 + + clocks: + maxItems: 28 + + clock-names: + items: + - const: camnoc_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb_clk + - const: cpas_vfe_lite + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: icp_ahb + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 21 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_lite2 + - const: csid_lite3 + - const: csid_lite4 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: tpg0 + - const: tpg1 + - const: tpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe_lite2 + - const: vfe_lite3 + - const: vfe_lite4 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 0-3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@ac78000 { + compatible = "qcom,sa8775p-camss"; + + reg = <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0x0f00>, + <0x0 0xac7c000 0x0 0x0f00>, + <0x0 0xac84000 0x0 0x0f00>, + <0x0 0xac88000 0x0 0x0f00>, + <0x0 0xac8c000 0x0 0x0f00>, + <0x0 0xac90000 0x0 0x0f00>, + <0x0 0xac94000 0x0 0x0f00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xaca2000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x0400>, + <0x0 0xacad000 0x0 0x0400>, + <0x0 0xacae000 0x0 0x0400>, + <0x0 0xac4d000 0x0 0xd000>, + <0x0 0xac5a000 0x0 0xd000>, + <0x0 0xac85000 0x0 0x0d00>, + <0x0 0xac89000 0x0 0x0d00>, + <0x0 0xac8d000 0x0 0x0d00>, + <0x0 0xac91000 0x0 0x0d00>, + <0x0 0xac95000 0x0 0x0d00>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x3400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + vdda-phy-supply = <&vreg_l4a_0p88>; + vdda-pll-supply = <&vreg_l1c_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; -- cgit v1.2.3 From 634a2958fae30b9ea2c603e7b12c2729407c8292 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Wed, 13 Aug 2025 11:07:18 +0530 Subject: media: dt-bindings: Add qcom,qcs8300-camss compatible Add the compatible string "qcom,qcs8300-camss" to support the Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. The QCS8300 platform provides: - 2 x VFE (version 690), each with 3 RDI - 5 x VFE Lite (version 690), each with 6 RDI - 2 x CSID (version 690) - 5 x CSID Lite (version 690) - 3 x CSIPHY (version 690) - 3 x TPG Signed-off-by: Vikram Sharma Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Signed-off-by: Bryan O'Donoghue Signed-off-by: Hans Verkuil --- .../bindings/media/qcom,qcs8300-camss.yaml | 336 +++++++++++++++++++++ 1 file changed, 336 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml new file mode 100644 index 000000000000..80a4540a22dc --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml @@ -0,0 +1,336 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS8300 CAMSS ISP + +maintainers: + - Vikram Sharma + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,qcs8300-camss + + reg: + maxItems: 21 + + reg-names: + items: + - const: csid_wrapper + - const: csid0 + - const: csid1 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_lite2 + - const: csid_lite3 + - const: csid_lite4 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: tpg0 + - const: tpg1 + - const: tpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe_lite2 + - const: vfe_lite3 + - const: vfe_lite4 + + clocks: + maxItems: 26 + + clock-names: + items: + - const: camnoc_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb_clk + - const: cpas_vfe_lite + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: icp_ahb + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 20 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_lite2 + - const: csid_lite3 + - const: csid_lite4 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: tpg0 + - const: tpg1 + - const: tpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe_lite2 + - const: vfe_lite3 + - const: vfe_lite4 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-2]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 0-2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@ac78000 { + compatible = "qcom,qcs8300-camss"; + + reg = <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0x0f00>, + <0x0 0xac7c000 0x0 0x0f00>, + <0x0 0xac84000 0x0 0x0f00>, + <0x0 0xac88000 0x0 0x0f00>, + <0x0 0xac8c000 0x0 0x0f00>, + <0x0 0xac90000 0x0 0x0f00>, + <0x0 0xac94000 0x0 0x0f00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x0400>, + <0x0 0xacad000 0x0 0x0400>, + <0x0 0xacae000 0x0 0x0400>, + <0x0 0xac4d000 0x0 0xd000>, + <0x0 0xac60000 0x0 0xd000>, + <0x0 0xac85000 0x0 0x0d00>, + <0x0 0xac89000 0x0 0x0d00>, + <0x0 0xac8d000 0x0 0x0d00>, + <0x0 0xac91000 0x0 0x0d00>, + <0x0 0xac95000 0x0 0x0d00>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x2400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; -- cgit v1.2.3 From d5ad57fc428c1e44335d25c822eb89645f425f32 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Sep 2025 16:03:32 +0200 Subject: dt-bindings: input: qcom,pm8941-pwrkey: Fix formatting of descriptions Property descriptions should indent with two spaces and they do not need to preserve formatting. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250909140331.69756-2-krzysztof.kozlowski@linaro.org Signed-off-by: Dmitry Torokhov --- .../bindings/input/qcom,pm8941-pwrkey.yaml | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml index 62314a5fdce5..72006a14fd41 100644 --- a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml +++ b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml @@ -25,23 +25,22 @@ properties: maxItems: 1 debounce: - description: | - Time in microseconds that key must be pressed or - released for state change interrupt to trigger. + description: + Time in microseconds that key must be pressed or released for state + change interrupt to trigger. $ref: /schemas/types.yaml#/definitions/uint32 bias-pull-up: - description: | - Presence of this property indicates that the KPDPWR_N - pin should be configured for pull up. + description: + Presence of this property indicates that the KPDPWR_N pin should be + configured for pull up. $ref: /schemas/types.yaml#/definitions/flag linux,code: - description: | - The input key-code associated with the power key. - Use the linux event codes defined in - include/dt-bindings/input/linux-event-codes.h - When property is omitted KEY_POWER is assumed. + description: + The input key-code associated with the power key. Use the linux event + codes defined in include/dt-bindings/input/linux-event-codes.h. + When property is omitted KEY_POWER is assumed. required: - compatible -- cgit v1.2.3 From 818045d1658fd4ceec06fb6efa62ed9c5b7f23cf Mon Sep 17 00:00:00 2001 From: Eric Gonçalves Date: Fri, 5 Sep 2025 19:09:30 +0000 Subject: dt-bindings: arm: qcom: document x1q board binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add binding for the Samsung Galaxy S20 board, codenamed X1Q, which is based on the Qualcomm Snapdragon 865 SoC. Signed-off-by: Eric Gonçalves Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250905190931.27481-3-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2698ba87cd93..cf49dd0000e0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -984,6 +984,7 @@ properties: - qcom,sm8250-hdk - qcom,sm8250-mtp - samsung,r8q + - samsung,x1q - sony,pdx203-generic - sony,pdx206-generic - xiaomi,elish -- cgit v1.2.3 From 87f8ae1d0faebbaaf163ecfd1321432d85ada178 Mon Sep 17 00:00:00 2001 From: Valentina Fernandez Date: Mon, 8 Sep 2025 12:57:28 +0100 Subject: dt-bindings: riscv: microchip: document icicle kit with production device With the introduction of the Icicle Kit using the production MPFS250T device, it's necessary to distinguish it from the engineering sample (-es) variant. Engineering samples cannot write to flash from the MSS, as noted in the PolarFire SoC FPGA ES errata. Add specific compatibles for the Icicle Kit with Production device (MPFS250T) and Icicle Kit with Engineering Sample (MPFS250T_ES). The icicle kit reference designs in the v2025.07 release include the Mi-V IHC IP v2, used to send/receive data between clusters when using Asymmetric Multiprocessing (AMP) mode. In reference design releases prior to v2025.07, the MI-V IHC subsystem was included as a proof of concept in the design prior to becoming an IP available in the Libero catalog. Among other improvements, the new Mi-V IHC IP v2 includes some changes to the register map. For this reason, make use of a new reference design compatible to denote that v2025.07 reference design releases are not backwards compatible. Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 78ce76ae1b6d..8ddc5c02973e 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -18,10 +18,18 @@ properties: const: '/' compatible: oneOf: + - items: + - const: microchip,mpfs-icicle-prod-reference-rtl-v2507 + - const: microchip,mpfs-icicle-kit-prod + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs-prod + - const: microchip,mpfs + - items: - enum: - microchip,mpfs-icicle-reference-rtlv2203 - microchip,mpfs-icicle-reference-rtlv2210 + - microchip,mpfs-icicle-es-reference-rtl-v2507 - const: microchip,mpfs-icicle-kit - const: microchip,mpfs -- cgit v1.2.3 From d6d9d9be2aa407c10911967a3115654b21a5c23d Mon Sep 17 00:00:00 2001 From: Valentina Fernandez Date: Mon, 8 Sep 2025 12:57:31 +0100 Subject: dt-bindings: riscv: microchip: document Discovery Kit The Discovery Kit (MPFS-DISCO-KIT) is a development board featuring a Microchip PolarFire SoC MPFS095T. Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 8ddc5c02973e..381d6eb6672e 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -33,6 +33,11 @@ properties: - const: microchip,mpfs-icicle-kit - const: microchip,mpfs + - items: + - const: microchip,mpfs-disco-kit-reference-rtl-v2507 + - const: microchip,mpfs-disco-kit + - const: microchip,mpfs + - items: - enum: - aldec,tysom-m-mpfs250t-rev2 -- cgit v1.2.3 From 3ef9c995fa51a90b08b0cc8d2951acb53c38936c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 4 Sep 2025 16:24:01 +0200 Subject: docs: dt: writing-schema: Describe defining properties in top-level Document established Devicetree bindings maintainers review practice: Properties having differences per each device in the binding, e.g. different constraints for lists or different allowed values, should still be defined in top-level 'properties' section and only customized in 'if:then:'. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250904142400.179955-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/writing-schema.rst | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index fcd4726f8df4..05c34248e544 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -165,6 +165,14 @@ The YAML Devicetree format also makes all string values an array and scalar values a matrix (in order to define groupings) even when only a single value is present. Single entries in schemas are fixed up to match this encoding. +When bindings cover multiple similar devices that differ in some properties, +those properties should be constrained for each device. This usually means: + + * In top level 'properties' define the property with the broadest constraints. + * In 'if:then:' blocks, further narrow the constraints for those properties. + * Do not define the properties within an 'if:then:' block (note that + 'additionalItems' also won't allow that). + Coding style ------------ -- cgit v1.2.3 From b132e9745e8cd5d383253dc3f21775d6cdea1fd8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 7 Sep 2025 00:48:52 +0300 Subject: dt-bindings: dp-connector: describe separate DP and AUX lines In some cases it's reasonable to describe DP lanes and AUX signal lines separately in the DT. One of the typical reasons is if the source of DP signals can support either USB-C or DP connections. In such a case the transmitter of DP signals have separate ports: one for SS lanes and another one for SBU / AUX signals. Instead of leaving AUX signals from the controller unconnected, add an option to the DT schema to AUX signal lines separately from the main link lanes. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250907-dp-conenctor-sbu-v1-1-de79c0fcd64d@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) --- .../bindings/display/connector/dp-connector.yaml | 52 +++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/connector/dp-connector.yaml b/Documentation/devicetree/bindings/display/connector/dp-connector.yaml index 22792a79e7ce..1f2b449dc910 100644 --- a/Documentation/devicetree/bindings/display/connector/dp-connector.yaml +++ b/Documentation/devicetree/bindings/display/connector/dp-connector.yaml @@ -31,10 +31,32 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Connection to controller providing DP signals + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: OF graph representation of signales routed to DP connector + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to controller providing DP signals + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to controller providing AUX signals + + required: + - port@0 + - port@1 + required: - compatible - type - - port + +oneOf: + - required: + - port + - required: + - ports additionalProperties: false @@ -52,4 +74,32 @@ examples: }; }; + - | + /* DP connecttor being driven by the USB+DP combo PHY */ + connector { + compatible = "dp-connector"; + label = "dp0"; + type = "full-size"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&phy_ss_out>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&phy_sbu_out>; + }; + }; + }; + }; ... -- cgit v1.2.3 From 2f572b0def6e90e4a6cf90f3a8cb11d4def7b637 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 18 Jul 2025 17:47:22 +0800 Subject: dt-bindings: firmware: imx95-scmi: Allow linux,code for protocol@81 BBM protocol supports a single power button, supported by driver imx-sm-bbm-key.c. By default this is KEY_POWER, but can also be overwritten using linux,code. Add a reference to this schema and add linux,code as a supported property. Reviewed-by: Rob Herring (Arm) Signed-off-by: Alexander Stein Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml index 2bda2e0e1369..7a5a02da2719 100644 --- a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml @@ -24,13 +24,19 @@ properties: const: 0x80 protocol@81: - $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' - unevaluatedProperties: false + type: object + allOf: + - $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + - $ref: /schemas/input/input.yaml# + additionalProperties: false properties: reg: const: 0x81 + linux,code: + default: 116 # KEY_POWER + protocol@82: description: SCMI CPU Protocol which allows an agent to start or stop a CPU. It is -- cgit v1.2.3 From 4a2bab7ccceb14b48e86794b87104248c75aa587 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Thu, 4 Sep 2025 21:07:08 +0800 Subject: dt-bindings: mtd: loongson,ls1b-nand-controller: Document the Loongson-2K0500 NAND controller Add new compatible for the Loongson-2K NAND controller used for Loongson-2K0500 SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Binbin Zhou Signed-off-by: Miquel Raynal --- .../devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml index a09e92e416c4..4ec2b5d1e89d 100644 --- a/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml @@ -4,13 +4,14 @@ $id: http://devicetree.org/schemas/mtd/loongson,ls1b-nand-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Loongson-1 NAND Controller +title: Loongson NAND Controller maintainers: - Keguang Zhang + - Binbin Zhou description: - The Loongson-1 NAND controller abstracts all supported operations, + The Loongson NAND controller abstracts all supported operations, meaning it does not support low-level access to raw NAND flash chips. Moreover, the controller is paired with the DMA engine to perform READ and PROGRAM functions. @@ -24,6 +25,7 @@ properties: - enum: - loongson,ls1b-nand-controller - loongson,ls1c-nand-controller + - loongson,ls2k0500-nand-controller - items: - enum: - loongson,ls1a-nand-controller -- cgit v1.2.3 From 0b1ae6480c3be58ad31afe757cbf1069ae072bb1 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Thu, 4 Sep 2025 21:07:10 +0800 Subject: dt-bindings: mtd: loongson,ls1b-nand-controller: Document the Loongson-2K1000 NAND controller Add new compatible for the Loongson-2K NAND controller used for Loongson-2K1000 SoC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Binbin Zhou Signed-off-by: Miquel Raynal --- .../mtd/loongson,ls1b-nand-controller.yaml | 50 +++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml index 4ec2b5d1e89d..cf85d0cede00 100644 --- a/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml @@ -26,18 +26,22 @@ properties: - loongson,ls1b-nand-controller - loongson,ls1c-nand-controller - loongson,ls2k0500-nand-controller + - loongson,ls2k1000-nand-controller - items: - enum: - loongson,ls1a-nand-controller - const: loongson,ls1b-nand-controller reg: - maxItems: 2 + minItems: 2 + maxItems: 3 reg-names: + minItems: 2 items: - const: nand - const: nand-dma + - const: dma-config dmas: maxItems: 1 @@ -54,6 +58,27 @@ required: unevaluatedProperties: false +if: + properties: + compatible: + contains: + enum: + - loongson,ls2k1000-nand-controller + +then: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + +else: + properties: + reg: + maxItems: 2 + reg-names: + maxItems: 2 + examples: - | nand-controller@1fe78000 { @@ -72,3 +97,26 @@ examples: nand-ecc-algo = "hamming"; }; }; + + - | + nand-controller@1fe26000 { + compatible = "loongson,ls2k1000-nand-controller"; + reg = <0x1fe26000 0x24>, + <0x1fe26040 0x4>, + <0x1fe00438 0x8>; + reg-names = "nand", "nand-dma", "dma-config"; + dmas = <&apbdma0 0>; + dma-names = "rxtx"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + label = "ls2k1000-nand"; + nand-use-soft-ecc-engine; + nand-ecc-algo = "bch"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + }; + }; -- cgit v1.2.3 From 550faad18505aac40a1551a5b467e0a63bf2d639 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Sat, 6 Sep 2025 15:16:52 -0500 Subject: dt-bindings: memory: tegra210: emc: Document OPP table and interconnect These are needed for dynamic frequency scaling of the EMC controller. Signed-off-by: Aaron Kling Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra210-emc.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml index bc8477e7ab19..4e4fb4acd7f9 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml @@ -33,6 +33,9 @@ properties: items: - description: EMC general interrupt + "#interconnect-cells": + const: 0 + memory-region: maxItems: 1 description: @@ -44,6 +47,11 @@ properties: description: phandle of the memory controller node + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + required: - compatible - reg @@ -79,4 +87,7 @@ examples: interrupts = ; memory-region = <&emc_table>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + + #interconnect-cells = <0>; }; -- cgit v1.2.3 From 930b6fe1a50c7ba69608230322614c87ea3dd35e Mon Sep 17 00:00:00 2001 From: Mateusz Koza Date: Mon, 8 Sep 2025 15:05:35 +0200 Subject: dt-bindings: arm: mediatek: Add grinn,genio-700-sbc Add device tree bindings support for the Grinn GenioSBC-700, a single-board computer based on the MediaTek Genio 700 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley Signed-off-by: Mateusz Koza Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250908130620.2309399-3-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 19ed9448c9c2..448241939a75 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -436,6 +436,7 @@ properties: - const: mediatek,mt8188 - items: - enum: + - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 -- cgit v1.2.3 From 12a565af705542c4380e95f4e3a505a2c25ad754 Mon Sep 17 00:00:00 2001 From: Mateusz Koza Date: Mon, 8 Sep 2025 15:05:37 +0200 Subject: dt-bindings: arm: mediatek: Add grinn,genio-510-sbc Add device tree bindings support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley Signed-off-by: Mateusz Koza Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250908130620.2309399-5-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 448241939a75..f04277873694 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -431,6 +431,7 @@ properties: - const: mediatek,mt8365 - items: - enum: + - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 -- cgit v1.2.3 From 350027a3ef3f30f68a06d87e72f9bcc0dba49fb8 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Mon, 8 Sep 2025 15:28:45 +0300 Subject: dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Add bindings for pin controller in SDM660 Low Power Audio SubSystem (LPASS). Reviewed-by: Krzysztof Kozlowski Co-developed-by: Richard Acayan Signed-off-by: Richard Acayan Signed-off-by: Nickolay Goppen Signed-off-by: Linus Walleij --- .../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml | 109 +++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..409e5a4d4da9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660 SoC LPASS LPI TLMM + +maintainers: + - Nickolay Goppen + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC. + +properties: + compatible: + const: qcom,sdm660-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm660-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm660-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm660-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-2][0-9]|3[0-1])$" + + function: + enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, + mclk0, pdm_tx, pdm_clk, pdm_rx, pdm_sync ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@15070000 { + compatible = "qcom,sdm660-lpass-lpi-pinctrl"; + reg = <0x15070000 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_pdm_default: cdc-pdm-default-state { + clk-pins { + pins = "gpio18"; + function = "pdm_clk"; + drive-strength = <8>; + output-high; + }; + + sync-pins{ + pins = "gpio19"; + function = "pdm_sync"; + drive-strength = <4>; + output-high; + }; + + tx-pins { + pins = "gpio20"; + function = "pdm_tx"; + drive-strength = <8>; + }; + + rx-pins { + pins = "gpio21", "gpio23", "gpio25"; + function = "pdm_rx"; + drive-strength = <4>; + output-high; + }; + }; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <8>; + }; + }; -- cgit v1.2.3 From cdb2511bf3925ce095c31e1647c12086d34f9cc2 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 8 Jul 2025 14:30:36 +0800 Subject: dt-bindings: phy: Add Sophgo CV1800 USB phy The USB phy of Sophgo CV18XX series SoC needs to sense a pin called "VBUS_DET" to get the right operation mode. If this pin is not connected, it only supports setting the mode manually. Add USB phy bindings for Sophgo CV18XX/SG200X series SoC. Signed-off-by: Inochi Amaoto Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250708063038.497473-2-inochiama@gmail.com Signed-off-by: Vinod Koul --- .../bindings/phy/sophgo,cv1800b-usb2-phy.yaml | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/sophgo,cv1800b-usb2-phy.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/sophgo,cv1800b-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/sophgo,cv1800b-usb2-phy.yaml new file mode 100644 index 000000000000..2ff8f85d0282 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/sophgo,cv1800b-usb2-phy.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/sophgo,cv1800b-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV18XX/SG200X USB 2.0 PHY + +maintainers: + - Inochi Amaoto + +properties: + compatible: + const: sophgo,cv1800b-usb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PHY app clock + - description: PHY stb clock + - description: PHY lpm clock + + clock-names: + items: + - const: app + - const: stb + - const: lpm + + resets: + maxItems: 1 + +required: + - compatible + - "#phy-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + phy@48 { + compatible = "sophgo,cv1800b-usb2-phy"; + reg = <0x48 0x4>; + #phy-cells = <0>; + clocks = <&clk 93>, <&clk 94>, <&clk 95>; + clock-names = "app", "stb", "lpm"; + resets = <&rst 58>; + }; -- cgit v1.2.3 From c254815b02673cc77a84103c4c0d6197bd90c0ef Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 3 Sep 2025 19:04:50 +0200 Subject: dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required There are variants of the Rockchip Innosilicon CSI DPHY (e.g., the RK3568 variant) that are powered on by default as they are part of the ALIVE power domain. Remove 'power-domains' from the required properties in order to avoid false positives. Fixes: 22c8e0a69b7f ("dt-bindings: phy: add compatible for rk356x to rockchip-inno-csi-dphy") Cc: stable@kernel.org Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-2-a4f340a7f0cf@collabora.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 5ac994b3c0aa..b304bc5a08c4 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -57,11 +57,24 @@ required: - clocks - clock-names - '#phy-cells' - - power-domains - resets - reset-names - rockchip,grf +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + then: + required: + - power-domains + additionalProperties: false examples: -- cgit v1.2.3 From 5072b8e98eef4685a5a9a8bae56072cb65a2ef69 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 3 Sep 2025 19:04:51 +0200 Subject: dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines. Add the variant and allow for the additional reset. While at it, fix the description of the first reset in order to avoid confusion. Signed-off-by: Michael Riesch Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-3-a4f340a7f0cf@collabora.com Signed-off-by: Vinod Koul --- .../bindings/phy/rockchip-inno-csi-dphy.yaml | 50 +++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index b304bc5a08c4..03950b3cad08 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -21,6 +21,7 @@ properties: - rockchip,rk3326-csi-dphy - rockchip,rk3368-csi-dphy - rockchip,rk3568-csi-dphy + - rockchip,rk3588-csi-dphy reg: maxItems: 1 @@ -40,11 +41,15 @@ properties: resets: items: - - description: exclusive PHY reset line + - description: APB reset line + - description: PHY reset line + minItems: 1 reset-names: items: - const: apb + - const: phy + minItems: 1 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -74,6 +79,30 @@ allOf: then: required: - power-domains + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-csi-dphy + - rockchip,rk1808-csi-dphy + - rockchip,rk3326-csi-dphy + - rockchip,rk3368-csi-dphy + - rockchip,rk3568-csi-dphy + then: + properties: + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + else: + properties: + resets: + minItems: 2 + + reset-names: + minItems: 2 additionalProperties: false @@ -91,3 +120,22 @@ examples: reset-names = "apb"; rockchip,grf = <&grf>; }; + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@fedc0000 { + compatible = "rockchip,rk3588-csi-dphy"; + reg = <0x0 0xfedc0000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY0>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names = "apb", "phy"; + rockchip,grf = <&csidphy0_grf>; + }; + }; -- cgit v1.2.3 From 4a09265c42350e6494d793191e6dbe59a4dddbe4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 18:48:33 +0200 Subject: dt-bindings: iio: adc: samsung,exynos: Drop S3C2410 Samsung S3C24xx family of SoCs was removed the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250830-s3c-cleanup-adc-v2-4-4f8299343d32@linaro.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml | 4 ---- 1 file changed, 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml index 8069e99ddac8..73d7ba0fda1d 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml @@ -18,10 +18,6 @@ properties: - samsung,exynos3250-adc - samsung,exynos4212-adc # Exynos4212 and Exynos4412 - samsung,exynos7-adc - - samsung,s3c2410-adc - - samsung,s3c2416-adc - - samsung,s3c2440-adc - - samsung,s3c2443-adc - samsung,s3c6410-adc - samsung,s5pv210-adc - items: -- cgit v1.2.3 From 0f2aeee58425faaa3117944711f8b41f8b42b5da Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 18:48:34 +0200 Subject: dt-bindings: iio: adc: samsung,exynos: Drop touchscreen support With last user of touchscreen via ADC (S3C24xx SoC) gone, drop the unused has-touchscreen property and optional touchscreen interrupt for samsung,s3c6410-adc. The samsung,s5pv210-adc is the only platform having two interrupts, so add a constrain for that. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250830-s3c-cleanup-adc-v2-5-4f8299343d32@linaro.org Signed-off-by: Jonathan Cameron --- .../bindings/iio/adc/samsung,exynos-adc.yaml | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml index 73d7ba0fda1d..def879f6ed20 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml @@ -42,8 +42,6 @@ properties: maxItems: 2 interrupts: - description: - ADC interrupt followed by optional touchscreen interrupt. minItems: 1 maxItems: 2 @@ -58,11 +56,6 @@ properties: Phandle to the PMU system controller node (to access the ADC_PHY register on Exynos3250/4x12/5250/5420/5800). - has-touchscreen: - description: - If present, indicates that a touchscreen is connected and usable. - type: boolean - required: - compatible - reg @@ -114,13 +107,20 @@ allOf: - const: adc - if: - required: - - has-touchscreen + properties: + compatible: + contains: + const: samsung,s5pv210-adc then: properties: interrupts: - minItems: 2 - maxItems: 2 + items: + - description: main (ADC) + - description: pending (PENDN) + else: + properties: + interrupts: + maxItems: 1 examples: - | -- cgit v1.2.3 From 8efd9d976652371ada359e717e0bf72ab453a5cf Mon Sep 17 00:00:00 2001 From: Dixit Parmar Date: Sat, 6 Sep 2025 14:07:56 +0530 Subject: dt-bindings: iio: magnetometer: Infineon TLV493D 3D Magnetic sensor Document the bindings for Infineon TLV493D Low-Power 3D Magnetic Sensor controlled by I2C interface. Main applications includes joysticks, control elements (white goods, multifunction knops), or electric meters (anti- tampering). Drop duplicate entry for infineon,tlv493d from trivial-devices.yaml as its documented in this separate dt-binding file now. Datasheet: https://www.infineon.com/assets/row/public/documents/24/49/infineon-tlv493d-a1b6-datasheet-en.pdf Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dixit Parmar Link: https://patch.msgid.link/20250906-tlv493d-sensor-v6_16-rc5-v6-1-b1a62d968353@gmail.com Signed-off-by: Jonathan Cameron --- .../iio/magnetometer/infineon,tlv493d-a1b6.yaml | 45 ++++++++++++++++++++++ .../devicetree/bindings/trivial-devices.yaml | 2 - MAINTAINERS | 7 ++++ 3 files changed, 52 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/magnetometer/infineon,tlv493d-a1b6.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/magnetometer/infineon,tlv493d-a1b6.yaml b/Documentation/devicetree/bindings/iio/magnetometer/infineon,tlv493d-a1b6.yaml new file mode 100644 index 000000000000..dd23a9370a71 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/infineon,tlv493d-a1b6.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/infineon,tlv493d-a1b6.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Infineon Technologies TLV493D Low-Power 3D Magnetic Sensor + +maintainers: + - Dixit Parmar + +properties: + $nodename: + pattern: '^magnetometer@[0-9a-f]+$' + + compatible: + const: infineon,tlv493d-a1b6 + + reg: + maxItems: 1 + + vdd-supply: + description: 2.8V to 3.5V VDD supply + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + magnetometer@5e { + compatible = "infineon,tlv493d-a1b6"; + reg = <0x5e>; + vdd-supply = <&hall_vcc>; + }; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index f3dd18681aa6..7656d8569766 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -133,8 +133,6 @@ properties: - infineon,ir36021 # Infineon IRPS5401 Voltage Regulator (PMIC) - infineon,irps5401 - # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor - - infineon,tlv493d-a1b6 # Infineon Hot-swap controller xdp710 - infineon,xdp710 # Infineon Multi-phase Digital VR Controller xdpe11280 diff --git a/MAINTAINERS b/MAINTAINERS index af1c8d2bfb3d..0d36fbaff145 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12008,6 +12008,13 @@ S: Maintained F: Documentation/devicetree/bindings/sound/infineon,peb2466.yaml F: sound/soc/codecs/peb2466.c +INFINEON TLV493D Driver +M: Dixit Parmar +L: linux-iio@vger.kernel.org +S: Maintained +W: https://www.infineon.com/part/TLV493D-A1B6 +F: Documentation/devicetree/bindings/iio/magnetometer/infineon,tlv493d-a1b6.yaml + INFINIBAND SUBSYSTEM M: Jason Gunthorpe M: Leon Romanovsky -- cgit v1.2.3 From b947d4edfc4fc23a912b0ba160f8af3543b0283b Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Fri, 5 Sep 2025 08:55:02 +0200 Subject: dt-bindings: iio: afe: current-sense-amplifier: Add io-channel-cells The current-sense-amplifier is an IIO provider thus can be referenced by IIO consumers (via "io-channels" property in consumer device node). Such provider is required to describe number of cells used in phandle lookup with "io-channel-cells" property. Signed-off-by: Primoz Fiser Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250905065503.3022107-1-primoz.fiser@norik.com Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/afe/current-sense-amplifier.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.yaml b/Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.yaml index 527501c1d695..bcf4ddcfd13b 100644 --- a/Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.yaml +++ b/Documentation/devicetree/bindings/iio/afe/current-sense-amplifier.yaml @@ -24,6 +24,9 @@ properties: description: | Channel node of a voltage io-channel. + "#io-channel-cells": + const: 0 + sense-resistor-micro-ohms: description: The sense resistance. @@ -46,6 +49,7 @@ examples: - | sysi { compatible = "current-sense-amplifier"; + #io-channel-cells = <0>; io-channels = <&tiadc 0>; sense-resistor-micro-ohms = <20000>; -- cgit v1.2.3 From b17b850da6f9c4440a49d96cded5faa85123aadf Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:41 +0300 Subject: dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms Make a formal change to reflect the actual NXP LPC32xx maintainership for the last years. Cc: Roland Stigge Acked-by: Rob Herring (Arm) Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml index f1bd6f50e726..6b7f5e6f99cf 100644 --- a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml +++ b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP LPC32xx Platforms maintainers: - - Roland Stigge + - Vladimir Zapolskiy properties: compatible: -- cgit v1.2.3 From 5e38d940a36c419622286251dd0efa96956d0ed5 Mon Sep 17 00:00:00 2001 From: Ray Chang Date: Fri, 22 Aug 2025 15:33:08 +0800 Subject: dt-bindings: arm: fsl: Add EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board Add support for TechNexion EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board. Signed-off-by: Ray Chang Signed-off-by: Richard Hu Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index ebafa6ecbcb6..8e48a34af890 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1201,6 +1201,13 @@ properties: - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A - const: fsl,imx8mp + - description: TechNexion EDM-G-IMX8M-PLUS SoM based boards + items: + - enum: + - technexion,edm-g-imx8mp-wb # TechNexion EDM-G-IMX8MP SOM on WB-EDM-G + - const: technexion,edm-g-imx8mp # TechNexion EDM-G-IMX8MP SOM + - const: fsl,imx8mp + - description: Toradex Boards with SMARC iMX8M Plus Modules items: - const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board -- cgit v1.2.3 From 1419c28eb246e181e7b917b1b0b65282201dfc34 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 22 Aug 2025 09:02:41 -0300 Subject: dt-bindings: soc: fsl,imx-iomuxc-gpr: Document i.MX53 imx53.dtsi has the following compatible entry: compatible = "fsl,imx53-iomuxc-gpr", "syscon"; Document the "fsl,imx53-iomuxc-gpr" entry to fix the following dt-schema warning: failed to match any schema with compatible: ['fsl,imx53-iomuxc-gpr', 'syscon'] Signed-off-by: Fabio Estevam Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml index 8451cb4dd87c..b77ce8c6a935 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -38,6 +38,7 @@ properties: - const: simple-mfd - items: - enum: + - fsl,imx53-iomuxc-gpr - fsl,imx8mm-iomuxc-gpr - fsl,imx8mn-iomuxc-gpr - fsl,imx8mp-iomuxc-gpr -- cgit v1.2.3 From 76e145f857e9dea47002f23965a21ea35caa8bbd Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sat, 23 Aug 2025 17:28:21 +0300 Subject: dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards Add bindings for SolidRun i.MX8M Plus System on Module based boards: - CuBox-M is a complete produc with enclosure including the SoM - HummingBoard Mate/Pro/Pulse/Ripple are evaluation boards with common design but different available interfaces. Signed-off-by: Josua Mayer Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 8e48a34af890..b98efb7bf6ee 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1201,6 +1201,17 @@ properties: - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A - const: fsl,imx8mp + - description: SolidRun i.MX8MP SoM based boards + items: + - enum: + - solidrun,imx8mp-cubox-m # SolidRun i.MX8MP SoM on CuBox-M + - solidrun,imx8mp-hummingboard-mate # SolidRun i.MX8MP SoM on HummingBoard Mate + - solidrun,imx8mp-hummingboard-pro # SolidRun i.MX8MP SoM on HummingBoard Pro + - solidrun,imx8mp-hummingboard-pulse # SolidRun i.MX8MP SoM on HummingBoard Pulse + - solidrun,imx8mp-hummingboard-ripple # SolidRun i.MX8MP SoM on HummingBoard Ripple + - const: solidrun,imx8mp-sr-som + - const: fsl,imx8mp + - description: TechNexion EDM-G-IMX8M-PLUS SoM based boards items: - enum: -- cgit v1.2.3 From 0463d9d492dfc896f61fd6319688e02341fea772 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 27 Aug 2025 17:24:45 -0400 Subject: dt-bindings: fsl: fsl,imx7ulp-smc1: Allow clocks and clock-names Allow clocks and clock-names to match existed dts file. 'hsrun_divcore' should be 'hsrun-divcore'. But use '_' to keep old dts back compatible. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx7ulp-com.dtb: clock-controller@40410000 (fsl,imx7ulp-smc1): '#clock-cells', 'clock-names', 'clocks' do not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-pm.yaml# Signed-off-by: Frank Li Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml index 3b26040f8f18..9d377e193c12 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml @@ -28,6 +28,14 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + items: + - const: divcore + - const: hsrun_divcore + required: - compatible - reg -- cgit v1.2.3 From f001225088b8736f55dd28a4616cdf1b1bdcdd2e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 1 Sep 2025 12:04:29 +0200 Subject: dt-bindings: arm: fsl: add TQMa91xx SOM series TQMa91xx series is using NXP i.MX91 CPU on an LGA or socketable type board. MBa91xxCA is a starterkit base board for TQMa91xx on an adapter board. Reviewed-by: Frank Li Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b98efb7bf6ee..00cdf490b062 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1451,6 +1451,24 @@ properties: - fsl,imxrt1170-evk # i.MXRT1170 EVK Board - const: fsl,imxrt1170 + - description: + TQMa91xxLA and TQMa91xxCA are two series of feature compatible SOM + using NXP i.MX91 SOC in 11x11 mm package. + TQMa91xxLA is designed to be soldered on different carrier boards. + TQMa91xxCA is a compatible variant using board to board connectors. + All SOM and CPU variants use the same device tree hence only one + compatible is needed. Bootloader disables all features not present + in the assembled SOC. + MBa91xxCA mainboard can be used as starterkit for the SOM + soldered on an adapter board or for the connector variant + MBa91xxLA mainboard is a single board computer using the solderable + SOM variant + items: + - enum: + - tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa91xxCA + - const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM + - const: fsl,imx91 + - description: TQMa93xxLA and TQMa93xxCA are two series of feature compatible SOM using NXP i.MX93 SOC in 11x11 mm package. -- cgit v1.2.3 From 92f96706947e902fd9156cdcdd61c9a44b4b186c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 3 Sep 2025 19:04:49 +0200 Subject: dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon Add CSIDPHY GRF syscon compatible for the Rockchip RK3588. Acked-by: "Rob Herring (Arm)" Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-1-a4f340a7f0cf@collabora.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 1d0f35e26311..01641692418b 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -48,6 +48,7 @@ properties: - rockchip,rk3576-vop-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-csidphy-grf - rockchip,rk3588-dcphy-grf - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc -- cgit v1.2.3 From 87c0881bd734a2cea12076716d5d9a050789d4b7 Mon Sep 17 00:00:00 2001 From: Stefan Kerkmann Date: Wed, 10 Sep 2025 11:34:05 +0200 Subject: ASoC: dt-bindings: ti,pcm1754: add binding documentation The Texas Instruments PCM1754 is a simple stereo DAC without any digital management interface but soft mute, PCM input format and 44.1 kHz digital de-emphasis can be configured via strapping pins. Only soft mute and PCM input format selection is currently exposed via optional GPIOs in the driver. Signed-off-by: Stefan Kerkmann Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250910-v6-12-topic-pcm1754-v2-1-0917dbe73c65@pengutronix.de Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/ti,pcm1754.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/ti,pcm1754.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ti,pcm1754.yaml b/Documentation/devicetree/bindings/sound/ti,pcm1754.yaml new file mode 100644 index 000000000000..a757f737690c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,pcm1754.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,pcm1754.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PCM1754 Stereo DAC + +description: + The PCM1754 is a simple stereo DAC that is controlled via hardware gpios. + +maintainers: + - Stefan Kerkmann + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - ti,pcm1754 + + vcc-supply: true + + '#sound-dai-cells': + const: 0 + + format-gpios: + maxItems: 1 + description: + GPIO used to select the PCM format + + mute-gpios: + maxItems: 1 + description: + GPIO used to mute all outputs + +required: + - compatible + - '#sound-dai-cells' + - vcc-supply + +additionalProperties: false + +examples: + - | + #include + codec { + compatible = "ti,pcm1754"; + #sound-dai-cells = <0>; + + vcc-supply = <&vcc_reg>; + mute-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + format-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; -- cgit v1.2.3 From 59ba108806516adeaed51a536d55d4f5e9645881 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 10 Sep 2025 18:36:15 -0500 Subject: ASoC: dt-bindings: linux,spdif: Add "port" node The SPDIF receiver/transmitter can be connected to a DAI device via OF graph port. It is already in use and supported. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250910233615.775397-2-robh@kernel.org Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/linux,spdif.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/linux,spdif.yaml b/Documentation/devicetree/bindings/sound/linux,spdif.yaml index 0f4893e11ec4..aea6230db54c 100644 --- a/Documentation/devicetree/bindings/sound/linux,spdif.yaml +++ b/Documentation/devicetree/bindings/sound/linux,spdif.yaml @@ -23,6 +23,9 @@ properties: sound-name-prefix: true + port: + $ref: /schemas/graph.yaml#/properties/port + required: - "#sound-dai-cells" - compatible -- cgit v1.2.3 From c7ec58c39b0252e6635dde55e5c708132ab25cfc Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Mon, 8 Sep 2025 13:49:55 +0530 Subject: dt-bindings: eeprom: at24: Add compatible for Giantec GT24C256C The gt24c256c is another 24c256 compatible EEPROM, and does not follow the generic name matching, so add a separate compatible for it. This ensures accurate device-tree representation and enables proper kernel support for systems using this part. Acked-by: Krzysztof Kozlowski Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250908-lemans-evk-bu-v4-5-5c319c696a7d@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/eeprom/at24.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml index 0ac68646c077..50af7ccf6e21 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.yaml +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -143,6 +143,7 @@ properties: - const: atmel,24c128 - items: - enum: + - giantec,gt24c256c - puya,p24c256c - const: atmel,24c256 - items: -- cgit v1.2.3 From 76bc2203a46ef704a4cd8003986f6bd74139a367 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 4 Sep 2025 11:05:26 -0500 Subject: dt-bindings: mfd: ti,bq25703a: Add TI BQ25703A Charger Document the Texas instruments BQ25703A series of charger managers/ buck/boost regulators. Signed-off-by: Chris Morgan Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250904160530.66178-2-macroalpha82@gmail.com Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/ti,bq25703a.yaml | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml new file mode 100644 index 000000000000..ba14663c9266 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,bq25703a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BQ25703A Charger Manager/Buck/Boost Converter + +maintainers: + - Chris Morgan + +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + +properties: + compatible: + const: ti,bq25703a + + reg: + const: 0x6b + + input-current-limit-microamp: + description: + Maximum total input current allowed used for both charging and + powering the device. + minimum: 50000 + maximum: 6400000 + default: 3250000 + + interrupts: + maxItems: 1 + + monitored-battery: + description: + A minimum of constant-charge-current-max-microamp, + constant-charge-voltage-max-microvolt, and + voltage-min-design-microvolt are required. + + regulators: + type: object + additionalProperties: false + description: + Boost converter regulator output of bq257xx. + + properties: + vbus: + type: object + $ref: /schemas/regulator/regulator.yaml + additionalProperties: false + + properties: + regulator-name: true + regulator-min-microamp: + minimum: 0 + maximum: 6350000 + regulator-max-microamp: + minimum: 0 + maximum: 6350000 + regulator-min-microvolt: + minimum: 4480000 + maximum: 20800000 + regulator-max-microvolt: + minimum: 4480000 + maximum: 20800000 + enable-gpios: + description: + The BQ25703 may require both a register write and a GPIO + toggle to enable the boost regulator. + + required: + - regulator-name + - regulator-min-microamp + - regulator-max-microamp + - regulator-min-microvolt + - regulator-max-microvolt + +unevaluatedProperties: false + +required: + - compatible + - reg + - input-current-limit-microamp + - monitored-battery + - power-supplies + +examples: + - | + #include + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bq25703: charger@6b { + compatible = "ti,bq25703a"; + reg = <0x6b>; + input-current-limit-microamp = <5000000>; + interrupt-parent = <&gpio0>; + interrupts = ; + monitored-battery = <&battery>; + power-supplies = <&fusb302>; + + regulators { + usb_otg_vbus: vbus { + enable-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + regulator-max-microamp = <960000>; + regulator-max-microvolt = <5088000>; + regulator-min-microamp = <512000>; + regulator-min-microvolt = <4992000>; + regulator-name = "usb_otg_vbus"; + }; + }; + }; + }; + +... -- cgit v1.2.3 From 804ebc2bdcc85f30973708835b47ee023a4be003 Mon Sep 17 00:00:00 2001 From: Kartik Rajput Date: Thu, 28 Aug 2025 11:29:29 +0530 Subject: dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C Tegra264 has 17 generic I2C controllers, two of which are in always-on partition of the SoC. In addition to the features supported by Tegra194 it also supports a SW mutex register to allow sharing the same I2C instance across multiple firmware. Document compatible string "nvidia,tegra264-i2c" for Tegra264 I2C. Signed-off-by: Kartik Rajput Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 6b6f6762d122..f0693b872cb6 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -80,6 +80,12 @@ properties: support for 64 KiB transactions whereas earlier chips supported no more than 4 KiB per transactions. const: nvidia,tegra194-i2c + - description: + Tegra264 has 17 generic I2C controllers, two of which are in the AON + (always-on) partition of the SoC. In addition to the features from + Tegra194, a SW mutex register is added to support use of the same I2C + instance across multiple firmwares. + const: nvidia,tegra264-i2c reg: maxItems: 1 @@ -186,6 +192,7 @@ allOf: contains: enum: - nvidia,tegra194-i2c + - nvidia,tegra264-i2c then: required: - resets -- cgit v1.2.3 From 6b670e53ac6ecd531d90324e9ef87a029d2c98b9 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 6 Sep 2025 16:53:33 +0300 Subject: dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI The avdd-dsi-csi-supply is CSI power supply, it has nothing to do with VI, like same supply is used with DSI and has nothing to do with DC. Move it to correct place. Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml | 3 --- .../devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml index 2181855a0920..644f42b942ad 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -70,9 +70,6 @@ properties: ranges: maxItems: 1 - avdd-dsi-csi-supply: - description: DSI/CSI power supply. Must supply 1.2 V. - vip: $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml index fa07a40d1004..37f6129c9c92 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml @@ -37,6 +37,9 @@ properties: - const: cile - const: csi_tpg + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + power-domains: maxItems: 1 -- cgit v1.2.3 From 669c71f6c6b0034f918430a2fdcf577683d31db6 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 9 Sep 2025 10:49:57 +0300 Subject: dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101) Add a compatible for the Xiaomi Mi Pad (A0101) tablet. Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 1634dab53269..5b0f03af370d 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -174,6 +174,10 @@ properties: - const: google,nyan-big - const: google,nyan - const: nvidia,tegra124 + - description: Xiaomi Mi Pad (A0101) + items: + - const: xiaomi,mocha + - const: nvidia,tegra124 - items: - enum: - nvidia,darcy -- cgit v1.2.3 From 04f27a0fda6b6be104531eeb95d07ef1b3a72af8 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 6 Sep 2025 09:29:33 +0300 Subject: dt-bindings: arm: tegra: Add ASUS TF101G and SL101 Add a compatible for ASUS Eee Pad Transformer TF101G and ASUS Eee Pad Slider SL101. Signed-off-by: Svyatoslav Ryhel Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 5b0f03af370d..6139407c2cbf 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -36,8 +36,12 @@ properties: - toradex,colibri_t20-iris - const: toradex,colibri_t20 - const: nvidia,tegra20 - - items: - - const: asus,tf101 + - description: ASUS Transformers T20 Device family + items: + - enum: + - asus,sl101 + - asus,tf101 + - asus,tf101g - const: nvidia,tegra20 - items: - const: acer,picasso -- cgit v1.2.3 From 1ed2786e9ef8f16204dc3f30c46412070cb7140e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 10 Sep 2025 02:01:37 +0000 Subject: dt-bindings: soc: renesas: Document R-Car X5H Ironhide Document the compatible values for the Renesas R-Car X5H (R8A78000) SoC, as used on the Renesas Ironhide board. Signed-off-by: Kuninori Morimoto Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/87ms73vzen.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 5f9d541d177a..f4947ac65460 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -473,6 +473,12 @@ properties: - const: renesas,r8a779mb - const: renesas,r8a7795 + - description: R-Car X5H (R8A78000) + items: + - enum: + - renesas,ironhide # Ironhide (RTP8A78000ASKB0F10S) + - const: renesas,r8a78000 + - description: RZ/N1D (R9A06G032) items: - enum: -- cgit v1.2.3 From 0b467f5a7f19853d8b7a920468d795e682442b80 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 8 Sep 2025 18:10:13 -0500 Subject: dt-bindings: net: Convert apm,xgene-enet to DT schema Convert the APM XGene Ethernet binding to DT schema format. Add the missing apm,xgene2-sgenet and apm,xgene2-xgenet compatibles. Drop "reg-names" as required. Add support for up to 16 interrupts. Reviewed-by: Jacob Keller Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250908231016.2070305-1-robh@kernel.org Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/apm,xgene-enet.yaml | 115 +++++++++++++++++++++ .../devicetree/bindings/net/apm-xgene-enet.txt | 91 ---------------- MAINTAINERS | 2 +- 3 files changed, 116 insertions(+), 92 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/apm,xgene-enet.yaml delete mode 100644 Documentation/devicetree/bindings/net/apm-xgene-enet.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/apm,xgene-enet.yaml b/Documentation/devicetree/bindings/net/apm,xgene-enet.yaml new file mode 100644 index 000000000000..1c767ef8fcc5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/apm,xgene-enet.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/apm,xgene-enet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC Ethernet + +maintainers: + - Iyappan Subramanian + - Keyur Chudgar + - Quan Nguyen + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + enum: + - apm,xgene-enet + - apm,xgene1-sgenet + - apm,xgene1-xgenet + - apm,xgene2-sgenet + - apm,xgene2-xgenet + + reg: + maxItems: 3 + + reg-names: + items: + - const: enet_csr + - const: ring_csr + - const: ring_cmd + + clocks: + maxItems: 1 + + dma-coherent: true + + interrupts: + description: An rx and tx completion interrupt pair per queue + minItems: 1 + maxItems: 16 + + channel: + description: Ethernet to CPU start channel number + $ref: /schemas/types.yaml#/definitions/uint32 + + port-id: + description: Port number + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 1 + + tx-delay: + description: Delay value for RGMII bridge TX clock + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 7 + default: 4 + + rx-delay: + description: Delay value for RGMII bridge RX clock + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 7 + default: 2 + + rxlos-gpios: + description: Input GPIO from SFP+ module indicating incoming signal + maxItems: 1 + + mdio: + description: MDIO bus subnode + $ref: mdio.yaml# + unevaluatedProperties: false + + properties: + compatible: + const: apm,xgene-mdio + + required: + - compatible + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + ethernet@17020000 { + compatible = "apm,xgene-enet"; + reg = <0x17020000 0xd100>, + <0x17030000 0x400>, + <0x10000000 0x200>; + reg-names = "enet_csr", "ring_csr", "ring_cmd"; + interrupts = <0x0 0x3c 0x4>; + channel = <0>; + port-id = <0>; + clocks = <&menetclk 0>; + local-mac-address = [00 01 73 00 00 01]; + phy-connection-type = "rgmii"; + phy-handle = <&menetphy>; + + mdio { + compatible = "apm,xgene-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + menetphy: ethernet-phy@3 { + compatible = "ethernet-phy-id001c.c915"; + reg = <3>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt deleted file mode 100644 index f591ab782dbc..000000000000 --- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt +++ /dev/null @@ -1,91 +0,0 @@ -APM X-Gene SoC Ethernet nodes - -Ethernet nodes are defined to describe on-chip ethernet interfaces in -APM X-Gene SoC. - -Required properties for all the ethernet interfaces: -- compatible: Should state binding information from the following list, - - "apm,xgene-enet": RGMII based 1G interface - - "apm,xgene1-sgenet": SGMII based 1G interface - - "apm,xgene1-xgenet": XFI based 10G interface -- reg: Address and length of the register set for the device. It contains the - information of registers in the same order as described by reg-names -- reg-names: Should contain the register set names - - "enet_csr": Ethernet control and status register address space - - "ring_csr": Descriptor ring control and status register address space - - "ring_cmd": Descriptor ring command register address space -- interrupts: Two interrupt specifiers can be specified. - - First is the Rx interrupt. This irq is mandatory. - - Second is the Tx completion interrupt. - This is supported only on SGMII based 1GbE and 10GbE interfaces. -- channel: Ethernet to CPU, start channel (prefetch buffer) number - - Must map to the first irq and irqs must be sequential -- port-id: Port number (0 or 1) -- clocks: Reference to the clock entry. -- local-mac-address: MAC address assigned to this device -- phy-connection-type: Interface type between ethernet device and PHY device - -Required properties for ethernet interfaces that have external PHY: -- phy-handle: Reference to a PHY node connected to this device - -- mdio: Device tree subnode with the following required properties: - - compatible: Must be "apm,xgene-mdio". - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - For the phy on the mdio bus, there must be a node with the following fields: - - compatible: PHY identifier. Please refer ./phy.txt for the format. - - reg: The ID number for the phy. - -Optional properties: -- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok". -- tx-delay: Delay value for RGMII bridge TX clock. - Valid values are between 0 to 7, that maps to - 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps - Default value is 4, which corresponds to 1611 ps -- rx-delay: Delay value for RGMII bridge RX clock. - Valid values are between 0 to 7, that maps to - 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps - Default value is 2, which corresponds to 899 ps -- rxlos-gpios: Input gpio from SFP+ module to indicate availability of - incoming signal. - - -Example: - menetclk: menetclk { - compatible = "apm,xgene-device-clock"; - clock-output-names = "menetclk"; - status = "ok"; - }; - - menet: ethernet@17020000 { - compatible = "apm,xgene-enet"; - status = "disabled"; - reg = <0x0 0x17020000 0x0 0xd100>, - <0x0 0x17030000 0x0 0x400>, - <0x0 0x10000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x3c 0x4>; - port-id = <0>; - clocks = <&menetclk 0>; - local-mac-address = [00 01 73 00 00 01]; - phy-connection-type = "rgmii"; - phy-handle = <&menetphy>; - mdio { - compatible = "apm,xgene-mdio"; - #address-cells = <1>; - #size-cells = <0>; - menetphy: menetphy@3 { - compatible = "ethernet-phy-id001c.c915"; - reg = <0x3>; - }; - - }; - }; - -/* Board-specific peripheral configurations */ -&menet { - tx-delay = <4>; - rx-delay = <2>; - status = "ok"; -}; diff --git a/MAINTAINERS b/MAINTAINERS index ebf9bf188f87..6b82739e26c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1886,7 +1886,7 @@ M: Iyappan Subramanian M: Keyur Chudgar M: Quan Nguyen S: Maintained -F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt +F: Documentation/devicetree/bindings/net/apm,xgene-enet.yaml F: Documentation/devicetree/bindings/net/apm-xgene-mdio.txt F: drivers/net/ethernet/apm/xgene/ F: drivers/net/mdio/mdio-xgene.c -- cgit v1.2.3 From e663ad6e06a776b739d490b51c59c07cb4d767a4 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 8 Sep 2025 18:10:14 -0500 Subject: dt-bindings: net: Convert APM XGene MDIO to DT schema Convert the APM XGene MDIO bus binding to DT schema format. It's a straight-forward conversion. Reviewed-by: Jacob Keller Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250908231016.2070305-2-robh@kernel.org Signed-off-by: Jakub Kicinski --- .../bindings/net/apm,xgene-mdio-rgmii.yaml | 54 ++++++++++++++++++++++ .../devicetree/bindings/net/apm-xgene-mdio.txt | 37 --------------- MAINTAINERS | 2 +- 3 files changed, 55 insertions(+), 38 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml delete mode 100644 Documentation/devicetree/bindings/net/apm-xgene-mdio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml b/Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml new file mode 100644 index 000000000000..470fb5f7f7b5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/apm,xgene-mdio-rgmii.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC MDIO + +maintainers: + - Iyappan Subramanian + - Keyur Chudgar + - Quan Nguyen + +allOf: + - $ref: mdio.yaml# + +properties: + compatible: + enum: + - apm,xgene-mdio-rgmii + - apm,xgene-mdio-xfi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + +examples: + - | + mdio@17020000 { + compatible = "apm,xgene-mdio-rgmii"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x17020000 0xd100>; + clocks = <&menetclk 0>; + + phy@3 { + reg = <0x3>; + }; + phy@4 { + reg = <0x4>; + }; + phy@5 { + reg = <0x5>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt b/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt deleted file mode 100644 index 78722d74cea8..000000000000 --- a/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt +++ /dev/null @@ -1,37 +0,0 @@ -APM X-Gene SoC MDIO node - -MDIO node is defined to describe on-chip MDIO controller. - -Required properties: - - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi" - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - reg: Address and length of the register set - - clocks: Reference to the clock entry - -For the phys on the mdio bus, there must be a node with the following fields: - - compatible: PHY identifier. Please refer ./phy.txt for the format. - - reg: The ID number for the phy. - -Example: - - mdio: mdio@17020000 { - compatible = "apm,xgene-mdio-rgmii"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x17020000 0x0 0xd100>; - clocks = <&menetclk 0>; - }; - - /* Board-specific peripheral configurations */ - &mdio { - menetphy: phy@3 { - reg = <0x3>; - }; - sgenet0phy: phy@4 { - reg = <0x4>; - }; - sgenet1phy: phy@5 { - reg = <0x5>; - }; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 6b82739e26c8..c930a961435e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1887,7 +1887,7 @@ M: Keyur Chudgar M: Quan Nguyen S: Maintained F: Documentation/devicetree/bindings/net/apm,xgene-enet.yaml -F: Documentation/devicetree/bindings/net/apm-xgene-mdio.txt +F: Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml F: drivers/net/ethernet/apm/xgene/ F: drivers/net/mdio/mdio-xgene.c -- cgit v1.2.3 From 3e915577cf0b7d3f9088c398888e5e01e10356d7 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Thu, 14 Aug 2025 19:15:28 +0530 Subject: dt-bindings: arm: ti: Add binding for AM625 SiP The AM6254atl SiP belongs to the K3 Multicore SoC architecture platform, providing AM625 SoC with 512MiB of integrated DDR in the package. For further information about the package check: https://www.ti.com/lit/ds/symlink/am625sip.pdf Signed-off-by: Anshul Dalal Reviewed-by: Bryan Brattlof Acked-by: Conor Dooley Link: https://patch.msgid.link/20250814134531.2743874-3-anshuld@ti.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index e80c653fa438..f98817e97d4c 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -58,6 +58,13 @@ properties: - ti,am62-lp-sk - const: ti,am625 + - description: K3 AM6254atl SiP + items: + - enum: + - ti,am6254atl-sk + - const: ti,am6254atl + - const: ti,am625 + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards items: - enum: -- cgit v1.2.3 From 03c7b1f0ee9f7c8d047a6ea5767ac96490d1385c Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 9 Sep 2025 23:37:39 +0200 Subject: dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Add devicetree bindings for Variscite VAR-SOM-AM62P System on Module and its carrier boards. Signed-off-by: Stefano Radaelli Reviewed-by: Judith Mendez Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250909213749.28098-2-stefano.radaelli21@gmail.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index f98817e97d4c..0105dcda6e04 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -113,6 +113,12 @@ properties: - const: toradex,verdin-am62p # Verdin AM62P Module - const: ti,am62p5 + - description: K3 AM62P5 SoC Variscite SOM and Carrier Boards + items: + - const: variscite,var-som-am62p-symphony + - const: variscite,var-som-am62p + - const: ti,am62p5 + - description: K3 AM642 SoC items: - enum: -- cgit v1.2.3 From 273532a0da09638d0e981df3d012199e2af38447 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Tue, 19 Aug 2025 11:24:46 +0000 Subject: dt-bindings: interconnect: Add OSM L3 compatible for QCS615 SoC Add Operation State Manager (OSM) L3 interconnect provider binding for QCS615 SoC. As the OSM hardware in QCS615 and SM8150 are same, added a family-level compatible for SM8150 SoC. Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250819-talos-l3-icc-v3-1-04529e85dac7@oss.qualcomm.com Signed-off-by: Georgi Djakov --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index ab5a921c3495..4b9b98fbe8f2 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -41,6 +41,11 @@ properties: - qcom,qcs8300-epss-l3 - const: qcom,sa8775p-epss-l3 - const: qcom,epss-l3 + - items: + - enum: + - qcom,qcs615-osm-l3 + - const: qcom,sm8150-osm-l3 + - const: qcom,osm-l3 reg: maxItems: 1 -- cgit v1.2.3 From c656c99c118b44bb360b0718fadfbf3754fd44d5 Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Wed, 3 Sep 2025 12:51:39 +0200 Subject: dt-bindings: mmc: sdhci-pxa: Add minItems to pinctrl-names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some older boards only require a default pinctrl. Add a minItems property so these don't cause dt-validate warnings. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202509030625.PBgLIAwG-lkp@intel.com/ Signed-off-by: Duje Mihanović Acked-by: Rob Herring (Arm) Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml index fba1cc50fdf0..186ce8ff4626 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -44,6 +44,7 @@ allOf: items: - const: default - const: state_cmd_gpio + minItems: 1 pinctrl-1: description: @@ -61,6 +62,7 @@ allOf: items: - const: default - const: state_uhs + minItems: 1 pinctrl-1: description: -- cgit v1.2.3 From ce55f63137919a1d943b0d883a6ac3744108af0f Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Mon, 8 Sep 2025 13:49:51 +0530 Subject: dt-bindings: mmc: sdhci-msm: Document the Lemans compatible Add the MSM SDHCI compatible name to support both eMMC and SD card for Lemans, which uses 'sa8775p' as the fallback SoC. Ensure the new compatible string matches existing Lemans-compatible formats without introducing a new naming convention. The SDHCI controller on Lemans is based on MSM SDHCI v5 IP. Hence, document the compatible with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Monish Chunara Acked-by: Krzysztof Kozlowski Signed-off-by: Wasim Nazir Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 22d1f50c3fd1..594bd174ff21 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -48,6 +48,7 @@ properties: - qcom,qcs615-sdhci - qcom,qcs8300-sdhci - qcom,qdu1000-sdhci + - qcom,sa8775p-sdhci - qcom,sar2130p-sdhci - qcom,sc7180-sdhci - qcom,sc7280-sdhci -- cgit v1.2.3 From 98682689a1a443067e1981d9eed8c6ddcef8cdf3 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Mon, 8 Sep 2025 16:11:20 +0530 Subject: dt-bindings: mmc: controller: Add max-sd-hs-hz property Introduce a new optional device tree property max-sd-hs-hz to limit the maximum frequency (in Hz) used for SD cards operating in High-Speed (HS) mode due to any board electrical limitations. Signed-off-by: Sarthak Garg Reviewed-by: Krzysztof Kozlowski Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml index 9a7235439759..7414d5522dfe 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -93,6 +93,14 @@ properties: minimum: 400000 maximum: 384000000 + max-sd-hs-hz: + description: | + Maximum frequency (in Hz) to be used for SD cards operating in + High-Speed (HS) mode. + minimum: 400000 + maximum: 50000000 + default: 50000000 + disable-wp: $ref: /schemas/types.yaml#/definitions/flag description: -- cgit v1.2.3 From d1a7bf9031b9f91b86187bcd5bd7a4bfd76bcaef Mon Sep 17 00:00:00 2001 From: Tomáš Macholda Date: Thu, 11 Sep 2025 18:13:07 +0200 Subject: dt-bindings: marvell: armada-37xx: add ripe,atlas-v5 compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document compatible for RIPE Atlas Probe v5. Signed-off-by: Tomáš Macholda Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml index 51e1386f0e01..b2f4fe81b97c 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml @@ -23,6 +23,7 @@ properties: - marvell,armada-3720-db - methode,edpu - methode,udpu + - ripe,atlas-v5 - const: marvell,armada3720 - const: marvell,armada3710 -- cgit v1.2.3 From 7cbba32a2d62c3c18128c04f88b1901d702bb2bf Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 12 Sep 2025 14:12:00 +0100 Subject: slimbus: qcom: remove unused qcom controller driver Qcom Slimbus controller driver is totally unused and dead code, there is no point in keeping this driver in the kernel without users. This patch removes the driver along with device tree bindings. Signed-off-by: Srinivas Kandagatla Acked-by: Rob Herring (Arm) Acked-by: Dmitry Baryshkov Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20250912131202.303026-2-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/slimbus/qcom,slim.yaml | 86 --- .../devicetree/bindings/slimbus/slimbus.yaml | 13 +- drivers/slimbus/Kconfig | 7 - drivers/slimbus/Makefile | 3 - drivers/slimbus/qcom-ctrl.c | 735 --------------------- 5 files changed, 4 insertions(+), 840 deletions(-) delete mode 100644 Documentation/devicetree/bindings/slimbus/qcom,slim.yaml delete mode 100644 drivers/slimbus/qcom-ctrl.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/slimbus/qcom,slim.yaml b/Documentation/devicetree/bindings/slimbus/qcom,slim.yaml deleted file mode 100644 index 883bda58ca97..000000000000 --- a/Documentation/devicetree/bindings/slimbus/qcom,slim.yaml +++ /dev/null @@ -1,86 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/slimbus/qcom,slim.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SoC SLIMbus controller - -maintainers: - - Krzysztof Kozlowski - - Srinivas Kandagatla - -description: - SLIMbus controller used when applications processor controls SLIMbus master - component. - -allOf: - - $ref: slimbus.yaml# - -properties: - compatible: - items: - - enum: - - qcom,apq8064-slim - - const: qcom,slim - - reg: - items: - - description: Physical address of controller register blocks - - description: SLEW RATE register - - reg-names: - items: - - const: ctrl - - const: slew - - clocks: - items: - - description: Interface clock for this controller - - description: Interrupt for controller core's BAM - - clock-names: - items: - - const: iface - - const: core - - interrupts: - maxItems: 1 - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - - interrupts - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - slim@28080000 { - compatible = "qcom,apq8064-slim", "qcom,slim"; - reg = <0x28080000 0x2000>, <0x80207c 4>; - reg-names = "ctrl", "slew"; - interrupts = ; - clocks = <&lcc SLIMBUS_SRC>, <&lcc AUDIO_SLIMBUS_CLK>; - clock-names = "iface", "core"; - #address-cells = <2>; - #size-cells = <0>; - - audio-codec@1,0 { - compatible = "slim217,60"; - reg = <1 0>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/slimbus/slimbus.yaml b/Documentation/devicetree/bindings/slimbus/slimbus.yaml index 3b8cae9d1016..89017d9cda10 100644 --- a/Documentation/devicetree/bindings/slimbus/slimbus.yaml +++ b/Documentation/devicetree/bindings/slimbus/slimbus.yaml @@ -68,8 +68,6 @@ additionalProperties: true examples: - | - #include - #include #include soc { @@ -78,17 +76,14 @@ examples: ranges; slim@28080000 { - compatible = "qcom,apq8064-slim", "qcom,slim"; - reg = <0x28080000 0x2000>, <0x80207c 4>; - reg-names = "ctrl", "slew"; - interrupts = ; - clocks = <&lcc SLIMBUS_SRC>, <&lcc AUDIO_SLIMBUS_CLK>; - clock-names = "iface", "core"; + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x091c0000 0x2c000>; + interrupts = ; #address-cells = <2>; #size-cells = <0>; audio-codec@1,0 { - compatible = "slim217,60"; + compatible = "slim217,1a0"; reg = <1 0>; }; }; diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig index a0fdf9d792cb..60b0dcbc0ebb 100644 --- a/drivers/slimbus/Kconfig +++ b/drivers/slimbus/Kconfig @@ -13,13 +13,6 @@ menuconfig SLIMBUS if SLIMBUS # SLIMbus controllers -config SLIM_QCOM_CTRL - tristate "Qualcomm SLIMbus Manager Component" - depends on HAS_IOMEM - help - Select driver if Qualcomm's SLIMbus Manager Component is - programmed using Linux kernel. - config SLIM_QCOM_NGD_CTRL tristate "Qualcomm SLIMbus Satellite Non-Generic Device Component" depends on HAS_IOMEM && DMA_ENGINE && NET diff --git a/drivers/slimbus/Makefile b/drivers/slimbus/Makefile index d9aa011b6804..3cfb41c3b592 100644 --- a/drivers/slimbus/Makefile +++ b/drivers/slimbus/Makefile @@ -6,8 +6,5 @@ obj-$(CONFIG_SLIMBUS) += slimbus.o slimbus-y := core.o messaging.o sched.o stream.o #Controllers -obj-$(CONFIG_SLIM_QCOM_CTRL) += slim-qcom-ctrl.o -slim-qcom-ctrl-y := qcom-ctrl.o - obj-$(CONFIG_SLIM_QCOM_NGD_CTRL) += slim-qcom-ngd-ctrl.o slim-qcom-ngd-ctrl-y := qcom-ngd-ctrl.o diff --git a/drivers/slimbus/qcom-ctrl.c b/drivers/slimbus/qcom-ctrl.c deleted file mode 100644 index ab344f7472f2..000000000000 --- a/drivers/slimbus/qcom-ctrl.c +++ /dev/null @@ -1,735 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2011-2017, The Linux Foundation - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "slimbus.h" - -/* Manager registers */ -#define MGR_CFG 0x200 -#define MGR_STATUS 0x204 -#define MGR_INT_EN 0x210 -#define MGR_INT_STAT 0x214 -#define MGR_INT_CLR 0x218 -#define MGR_TX_MSG 0x230 -#define MGR_RX_MSG 0x270 -#define MGR_IE_STAT 0x2F0 -#define MGR_VE_STAT 0x300 -#define MGR_CFG_ENABLE 1 - -/* Framer registers */ -#define FRM_CFG 0x400 -#define FRM_STAT 0x404 -#define FRM_INT_EN 0x410 -#define FRM_INT_STAT 0x414 -#define FRM_INT_CLR 0x418 -#define FRM_WAKEUP 0x41C -#define FRM_CLKCTL_DONE 0x420 -#define FRM_IE_STAT 0x430 -#define FRM_VE_STAT 0x440 - -/* Interface registers */ -#define INTF_CFG 0x600 -#define INTF_STAT 0x604 -#define INTF_INT_EN 0x610 -#define INTF_INT_STAT 0x614 -#define INTF_INT_CLR 0x618 -#define INTF_IE_STAT 0x630 -#define INTF_VE_STAT 0x640 - -/* Interrupt status bits */ -#define MGR_INT_TX_NACKED_2 BIT(25) -#define MGR_INT_MSG_BUF_CONTE BIT(26) -#define MGR_INT_RX_MSG_RCVD BIT(30) -#define MGR_INT_TX_MSG_SENT BIT(31) - -/* Framer config register settings */ -#define FRM_ACTIVE 1 -#define CLK_GEAR 7 -#define ROOT_FREQ 11 -#define REF_CLK_GEAR 15 -#define INTR_WAKE 19 - -#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \ - ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16)) - -#define SLIM_ROOT_FREQ 24576000 -#define QCOM_SLIM_AUTOSUSPEND 1000 - -/* MAX message size over control channel */ -#define SLIM_MSGQ_BUF_LEN 40 -#define QCOM_TX_MSGS 2 -#define QCOM_RX_MSGS 8 -#define QCOM_BUF_ALLOC_RETRIES 10 - -#define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r)) - -/* V2 Component registers */ -#define CFG_PORT_V2(r) ((r ## _V2)) -#define COMP_CFG_V2 4 -#define COMP_TRUST_CFG_V2 0x3000 - -/* V1 Component registers */ -#define CFG_PORT_V1(r) ((r ## _V1)) -#define COMP_CFG_V1 0 -#define COMP_TRUST_CFG_V1 0x14 - -/* Resource group info for manager, and non-ported generic device-components */ -#define EE_MGR_RSC_GRP (1 << 10) -#define EE_NGD_2 (2 << 6) -#define EE_NGD_1 0 - -struct slim_ctrl_buf { - void *base; - spinlock_t lock; - int head; - int tail; - int sl_sz; - int n; -}; - -struct qcom_slim_ctrl { - struct slim_controller ctrl; - struct slim_framer framer; - struct device *dev; - void __iomem *base; - void __iomem *slew_reg; - - struct slim_ctrl_buf rx; - struct slim_ctrl_buf tx; - - struct completion **wr_comp; - int irq; - struct workqueue_struct *rxwq; - struct work_struct wd; - struct clk *rclk; - struct clk *hclk; -}; - -static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf, - u8 len, u32 tx_reg) -{ - int count = (len + 3) >> 2; - - __iowrite32_copy(ctrl->base + tx_reg, buf, count); - - /* Ensure Oder of subsequent writes */ - mb(); -} - -static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl) -{ - unsigned long flags; - int idx; - - spin_lock_irqsave(&ctrl->rx.lock, flags); - if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { - spin_unlock_irqrestore(&ctrl->rx.lock, flags); - dev_err(ctrl->dev, "RX QUEUE full!"); - return NULL; - } - idx = ctrl->rx.tail; - ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n; - spin_unlock_irqrestore(&ctrl->rx.lock, flags); - - return ctrl->rx.base + (idx * ctrl->rx.sl_sz); -} - -static void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err) -{ - struct completion *comp; - unsigned long flags; - int idx; - - spin_lock_irqsave(&ctrl->tx.lock, flags); - idx = ctrl->tx.head; - ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n; - spin_unlock_irqrestore(&ctrl->tx.lock, flags); - - comp = ctrl->wr_comp[idx]; - ctrl->wr_comp[idx] = NULL; - - complete(comp); -} - -static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl, - u32 stat) -{ - int err = 0; - - if (stat & MGR_INT_TX_MSG_SENT) - writel_relaxed(MGR_INT_TX_MSG_SENT, - ctrl->base + MGR_INT_CLR); - - if (stat & MGR_INT_TX_NACKED_2) { - u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS); - u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT); - u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT); - u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG); - u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT); - u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT); - u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT); - u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT); - u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT); - - writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR); - - dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n", - stat, mgr_stat); - dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat); - dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n", - frm_intr_stat, frm_stat); - dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n", - frm_cfg, frm_ie_stat); - dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n", - intf_intr_stat, intf_stat); - dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n", - intf_ie_stat); - err = -ENOTCONN; - } - - slim_ack_txn(ctrl, err); - - return IRQ_HANDLED; -} - -static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl, - u32 stat) -{ - u32 *rx_buf, pkt[10]; - bool q_rx = false; - u8 mc, mt, len; - - pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG); - mt = SLIM_HEADER_GET_MT(pkt[0]); - len = SLIM_HEADER_GET_RL(pkt[0]); - mc = SLIM_HEADER_GET_MC(pkt[0]>>8); - - /* - * this message cannot be handled by ISR, so - * let work-queue handle it - */ - if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) { - rx_buf = (u32 *)slim_alloc_rxbuf(ctrl); - if (!rx_buf) { - dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n", - pkt[0]); - goto rx_ret_irq; - } - rx_buf[0] = pkt[0]; - - } else { - rx_buf = pkt; - } - - __ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4, - DIV_ROUND_UP(len, 4)); - - switch (mc) { - - case SLIM_MSG_MC_REPORT_PRESENT: - q_rx = true; - break; - case SLIM_MSG_MC_REPLY_INFORMATION: - case SLIM_MSG_MC_REPLY_VALUE: - slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1), - (u8)(*rx_buf >> 24), (len - 4)); - break; - default: - dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n", - mc, mt); - break; - } -rx_ret_irq: - writel(MGR_INT_RX_MSG_RCVD, ctrl->base + - MGR_INT_CLR); - if (q_rx) - queue_work(ctrl->rxwq, &ctrl->wd); - - return IRQ_HANDLED; -} - -static irqreturn_t qcom_slim_interrupt(int irq, void *d) -{ - struct qcom_slim_ctrl *ctrl = d; - u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT); - int ret = IRQ_NONE; - - if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2) - ret = qcom_slim_handle_tx_irq(ctrl, stat); - - if (stat & MGR_INT_RX_MSG_RCVD) - ret = qcom_slim_handle_rx_irq(ctrl, stat); - - return ret; -} - -static int qcom_clk_pause_wakeup(struct slim_controller *sctrl) -{ - struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); - - clk_prepare_enable(ctrl->hclk); - clk_prepare_enable(ctrl->rclk); - enable_irq(ctrl->irq); - - writel_relaxed(1, ctrl->base + FRM_WAKEUP); - /* Make sure framer wakeup write goes through before ISR fires */ - mb(); - /* - * HW Workaround: Currently, slave is reporting lost-sync messages - * after SLIMbus comes out of clock pause. - * Transaction with slave fail before slave reports that message - * Give some time for that report to come - * SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe - * being 250 usecs, we wait for 5-10 superframes here to ensure - * we get the message - */ - usleep_range(1250, 2500); - return 0; -} - -static void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl, - struct slim_msg_txn *txn, - struct completion *done) -{ - unsigned long flags; - int idx; - - spin_lock_irqsave(&ctrl->tx.lock, flags); - if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) { - spin_unlock_irqrestore(&ctrl->tx.lock, flags); - dev_err(ctrl->dev, "controller TX buf unavailable"); - return NULL; - } - idx = ctrl->tx.tail; - ctrl->wr_comp[idx] = done; - ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n; - - spin_unlock_irqrestore(&ctrl->tx.lock, flags); - - return ctrl->tx.base + (idx * ctrl->tx.sl_sz); -} - - -static int qcom_xfer_msg(struct slim_controller *sctrl, - struct slim_msg_txn *txn) -{ - struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); - DECLARE_COMPLETION_ONSTACK(done); - void *pbuf = slim_alloc_txbuf(ctrl, txn, &done); - unsigned long ms = txn->rl + HZ; - u8 *puc; - int ret = 0, retries = QCOM_BUF_ALLOC_RETRIES; - unsigned long time_left; - u8 la = txn->la; - u32 *head; - /* HW expects length field to be excluded */ - txn->rl--; - - /* spin till buffer is made available */ - if (!pbuf) { - while (retries--) { - usleep_range(10000, 15000); - pbuf = slim_alloc_txbuf(ctrl, txn, &done); - if (pbuf) - break; - } - } - - if (retries < 0 && !pbuf) - return -ENOMEM; - - puc = (u8 *)pbuf; - head = (u32 *)pbuf; - - if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) { - *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, - txn->mc, 0, la); - puc += 3; - } else { - *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, - txn->mc, 1, la); - puc += 2; - } - - if (slim_tid_txn(txn->mt, txn->mc)) - *(puc++) = txn->tid; - - if (slim_ec_txn(txn->mt, txn->mc)) { - *(puc++) = (txn->ec & 0xFF); - *(puc++) = (txn->ec >> 8) & 0xFF; - } - - if (txn->msg && txn->msg->wbuf) - memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes); - - qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG); - time_left = wait_for_completion_timeout(&done, msecs_to_jiffies(ms)); - - if (!time_left) { - dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, - txn->mt); - ret = -ETIMEDOUT; - } - - return ret; - -} - -static int qcom_set_laddr(struct slim_controller *sctrl, - struct slim_eaddr *ead, u8 laddr) -{ - struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); - struct { - __be16 manf_id; - __be16 prod_code; - u8 dev_index; - u8 instance; - u8 laddr; - } __packed p; - struct slim_val_inf msg = {0}; - DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS, - 10, laddr, &msg); - int ret; - - p.manf_id = cpu_to_be16(ead->manf_id); - p.prod_code = cpu_to_be16(ead->prod_code); - p.dev_index = ead->dev_index; - p.instance = ead->instance; - p.laddr = laddr; - - msg.wbuf = (void *)&p; - msg.num_bytes = 7; - ret = slim_do_transfer(&ctrl->ctrl, &txn); - - if (ret) - dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n", - laddr, ret); - return ret; -} - -static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf) -{ - unsigned long flags; - - spin_lock_irqsave(&ctrl->rx.lock, flags); - if (ctrl->rx.tail == ctrl->rx.head) { - spin_unlock_irqrestore(&ctrl->rx.lock, flags); - return -ENODATA; - } - memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz), - ctrl->rx.sl_sz); - - ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n; - spin_unlock_irqrestore(&ctrl->rx.lock, flags); - - return 0; -} - -static void qcom_slim_rxwq(struct work_struct *work) -{ - u8 buf[SLIM_MSGQ_BUF_LEN]; - u8 mc, mt; - int ret; - struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl, - wd); - - while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) { - mt = SLIM_HEADER_GET_MT(buf[0]); - mc = SLIM_HEADER_GET_MC(buf[1]); - if (mt == SLIM_MSG_MT_CORE && - mc == SLIM_MSG_MC_REPORT_PRESENT) { - struct slim_eaddr ea; - u8 laddr; - - ea.manf_id = be16_to_cpup((__be16 *)&buf[2]); - ea.prod_code = be16_to_cpup((__be16 *)&buf[4]); - ea.dev_index = buf[6]; - ea.instance = buf[7]; - - ret = slim_device_report_present(&ctrl->ctrl, &ea, - &laddr); - if (ret < 0) - dev_err(ctrl->dev, "assign laddr failed:%d\n", - ret); - } else { - dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n", - mc, mt); - } - } -} - -static void qcom_slim_prg_slew(struct platform_device *pdev, - struct qcom_slim_ctrl *ctrl) -{ - if (!ctrl->slew_reg) { - /* SLEW RATE register for this SLIMbus */ - ctrl->slew_reg = devm_platform_ioremap_resource_byname(pdev, "slew"); - if (IS_ERR(ctrl->slew_reg)) - return; - } - - writel_relaxed(1, ctrl->slew_reg); - /* Make sure SLIMbus-slew rate enabling goes through */ - wmb(); -} - -static int qcom_slim_probe(struct platform_device *pdev) -{ - struct qcom_slim_ctrl *ctrl; - struct slim_controller *sctrl; - int ret, ver; - - ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); - if (!ctrl) - return -ENOMEM; - - ctrl->hclk = devm_clk_get(&pdev->dev, "iface"); - if (IS_ERR(ctrl->hclk)) - return PTR_ERR(ctrl->hclk); - - ctrl->rclk = devm_clk_get(&pdev->dev, "core"); - if (IS_ERR(ctrl->rclk)) - return PTR_ERR(ctrl->rclk); - - ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ); - if (ret) { - dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret); - return ret; - } - - ctrl->irq = platform_get_irq(pdev, 0); - if (ctrl->irq < 0) - return ctrl->irq; - - sctrl = &ctrl->ctrl; - sctrl->dev = &pdev->dev; - ctrl->dev = &pdev->dev; - platform_set_drvdata(pdev, ctrl); - dev_set_drvdata(ctrl->dev, ctrl); - - ctrl->base = devm_platform_ioremap_resource_byname(pdev, "ctrl"); - if (IS_ERR(ctrl->base)) - return PTR_ERR(ctrl->base); - - sctrl->set_laddr = qcom_set_laddr; - sctrl->xfer_msg = qcom_xfer_msg; - sctrl->wakeup = qcom_clk_pause_wakeup; - ctrl->tx.n = QCOM_TX_MSGS; - ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN; - ctrl->rx.n = QCOM_RX_MSGS; - ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN; - ctrl->wr_comp = kcalloc(QCOM_TX_MSGS, sizeof(struct completion *), - GFP_KERNEL); - if (!ctrl->wr_comp) - return -ENOMEM; - - spin_lock_init(&ctrl->rx.lock); - spin_lock_init(&ctrl->tx.lock); - INIT_WORK(&ctrl->wd, qcom_slim_rxwq); - ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx"); - if (!ctrl->rxwq) { - dev_err(ctrl->dev, "Failed to start Rx WQ\n"); - return -ENOMEM; - } - - ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8; - ctrl->framer.superfreq = - ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8; - sctrl->a_framer = &ctrl->framer; - sctrl->clkgear = SLIM_MAX_CLK_GEAR; - - qcom_slim_prg_slew(pdev, ctrl); - - ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt, - IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl); - if (ret) { - dev_err(&pdev->dev, "request IRQ failed\n"); - goto err_request_irq_failed; - } - - ret = clk_prepare_enable(ctrl->hclk); - if (ret) - goto err_hclk_enable_failed; - - ret = clk_prepare_enable(ctrl->rclk); - if (ret) - goto err_rclk_enable_failed; - - ctrl->tx.base = devm_kcalloc(&pdev->dev, ctrl->tx.n, ctrl->tx.sl_sz, - GFP_KERNEL); - if (!ctrl->tx.base) { - ret = -ENOMEM; - goto err; - } - - ctrl->rx.base = devm_kcalloc(&pdev->dev,ctrl->rx.n, ctrl->rx.sl_sz, - GFP_KERNEL); - if (!ctrl->rx.base) { - ret = -ENOMEM; - goto err; - } - - /* Register with framework before enabling frame, clock */ - ret = slim_register_controller(&ctrl->ctrl); - if (ret) { - dev_err(ctrl->dev, "error adding controller\n"); - goto err; - } - - ver = readl_relaxed(ctrl->base); - /* Version info in 16 MSbits */ - ver >>= 16; - /* Component register initialization */ - writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); - writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1), - ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver)); - - writel((MGR_INT_TX_NACKED_2 | - MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD | - MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN); - writel(1, ctrl->base + MGR_CFG); - /* Framer register initialization */ - writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) | - (0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1, - ctrl->base + FRM_CFG); - writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG); - writel(1, ctrl->base + INTF_CFG); - writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); - - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND); - pm_runtime_set_active(&pdev->dev); - pm_runtime_mark_last_busy(&pdev->dev); - pm_runtime_enable(&pdev->dev); - - dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver); - return 0; - -err: - clk_disable_unprepare(ctrl->rclk); -err_rclk_enable_failed: - clk_disable_unprepare(ctrl->hclk); -err_hclk_enable_failed: -err_request_irq_failed: - destroy_workqueue(ctrl->rxwq); - return ret; -} - -static void qcom_slim_remove(struct platform_device *pdev) -{ - struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev); - - pm_runtime_disable(&pdev->dev); - slim_unregister_controller(&ctrl->ctrl); - clk_disable_unprepare(ctrl->rclk); - clk_disable_unprepare(ctrl->hclk); - destroy_workqueue(ctrl->rxwq); -} - -/* - * If PM_RUNTIME is not defined, these 2 functions become helper - * functions to be called from system suspend/resume. - */ -#ifdef CONFIG_PM -static int qcom_slim_runtime_suspend(struct device *device) -{ - struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device); - int ret; - - dev_dbg(device, "pm_runtime: suspending...\n"); - ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED); - if (ret) { - dev_err(device, "clk pause not entered:%d", ret); - } else { - disable_irq(ctrl->irq); - clk_disable_unprepare(ctrl->hclk); - clk_disable_unprepare(ctrl->rclk); - } - return ret; -} - -static int qcom_slim_runtime_resume(struct device *device) -{ - struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device); - int ret = 0; - - dev_dbg(device, "pm_runtime: resuming...\n"); - ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0); - if (ret) - dev_err(device, "clk pause not exited:%d", ret); - return ret; -} -#endif - -#ifdef CONFIG_PM_SLEEP -static int qcom_slim_suspend(struct device *dev) -{ - int ret = 0; - - if (!pm_runtime_enabled(dev) || - (!pm_runtime_suspended(dev))) { - dev_dbg(dev, "system suspend"); - ret = qcom_slim_runtime_suspend(dev); - } - - return ret; -} - -static int qcom_slim_resume(struct device *dev) -{ - if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { - int ret; - - dev_dbg(dev, "system resume"); - ret = qcom_slim_runtime_resume(dev); - if (!ret) { - pm_runtime_mark_last_busy(dev); - pm_request_autosuspend(dev); - } - return ret; - - } - return 0; -} -#endif /* CONFIG_PM_SLEEP */ - -static const struct dev_pm_ops qcom_slim_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume) - SET_RUNTIME_PM_OPS( - qcom_slim_runtime_suspend, - qcom_slim_runtime_resume, - NULL - ) -}; - -static const struct of_device_id qcom_slim_dt_match[] = { - { .compatible = "qcom,slim", }, - {} -}; -MODULE_DEVICE_TABLE(of, qcom_slim_dt_match); - -static struct platform_driver qcom_slim_driver = { - .probe = qcom_slim_probe, - .remove = qcom_slim_remove, - .driver = { - .name = "qcom_slim_ctrl", - .of_match_table = qcom_slim_dt_match, - .pm = &qcom_slim_dev_pm_ops, - }, -}; -module_platform_driver(qcom_slim_driver); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("Qualcomm SLIMbus Controller"); -- cgit v1.2.3 From 8de0848447b9d94db3c09e6aea62181ac1329706 Mon Sep 17 00:00:00 2001 From: Ling Xu Date: Fri, 12 Sep 2025 14:12:59 +0100 Subject: dt-bindings: misc: qcom,fastrpc: Add GDSP label There are some products which support GDSP remoteprocs. GDSP is General Purpose DSP where tasks can be offloaded. There are 2 GDSPs named gdsp0 and gdsp1. Add "gdsp0" and "gdsp1" as the new supported labels for GDSP fastrpc domains. Acked-by: Krzysztof Kozlowski Reviewed-by: Ekansh Gupta Signed-off-by: Ling Xu Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20250912131302.303199-2-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml index 0840a3d92513..3f6199fc9ae6 100644 --- a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml +++ b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml @@ -27,6 +27,8 @@ properties: - sdsp - cdsp - cdsp1 + - gdsp0 + - gdsp1 memory-region: maxItems: 1 -- cgit v1.2.3 From 9b58f88a1f48b75e98ebb03490340c48b54cb804 Mon Sep 17 00:00:00 2001 From: Ciprian Costea Date: Fri, 12 Sep 2025 14:14:11 +0100 Subject: dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible. Signed-off-by: Ciprian Costea Signed-off-by: Dan Carpenter Reviewed-by: Rob Herring (Arm) Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20250912131415.303407-2-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file mode 100644 index 000000000000..8d46e7d28da6 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G OCOTP NVMEM driver + +maintainers: + - Ciprian Costea + +description: + The drivers provides an interface to access One Time + Programmable memory pages, such as TMU fuse values. + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-ocotp + - items: + - enum: + - nxp,s32g3-ocotp + - nxp,s32r45-ocotp + - const: nxp,s32g2-ocotp + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +allOf: + - $ref: nvmem.yaml# + +examples: + - | + nvmem@400a4000 { + compatible = "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; -- cgit v1.2.3 From 4a9b344e90c7ca654d7a469d0a467f90ef2add64 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 12 Sep 2025 14:14:13 +0100 Subject: dt-bindings: nvmem: sl28cpld: add sa67mcu compatible The Kontron SMARC-sAM67 has the same nvmem layout as the SMARC-sAL28. To To be prepared for any board specific quirks, add a specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20250912131415.303407-4-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml index c713e23819f1..afd1919c6b1c 100644 --- a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml +++ b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml @@ -19,7 +19,12 @@ select: false properties: compatible: - const: kontron,sl28-vpd + oneOf: + - items: + - enum: + - kontron,sa67-vpd + - const: kontron,sl28-vpd + - const: kontron,sl28-vpd serial-number: type: object -- cgit v1.2.3 From ddb095e81d60902d76be250fa5f7f1d1e32f65ec Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 12 Sep 2025 14:14:14 +0100 Subject: dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE Document support for Airoha AN8855 Switch EFUSE used to calibrate internal PHYs and store additional configuration info. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20250912131415.303407-5-srini@kernel.org Signed-off-by: Greg Kroah-Hartman --- .../bindings/nvmem/airoha,an8855-efuse.yaml | 123 +++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml b/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml new file mode 100644 index 000000000000..9802d9ea2176 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/airoha,an8855-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Switch EFUSE + +maintainers: + - Christian Marangi + +description: + Airoha AN8855 EFUSE used to calibrate internal PHYs and store additional + configuration info. + +$ref: nvmem.yaml# + +properties: + compatible: + const: airoha,an8855-efuse + + '#nvmem-cell-cells': + const: 0 + +required: + - compatible + - '#nvmem-cell-cells' + +unevaluatedProperties: false + +examples: + - | + efuse { + compatible = "airoha,an8855-efuse"; + + #nvmem-cell-cells = <0>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + shift_sel_port0_tx_a: shift-sel-port0-tx-a@c { + reg = <0xc 0x4>; + }; + + shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 { + reg = <0x10 0x4>; + }; + + shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 { + reg = <0x14 0x4>; + }; + + shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 { + reg = <0x18 0x4>; + }; + + shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c { + reg = <0x1c 0x4>; + }; + + shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 { + reg = <0x20 0x4>; + }; + + shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 { + reg = <0x24 0x4>; + }; + + shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 { + reg = <0x28 0x4>; + }; + + shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c { + reg = <0x2c 0x4>; + }; + + shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 { + reg = <0x30 0x4>; + }; + + shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 { + reg = <0x34 0x4>; + }; + + shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 { + reg = <0x38 0x4>; + }; + + shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c { + reg = <0x4c 0x4>; + }; + + shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 { + reg = <0x50 0x4>; + }; + + shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 { + reg = <0x54 0x4>; + }; + + shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 { + reg = <0x58 0x4>; + }; + + shift_sel_port4_tx_a: shift-sel-port4-tx-a@5c { + reg = <0x5c 0x4>; + }; + + shift_sel_port4_tx_b: shift-sel-port4-tx-b@60 { + reg = <0x60 0x4>; + }; + + shift_sel_port4_tx_c: shift-sel-port4-tx-c@64 { + reg = <0x64 0x4>; + }; + + shift_sel_port4_tx_d: shift-sel-port4-tx-d@68 { + reg = <0x68 0x4>; + }; + }; + }; -- cgit v1.2.3 From 49fce0730fd3c028982574c85eb2eb824d6e63f7 Mon Sep 17 00:00:00 2001 From: Markus Schneider-Pargmann Date: Wed, 10 Sep 2025 16:23:31 -0500 Subject: dt-bindings: serial: 8250_omap: Add wakeup pinctrl state Pins associated with the 8250 omap unit can be the source of a wakeup in deep sleep states. To be able to wakeup, these pins have to be configured in a special way. To support this configuration add the default and wakeup pinctrl states. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Kendall Willis Link: https://lore.kernel.org/r/20250910-uart-daisy-chain-8250-omap-v2-1-e90d44c1a9ac@ti.com Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/8250_omap.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/8250_omap.yaml b/Documentation/devicetree/bindings/serial/8250_omap.yaml index 1859f71297ff..aabacca2b2fa 100644 --- a/Documentation/devicetree/bindings/serial/8250_omap.yaml +++ b/Documentation/devicetree/bindings/serial/8250_omap.yaml @@ -71,6 +71,22 @@ properties: overrun-throttle-ms: true wakeup-source: true + pinctrl-0: + description: Default pinctrl state + + pinctrl-1: + description: Wakeup pinctrl state + + pinctrl-names: + description: + When present should contain at least "default" describing the default pin + states. The second state called "wakeup" describes the pins in their + wakeup configuration required to exit sleep states. + minItems: 1 + items: + - const: default + - const: wakeup + required: - compatible - reg -- cgit v1.2.3 From 5cacd26436a66e24b1f0335a5d2b71eed4ab0d74 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:23:17 +0100 Subject: dt-bindings: watchdog: renesas,wdt: Add support for RZ/T2H and RZ/N2H Extend the Renesas WDT device tree bindings to support the watchdog timer found on the RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The RZ/T2H WDT is mostly compatible with the one found on the RZ/V2H(P), but includes an additional register and differs in the clock division ratio settings for the WDTCR[CKS] field. To reflect these differences, introduce a new compatible string, "renesas,r9a09g077-wdt". The binding schema is updated accordingly. On RZ/T2H, the WDT does not require the "resets" property. It also requires two register regions and the presence of a "power-domains" property. The "clock-names" property is limited to a single entry, "pclk", for this SoC. The RZ/N2H SoC uses the same WDT IP as the RZ/T2H. It is supported by using "renesas,r9a09g087-wdt" as the primary compatible string, with "renesas,r9a09g077-wdt" listed as a fallback to describe the shared hardware features. Example: wdt0: watchdog@80082000 { compatible = "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, <0 0x81295100 0 0x04>; clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; clock-names = "pclk"; power-domains = <&cpg>; status = "disabled"; }; Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven Reviewed-by: Guenter Roeck Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- .../devicetree/bindings/watchdog/renesas,wdt.yaml | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 78874b90c88c..b6e60162c263 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -81,10 +81,17 @@ properties: - renesas,r9a09g056-wdt # RZ/V2N - const: renesas,r9a09g057-wdt # RZ/V2H(P) - - const: renesas,r9a09g057-wdt # RZ/V2H(P) + - enum: + - renesas,r9a09g057-wdt # RZ/V2H(P) + - renesas,r9a09g077-wdt # RZ/T2H + + - items: + - const: renesas,r9a09g087-wdt # RZ/N2H + - const: renesas,r9a09g077-wdt # RZ/T2H reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: minItems: 1 @@ -132,6 +139,7 @@ allOf: compatible: contains: enum: + - renesas,r9a09g077-wdt - renesas,rza-wdt - renesas,rzn1-wdt then: @@ -183,7 +191,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g057-wdt + enum: + - renesas,r9a09g057-wdt + - renesas,r9a09g077-wdt then: properties: interrupts: false @@ -192,6 +202,26 @@ allOf: required: - interrupts + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-wdt + then: + properties: + resets: false + clock-names: + maxItems: 1 + reg: + minItems: 2 + required: + - clock-names + - power-domains + else: + properties: + reg: + maxItems: 1 + additionalProperties: false examples: -- cgit v1.2.3 From 3e403c2faad9398fb70313f7cc0303c38f1ade9c Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 11 Sep 2025 23:21:01 +0200 Subject: dt-bindings: i2c: qcom-cci: Document QCM2290 compatible The CCI on QCM2290 is the interface for controlling camera sensor over I2C. It requires only two clocks. Signed-off-by: Loic Poulain Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 73144473b9b2..83b13370ff6c 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: + - qcom,qcm2290-cci - qcom,sc7280-cci - qcom,sc8280xp-cci - qcom,sdm670-cci @@ -44,11 +45,11 @@ properties: const: 0 clocks: - minItems: 3 + minItems: 2 maxItems: 6 clock-names: - minItems: 3 + minItems: 2 maxItems: 6 interrupts: @@ -113,6 +114,7 @@ allOf: then: properties: clocks: + minItems: 3 maxItems: 3 clock-names: items: @@ -120,6 +122,22 @@ allOf: - const: cci_ahb - const: cci + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-cci + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: ahb + - const: cci + - if: properties: compatible: -- cgit v1.2.3 From c62859e13712334bd17d46ee0c1b26e8673d2961 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 12 Sep 2025 23:19:25 +0800 Subject: dt-bindings: i2c: qcom-cci: Document sa8775p compatible Add the sa8775p CCI device string compatible. Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue Signed-off-by: Wenmeng Liu Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 83b13370ff6c..7456783d1f8e 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - qcom,qcm2290-cci + - qcom,sa8775p-cci - qcom,sc7280-cci - qcom,sc8280xp-cci - qcom,sdm670-cci @@ -241,6 +242,7 @@ allOf: compatible: contains: enum: + - qcom,sa8775p-cci - qcom,sm8550-cci - qcom,sm8650-cci - qcom,x1e80100-cci -- cgit v1.2.3 From 947e2d6414b3118bab920f1b0c27b4301dc5a361 Mon Sep 17 00:00:00 2001 From: Denzeel Oliva Date: Sun, 7 Sep 2025 22:13:38 +0000 Subject: dt-bindings: i2c: exynos5: Add exynos990-hsi2c compatible Add samsung,exynos990-hsi2c dedicated compatible for representing I2C of Exynos990 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Denzeel Oliva Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index 7ae8c7b1d006..6fc03281a8f8 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -38,6 +38,7 @@ properties: - google,gs101-hsi2c - samsung,exynos2200-hsi2c - samsung,exynos850-hsi2c + - samsung,exynos990-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 deprecated: true -- cgit v1.2.3 From f77a13df57e803fe574dd29c5454088fcc6f3285 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:29 +0200 Subject: dt-bindings: i2c: apple,i2c: Add apple,t6020-i2c compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,i2c" anymore [1]. Use "apple,t8103-i2c" as fallback compatible as it is the SoC the driver and bindings were written for. This block is compatible with t8103, so just add the new per-SoC compatible using apple,t8103-i2c as base. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Signed-off-by: Janne Grunau Acked-by: Andi Shyti Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/apple,i2c.yaml | 27 +++++++++++++--------- 1 file changed, 16 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index fed3e1b8c43f..500a965bdb7a 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -20,17 +20,22 @@ allOf: properties: compatible: - items: - - enum: - - apple,s5l8960x-i2c - - apple,t7000-i2c - - apple,s8000-i2c - - apple,t8010-i2c - - apple,t8015-i2c - - apple,t8103-i2c - - apple,t8112-i2c - - apple,t6000-i2c - - const: apple,i2c + oneOf: + - items: + - const: apple,t6020-i2c + - const: apple,t8103-i2c + - items: + - enum: + # Do not add additional SoC to this list. + - apple,s5l8960x-i2c + - apple,t7000-i2c + - apple,s8000-i2c + - apple,t8010-i2c + - apple,t8015-i2c + - apple,t8103-i2c + - apple,t8112-i2c + - apple,t6000-i2c + - const: apple,i2c reg: maxItems: 1 -- cgit v1.2.3 From 69329daf16af7d0ec189a760f28ea6a1ffb7f23a Mon Sep 17 00:00:00 2001 From: Akhil R Date: Mon, 18 Aug 2025 10:03:44 +0530 Subject: dt-bindings: i2c: nvidia,tegra20-i2c: Add Tegra256 I2C compatible Add compatible for Tegra256 I2C controllers. Tegra256 consists of 8 generic Tegra I2C controllers similar to previous generations. The parent clock frequency is different in these controllers and hence the timing parameter values are different from the previous ones. Signed-off-by: Akhil R Acked-by: Rob Herring (Arm) Acked-by: Thierry Reding Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 6b6f6762d122..32c3b69ccf34 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -80,6 +80,11 @@ properties: support for 64 KiB transactions whereas earlier chips supported no more than 4 KiB per transactions. const: nvidia,tegra194-i2c + - description: | + Tegra256 has 8 generic I2C controllers. The controllers are similar to + the previous generations, but have a different parent clock and hence + the timing parameters are configured differently. + const: nvidia,tegra256-i2c reg: maxItems: 1 @@ -186,6 +191,7 @@ allOf: contains: enum: - nvidia,tegra194-i2c + - nvidia,tegra256-i2c then: required: - resets -- cgit v1.2.3 From 3456820e01f9b40167e8438f5a43c76e4361c2d6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 9 Sep 2025 09:23:38 -0500 Subject: dt-bindings: net: Drop duplicate brcm,bcm7445-switch-v4.0.txt The brcm,bcm7445-switch-v4.0.txt binding is already covered by dsa/brcm,sf2.yaml. The listed deprecated properties aren't used anywhere either. Signed-off-by: Rob Herring (Arm) Acked-by: Florian Fainelli Link: https://patch.msgid.link/20250909142339.3219200-2-robh@kernel.org Signed-off-by: Jakub Kicinski --- .../bindings/net/brcm,bcm7445-switch-v4.0.txt | 50 ---------------------- 1 file changed, 50 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt b/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt deleted file mode 100644 index 284cddb3118e..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Broadcom Starfighter 2 integrated switch - -See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation. - -*Deprecated* binding required properties: - -- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt -- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt -- #address-cells: must be 2, see dsa/dsa.txt - -Example using the old DSA DeviceTree binding: - -switch_top@f0b00000 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0 0xf0b00000 0x40804>; - - ethernet_switch@0 { - compatible = "brcm,bcm7445-switch-v4.0"; - #size-cells = <0>; - #address-cells = <2>; - reg = <0x0 0x40000 - 0x40000 0x110 - 0x40340 0x30 - 0x40380 0x30 - 0x40400 0x34 - 0x40600 0x208>; - interrupts = <0 0x18 0 - 0 0x19 0>; - brcm,num-gphy = <1>; - brcm,num-rgmii-ports = <2>; - brcm,fcb-pause-override; - brcm,acb-packets-inflight; - - ... - switch@0 { - reg = <0 0>; - #size-cells = <0>; - #address-cells = <1>; - - port@0 { - label = "gphy"; - reg = <0>; - brcm,use-bcm-hdr; - }; - ... - }; - }; -}; -- cgit v1.2.3 From 0f610e650d4e979490ccfa4c22ca29ca547f41e7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:05 +0800 Subject: dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../bindings/clock/allwinner,sun55i-a523-ccu.yaml | 37 ++++++++++++++- include/dt-bindings/clock/sun55i-a523-mcu-ccu.h | 54 ++++++++++++++++++++++ include/dt-bindings/reset/sun55i-a523-mcu-ccu.h | 30 ++++++++++++ 3 files changed, 119 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/sun55i-a523-mcu-ccu.h create mode 100644 include/dt-bindings/reset/sun55i-a523-mcu-ccu.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml index f5f62e9a10a1..58be701a720e 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-mcu-ccu - allwinner,sun55i-a523-r-ccu reg: @@ -26,11 +27,11 @@ properties: clocks: minItems: 4 - maxItems: 5 + maxItems: 9 clock-names: minItems: 4 - maxItems: 5 + maxItems: 9 required: - "#clock-cells" @@ -63,6 +64,38 @@ allOf: - const: iosc - const: losc-fanout + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-mcu-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Audio PLL (4x) + - description: Peripherals PLL 0 (300 MHz output) + - description: DSP module clock + - description: MBUS clock + - description: PRCM AHB clock + - description: PRCM APB0 clock + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-audio0-4x + - const: pll-periph0-300m + - const: dsp + - const: mbus + - const: r-ahb + - const: r-apb0 + - if: properties: compatible: diff --git a/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..6efc6bc7e11a --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ + +#define CLK_MCU_PLL_AUDIO1 0 +#define CLK_MCU_PLL_AUDIO1_DIV2 1 +#define CLK_MCU_PLL_AUDIO1_DIV5 2 +#define CLK_MCU_AUDIO_OUT 3 +#define CLK_MCU_DSP 4 +#define CLK_MCU_I2S0 5 +#define CLK_MCU_I2S1 6 +#define CLK_MCU_I2S2 7 +#define CLK_MCU_I2S3 8 +#define CLK_MCU_I2S3_ASRC 9 +#define CLK_BUS_MCU_I2S0 10 +#define CLK_BUS_MCU_I2S1 11 +#define CLK_BUS_MCU_I2S2 12 +#define CLK_BUS_MCU_I2S3 13 +#define CLK_MCU_SPDIF_TX 14 +#define CLK_MCU_SPDIF_RX 15 +#define CLK_BUS_MCU_SPDIF 16 +#define CLK_MCU_DMIC 17 +#define CLK_BUS_MCU_DMIC 18 +#define CLK_MCU_AUDIO_CODEC_DAC 19 +#define CLK_MCU_AUDIO_CODEC_ADC 20 +#define CLK_BUS_MCU_AUDIO_CODEC 21 +#define CLK_BUS_MCU_DSP_MSGBOX 22 +#define CLK_BUS_MCU_DSP_CFG 23 +#define CLK_BUS_MCU_NPU_HCLK 24 +#define CLK_BUS_MCU_NPU_ACLK 25 +#define CLK_MCU_TIMER0 26 +#define CLK_MCU_TIMER1 27 +#define CLK_MCU_TIMER2 28 +#define CLK_MCU_TIMER3 29 +#define CLK_MCU_TIMER4 30 +#define CLK_MCU_TIMER5 31 +#define CLK_BUS_MCU_TIMER 32 +#define CLK_BUS_MCU_DMA 33 +#define CLK_MCU_TZMA0 34 +#define CLK_MCU_TZMA1 35 +#define CLK_BUS_MCU_PUBSRAM 36 +#define CLK_MCU_MBUS_DMA 37 +#define CLK_MCU_MBUS 38 +#define CLK_MCU_RISCV 39 +#define CLK_BUS_MCU_RISCV_CFG 40 +#define CLK_BUS_MCU_RISCV_MSGBOX 41 +#define CLK_MCU_PWM0 42 +#define CLK_BUS_MCU_PWM0 43 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..a89a0b44f08b --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ + +#define RST_BUS_MCU_I2S0 0 +#define RST_BUS_MCU_I2S1 1 +#define RST_BUS_MCU_I2S2 2 +#define RST_BUS_MCU_I2S3 3 +#define RST_BUS_MCU_SPDIF 4 +#define RST_BUS_MCU_DMIC 5 +#define RST_BUS_MCU_AUDIO_CODEC 6 +#define RST_BUS_MCU_DSP_MSGBOX 7 +#define RST_BUS_MCU_DSP_CFG 8 +#define RST_BUS_MCU_NPU 9 +#define RST_BUS_MCU_TIMER 10 +#define RST_BUS_MCU_DSP_DEBUG 11 +#define RST_BUS_MCU_DSP 12 +#define RST_BUS_MCU_DMA 13 +#define RST_BUS_MCU_PUBSRAM 14 +#define RST_BUS_MCU_RISCV_CFG 15 +#define RST_BUS_MCU_RISCV_DEBUG 16 +#define RST_BUS_MCU_RISCV_CORE 17 +#define RST_BUS_MCU_RISCV_MSGBOX 18 +#define RST_BUS_MCU_PWM0 19 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ */ -- cgit v1.2.3 From db5796c5c5c6db72339e818b54e6a2e043f7032c Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:30 +0200 Subject: dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings The NetCube Systems Nagami is an System on Module base on the Allwinner T113s SoC. It is intended to be used in low cost devices which require simple layouts and low BOM cost. The NetCube Systems Nagami Basic Carrier Board is a simple carrier for the Nagami SoM. It is intended to serve as a simple reference design for a custom implementation or just evaluating the module with other peripherals The NetCube Systems Nagami Keypad Carrier is a custom board intended to fit a standard Ritto Intercom enclosure and provides a Keypad, NFC-Reader and Status-LED all controllable over Ethernet with PoE support. Signed-off-by: Lukas Schmid Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250831162536.2380589-2-lukas.schmid@netcube.li Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c25a22fe4d25..72ef861a0b68 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -595,6 +595,14 @@ properties: - const: netcube,kumquat - const: allwinner,sun8i-v3s + - description: NetCube Systems Nagami SoM based boards + items: + - enum: + - netcube,nagami-basic-carrier + - netcube,nagami-keypad-carrier + - const: netcube,nagami + - const: allwinner,sun8i-t113s + - description: NextThing Co. CHIP items: - const: nextthing,chip -- cgit v1.2.3 From a29d1137efd9c20b6801caf14f3b7a1053e75839 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Mon, 8 Sep 2025 07:35:23 +0000 Subject: dt-bindings: iio: adc: add ade9000 Add devicetree bindings support for ade9000. Signed-off-by: Antoniu Miclaus Reviewed-by: Conor Dooley Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/adi,ade9000.yaml | 95 ++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ade9000.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ade9000.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ade9000.yaml new file mode 100644 index 000000000000..bd429552d568 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ade9000.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ade9000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADE9000 High Performance, Polyphase Energy Metering + +maintainers: + - Antoniu Miclaus + +description: | + The ADE9000 is a highly accurate, fully integrated, multiphase energy and power + quality monitoring device. Superior analog performance and a digital signal + processing (DSP) core enable accurate energy monitoring over a wide dynamic + range. An integrated high end reference ensures low drift over temperature + with a combined drift of less than ±25 ppm/°C maximum for the entire channel + including a programmable gain amplifier (PGA) and an analog-to-digital + converter (ADC). + + https://www.analog.com/media/en/technical-documentation/data-sheets/ADE9000.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ade9000 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 20000000 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + enum: [irq0, irq1, dready] + minItems: 1 + maxItems: 3 + + reset-gpios: + description: + Must be the device tree identifier of the RESET pin. As the line is + active low, it should be marked GPIO_ACTIVE_LOW. + maxItems: 1 + + vdd-supply: true + + vref-supply: true + + clocks: + description: External clock source when not using crystal + maxItems: 1 + + + "#clock-cells": + description: + ADE9000 can provide clock output via CLKOUT pin with external buffer. + const: 0 + +required: + - compatible + - reg + - vdd-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ade9000"; + reg = <0>; + spi-max-frequency = <7000000>; + + #clock-cells = <0>; + reset-gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>, <3 IRQ_TYPE_EDGE_FALLING>, <4 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "irq0", "irq1", "dready"; + interrupt-parent = <&gpio>; + clocks = <&ext_clock_24576khz>; + vdd-supply = <&vdd_reg>; + }; + }; -- cgit v1.2.3 From 0f06e28747b3d896b9c71c2a7e9f48061755162b Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Thu, 11 Sep 2025 14:43:44 +0200 Subject: dt-bindings: mfd: 88pm886: Add #io-channel-cells MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an #io-channel-cells property to the Marvell 88PM886 PMIC binding to allow referencing the IO channels exposed by its GPADC. Acked-by: Karel Balej # for the PMIC Acked-by: Krzysztof Kozlowski Signed-off-by: Duje Mihanović Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml b/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml index d6a71c912b76..92a72a99fd79 100644 --- a/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml +++ b/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml @@ -35,6 +35,9 @@ properties: description: LDO or buck regulator. unevaluatedProperties: false + '#io-channel-cells': + const: 1 + required: - compatible - reg @@ -53,6 +56,7 @@ examples: reg = <0x30>; interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; + #io-channel-cells = <1>; wakeup-source; regulators { -- cgit v1.2.3 From d43ce98223496e68bf8f12b42325e39ea5ae7247 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 8 Sep 2025 11:58:59 +0100 Subject: dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/T2H and RZ/N2H SoCs Add device tree binding support for the Gigabit Ethernet MAC (GMAC) IP on Renesas RZ/T2H and RZ/N2H SoCs. While these SoCs use the same Synopsys DesignWare MAC version 5.20 as RZ/V2H, they are synthesized with different hardware configurations. Add new compatible strings "renesas,r9a09g077-gbeth" for RZ/T2H and "renesas,r9a09g087-gbeth" for RZ/N2H, with the latter using RZ/T2H as fallback since they share identical GMAC IP. Update the schema to handle hardware differences between SoC variants. RZ/T2H requires only 3 clocks compared to 7 on RZ/V2H, supports 8 RX/TX queue pairs instead of 4, and needs 2 reset controls with reset-names property versus a single unnamed reset. RZ/T2H also has the split header feature enabled which is disabled on RZ/V2H. Add support for an optional pcs-handle property to connect the GMAC to the MIIC PCS converter on RZ/T2H. Use conditional schema validation to enforce the correct clock, reset, and interrupt configurations per SoC variant. Extend the base snps,dwmac.yaml schema to accommodate the increased interrupt count, supporting up to 19 interrupts and extending the rx-queue and tx-queue interrupt name patterns to cover queues 0-7. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250908105901.3198975-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski --- .../bindings/net/renesas,rzv2h-gbeth.yaml | 178 ++++++++++++++++----- .../devicetree/bindings/net/snps,dwmac.yaml | 9 +- 2 files changed, 143 insertions(+), 44 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index 23e39bcea96b..bd53ab300f50 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -17,63 +17,111 @@ select: - renesas,r9a09g047-gbeth - renesas,r9a09g056-gbeth - renesas,r9a09g057-gbeth + - renesas,r9a09g077-gbeth + - renesas,r9a09g087-gbeth - renesas,rzv2h-gbeth required: - compatible properties: compatible: - items: - - enum: - - renesas,r9a09g047-gbeth # RZ/G3E - - renesas,r9a09g056-gbeth # RZ/V2N - - renesas,r9a09g057-gbeth # RZ/V2H(P) - - const: renesas,rzv2h-gbeth - - const: snps,dwmac-5.20 + oneOf: + - items: + - enum: + - renesas,r9a09g047-gbeth # RZ/G3E + - renesas,r9a09g056-gbeth # RZ/V2N + - renesas,r9a09g057-gbeth # RZ/V2H(P) + - const: renesas,rzv2h-gbeth + - const: snps,dwmac-5.20 + - items: + - const: renesas,r9a09g077-gbeth # RZ/T2H + - const: snps,dwmac-5.20 + - items: + - const: renesas,r9a09g087-gbeth # RZ/N2H + - const: renesas,r9a09g077-gbeth + - const: snps,dwmac-5.20 reg: maxItems: 1 clocks: - items: - - description: CSR clock - - description: AXI system clock - - description: PTP clock - - description: TX clock - - description: RX clock - - description: TX clock phase-shifted by 180 degrees - - description: RX clock phase-shifted by 180 degrees + oneOf: + - items: + - description: CSR clock + - description: AXI system clock + - description: PTP clock + - description: TX clock + - description: RX clock + - description: TX clock phase-shifted by 180 degrees + - description: RX clock phase-shifted by 180 degrees + - items: + - description: CSR clock + - description: AXI system clock + - description: TX clock clock-names: - items: - - const: stmmaceth - - const: pclk - - const: ptp_ref - - const: tx - - const: rx - - const: tx-180 - - const: rx-180 - - interrupts: - minItems: 11 + oneOf: + - items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: tx + - const: rx + - const: tx-180 + - const: rx-180 + - items: + - const: stmmaceth + - const: pclk + - const: tx interrupt-names: - items: - - const: macirq - - const: eth_wake_irq - - const: eth_lpi - - const: rx-queue-0 - - const: rx-queue-1 - - const: rx-queue-2 - - const: rx-queue-3 - - const: tx-queue-0 - - const: tx-queue-1 - - const: tx-queue-2 - - const: tx-queue-3 + oneOf: + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: rx-queue-4 + - const: rx-queue-5 + - const: rx-queue-6 + - const: rx-queue-7 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: tx-queue-4 + - const: tx-queue-5 + - const: tx-queue-6 + - const: tx-queue-7 resets: - items: - - description: AXI power-on system reset + oneOf: + - items: + - description: AXI power-on system reset + - items: + - description: AXI power-on system reset + - description: AHB reset + + pcs-handle: + description: + phandle pointing to a PCS sub-node compatible with + Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml# + (Refer RZ/T2H portion in the DT-binding file) required: - compatible @@ -87,6 +135,56 @@ required: allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-gbeth + then: + properties: + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + interrupts: + minItems: 19 + + interrupt-names: + minItems: 19 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + required: + - reset-names + else: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + + interrupts: + minItems: 11 + maxItems: 11 + + interrupt-names: + minItems: 11 + maxItems: 11 + + resets: + maxItems: 1 + + pcs-handle: false + + reset-names: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 4e3cbaa06229..658c004e6a5c 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -75,6 +75,7 @@ properties: - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos - renesas,r9a06g032-gmac + - renesas,r9a09g077-gbeth - renesas,rzn1-gmac - renesas,rzv2h-gbeth - rockchip,px30-gmac @@ -118,11 +119,11 @@ properties: interrupts: minItems: 1 - maxItems: 11 + maxItems: 19 interrupt-names: minItems: 1 - maxItems: 11 + maxItems: 19 items: oneOf: - description: Combined signal for various interrupt events @@ -134,9 +135,9 @@ properties: - description: The interrupt that occurs when HW safety error triggered const: sfty - description: Per channel receive completion interrupt - pattern: '^rx-queue-[0-3]$' + pattern: '^rx-queue-[0-7]$' - description: Per channel transmit completion interrupt - pattern: '^tx-queue-[0-3]$' + pattern: '^tx-queue-[0-7]$' clocks: minItems: 1 -- cgit v1.2.3 From e13f988c4591eed99f5f34d396458f315f0f5651 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:21 +0200 Subject: dt-bindings: arm: apple: apple,pmgr: Add t6020-pmgr compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,pmgr" anymore [1]. Use "apple,t8103-pmgr" as base compatible as it is the SoC the bindings were written for. The block on Apple M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-pmgr" so use it as fallback compatible and add t6020 as per-SoC compatible. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Krzysztof Kozlowski Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- .../devicetree/bindings/arm/apple/apple,pmgr.yaml | 33 +++++++++++++--------- 1 file changed, 20 insertions(+), 13 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index 5001f4d5a0dc..b88f41a225a3 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -20,19 +20,26 @@ properties: pattern: "^power-management@[0-9a-f]+$" compatible: - items: - - enum: - - apple,s5l8960x-pmgr - - apple,t7000-pmgr - - apple,s8000-pmgr - - apple,t8010-pmgr - - apple,t8015-pmgr - - apple,t8103-pmgr - - apple,t8112-pmgr - - apple,t6000-pmgr - - const: apple,pmgr - - const: syscon - - const: simple-mfd + oneOf: + - items: + - enum: + # Do not add additional SoC to this list. + - apple,s5l8960x-pmgr + - apple,t7000-pmgr + - apple,s8000-pmgr + - apple,t8010-pmgr + - apple,t8015-pmgr + - apple,t8103-pmgr + - apple,t8112-pmgr + - apple,t6000-pmgr + - const: apple,pmgr + - const: syscon + - const: simple-mfd + - items: + - const: apple,t6020-pmgr + - const: apple,t8103-pmgr + - const: syscon + - const: simple-mfd reg: maxItems: 1 -- cgit v1.2.3 From 48553ae8cc09ca7f720b20f7253d528cb8052847 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:23 +0200 Subject: dt-bindings: power: apple,pmgr-pwrstate: Add t6020 compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,pmgr-pwrstate" anymore [1]. Use "apple,t8103-pmgr-pwrstate" as base compatible as it is the SoC the driver and bindings were written for. The implementation on Apple M2 Pro/Max/Ultra SoCs is compatible so add its per-SoC compatible with the new base. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- .../bindings/power/apple,pmgr-pwrstate.yaml | 27 +++++++++++++--------- 1 file changed, 16 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 6e9a670eaf56..caf151880999 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -29,17 +29,22 @@ description: | properties: compatible: - items: - - enum: - - apple,s5l8960x-pmgr-pwrstate - - apple,t7000-pmgr-pwrstate - - apple,s8000-pmgr-pwrstate - - apple,t8010-pmgr-pwrstate - - apple,t8015-pmgr-pwrstate - - apple,t8103-pmgr-pwrstate - - apple,t8112-pmgr-pwrstate - - apple,t6000-pmgr-pwrstate - - const: apple,pmgr-pwrstate + oneOf: + - items: + - enum: + # Do not add additional SoC to this list. + - apple,s5l8960x-pmgr-pwrstate + - apple,t7000-pmgr-pwrstate + - apple,s8000-pmgr-pwrstate + - apple,t8010-pmgr-pwrstate + - apple,t8015-pmgr-pwrstate + - apple,t8103-pmgr-pwrstate + - apple,t8112-pmgr-pwrstate + - apple,t6000-pmgr-pwrstate + - const: apple,pmgr-pwrstate + - items: + - const: apple,t6020-pmgr-pwrstate + - const: apple,t8103-pmgr-pwrstate reg: maxItems: 1 -- cgit v1.2.3 From 5a606b577cba2326e122811ab5130ff56568902f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:24 +0200 Subject: dt-bindings: cpufreq: apple,cluster-cpufreq: Add t6020 compatible The CPU frequency control on M2 Pro/Max/Ultra SoCs is compatible to the M2 (T8112) one. So add this with the per-SoC compatible to the bindings. Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml b/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml index 896276b8c6bb..b51913a81791 100644 --- a/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml +++ b/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml @@ -35,6 +35,9 @@ properties: - const: apple,t7000-cluster-cpufreq - const: apple,s5l8960x-cluster-cpufreq - const: apple,s5l8960x-cluster-cpufreq + - items: + - const: apple,t6020-cluster-cpufreq + - const: apple,t8112-cluster-cpufreq reg: maxItems: 1 -- cgit v1.2.3 From 0b95df9004b150c38cf9177735c39a51fff00561 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:25 +0200 Subject: dt-bindings: interrupt-controller: apple,aic2: Add apple,t6020-aic compatible The Apple M2 Pro/Max/Ultra SoCs use AIC2 as interrupt controller. This is the final SoC added as compatible as Apple M3 and later use AIC3. Apple's A15 uses AIC2 as well but has no official support for alternate operating systems. Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml index 2bde6cc6fe0a..ee5a0dfff437 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -34,6 +34,7 @@ properties: - enum: - apple,t8112-aic - apple,t6000-aic + - apple,t6020-aic - const: apple,aic2 interrupt-controller: true -- cgit v1.2.3 From 874c90221e261b7a778f6beacd3d5f7e9a701a64 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:26 +0200 Subject: dt-bindings: iommu: dart: Add apple,t6020-dart compatible t6020-dart is compatible to t8110-dart and annotated as such in Apple's device tree. Add its per-SoC compatible in case t6020 specific handling becomes necessary. The dart instances on M2 Pro/Max/Ultra based SoCs differ in one aspect from the M2 based ones. They indicate an IAS of 42 requiring implementing support for a fouth page table level in the dart driver and its io-pgtable [1]. [1]: https://lore.kernel.org/asahi/20250821-apple-dart-4levels-v2-0-e39af79daa37@jannau.net/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/iommu/apple,dart.yaml | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Documentation/devicetree/bindings/iommu/apple,dart.yaml index 7adb1de455a5..47ec7fa52c3a 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -22,11 +22,15 @@ description: |+ properties: compatible: - enum: - - apple,t8103-dart - - apple,t8103-usb4-dart - - apple,t8110-dart - - apple,t6000-dart + oneOf: + - enum: + - apple,t8103-dart + - apple,t8103-usb4-dart + - apple,t8110-dart + - apple,t6000-dart + - items: + - const: apple,t6020-dart + - const: apple,t8110-dart reg: maxItems: 1 -- cgit v1.2.3 From aa5272300c5acaef878d32205b3b3bfd80084c14 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:28 +0200 Subject: dt-bindings: pinctrl: apple,pinctrl: Add apple,t6020-pinctrl compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,pinctrl" anymore [1]. Use "apple,t8103-pinctrl" as fallback compatible as it is the SoC the driver and bindings were written for. The M2 Pro/Max/Ultra SoCs use the same pinctrl hardware, so just add its per-SoC compatible using the new base as fallback. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Linus Walleij Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- .../devicetree/bindings/pinctrl/apple,pinctrl.yaml | 27 +++++++++++++--------- 1 file changed, 16 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 63737d858944..665ec79a69f1 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -16,17 +16,22 @@ description: | properties: compatible: - items: - - enum: - - apple,s5l8960x-pinctrl - - apple,t7000-pinctrl - - apple,s8000-pinctrl - - apple,t8010-pinctrl - - apple,t8015-pinctrl - - apple,t8103-pinctrl - - apple,t8112-pinctrl - - apple,t6000-pinctrl - - const: apple,pinctrl + oneOf: + - items: + - const: apple,t6020-pinctrl + - const: apple,t8103-pinctrl + - items: + # Do not add additional SoC to this list. + - enum: + - apple,s5l8960x-pinctrl + - apple,t7000-pinctrl + - apple,s8000-pinctrl + - apple,t8010-pinctrl + - apple,t8015-pinctrl + - apple,t8103-pinctrl + - apple,t8112-pinctrl + - apple,t6000-pinctrl + - const: apple,pinctrl reg: maxItems: 1 -- cgit v1.2.3 From 9f601db6a1c0c7e191f7948a18f9daedde009836 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:30 +0200 Subject: dt-bindings: mailbox: apple,mailbox: Add t6020 compatible The mailbox hardware remains unchanged on M2 Pro/Max/Ultra SoCs so just add its per-SoC compatible. Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index bdf58f03b848..28985cc62c25 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -31,6 +31,7 @@ properties: - apple,t8103-asc-mailbox - apple,t8112-asc-mailbox - apple,t6000-asc-mailbox + - apple,t6020-asc-mailbox - const: apple,asc-mailbox-v4 - description: -- cgit v1.2.3 From c7a4fe4086ad5fabb1ca8a8bd3f02e728eab1eb9 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:31 +0200 Subject: dt-bindings: gpu: apple,agx: Add agx-{g14s,g14c,g14d} compatibles Add compatibles for the GPU variants found on Apple's M2 Pro/Max/Ultra SoCs. Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/gpu/apple,agx.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/apple,agx.yaml b/Documentation/devicetree/bindings/gpu/apple,agx.yaml index 51629b3833b0..05af942ad174 100644 --- a/Documentation/devicetree/bindings/gpu/apple,agx.yaml +++ b/Documentation/devicetree/bindings/gpu/apple,agx.yaml @@ -16,11 +16,17 @@ properties: - apple,agx-g13g - apple,agx-g13s - apple,agx-g14g + - apple,agx-g14s - items: - enum: - apple,agx-g13c - apple,agx-g13d - const: apple,agx-g13s + - items: + - enum: + - apple,agx-g14c + - apple,agx-g14d + - const: apple,agx-g14s reg: items: -- cgit v1.2.3 From 9d7b6d117df245721902a497d90da220d7c27ee5 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:32 +0200 Subject: dt-bindings: iommu: apple,sart: Add apple,t6020-sart compatible "apple,t6020-sart" as found in Apple's M2 Pro/Max/Ultra SoCs is compatible with SART3 used in t6000. Add its per-SoC compatible to allow a distinction should it become necessary. Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/iommu/apple,sart.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/apple,sart.yaml b/Documentation/devicetree/bindings/iommu/apple,sart.yaml index c8c62f329882..88e66d4b13c6 100644 --- a/Documentation/devicetree/bindings/iommu/apple,sart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,sart.yaml @@ -30,7 +30,9 @@ properties: compatible: oneOf: - items: - - const: apple,t8112-sart + - enum: + - apple,t6020-sart + - apple,t8112-sart - const: apple,t6000-sart - enum: - apple,t6000-sart -- cgit v1.2.3 From a3ee3333467c076a1f0655dbe6d4950af360c3a5 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:34 +0200 Subject: dt-bindings: nvme: apple: Add apple,t6020-nvme-ans2 compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,nvme-ans2" anymore [1]. Add "apple,t8103-nvme-ans2" as fallback compatible as it is the SoC the driver and bindings were written for. Invert the condition for the 2 or 3 power-domains check to allow using "apple,t8103-nvme-ans2" as base compatible. "apple,t6020-nvme-ans2" on Apple M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-nvme-ans2" so add its per-SoC compatible. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- .../devicetree/bindings/nvme/apple,nvme-ans.yaml | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml index 4127d7b0a0f0..4c0b1f90aff8 100644 --- a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml +++ b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml @@ -13,8 +13,12 @@ properties: compatible: oneOf: - const: apple,t8015-nvme-ans2 + - items: + - const: apple,t6020-nvme-ans2 + - const: apple,t8103-nvme-ans2 - items: - enum: + # Do not add additional SoC to this list. - apple,t8103-nvme-ans2 - apple,t8112-nvme-ans2 - apple,t6000-nvme-ans2 @@ -69,21 +73,20 @@ if: compatible: contains: enum: - - apple,t8015-nvme-ans2 - - apple,t8103-nvme-ans2 - - apple,t8112-nvme-ans2 + - apple,t6000-nvme-ans2 + - apple,t6020-nvme-ans2 then: properties: power-domains: - maxItems: 2 + minItems: 3 power-domain-names: - maxItems: 2 + minItems: 3 else: properties: power-domains: - minItems: 3 + maxItems: 2 power-domain-names: - minItems: 3 + maxItems: 2 required: - compatible -- cgit v1.2.3 From ef4d6ea11df035d742d4ef4ba21fbe401fc05d86 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:35 +0200 Subject: dt-bindings: net: bcm4377-bluetooth: Add BCM4388 compatible Add BCM4388 PCI vendor/product ID as compatible. The BCM4388 WiFi/BT module is found on Apple silicon devices with M2 Pro/Max/Ultra and later. Support for this variant was added in 2024 without amending the dt-bindings. Link: https://lore.kernel.org/asahi/20240602-btbcm4388-v1-1-210e4b4eeb3b@svenpeter.dev/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- .../devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml b/Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml index 37cb39a3a62e..fd78258d71b4 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml @@ -23,6 +23,7 @@ properties: - pci14e4,5fa0 # BCM4377 - pci14e4,5f69 # BCM4378 - pci14e4,5f71 # BCM4387 + - pci14e4,5f72 # BCM4388 reg: maxItems: 1 -- cgit v1.2.3 From 4fb80f2f90d6882ead09d5333dee82ec8df580b0 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:36 +0200 Subject: dt-bindings: net: bcm4329-fmac: Add BCM4388 PCI compatible BCM4388 WiFi/BT modules are found on Apple silicon devices using M2 Pro/Max/Ultra and later. Driver support for this module is not submitted yet. Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml index 7c8100e59a6c..3be757678764 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml @@ -53,6 +53,7 @@ properties: - pci14e4,4488 # BCM4377 - pci14e4,4425 # BCM4378 - pci14e4,4433 # BCM4387 + - pci14e4,4434 # BCM4388 - pci14e4,449d # BCM43752 reg: -- cgit v1.2.3 From b7e4229a5a2c9c25be4acf99153071779864be95 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:38 +0200 Subject: dt-bindings: mfd: apple,smc: Add t6020-smc compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,smc" anymore [1]. Use "apple,t8103-smc" as base compatible as it is the SoC the driver and bindings were written for. SMC on Apple's M2 Pro/Max/Ultra SoCs is compatible with the existing driver so add its per-SoC compatible with the new base compatible as fallback used by the driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/mfd/apple,smc.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/apple,smc.yaml b/Documentation/devicetree/bindings/mfd/apple,smc.yaml index 8a10e270d421..5429538f7e2e 100644 --- a/Documentation/devicetree/bindings/mfd/apple,smc.yaml +++ b/Documentation/devicetree/bindings/mfd/apple,smc.yaml @@ -15,12 +15,17 @@ description: properties: compatible: - items: - - enum: - - apple,t6000-smc - - apple,t8103-smc - - apple,t8112-smc - - const: apple,smc + oneOf: + - items: + - const: apple,t6020-smc + - const: apple,t8103-smc + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t6000-smc + - apple,t8103-smc + - apple,t8112-smc + - const: apple,smc reg: items: -- cgit v1.2.3 From 006d3506094ce32984d53001b502826b8fe410d3 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:41 +0200 Subject: dt-bindings: spmi: apple,spmi: Add t6020-spmi compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,spmi" anymore [1]. Use "apple,t8103-spmi" as base compatible as it is the SoC the driver and bindings were written for. The SPMI controller on Apple M2 Pro/Max/Ultra is compatible to "apple,t8103-spmi" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/spmi/apple,spmi.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml index 16bd7eb2b7af..dbf09ad0ecde 100644 --- a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml @@ -16,12 +16,17 @@ allOf: properties: compatible: - items: - - enum: - - apple,t8103-spmi - - apple,t6000-spmi - - apple,t8112-spmi - - const: apple,spmi + oneOf: + - items: + - const: apple,t6020-spmi + - const: apple,t8103-spmi + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t8103-spmi + - apple,t6000-spmi + - apple,t8112-spmi + - const: apple,spmi reg: maxItems: 1 -- cgit v1.2.3 From 5410df1a5a4b1d23abcb0dfe1b43c9745b731749 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:43 +0200 Subject: dt-bindings: watchdog: apple,wdt: Add t6020-wdt compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,wdt" anymore [1]. Use "apple,t8103-wdt" as base compatible as it is the SoC the driver and bindings were written for. The block on the Apple M2 Pro/Max/Ultra SoCs is compatible with the existing driver so add its per-SoC compatible. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- .../devicetree/bindings/watchdog/apple,wdt.yaml | 27 +++++++++++++--------- 1 file changed, 16 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml index 310832fa8c28..05602678c070 100644 --- a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -14,17 +14,22 @@ allOf: properties: compatible: - items: - - enum: - - apple,s5l8960x-wdt - - apple,t7000-wdt - - apple,s8000-wdt - - apple,t8010-wdt - - apple,t8015-wdt - - apple,t8103-wdt - - apple,t8112-wdt - - apple,t6000-wdt - - const: apple,wdt + oneOf: + - items: + - const: apple,t6020-wdt + - const: apple,t8103-wdt + - items: + - enum: + # Do not add additional SoC to this list. + - apple,s5l8960x-wdt + - apple,t7000-wdt + - apple,s8000-wdt + - apple,t8010-wdt + - apple,t8015-wdt + - apple,t8103-wdt + - apple,t8112-wdt + - apple,t6000-wdt + - const: apple,wdt reg: maxItems: 1 -- cgit v1.2.3 From ff0b47ab71a6171da70319b147efe6fa675a471f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:45 +0200 Subject: dt-bindings: clock: apple,nco: Add t6020-nco compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,nco" anymore [1]. Use "apple,t8103-nco" as base compatible as it is the SoC the driver and bindings were written for. The block found on Apple's M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-nco" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/clock/apple,nco.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/apple,nco.yaml b/Documentation/devicetree/bindings/clock/apple,nco.yaml index 8b8411dc42f6..080454f56721 100644 --- a/Documentation/devicetree/bindings/clock/apple,nco.yaml +++ b/Documentation/devicetree/bindings/clock/apple,nco.yaml @@ -19,12 +19,17 @@ description: | properties: compatible: - items: - - enum: - - apple,t6000-nco - - apple,t8103-nco - - apple,t8112-nco - - const: apple,nco + oneOf: + - items: + - const: apple,t6020-nco + - const: apple,t8103-nco + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t6000-nco + - apple,t8103-nco + - apple,t8112-nco + - const: apple,nco clocks: description: -- cgit v1.2.3 From 19cf142ab94d326fb06582fda57485801e1c328d Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:47 +0200 Subject: dt-bindings: dma: apple,admac: Add t6020-admac compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,admac" anymore [1]. Use "apple,t8103-admac" as base compatible as it is the SoC the driver and bindings were written for. admac on Apple's M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-admac" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/dma/apple,admac.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/apple,admac.yaml b/Documentation/devicetree/bindings/dma/apple,admac.yaml index ab193bc8bdbb..6a200cbd7d02 100644 --- a/Documentation/devicetree/bindings/dma/apple,admac.yaml +++ b/Documentation/devicetree/bindings/dma/apple,admac.yaml @@ -22,12 +22,17 @@ allOf: properties: compatible: - items: - - enum: - - apple,t6000-admac - - apple,t8103-admac - - apple,t8112-admac - - const: apple,admac + oneOf: + - items: + - const: apple,t6020-admac + - const: apple,t8103-admac + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t6000-admac + - apple,t8103-admac + - apple,t8112-admac + - const: apple,admac reg: maxItems: 1 -- cgit v1.2.3 From a3ec6ef203e436dfa7fd007d2122b3bc3679edb6 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:49 +0200 Subject: ASoC: dt-bindings: apple,mca: Add t6020-mca compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,mca" anymore [1]. Use "apple,t8103-mca" as base compatible as it is the SoC the driver and bindings were written for. mca on Apple's M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-mca" so add its per-SoC compatible with the former as fallbeck used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Mark Brown Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/sound/apple,mca.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/apple,mca.yaml b/Documentation/devicetree/bindings/sound/apple,mca.yaml index 5c6ec08c7d24..2beb725118ad 100644 --- a/Documentation/devicetree/bindings/sound/apple,mca.yaml +++ b/Documentation/devicetree/bindings/sound/apple,mca.yaml @@ -19,12 +19,17 @@ allOf: properties: compatible: - items: - - enum: - - apple,t6000-mca - - apple,t8103-mca - - apple,t8112-mca - - const: apple,mca + oneOf: + - items: + - const: apple,t6020-mca + - const: apple,t8103-mca + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t6000-mca + - apple,t8103-mca + - apple,t8112-mca + - const: apple,mca reg: items: -- cgit v1.2.3 From b85efa8dcbb3b4147ebab9dc053e8bb20c7c48f9 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:52:10 +0200 Subject: spi: dt-bindings: apple,spi: Add t6020-spi compatible After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,spi" anymore [1]. Use "apple,t8103-spi" as base compatible as it is the SoC the driver and bindings were written for. The SPI controller on Apple M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-spi" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Mark Brown Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/spi/apple,spi.yaml | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/apple,spi.yaml b/Documentation/devicetree/bindings/spi/apple,spi.yaml index 7bef605a2963..9356b9c337c8 100644 --- a/Documentation/devicetree/bindings/spi/apple,spi.yaml +++ b/Documentation/devicetree/bindings/spi/apple,spi.yaml @@ -14,12 +14,16 @@ maintainers: properties: compatible: - items: - - enum: - - apple,t8103-spi - - apple,t8112-spi - - apple,t6000-spi - - const: apple,spi + oneOf: + - items: + - const: apple,t6020-spi + - const: apple,t8103-spi + - items: + - enum: + - apple,t8103-spi + - apple,t8112-spi + - apple,t6000-spi + - const: apple,spi reg: maxItems: 1 -- cgit v1.2.3 From eb391228ae08dfc153f8838ed700bb75a28b1493 Mon Sep 17 00:00:00 2001 From: Parvathi Pudi Date: Fri, 12 Sep 2025 16:14:50 +0530 Subject: dt-bindings: net: ti: Adds DUAL-EMAC mode support on PRU-ICSS2 for AM57xx, AM43xx and AM33xx SOCs Documentation update for the newly added "pruss2_eth" device tree node and its dependencies along with compatibility for PRU-ICSS Industrial Ethernet Peripheral (IEP), PRU-ICSS Enhanced Capture (eCAP) peripheral and using YAML binding document for AM57xx SoCs. Reviewed-by: Mohan Reddy Putluru Co-developed-by: Basharath Hussain Khaja Signed-off-by: Basharath Hussain Khaja Signed-off-by: Parvathi Pudi Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250912104741.528721-2-parvathi@couthit.com Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/ti,icss-iep.yaml | 10 +- .../devicetree/bindings/net/ti,icssm-prueth.yaml | 233 +++++++++++++++++++++ .../devicetree/bindings/net/ti,pruss-ecap.yaml | 32 +++ .../devicetree/bindings/soc/ti/ti,pruss.yaml | 9 + 4 files changed, 281 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml create mode 100644 Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/ti,icss-iep.yaml b/Documentation/devicetree/bindings/net/ti,icss-iep.yaml index e36e3a622904..ea2659d90a52 100644 --- a/Documentation/devicetree/bindings/net/ti,icss-iep.yaml +++ b/Documentation/devicetree/bindings/net/ti,icss-iep.yaml @@ -8,6 +8,8 @@ title: Texas Instruments ICSS Industrial Ethernet Peripheral (IEP) module maintainers: - Md Danish Anwar + - Parvathi Pudi + - Basharath Hussain Khaja properties: compatible: @@ -17,9 +19,11 @@ properties: - ti,am642-icss-iep - ti,j721e-icss-iep - const: ti,am654-icss-iep - - - const: ti,am654-icss-iep - + - enum: + - ti,am654-icss-iep + - ti,am5728-icss-iep + - ti,am4376-icss-iep + - ti,am3356-icss-iep reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml new file mode 100644 index 000000000000..a98ad45ca66f --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml @@ -0,0 +1,233 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,icssm-prueth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments ICSSM PRUSS Ethernet + +maintainers: + - Roger Quadros + - Andrew F. Davis + - Parvathi Pudi + - Basharath Hussain Khaja + +description: + Ethernet based on the Programmable Real-Time Unit and Industrial + Communication Subsystem. + +properties: + compatible: + enum: + - ti,am57-prueth # for AM57x SoC family + - ti,am4376-prueth # for AM43x SoC family + - ti,am3359-prueth # for AM33x SoC family + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to OCMC SRAM node + + ti,mii-rt: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the MII_RT peripheral for ICSS + + ti,iep: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to IEP (Industrial Ethernet Peripheral) for ICSS + + ti,ecap: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to Enhanced Capture (eCAP) event for ICSS + + interrupts: + items: + - description: High priority Rx Interrupt specifier. + - description: Low priority Rx Interrupt specifier. + + interrupt-names: + items: + - const: rx_hp + - const: rx_lp + + ethernet-ports: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + ^ethernet-port@[0-1]$: + type: object + description: ICSSM PRUETH external ports + $ref: ethernet-controller.yaml# + unevaluatedProperties: false + + properties: + reg: + items: + - enum: [0, 1] + description: ICSSM PRUETH port number + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: rx + - const: emac_ptp_tx + - const: hsr_ptp_tx + + required: + - reg + + anyOf: + - required: + - ethernet-port@0 + - required: + - ethernet-port@1 + +required: + - compatible + - sram + - ti,mii-rt + - ti,iep + - ti,ecap + - ethernet-ports + - interrupts + - interrupt-names + +allOf: + - $ref: /schemas/remoteproc/ti,pru-consumer.yaml# + +unevaluatedProperties: false + +examples: + - | + /* Dual-MAC Ethernet application node on PRU-ICSS2 */ + pruss2_eth: pruss2-eth { + compatible = "ti,am57-prueth"; + ti,prus = <&pru2_0>, <&pru2_1>; + sram = <&ocmcram1>; + ti,mii-rt = <&pruss2_mii_rt>; + ti,iep = <&pruss2_iep>; + ti,ecap = <&pruss2_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss2_intc>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss2_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss2_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss2_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss2_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + - | + /* Dual-MAC Ethernet application node on PRU-ICSS1 */ + pruss1_eth: pruss1-eth { + compatible = "ti,am4376-prueth"; + ti,prus = <&pru1_0>, <&pru1_1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss1_mii_rt>; + ti,iep = <&pruss1_iep>; + ti,ecap = <&pruss1_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss1_intc>; + + pinctrl-0 = <&pruss1_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss1_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss1_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss1_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss1_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + - | + /* Dual-MAC Ethernet application node on PRU-ICSS */ + pruss_eth: pruss-eth { + compatible = "ti,am3359-prueth"; + ti,prus = <&pru0>, <&pru1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss_mii_rt>; + ti,iep = <&pruss_iep>; + ti,ecap = <&pruss_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss_intc>; + + pinctrl-0 = <&pruss_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml b/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml new file mode 100644 index 000000000000..42f217099b2e --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,pruss-ecap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PRU-ICSS Enhanced Capture (eCAP) event module + +maintainers: + - Murali Karicheri + - Parvathi Pudi + - Basharath Hussain Khaja + +properties: + compatible: + const: ti,pruss-ecap + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pruss2_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml index 927b3200e29e..b5336bcbfb01 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -251,6 +251,15 @@ patternProperties: type: object + ecap@[a-f0-9]+$: + description: + PRU-ICSS has a Enhanced Capture (eCAP) event module which can generate + and capture periodic timer based events which will be used for features + like RX Pacing to rise interrupt when the timer event has occurred. + Each PRU-ICSS instance has one eCAP module irrespective of SOCs. + $ref: /schemas/net/ti,pruss-ecap.yaml# + type: object + mii-rt@[a-f0-9]+$: description: | Real-Time Ethernet to support multiple industrial communication protocols. -- cgit v1.2.3 From 09cbe54681241ac67ca595743d29f7da85363928 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 27 May 2025 22:58:22 +0200 Subject: dt-bindings: timer: renesas,rz-mtu3: Use #pwm-cells = <3> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the goal to unify all PWM bindings to use #pwm-cells = <3> update the renesas,rz-mtu3 binding accordingly. Keep <2> documented as a deprecated value at least until the in-tree device trees are fixed accordingly. Signed-off-by: Uwe Kleine-König Acked-by: Rob Herring (Arm) Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20250527205823.377785-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml index 3931054b42fb..3ad10c5b66ba 100644 --- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml @@ -221,7 +221,10 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + oneOf: + - const: 2 + deprecated: true + - const: 3 required: - compatible @@ -299,5 +302,5 @@ examples: clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; - #pwm-cells = <2>; + #pwm-cells = <3>; }; -- cgit v1.2.3 From 3513752cfe6fc1cfb0d99b3b4c554eb56e8bf8a1 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Tue, 12 Aug 2025 22:00:35 +0200 Subject: dt-bindings: pwm: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The S32G2 and S32G3 have a FlexTimer (FTM) available which is the same as the one found on the Vybrid Family and the i.MX8. Add the compatibles in the bindings Signed-off-by: Daniel Lezcano Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250812200036.3432917-2-daniel.lezcano@linaro.org Signed-off-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml index 7f9f72d95e7a..c7a10180208e 100644 --- a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml @@ -26,9 +26,14 @@ maintainers: properties: compatible: - enum: - - fsl,vf610-ftm-pwm - - fsl,imx8qm-ftm-pwm + oneOf: + - enum: + - fsl,vf610-ftm-pwm + - fsl,imx8qm-ftm-pwm + - nxp,s32g2-ftm-pwm + - items: + - const: nxp,s32g3-ftm-pwm + - const: nxp,s32g2-ftm-pwm reg: maxItems: 1 -- cgit v1.2.3 From efedb508591e231b47b23ce6b353c81eeb3b9a84 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 21 Aug 2025 10:31:11 +0200 Subject: dt-bindings: pwm: nxp,lpc1850-sct-pwm: Minor whitespace cleanup in example MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250821083110.46420-2-krzysztof.kozlowski@linaro.org Signed-off-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml b/Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml index ffda0123878e..920e0413d431 100644 --- a/Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml @@ -48,7 +48,7 @@ examples: pwm@40000000 { compatible = "nxp,lpc1850-sct-pwm"; reg = <0x40000000 0x1000>; - clocks =<&ccu1 CLK_CPU_SCT>; + clocks = <&ccu1 CLK_CPU_SCT>; clock-names = "pwm"; #pwm-cells = <3>; }; -- cgit v1.2.3 From d322a0e01d9ecc91881d7a6ad388a37a1a81471f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 28 Aug 2025 16:01:39 +0200 Subject: dt-bindings: pwm: apple,s5l-fpwm: Add t6020-fpwm compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PWM controller on Apple's M2 Pro/Max SoCs behaves in the same way as on previous M1 and M2 SoCs. Add its per SoC compatible. At the same time fix the order of existing entries. The sort order logic is having SoC numeric code families in release order, and SoCs within each family in release order: - t8xxx (Apple HxxP/G series, "phone"/"tablet" chips) - t8103 (Apple H13G/M1) - t8112 (Apple H14G/M2) - t6xxx (Apple HxxJ series, "desktop" chips) - t6000/t6001/t6002 (Apple H13J(S/C/D) / M1 Pro/Max/Ultra) - t6020/t6021/t6022 (Apple H14J(S/C/D) / M2 Pro/Max/Ultra) Note that SoCs of the t600[0-2] / t602[0-2] family share the t6000 / t6020 compatible where the hardware is 100% compatible, which is usually the case in this highly related set of SoCs. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250828-dt-apple-t6020-v1-20-507ba4c4b98e@jannau.net Signed-off-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml index 142157bff0cd..04519b0c581d 100644 --- a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +++ b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml @@ -17,8 +17,9 @@ properties: items: - enum: - apple,t8103-fpwm - - apple,t6000-fpwm - apple,t8112-fpwm + - apple,t6000-fpwm + - apple,t6020-fpwm - const: apple,s5l-fpwm reg: -- cgit v1.2.3 From ebd524a3ac3a172aa26f99d20d4d00d57da9a875 Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 14 Sep 2025 16:20:33 +0300 Subject: dt-bindings: pwm: samsung: add exynos8890 compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add samsung,exynos8890-pwm compatible string to binding document. Signed-off-by: Ivaylo Ivanov Link: https://lore.kernel.org/r/20250914132033.2622886-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/pwm-samsung.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml index 17a2b927af33..97acbdec39f1 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -31,6 +31,7 @@ properties: - enum: - samsung,exynos5433-pwm - samsung,exynos7-pwm + - samsung,exynos8890-pwm - samsung,exynosautov9-pwm - samsung,exynosautov920-pwm - tesla,fsd-pwm -- cgit v1.2.3 From 7f8d35b589c9f6acda0e36b184c193d38f092c36 Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Sun, 6 Jul 2025 23:55:45 +0530 Subject: dt-bindings: samsung,mipi-dsim: document exynos7870 DSIM compatible Add compatible string for Exynos7870 DSIM bridge controller. The device requires four clock sources, in schema they're named as "bus", "pll", "byte", and "esc". Suggested-by: Krzysztof Kozlowski Reviewed-by: Rob Herring (Arm) Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae --- .../bindings/display/bridge/samsung,mipi-dsim.yaml | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml index 1acad99f3965..ad279f0993fa 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -24,6 +24,7 @@ properties: - samsung,exynos5410-mipi-dsi - samsung,exynos5422-mipi-dsi - samsung,exynos5433-mipi-dsi + - samsung,exynos7870-mipi-dsi - fsl,imx8mm-mipi-dsim - fsl,imx8mp-mipi-dsim - items: @@ -144,6 +145,32 @@ required: allOf: - $ref: ../dsi-controller.yaml# + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-mipi-dsi + + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: bus + - const: pll + - const: byte + - const: esc + + ports: + required: + - port@0 + + required: + - ports + - if: properties: compatible: -- cgit v1.2.3 From 0e6ee83c4b68448063e88e14c13c17d83e7d9735 Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Sun, 6 Jul 2025 22:59:45 +0530 Subject: dt-bindings: display: samsung,exynos7-decon: document iommus, memory-region, and ports Similar to FIMD and Exynos5433's DECON, the Exynos7 DECON hardware: - May optionally require an IOMMU to initialize a display region. - Outputs image data to another block, say an MIC or a DSI master. If an IOMMU is present, it may also require to access the reserved framebuffer region. Document these bindings in the devicetree schema. Signed-off-by: Kaustabh Chakraborty Reviewed-by: Krzysztof Kozlowski Signed-off-by: Inki Dae --- .../display/samsung/samsung,exynos7-decon.yaml | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml index 53916e4c95d8..14b954718008 100644 --- a/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml +++ b/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml @@ -80,6 +80,21 @@ properties: - const: vsync - const: lcd_sys + iommus: + maxItems: 1 + + memory-region: + maxItems: 1 + description: + A phandle to a node describing a reserved framebuffer memory region. + For example, the splash memory region set up by the bootloader. + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port which is connected to either a Mobile Image Compressor + (MIC) or a DSI Master device. + power-domains: maxItems: 1 @@ -92,6 +107,7 @@ required: - clock-names - interrupts - interrupt-names + - port - reg additionalProperties: false @@ -118,4 +134,9 @@ examples: "decon0_vclk"; pinctrl-0 = <&lcd_clk &pwm1_out>; pinctrl-names = "default"; + port { + decon_to_dsi: endpoint { + remote-endpoint = <&dsi_to_decon>; + }; + }; }; -- cgit v1.2.3 From 8d978222e87c5ea50f912141b18421882f89492a Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Mon, 8 Sep 2025 17:26:48 +0530 Subject: dt-bindings: memory-controllers: Add support for Versal NET EDAC Add device tree bindings for AMD Versal NET EDAC for DDR controller. Signed-off-by: Shubhrajyoti Datta Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20250908115649.22903-1-shubhrajyoti.datta@amd.com --- .../memory-controllers/xlnx,versal-net-ddrmc5.yaml | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml new file mode 100644 index 000000000000..479288567d0b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal NET Memory Controller + +maintainers: + - Shubhrajyoti Datta + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 + compact and extended memory interfaces. Versal NET DDR memory controller + has an optional ECC support which correct single bit ECC errors and detect + double bit ECC errors. It also has support for reporting other errors like + MMCM (Mixed-Mode Clock Manager) errors and General software errors. + +properties: + compatible: + const: xlnx,versal-net-ddrmc5 + + amd,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the remoteproc_r5 rproc node using which APU interacts + with remote processor. APU primarily communicates with the RPU for + accessing the DDRMC address space and getting error notification. + +required: + - compatible + - amd,rproc + +additionalProperties: false + +examples: + - | + memory-controller { + compatible = "xlnx,versal-net-ddrmc5"; + amd,rproc = <&remoteproc_r5>; + }; -- cgit v1.2.3 From dd1704a50738605997e0aff71981c33241c3df67 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Thu, 7 Aug 2025 08:09:30 +0200 Subject: dt-binding: can: m_can: add optional resets property The m_can IP core has an external reset line. Add it to the bindings documentation. Signed-off-by: Marc Kleine-Budde Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250807-stm32mp15-m_can-add-reset-v2-1-f69ebbfced1f@pengutronix.de Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index c4887522e8fe..61ef60d8f1c7 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -50,6 +50,9 @@ properties: - const: hclk - const: cclk + resets: + maxItems: 1 + bosch,mram-cfg: description: | Message RAM configuration data. -- cgit v1.2.3 From 0f101028407605c7b7cea53946ee4d25f82cfb6c Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 14 Sep 2025 16:02:29 +0300 Subject: dt-bindings: regulator: document max77838 pmic The max77838 is a pmic, containing a BUCK regulator and 4 LDOs. It's primarily used in the Samsung Galaxy S7 lineup and is accessed over I2C. Document it. Signed-off-by: Ivaylo Ivanov Acked-by: Conor Dooley Reviewed-by: Igor Belwon Link: https://patch.msgid.link/20250914130230.2622030-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Mark Brown --- .../bindings/regulator/maxim,max77838.yaml | 68 ++++++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/maxim,max77838.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/maxim,max77838.yaml b/Documentation/devicetree/bindings/regulator/maxim,max77838.yaml new file mode 100644 index 000000000000..bed36af5493d --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/maxim,max77838.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/maxim,max77838.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77838 PMIC + +maintainers: + - Ivaylo Ivanov + +properties: + $nodename: + pattern: "pmic@[0-9a-f]{1,2}" + compatible: + enum: + - maxim,max77838 + + reg: + maxItems: 1 + + regulators: + type: object + $ref: regulator.yaml# + description: | + list of regulators provided by this controller, must be named + after their hardware counterparts ldo[1-4] and buck + + properties: + buck: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + patternProperties: + "^ldo([1-4])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@60 { + compatible = "maxim,max77838"; + reg = <0x60>; + + regulators { + ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index f6206963efbf..7554c7f2570a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15069,6 +15069,12 @@ F: Documentation/devicetree/bindings/*/*max77802.yaml F: drivers/regulator/max77802-regulator.c F: include/dt-bindings/*/*max77802.h +MAXIM MAX77838 PMIC REGULATOR DEVICE DRIVER +M: Ivaylo Ivanov +L: linux-kernel@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/regulator/maxim,max77838.yaml + MAXIM MAX77976 BATTERY CHARGER M: Luca Ceresoli S: Supported -- cgit v1.2.3 From d021fb3ae844dad0a1d2f037a9657fde330955bb Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Mon, 15 Sep 2025 10:12:26 +0300 Subject: dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported. The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS. Add a device tree binding document for the ROHM BD79112. Signed-off-by: Matti Vaittinen Acked-by: Conor Dooley Reviewed-by: Linus Walleij Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/rohm,bd79112.yaml | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml b/Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file mode 100644 index 000000000000..aa8b07c3fac1 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/rohm,bd79112.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD79112 ADC/GPO + +maintainers: + - Matti Vaittinen + +description: | + The ROHM BD79112 is a 12-bit, 32-channel, SAR ADC. ADC input pins can be + also configured as general purpose inputs/outputs. SPI should use MODE 3. + +properties: + compatible: + const: rohm,bd79112 + + reg: + maxItems: 1 + + spi-cpha: true + spi-cpol: true + + gpio-controller: true + "#gpio-cells": + const: 2 + + vdd-supply: true + + iovdd-supply: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@([0-9]|[12][0-9]|3[01])$": + type: object + $ref: /schemas/iio/adc/adc.yaml# + description: Represents ADC channel. Omitted channels' inputs are GPIOs. + + properties: + reg: + description: AIN pin number + minimum: 0 + maximum: 31 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - iovdd-supply + - vdd-supply + - spi-cpha + - spi-cpol + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + adc: adc@0 { + compatible = "rohm,bd79112"; + reg = <0x0>; + + spi-cpha; + spi-cpol; + + vdd-supply = <&dummyreg>; + iovdd-supply = <&dummyreg>; + + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@16 { + reg = <16>; + }; + channel@20 { + reg = <20>; + }; + }; + }; -- cgit v1.2.3 From 8c01cc2382bc351672c8eb946c16f567cfffef60 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 10 Sep 2025 21:41:22 +0100 Subject: dt-bindings: net: pcs: renesas,rzn1-miic: Add RZ/T2H and RZ/N2H support Add device tree binding support for RZ/T2H and RZ/N2H SoCs to the existing RZ/N1 MIIC converter binding. These SoCs share similar MIIC functionality but have architectural differences that require schema updates. Add new compatible strings "renesas,r9a09g077-miic" for RZ/T2H and "renesas,r9a09g087-miic" for RZ/N2H, with the latter falling back to the RZ/T2H variant. The new SoCs require reset support with two reset lines for converter register reset and converter reset, which are not present on RZ/N1. Update port configurations to accommodate the different architectures. RZ/N1 supports 5 ports numbered 1-5 with complex input mappings covering indices 0-13, while RZ/T2H and RZ/N2H support 4 ports numbered 0-3 with simplified input mappings covering indices 0-8. Extend the switch port configuration property to support value 0 for the new SoCs. Add a new dt-bindings header file with media interface connection matrix constants that map GMAC, ESC, and ETHSW ports to numeric identifiers for use with RZ/T2H and RZ/N2H device trees. Update DT schema validation to ensure proper port numbering and input mappings per SoC variant. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250910204132.319975-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski --- .../bindings/net/pcs/renesas,rzn1-miic.yaml | 177 +++++++++++++++------ .../dt-bindings/net/renesas,r9a09g077-pcs-miic.h | 36 +++++ 2 files changed, 165 insertions(+), 48 deletions(-) create mode 100644 include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml index 2d33bbab7163..3adbcf56d2be 100644 --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -4,14 +4,15 @@ $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/N1 MII converter +title: Renesas RZ/N1, RZ/N2H and RZ/T2H MII converter maintainers: - Clément Léger + - Lad Prabhakar description: | - This MII converter is present on the Renesas RZ/N1 SoC family. It is - responsible to do MII passthrough or convert it to RMII/RGMII. + This MII converter is present on the Renesas RZ/N1, RZ/N2H and RZ/T2H SoC + families. It is responsible to do MII passthrough or convert it to RMII/RGMII. properties: '#address-cells': @@ -21,10 +22,16 @@ properties: const: 0 compatible: - items: - - enum: - - renesas,r9a06g032-miic - - const: renesas,rzn1-miic + oneOf: + - items: + - enum: + - renesas,r9a06g032-miic + - const: renesas,rzn1-miic + - items: + - const: renesas,r9a09g077-miic # RZ/T2H + - items: + - const: renesas,r9a09g087-miic # RZ/N2H + - const: renesas,r9a09g077-miic reg: maxItems: 1 @@ -43,11 +50,22 @@ properties: - const: rmii_ref - const: hclk + resets: + items: + - description: Converter register reset + - description: Converter reset + + reset-names: + items: + - const: rst + - const: crst + renesas,miic-switch-portin: description: MII Switch PORTIN configuration. This value should use one of - the values defined in dt-bindings/net/pcs-rzn1-miic.h. + the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC and + include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2] + enum: [0, 1, 2] power-domains: maxItems: 1 @@ -60,11 +78,12 @@ patternProperties: properties: reg: description: MII Converter port number. - enum: [1, 2, 3, 4, 5] + enum: [0, 1, 2, 3, 4, 5] renesas,miic-input: description: Converter input port configuration. This value should use - one of the values defined in dt-bindings/net/pcs-rzn1-miic.h. + one of the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC + and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 required: @@ -73,47 +92,109 @@ patternProperties: additionalProperties: false - allOf: - - if: - properties: - reg: - const: 1 - then: - properties: - renesas,miic-input: - const: 0 - - if: +allOf: + - if: + properties: + compatible: + contains: + const: renesas,rzn1-miic + then: + properties: + renesas,miic-switch-portin: + enum: [1, 2] + resets: false + reset-names: false + patternProperties: + "^mii-conv@[0-5]$": properties: reg: - const: 2 - then: - properties: - renesas,miic-input: - enum: [1, 11] - - if: - properties: - reg: - const: 3 - then: - properties: - renesas,miic-input: - enum: [7, 10] - - if: + enum: [1, 2, 3, 4, 5] + allOf: + - if: + properties: + reg: + const: 1 + then: + properties: + renesas,miic-input: + const: 0 + - if: + properties: + reg: + const: 2 + then: + properties: + renesas,miic-input: + enum: [1, 11] + - if: + properties: + reg: + const: 3 + then: + properties: + renesas,miic-input: + enum: [7, 10] + - if: + properties: + reg: + const: 4 + then: + properties: + renesas,miic-input: + enum: [4, 6, 9, 13] + - if: + properties: + reg: + const: 5 + then: + properties: + renesas,miic-input: + enum: [3, 5, 8, 12] + else: + properties: + renesas,miic-switch-portin: + const: 0 + required: + - resets + - reset-names + patternProperties: + "^mii-conv@[0-5]$": properties: reg: - const: 4 - then: - properties: - renesas,miic-input: - enum: [4, 6, 9, 13] - - if: - properties: - reg: - const: 5 - then: - properties: - renesas,miic-input: - enum: [3, 5, 8, 12] + enum: [0, 1, 2, 3] + allOf: + - if: + properties: + reg: + const: 0 + then: + properties: + renesas,miic-input: + enum: [0, 3, 6] + - if: + properties: + reg: + const: 1 + then: + properties: + renesas,miic-input: + enum: [1, 4, 7] + - if: + properties: + reg: + const: 2 + then: + properties: + renesas,miic-input: + enum: [2, 5, 8] + - if: + properties: + reg: + const: 3 + then: + properties: + renesas,miic-input: + const: 1 required: - '#address-cells' diff --git a/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h b/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h new file mode 100644 index 000000000000..43a2b5743a63 --- /dev/null +++ b/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corporation. + */ + +#ifndef _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H +#define _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H + +/* + * Media Interface Connection Matrix + * =========================================================== + * + * Selects the function of the Media interface of the MAC to be used + * + * SW_MODE[2:0] | Port 0 | Port 1 | Port 2 | Port 3 + * -------------|-------------|-------------|-------------|------------- + * 000b | ETHSW Port0 | ETHSW Port1 | ETHSW Port2 | GMAC1 + * 001b | ESC Port0 | ESC Port1 | GMAC2 | GMAC1 + * 010b | ESC Port0 | ESC Port1 | ETHSW Port2 | GMAC1 + * 011b | ESC Port0 | ESC Port1 | ESC Port2 | GMAC1 + * 100b | ETHSW Port0 | ESC Port1 | ESC Port2 | GMAC1 + * 101b | ETHSW Port0 | ESC Port1 | ETHSW Port2 | GMAC1 + * 110b | ETHSW Port0 | ETHSW Port1 | GMAC2 | GMAC1 + * 111b | GMAC0 | GMAC1 | GMAC2 | - + */ +#define ETHSS_GMAC0_PORT 0 +#define ETHSS_GMAC1_PORT 1 +#define ETHSS_GMAC2_PORT 2 +#define ETHSS_ESC_PORT0 3 +#define ETHSS_ESC_PORT1 4 +#define ETHSS_ESC_PORT2 5 +#define ETHSS_ETHSW_PORT0 6 +#define ETHSS_ETHSW_PORT1 7 +#define ETHSS_ETHSW_PORT2 8 + +#endif -- cgit v1.2.3 From 17628f1abbf4bd4162c655f3260d68bc1934ec73 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 12 Sep 2025 19:59:16 +0300 Subject: dt-bindings: gpio: fix trivial-gpio's schema id In case the trivial-gpio schema is referenced through a $ref like /schemas/trivial-gpio.yaml to match its current schema ID, the following error message is displayed: Error in referenced schema matching $id: http://devicetree.org/schemas/trivial-gpio.yaml Tried these paths (check schema $id if path is wrong): /path/to/linux/Documentation/devicetree/bindings/trivial-gpio.yaml /path/to/dtchema/schemas/trivial-gpio.yaml Fix this by adding the 'gpio' folder to the schema's ID to match its file path. Fixes: f03a7f20b23c ("dt-bindings: gpio: Create a trivial GPIO schema") Signed-off-by: Ioana Ciornei Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250912165916.3098215-1-ioana.ciornei@nxp.com Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/gpio/trivial-gpio.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml index 0299d4a25086..c994177de940 100644 --- a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/trivial-gpio.yaml# +$id: http://devicetree.org/schemas/gpio/trivial-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Trivial 2-cell GPIO controllers -- cgit v1.2.3 From 8d7de4a014f589c1776959f7fdadbf7b12045aac Mon Sep 17 00:00:00 2001 From: Jonas Rebmann Date: Wed, 10 Sep 2025 14:35:22 +0200 Subject: ASoC: dt-bindings: asahi-kasei,ak4458: Reference common DAI properties Reference the dai-common.yaml schema to allow '#sound-dai-cells' and "sound-name-prefix' to be used. Signed-off-by: Jonas Rebmann Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250910-imx8mp-prt8ml-v1-2-fd04aed15670@pengutronix.de Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml b/Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml index 4477f84b7acc..1fdbeecc5eff 100644 --- a/Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml +++ b/Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml @@ -15,6 +15,9 @@ properties: - asahi-kasei,ak4458 - asahi-kasei,ak4497 + "#sound-dai-cells": + const: 0 + reg: maxItems: 1 @@ -46,6 +49,7 @@ required: - reg allOf: + - $ref: dai-common.yaml# - if: properties: compatible: -- cgit v1.2.3 From 62a12a221769f102062c014dc227555d3a6a6df1 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Sun, 14 Sep 2025 12:23:12 +0800 Subject: dt-bindings: net: Add support for SpacemiT K1 The Ethernet MACs on SpacemiT K1 appears to be a custom design. SpacemiT refers to them as "EMAC", so let's just call them "spacemit,k1-emac". Signed-off-by: Vivian Wang Reviewed-by: Conor Dooley Link: https://patch.msgid.link/20250914-net-k1-emac-v12-1-65b31b398f44@iscas.ac.cn Signed-off-by: Paolo Abeni --- .../devicetree/bindings/net/spacemit,k1-emac.yaml | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/spacemit,k1-emac.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/spacemit,k1-emac.yaml b/Documentation/devicetree/bindings/net/spacemit,k1-emac.yaml new file mode 100644 index 000000000000..500a3e1daa23 --- /dev/null +++ b/Documentation/devicetree/bindings/net/spacemit,k1-emac.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/spacemit,k1-emac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 Ethernet MAC + +allOf: + - $ref: ethernet-controller.yaml# + +maintainers: + - Vivian Wang + +properties: + compatible: + const: spacemit,k1-emac + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + mdio-bus: + $ref: mdio.yaml# + unevaluatedProperties: false + + resets: + maxItems: 1 + + spacemit,apmu: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to syscon that controls this MAC + - description: offset of control registers + description: + A phandle to syscon with byte offset to control registers for this MAC + +required: + - compatible + - reg + - clocks + - interrupts + - resets + - spacemit,apmu + +unevaluatedProperties: false + +examples: + - | + #include + + ethernet@cac80000 { + compatible = "spacemit,k1-emac"; + reg = <0xcac80000 0x00000420>; + clocks = <&syscon_apmu CLK_EMAC0_BUS>; + interrupts = <131>; + mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_cfg>; + resets = <&syscon_apmu RESET_EMAC0>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + spacemit,apmu = <&syscon_apmu 0x3e4>; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + rgmii0: phy@1 { + reg = <0x1>; + }; + }; + }; -- cgit v1.2.3 From 88d0d17192c5a850dc07bb38035b69c4cefde270 Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Mon, 15 Sep 2025 17:27:48 +0100 Subject: ASoC: dt-bindings: add bindings for pm4125 audio codec The audio codec IC is found on Qualcomm PM4125/PM2250 PMIC. It has TX and RX soundwire slave devices hence two files are added. Signed-off-by: Alexey Klimov Reviewed-by: Srinivas Kandagatla Tested-by: Srinivas Kandagatla Link: https://patch.msgid.link/20250915-pm4125_audio_codec_v1-v4-1-b247b64eec52@linaro.org Signed-off-by: Mark Brown --- .../bindings/sound/qcom,pm4125-codec.yaml | 134 +++++++++++++++++++++ .../devicetree/bindings/sound/qcom,pm4125-sdw.yaml | 79 ++++++++++++ 2 files changed, 213 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/qcom,pm4125-codec.yaml create mode 100644 Documentation/devicetree/bindings/sound/qcom,pm4125-sdw.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/qcom,pm4125-codec.yaml b/Documentation/devicetree/bindings/sound/qcom,pm4125-codec.yaml new file mode 100644 index 000000000000..6e2f103be1d3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,pm4125-codec.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,pm4125-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PM4125 Audio Codec + +maintainers: + - Alexey Klimov + +description: + The audio codec IC found on Qualcomm PM4125/PM2250 PMIC. + It has RX and TX Soundwire slave devices. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: qcom,pm4125-codec + + reg: + description: + Specifies the SPMI base address for the audio codec peripherals. The + address space contains reset register needed to power-on the codec. + maxItems: 1 + + reg-names: + maxItems: 1 + + vdd-io-supply: + description: A reference to the 1.8V I/O supply + + vdd-cp-supply: + description: A reference to the charge pump I/O supply + + vdd-mic-bias-supply: + description: A reference to the 3.3V mic bias supply + + vdd-pa-vpos-supply: + description: A reference to the PA VPOS supply + + qcom,tx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire tx device phandle + + qcom,rx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire rx device phandle + + qcom,micbias1-microvolt: + description: micbias1 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias2-microvolt: + description: micbias2 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias3-microvolt: + description: micbias3 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,mbhc-buttons-vthreshold-microvolt: + description: + Array of 8 Voltage threshold values corresponding to headset + button0 - button7 + minItems: 8 + maxItems: 8 + + '#sound-dai-cells': + const: 1 + +required: + - compatible + - reg + - vdd-io-supply + - vdd-cp-supply + - vdd-mic-bias-supply + - vdd-pa-vpos-supply + - qcom,tx-device + - qcom,rx-device + - qcom,micbias1-microvolt + - qcom,micbias2-microvolt + - qcom,micbias3-microvolt + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + spmi { + #address-cells = <2>; + #size-cells = <0>; + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + audio-codec@f000 { + compatible = "qcom,pm4125-codec"; + reg = <0xf000>; + vdd-io-supply = <&pm4125_l15>; + vdd-cp-supply = <&pm4125_s4>; + vdd-pa-vpos-supply = <&pm4125_s4>; + vdd-mic-bias-supply = <&pm4125_l22>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,rx-device = <&pm4125_rx>; + qcom,tx-device = <&pm4125_tx>; + #sound-dai-cells = <1>; + }; + }; + }; + + /* ... */ + + soundwire@a610000 { + reg = <0x0a610000 0x2000>; + #address-cells = <2>; + #size-cells = <0>; + pm4125_rx: audio-codec@0,4 { + compatible = "sdw20217010c00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 3>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/sound/qcom,pm4125-sdw.yaml b/Documentation/devicetree/bindings/sound/qcom,pm4125-sdw.yaml new file mode 100644 index 000000000000..23624f32ac30 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,pm4125-sdw.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,pm4125-sdw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoundWire Slave devices on PM4125/PM2250 PMIC audio codec. + +maintainers: + - Alexey Klimov + +description: + The audio codec IC found on Qualcomm PM4125/PM2250 PMICs. + It has RX and TX Soundwire slave devices. + +properties: + compatible: + const: sdw20217010c00 + + reg: + maxItems: 1 + + qcom,tx-port-mapping: + description: | + Specifies static port mapping between device and host tx ports. + In the order of the device port index which are adc1_port, adc23_port, + dmic03_mbhc_port, dmic46_port. + Supports maximum 2 tx soundwire ports. + + PM4125 TX Port 1 (ADC1,2 & DMIC0 & MBHC) <=> SWR0 Port 1 + PM4125 TX Port 2 (ADC1 & DMIC0,1,2 & MBHC) <=> SWR0 Port 2 + + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + enum: [1, 2, 3, 4] + + qcom,rx-port-mapping: + description: | + Specifies static port mapping between device and host rx ports. + In the order of device port index which are hph_port, clsh_port, + comp_port, lo_port, dsd port. + Supports maximum 2 rx soundwire ports. + + PM4125 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R) + PM4125 RX Port 2 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R) + + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + enum: [1, 2, 3, 4, 5] + +required: + - compatible + - reg + +oneOf: + - required: + - qcom,tx-port-mapping + - required: + - qcom,rx-port-mapping + +additionalProperties: false + +examples: + - | + soundwire@a610000 { + reg = <0x0a610000 0x2000>; + #address-cells = <2>; + #size-cells = <0>; + pm4125_rx: codec@0,1 { + compatible = "sdw20217010c00"; + reg = <0 1>; + qcom,rx-port-mapping = <1 3>; + }; + }; +... -- cgit v1.2.3 From aee814458fb98819876442f0261fad0bb9842224 Mon Sep 17 00:00:00 2001 From: Mathieu Dubois-Briand Date: Sun, 24 Aug 2025 13:57:20 +0200 Subject: dt-bindings: mfd: gpio: Add MAX7360 Add device tree bindings for Maxim Integrated MAX7360 device with support for keypad, rotary, gpios and pwm functionalities. Reviewed-by: "Rob Herring (Arm)" Reviewed-by: Krzysztof Kozlowski Signed-off-by: Mathieu Dubois-Briand Link: https://lore.kernel.org/r/20250824-mdb-max7360-support-v14-1-435cfda2b1ea@bootlin.com Signed-off-by: Lee Jones --- .../bindings/gpio/maxim,max7360-gpio.yaml | 83 +++++++++ .../devicetree/bindings/mfd/maxim,max7360.yaml | 191 +++++++++++++++++++++ 2 files changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml create mode 100644 Documentation/devicetree/bindings/mfd/maxim,max7360.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml b/Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml new file mode 100644 index 000000000000..c5c3fc4c816f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/maxim,max7360-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX7360 GPIO controller + +maintainers: + - Kamel Bouhara + - Mathieu Dubois-Briand + +description: | + Maxim MAX7360 GPIO controller, in MAX7360 chipset + https://www.analog.com/en/products/max7360.html + + The device provides two series of GPIOs, referred here as GPIOs and GPOs. + + PORT0 to PORT7 pins can be used as GPIOs, with support for interrupts and + constant-current mode. These pins will also be used by the rotary encoder and + PWM functionalities. + + COL2 to COL7 pins can be used as GPOs, there is no input capability. COL pins + will be partitioned, with the first pins being affected to the keypad + functionality and the last ones as GPOs. + +properties: + compatible: + enum: + - maxim,max7360-gpio + - maxim,max7360-gpo + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + maxim,constant-current-disable: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bit field, each bit disables constant-current output of the associated + GPIO, starting from the least significant bit for the first GPIO. + maximum: 0xff + +required: + - compatible + - gpio-controller + +allOf: + - if: + properties: + compatible: + contains: + enum: + - maxim,max7360-gpio + ngpios: false + then: + required: + - interrupt-controller + else: + properties: + interrupt-controller: false + maxim,constant-current-disable: false + +additionalProperties: false + +examples: + - | + gpio { + compatible = "maxim,max7360-gpio"; + + gpio-controller; + #gpio-cells = <2>; + maxim,constant-current-disable = <0x06>; + + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/mfd/maxim,max7360.yaml b/Documentation/devicetree/bindings/mfd/maxim,max7360.yaml new file mode 100644 index 000000000000..3fc920c8639d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/maxim,max7360.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max7360.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX7360 Keypad, Rotary encoder, PWM and GPIO controller + +maintainers: + - Kamel Bouhara + - Mathieu Dubois-Briand + +description: | + Maxim MAX7360 device, with following functions: + - keypad controller + - rotary controller + - GPIO and GPO controller + - PWM controller + + https://www.analog.com/en/products/max7360.html + +allOf: + - $ref: /schemas/input/matrix-keymap.yaml# + - $ref: /schemas/input/input.yaml# + +properties: + compatible: + enum: + - maxim,max7360 + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: inti + - const: intk + + keypad-debounce-delay-ms: + description: Keypad debounce delay in ms + minimum: 9 + maximum: 40 + default: 9 + + rotary-debounce-delay-ms: + description: Rotary encoder debounce delay in ms + minimum: 0 + maximum: 15 + default: 0 + + linux,axis: + $ref: /schemas/input/rotary-encoder.yaml#/properties/linux,axis + + rotary-encoder,relative-axis: + $ref: /schemas/types.yaml#/definitions/flag + description: + Register a relative axis rather than an absolute one. + + rotary-encoder,steps: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 24 + description: + Number of steps in a full turnaround of the + encoder. Only relevant for absolute axis. Defaults to 24 which is a + typical value for such devices. + + rotary-encoder,rollover: + $ref: /schemas/types.yaml#/definitions/flag + description: + Automatic rollover when the rotary value becomes + greater than the specified steps or smaller than 0. For absolute axis only. + + "#pwm-cells": + const: 3 + + gpio: + $ref: /schemas/gpio/maxim,max7360-gpio.yaml# + description: + PORT0 to PORT7 general purpose input/output pins configuration. + + gpo: + $ref: /schemas/gpio/maxim,max7360-gpio.yaml# + description: > + COL2 to COL7 general purpose output pins configuration. Allows to use + unused keypad columns as outputs. + + The MAX7360 has 8 column lines and 6 of them can be used as GPOs. GPIOs + numbers used for this gpio-controller node do correspond to the column + numbers: values 0 and 1 are never valid, values from 2 to 7 might be valid + depending on the value of the keypad,num-column property. + +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: '^(PORT[0-7]|ROTARY)$' + minItems: 1 + maxItems: 8 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [gpio, pwm, rotary] + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - linux,keymap + - linux,axis + - "#pwm-cells" + - gpio + - gpo + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + io-expander@38 { + compatible = "maxim,max7360"; + reg = <0x38>; + + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>, + <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "inti", "intk"; + + keypad,num-rows = <8>; + keypad,num-columns = <4>; + linux,keymap = < + MATRIX_KEY(0x00, 0x00, KEY_F5) + MATRIX_KEY(0x01, 0x00, KEY_F4) + MATRIX_KEY(0x02, 0x01, KEY_F6) + >; + keypad-debounce-delay-ms = <10>; + autorepeat; + + rotary-debounce-delay-ms = <2>; + linux,axis = <0>; /* REL_X */ + rotary-encoder,relative-axis; + + #pwm-cells = <3>; + + max7360_gpio: gpio { + compatible = "maxim,max7360-gpio"; + + gpio-controller; + #gpio-cells = <2>; + maxim,constant-current-disable = <0x06>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + max7360_gpo: gpo { + compatible = "maxim,max7360-gpo"; + + gpio-controller; + #gpio-cells = <2>; + }; + + backlight_pins: backlight-pins { + pins = "PORT2"; + function = "pwm"; + }; + }; + }; -- cgit v1.2.3 From 3f5df63955756fbe253a2a26043accf7318fa53a Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Wed, 10 Sep 2025 14:01:08 +0200 Subject: dt-bindings: leds: Add generic LED consumer documentation Introduce common generic led consumer binding, where consumer defines led(s) by phandle, as opposed to trigger-source binding where the trigger source is defined in led itself. Add already used in some schemas 'leds' parameter which expects phandle-array. Additionally, introduce 'led-names' which could be used by consumers to map LED devices to their respective functions. Signed-off-by: Aleksandrs Vinarskis Reviewed-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250910-leds-v5-1-bb90a0f897d5@vinarskis.com Signed-off-by: Lee Jones --- .../devicetree/bindings/leds/leds-consumer.yaml | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/leds-consumer.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/leds/leds-consumer.yaml b/Documentation/devicetree/bindings/leds/leds-consumer.yaml new file mode 100644 index 000000000000..fe6a0faa1d3b --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-consumer.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common leds consumer + +maintainers: + - Aleksandrs Vinarskis + +description: + Some LED defined in DT are required by other DT consumers, for example + v4l2 subnode may require privacy or flash LED. Unlike trigger-source + approach which is typically used as 'soft' binding, referencing LED + devices by phandle makes things simpler when 'hard' binding is desired. + + Document LED properties that its consumers may define. + +select: true + +properties: + leds: + oneOf: + - type: object + - $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A list of LED device(s) required by a particular consumer. + items: + maxItems: 1 + + led-names: + description: + A list of device name(s). Used to map LED devices to their respective + functions, when consumer requires more than one LED. + +additionalProperties: true + +examples: + - | + #include + #include + + leds { + compatible = "gpio-leds"; + + privacy_led: privacy-led { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + v4l2_node: camera@36 { + reg = <0x36>; + + leds = <&privacy_led>; + led-names = "privacy"; + }; + }; + +... -- cgit v1.2.3 From 22420da3662a69d8894ee624494213a5888a1e87 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Wed, 10 Sep 2025 14:01:09 +0200 Subject: dt-bindings: leds: Unify 'leds' property A number of existing schemas use 'leds' property to provide phandle-array of LED(s) to the consumer. Additionally, with the upcoming privacy-led support in device-tree, v4l2 subnode could be a LED consumer, meaning that all camera sensors should support 'leds' and 'led-names' property via common 'video-interface-devices.yaml'. To avoid duplication, unify 'leds' property from existing schemas to newly introduced 'led-consumer.yaml'. Signed-off-by: Aleksandrs Vinarskis Reviewed-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250910-leds-v5-2-bb90a0f897d5@vinarskis.com Signed-off-by: Lee Jones --- .../devicetree/bindings/leds/backlight/led-backlight.yaml | 6 +----- Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml | 5 +---- .../devicetree/bindings/media/video-interface-devices.yaml | 8 ++++++++ 3 files changed, 10 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml b/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml index f5554da6bc6c..8fc5af8f27f9 100644 --- a/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml +++ b/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml @@ -23,11 +23,7 @@ properties: compatible: const: led-backlight - leds: - description: A list of LED nodes - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - maxItems: 1 + leds: true required: - compatible diff --git a/Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml index 8ed059a5a724..5c9cfa39396b 100644 --- a/Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml +++ b/Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml @@ -17,10 +17,7 @@ properties: compatible: const: leds-group-multicolor - leds: - description: - An aray of monochromatic leds - $ref: /schemas/types.yaml#/definitions/phandle-array + leds: true required: - leds diff --git a/Documentation/devicetree/bindings/media/video-interface-devices.yaml b/Documentation/devicetree/bindings/media/video-interface-devices.yaml index cf7712ad297c..3ad1590b0496 100644 --- a/Documentation/devicetree/bindings/media/video-interface-devices.yaml +++ b/Documentation/devicetree/bindings/media/video-interface-devices.yaml @@ -17,6 +17,14 @@ properties: An array of phandles, each referring to a flash LED, a sub-node of the LED driver device node. + leds: + minItems: 1 + maxItems: 1 + + led-names: + enum: + - privacy + lens-focus: $ref: /schemas/types.yaml#/definitions/phandle description: -- cgit v1.2.3 From 3bc3ff8fd2fe5886043b38d3d3c9d6ecb12d0a83 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 15 Sep 2025 23:24:15 -0500 Subject: dt-bindings: vendor-prefixes: Add Particle Industries Particle is a San Francisco-based company providing an integrated IoT Platform-as-a-Service. https://www.particle.io/ Acked-by: Rob Herring (Arm) Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20250915-tachyon-v2-1-4f8b02a17512@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b60957808e5f..50850df73187 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1181,6 +1181,8 @@ patternProperties: description: Parade Technologies Inc. "^parallax,.*": description: Parallax Inc. + "^particle,.*": + description: Particle Industries, Inc. "^pda,.*": description: Precision Design Associates, Inc. "^pegatron,.*": -- cgit v1.2.3 From b727cf24feb56a93f7bafbcdce7ea99b9ccb16cd Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 15 Sep 2025 23:24:16 -0500 Subject: dt-bindings: arm: qcom: Add Particle Tachyon The Particle Tachyon is a single board computer with 5G connectivity with AI accelerator, based on the Qualcomm QCM6490 platform. Document the top-level compatible for this board. Acked-by: Rob Herring (Arm) Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20250915-tachyon-v2-2-4f8b02a17512@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index cf49dd0000e0..0a05426acb6a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -331,6 +331,7 @@ properties: - items: - enum: - fairphone,fp5 + - particle,tachyon - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 - shift,otter -- cgit v1.2.3 From a58d6100ee2c4a732fb4e1520885958480a82110 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Mon, 15 Sep 2025 09:35:04 +0200 Subject: dt-bindings: arm: qcom: Add HP Omnibook X14 AI X1P4200 variant The HP Omnibook X14 AI PC is available in fe0 (Hamoa, x1e80100) and fe1 (Purwa, x1p42100) SKUs. Since they are not completely dtb-compatible, add another variant: hp,omnibook-x14-fe1 compatible to cqom,x1p42100 Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jens Glathe Link: https://lore.kernel.org/r/20250915-hp-x14-x1p-v9-1-fa457ca30ffe@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 0a05426acb6a..68cc458ca6bf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1072,6 +1072,7 @@ properties: - items: - enum: - asus,zenbook-a14-ux3407qa + - hp,omnibook-x14-fe1 - lenovo,thinkbook-16 - qcom,x1p42100-crd - const: qcom,x1p42100 -- cgit v1.2.3 From f3317e8c36a26d3374f29b8475982a96c6d44ccf Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Wed, 27 Aug 2025 15:51:58 +0200 Subject: dt-bindings: i3c: Add adi-i3c-master Add bindings doc for ADI I3C Controller IP core, a FPGA synthesizable IP core that implements the MIPI I3C Basic controller specification. The IP Core is versioned following Semantic Versioning 2.0.0 and ADI's open-source HDL guidelines for devicetree bindings and drivers. Reviewed-by: Conor Dooley Signed-off-by: Jorge Marques Link: https://lore.kernel.org/r/20250827-adi-i3c-master-v9-1-04413925abe1@analog.com Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/i3c/adi,i3c-master.yaml | 72 ++++++++++++++++++++++ MAINTAINERS | 5 ++ 2 files changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml new file mode 100644 index 000000000000..2498672d2654 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/adi,i3c-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices I3C Controller + +description: + FPGA-based I3C controller designed to interface with I3C and I2C peripherals, + implementing a subset of the I3C-basic specification. The IP core is tested + on arm, microblaze, and arm64 architectures. + + https://analogdevicesinc.github.io/hdl/library/i3c_controller + +maintainers: + - Jorge Marques + +properties: + compatible: + const: adi,i3c-master-v1 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: The AXI interconnect clock, drives the register map. + - description: + The secondary clock, drives the internal logic asynchronously to the + register map. The presence of this entry states that the IP Core was + synthesized with a second clock input, and the absence of this entry + indicates a topology where a single clock input drives all the + internal logic. + + clock-names: + minItems: 1 + items: + - const: axi + - const: i3c + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: i3c.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + i3c@44a00000 { + compatible = "adi,i3c-master-v1"; + reg = <0x44a00000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>, <&clkc 15>; + clock-names = "axi", "i3c"; + #address-cells = <3>; + #size-cells = <0>; + + /* I3C and I2C devices */ + }; diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..e6c913e7b0ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11606,6 +11606,11 @@ S: Maintained F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml F: drivers/i3c/master/ast2600-i3c-master.c +I3C DRIVER FOR ANALOG DEVICES I3C CONTROLLER IP +M: Jorge Marques +S: Maintained +F: Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml + I3C DRIVER FOR CADENCE I3C MASTER IP M: Przemysław Gaj S: Maintained -- cgit v1.2.3 From c5d0df4945085098e4778b27267a225efacf4d2a Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 8 Sep 2025 10:39:30 +0100 Subject: dt-bindings: i3c: renesas,i3c: Add RZ/V2H(P) and RZ/V2N support Add device tree binding support for the I3C Bus Interface on Renesas RZ/V2H(P) and RZ/V2N SoCs. The I3C IP on these SoCs is identical to that found on the RZ/G3E SoC. Add new compatible strings "renesas,r9a09g056-i3c" for RZ/V2N and "renesas,r9a09g057-i3c" for RZ/V2H(P). Both variants use "renesas,r9a09g047-i3c" as a fallback compatible to indicate hardware compatibility with the RZ/G3E implementation. Update the title to be more generic as it now covers multiple SoC families beyond just RZ/G3S and RZ/G3E. Signed-off-by: Lad Prabhakar Reviewed-by: Tommaso Merciai Acked-by: Rob Herring (Arm) Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/20250908093930.12591-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/i3c/renesas,i3c.yaml | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml index fe2e9633c46f..a20d875086d4 100644 --- a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml +++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface +title: Renesas I3C Bus Interface maintainers: - Wolfram Sang @@ -12,10 +12,16 @@ maintainers: properties: compatible: - items: - - enum: - - renesas,r9a08g045-i3c # RZ/G3S - - renesas,r9a09g047-i3c # RZ/G3E + oneOf: + - items: + - enum: + - renesas,r9a08g045-i3c # RZ/G3S + - renesas,r9a09g047-i3c # RZ/G3E + - items: + - enum: + - renesas,r9a09g056-i3c # RZ/V2N + - renesas,r9a09g057-i3c # RZ/V2H(P) + - const: renesas,r9a09g047-i3c reg: maxItems: 1 -- cgit v1.2.3 From 06ce29264f1d46f00fdb46b0c2d9fb060ce72368 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 15:11:27 -0400 Subject: dt-bindings: rtc: pcf85063: remove quartz-load-femtofarads restriction for nxp,pcf85063 Original TXT binding doc have not limitition about quartz-load-femtofarads, which only allow 7000 for nxp,pcf85063. So remove it to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dtb: rtc@51 (nxp,pcf85063): quartz-load-femtofarads:0: 7000 was expected from schema $id: http://devicetree.org/schemas/rtc/nxp,pcf85063.yaml# Signed-off-by: Frank Li Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250903191128.439164-1-Frank.Li@nxp.com Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml index 1e6277e524c2..f7013cd8fc20 100644 --- a/Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.yaml @@ -62,16 +62,6 @@ allOf: then: properties: quartz-load-femtofarads: false - - if: - properties: - compatible: - contains: - enum: - - nxp,pcf85063 - then: - properties: - quartz-load-femtofarads: - const: 7000 - if: properties: compatible: -- cgit v1.2.3 From 0dbb84b5c447ddf2681ed0248a6fb7c9fc3fdb6c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 27 Aug 2025 15:33:55 -0400 Subject: dt-bindings: rtc: trivial-rtc: add dallas,m41t00 Add compatible string dallas,m41t00 for dallas m41t00 RTC. Signed-off-by: Frank Li Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250827193356.78368-1-Frank.Li@nxp.com Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/trivial-rtc.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml index 5e0c7cd25cc6..587b7cd5806c 100644 --- a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml @@ -38,6 +38,8 @@ properties: - dallas,ds1672 # Extremely Accurate I²C RTC with Integrated Crystal and SRAM - dallas,ds3232 + # Dallas m41t00 Real-time Clock + - dallas,m41t00 # SD2405AL Real-Time Clock - dfrobot,sd2405al # EM Microelectronic EM3027 RTC -- cgit v1.2.3 From bf7ab18cd741ae82ee8d8e356f73ce3003f6b2fc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 15:00:27 +0200 Subject: dt-bindings: rtc: s3c: Drop S3C2410 Samsung S3C24xx family of SoCs was removed the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250830130024.142815-6-krzysztof.kozlowski@linaro.org Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/s3c-rtc.yaml | 40 ++-------------------- 1 file changed, 3 insertions(+), 37 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml b/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml index bf4e11d6dffb..338874e7ed7f 100644 --- a/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml @@ -13,9 +13,6 @@ properties: compatible: oneOf: - enum: - - samsung,s3c2410-rtc - - samsung,s3c2416-rtc - - samsung,s3c2443-rtc - samsung,s3c6410-rtc - items: - enum: @@ -29,19 +26,12 @@ properties: maxItems: 1 clocks: - description: - Must contain a list of phandle and clock specifier for the rtc - clock and in the case of a s3c6410 compatible controller, also - a source clock. - minItems: 1 maxItems: 2 clock-names: - description: - Must contain "rtc" and for a s3c6410 compatible controller - also "rtc_src". - minItems: 1 - maxItems: 2 + items: + - const: rtc + - const: rtc_src interrupts: description: @@ -54,30 +44,6 @@ properties: allOf: - $ref: rtc.yaml# - - if: - properties: - compatible: - contains: - enum: - - samsung,s3c6410-rtc - - samsung,exynos3250-rtc - then: - properties: - clocks: - minItems: 2 - maxItems: 2 - clock-names: - items: - - const: rtc - - const: rtc_src - else: - properties: - clocks: - minItems: 1 - maxItems: 1 - clock-names: - items: - - const: rtc unevaluatedProperties: false -- cgit v1.2.3 From 84454c4e504b1fe86f77a898190d63b4193ca25d Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 7 Aug 2025 16:44:13 -0500 Subject: dt-bindings: rtc: Drop isil,isl12057.txt The "isil,isl12057" compatible is already supported by rtc-ds1307.yaml, so remove the old text binding. Signed-off-by: Rob Herring (Arm) Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250807214414.4172910-1-robh@kernel.org Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/isil,isl12057.txt | 74 ---------------------- 1 file changed, 74 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12057.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12057.txt b/Documentation/devicetree/bindings/rtc/isil,isl12057.txt deleted file mode 100644 index ff7c43555199..000000000000 --- a/Documentation/devicetree/bindings/rtc/isil,isl12057.txt +++ /dev/null @@ -1,74 +0,0 @@ -Intersil ISL12057 I2C RTC/Alarm chip - -ISL12057 is a trivial I2C device (it has simple device tree bindings, -consisting of a compatible field, an address and possibly an interrupt -line). - -Nonetheless, it also supports an option boolean property -("wakeup-source") to handle the specific use-case found -on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104 -and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip -(associated with the alarm supported by the driver) is not connected -to the SoC but to a PMIC. It allows the device to be powered up when -RTC alarm rings. In order to mark the device has a wakeup source and -get access to the 'wakealarm' sysfs entry, this specific property can -be set when the IRQ#2 pin of the chip is not connected to the SoC but -can wake up the device. - -Required properties supported by the device: - - - "compatible": must be "isil,isl12057" - - "reg": I2C bus address of the device - -Optional properties: - - - "wakeup-source": mark the chip as a wakeup source, independently of - the availability of an IRQ line connected to the SoC. - - -Example isl12057 node without IRQ#2 pin connected (no alarm support): - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - }; - - -Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note -that the pinctrl-related properties below are given for completeness and -may not be required or may be different depending on your system or -SoC, and the main function of the MPP used as IRQ line, i.e. -"interrupt-parent" and "interrupts" are usually sufficient): - - pinctrl { - ... - - rtc_alarm_pin: rtc_alarm_pin { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - ... - - }; - - ... - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - pinctrl-0 = <&rtc_alarm_pin>; - pinctrl-names = "default"; - interrupt-parent = <&gpio0>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - }; - - -Example isl12057 node without IRQ#2 pin connected to the SoC but to a -PMIC, allowing the device to be started based on configured alarm: - - isl12057: isl12057@68 { - compatible = "isil,isl12057"; - reg = <0x68>; - wakeup-source; - }; -- cgit v1.2.3 From f2e44e5fb2de9a464b4fc94d8de071da7ebfda15 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 21 Aug 2025 16:57:01 -0500 Subject: dt-bindings: rtc: Fix Xicor X1205 vendor prefix The vendor for the Xircom X1205 RTC is not Xircom, but Xicor which was acquired by Intersil. Signed-off-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20250821215703.869628-1-robh@kernel.org Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/trivial-rtc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml index 587b7cd5806c..b47822370d6f 100644 --- a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml @@ -85,8 +85,8 @@ properties: - via,vt8500-rtc # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC - whwave,sd3078 - # Xircom X1205 I2C RTC - - xircom,x1205 + # Xicor/Intersil X1205 I2C RTC + - xicor,x1205 reg: maxItems: 1 -- cgit v1.2.3 From b4f7a727c29cd1fa6149a81f16408ee7c1f7de0c Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 9 Sep 2025 17:34:32 +0300 Subject: dt-bindings: power: supply: bq27xxx: document optional interrupt Document an optional interrupt found in some controllers of BQ27xxx series. The pin to which the interrupt is connected is called SOC_INT or GPOUT. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/supply/bq27xxx.yaml | 37 ++++++++++++++++++++-- 1 file changed, 34 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml index 309ea33b5b25..bc05400186cf 100644 --- a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml @@ -16,9 +16,6 @@ description: | Support various Texas Instruments fuel gauge devices that share similar register maps and power supply properties -allOf: - - $ref: power-supply.yaml# - properties: compatible: enum: @@ -58,6 +55,10 @@ properties: maxItems: 1 description: integer, I2C address of the fuel gauge. + interrupts: + maxItems: 1 + description: the SOC_INT or GPOUT pin + monitored-battery: description: | The fuel gauge uses the following battery properties: @@ -68,6 +69,36 @@ properties: power-supplies: true +allOf: + - $ref: power-supply.yaml# + - if: + properties: + compatible: + contains: + enum: + - ti,bq27200 + - ti,bq27210 + - ti,bq27500 # deprecated, use revision specific property below + - ti,bq27510 # deprecated, use revision specific property below + - ti,bq27520 # deprecated, use revision specific property below + - ti,bq27500-1 + - ti,bq27510g1 + - ti,bq27510g2 + - ti,bq27521 + - ti,bq27541 + - ti,bq27542 + - ti,bq27546 + - ti,bq27742 + - ti,bq27545 + - ti,bq27411 + - ti,bq27z561 + - ti,bq28z610 + - ti,bq34z100 + - ti,bq78z100 + then: + properties: + interrupts: false + required: - compatible - reg -- cgit v1.2.3 From d1829e0b2f0619c39b0ce0b84fcbf67569108376 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 5 Sep 2025 07:39:40 -0700 Subject: dt-bindings: riscv: starfive: add milkv,marscm-emmc Add "milkv,marscm-emmc" as a StarFive JH7110 SoC-based system-on-module. Signed-off-by: E Shattow Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 7ef85174353d..0713edb687fe 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -28,6 +28,7 @@ properties: - enum: - deepcomputing,fml13v01 - milkv,mars + - milkv,marscm-emmc - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b -- cgit v1.2.3 From 12a29108384cfe073a4de778d5207d53b492f85e Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 5 Sep 2025 07:39:42 -0700 Subject: dt-bindings: riscv: starfive: add milkv,marscm-lite Add "milkv,marscm-lite" as a StarFive JH7110 SoC-based system-on-module. Signed-off-by: E Shattow Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 0713edb687fe..04510341a71e 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -29,6 +29,7 @@ properties: - deepcomputing,fml13v01 - milkv,mars - milkv,marscm-emmc + - milkv,marscm-lite - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b -- cgit v1.2.3 From 7c85e4da8ce734eaca66a921aabeb6107842169f Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Sat, 6 Sep 2025 15:16:56 -0500 Subject: dt-bindings: clock: silabs,si5341: Add missing properties Add "clock-output-names" which is a standard property for clock providers. Add the "always-on" boolean property which was undocumented, but already in use for some time. The flag prevents a clock output from being disabled. Signed-off-by: Rob Herring (Arm) Tested-by: Michal Simek Reviewed-by: Michal Simek Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/silabs,si5341.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/silabs,si5341.yaml b/Documentation/devicetree/bindings/clock/silabs,si5341.yaml index b4f7efdf0b7b..d6416bded3d5 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5341.yaml +++ b/Documentation/devicetree/bindings/clock/silabs,si5341.yaml @@ -73,6 +73,8 @@ properties: - const: in1 - const: in2 + clock-output-names: true + interrupts: maxItems: 1 description: Interrupt for INTRb pin @@ -130,6 +132,10 @@ patternProperties: description: Number of clock output maximum: 9 + always-on: + description: Set to keep the clock output always running + type: boolean + silabs,format: description: Output format $ref: /schemas/types.yaml#/definitions/uint32 -- cgit v1.2.3 From 7d547c1c249872b7732767e483758cb4fcb2d99b Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sat, 13 Sep 2025 00:53:47 +0800 Subject: dt-bindings: usb: dwc3: add support for SpacemiT K1 Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded in the SpacemiT K1 SoC. The controller is based on the Synopsys DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0 DRD mode. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Ze Huang Link: https://lore.kernel.org/r/20250913-dwc3_generic-v8-1-b50f81f05f95@linux.dev Signed-off-by: Greg Kroah-Hartman Link: https://lore.kernel.org/r/20250913-dwc3_generic-v8-1-b50f81f05f95@linux.dev --- .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml new file mode 100644 index 000000000000..0f0b5e061ca1 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller + +maintainers: + - Ze Huang + +description: | + The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions + for USB 3.0 and DRD for USB 2.0. + + Key features: + - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support + - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3) + - Internal DMA controller and flexible endpoint FIFO sizing + + Communication Interface: + - Use of PIPE3 (125MHz) interface for USB3.0 PHY + - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: spacemit,k1-dwc3 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: usbdrd30 + + interrupts: + maxItems: 1 + + phys: + items: + - description: phandle to USB2/HS PHY + - description: phandle to USB3/SS PHY + + phy-names: + items: + - const: usb2-phy + - const: usb3-phy + + resets: + items: + - description: USB3.0 AHB reset + - description: USB3.0 VCC reset + - description: USB3.0 PHY reset + + reset-names: + items: + - const: ahb + - const: vcc + - const: phy + + reset-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 2 + description: delay after reset sequence [us] + + vbus-supply: + description: A phandle to the regulator supplying the VBUS voltage. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - phy-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + usb@c0a00000 { + compatible = "spacemit,k1-dwc3"; + reg = <0xc0a00000 0x10000>; + clocks = <&syscon_apmu 16>; + clock-names = "usbdrd30"; + interrupts = <125>; + phys = <&usb2phy>, <&usb3phy>; + phy-names = "usb2-phy", "usb3-phy"; + resets = <&syscon_apmu 8>, + <&syscon_apmu 9>, + <&syscon_apmu 10>; + reset-names = "ahb", "vcc", "phy"; + reset-delay = <2>; + vbus-supply = <&usb3_vbus>; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <1>; + vdd-supply = <&usb3_vhub>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio 3 28 1>; + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <2>; + vdd-supply = <&usb3_vhub>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio 3 28 1>; + }; + }; -- cgit v1.2.3 From dd0d2618e3f815a030622599e540d3be1964a888 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 16 Sep 2025 16:02:39 +0100 Subject: dt-bindings: usb: Document Renesas RZ/G3E USB3HOST Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST). The USB3HOST is compliant with the Universal Serial Bus 3.2 Specification Revision 1.0. - Supports 1 downstream USB receptacles - Number of SSP Gen2 or SS ports: 1 - Number of HS or FS or LS ports: 1 - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps), High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps). - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and these split-transactions. - Supports Power Control and Over Current Detection. Reviewed-by: Rob Herring (Arm) Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20250916150255.4231-4-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman --- .../bindings/usb/renesas,rzg3e-xhci.yaml | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml new file mode 100644 index 000000000000..98260f9fb442 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E USB 3.2 Gen2 Host controller + +maintainers: + - Biju Das + +properties: + compatible: + const: renesas,r9a09g047-xhci + + reg: + maxItems: 1 + + interrupts: + items: + - description: Logical OR of all interrupt signals. + - description: System management interrupt + - description: Host system error interrupt + - description: Power management event interrupt + - description: xHC interrupt + + interrupt-names: + items: + - const: all + - const: smi + - const: hse + - const: pme + - const: xhc + + clocks: + maxItems: 1 + + phys: + maxItems: 2 + + phy-names: + items: + - const: usb2-phy + - const: usb3-phy + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - power-domains + - resets + - phys + - phy-names + +allOf: + - $ref: usb-xhci.yaml + +additionalProperties: false + +examples: + - | + #include + #include + + usb@15850000 { + compatible = "renesas,r9a09g047-xhci"; + reg = <0x15850000 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + }; -- cgit v1.2.3 From 5bcf9e1d0a5da750ff180e7385b0bd4041686516 Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Sat, 13 Sep 2025 23:12:48 +0200 Subject: dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add required syscon compatible and #power-domain-cells to the APMU controller. This is required for the SoC's power domain controller as the registers are shared. Device tree bindings for said power domains are also added. Reviewed-by: Rob Herring (Arm) Signed-off-by: Duje Mihanović Signed-off-by: Ulf Hansson --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 30 +++++++++++++++++----- MAINTAINERS | 1 + include/dt-bindings/power/marvell,pxa1908-power.h | 17 ++++++++++++ 3 files changed, 42 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/power/marvell,pxa1908-power.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml index 4e78933232b6..6f3a8578fe2a 100644 --- a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -19,11 +19,14 @@ description: | properties: compatible: - enum: - - marvell,pxa1908-apbc - - marvell,pxa1908-apbcp - - marvell,pxa1908-mpmu - - marvell,pxa1908-apmu + oneOf: + - enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - items: + - const: marvell,pxa1908-apmu + - const: syscon reg: maxItems: 1 @@ -31,6 +34,9 @@ properties: '#clock-cells': const: 1 + '#power-domain-cells': + const: 1 + required: - compatible - reg @@ -38,11 +44,23 @@ required: additionalProperties: false +if: + not: + properties: + compatible: + contains: + const: marvell,pxa1908-apmu + +then: + properties: + '#power-domain-cells': false + examples: # APMU block: - | clock-controller@d4282800 { - compatible = "marvell,pxa1908-apmu"; + compatible = "marvell,pxa1908-apmu", "syscon"; reg = <0xd4282800 0x400>; #clock-cells = <1>; + #power-domain-cells = <1>; }; diff --git a/MAINTAINERS b/MAINTAINERS index daf520a13bdf..22aa7ce417b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2872,6 +2872,7 @@ S: Maintained F: arch/arm64/boot/dts/marvell/mmp/ F: drivers/clk/mmp/clk-pxa1908*.c F: include/dt-bindings/clock/marvell,pxa1908.h +F: include/dt-bindings/power/marvell,pxa1908-power.h ARM/Mediatek RTC DRIVER M: Eddie Huang diff --git a/include/dt-bindings/power/marvell,pxa1908-power.h b/include/dt-bindings/power/marvell,pxa1908-power.h new file mode 100644 index 000000000000..19b088351af1 --- /dev/null +++ b/include/dt-bindings/power/marvell,pxa1908-power.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Marvell PXA1908 power domains + * + * Copyright 2025, Duje Mihanović + */ + +#ifndef __DTS_MARVELL_PXA1908_POWER_H +#define __DTS_MARVELL_PXA1908_POWER_H + +#define PXA1908_POWER_DOMAIN_VPU 0 +#define PXA1908_POWER_DOMAIN_GPU 1 +#define PXA1908_POWER_DOMAIN_GPU2D 2 +#define PXA1908_POWER_DOMAIN_DSI 3 +#define PXA1908_POWER_DOMAIN_ISP 4 + +#endif -- cgit v1.2.3 From 9bc7130822c4c7f3ef39f20174a379e476586ab3 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Thu, 11 Sep 2025 10:02:51 +0530 Subject: dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus Introduce a new YAML schema for QUP-supported peripherals. Define common properties used across QUP-supported peripherals. Add property `qcom,enable-gsi-dma` to configure the Serial Engine (SE) for QCOM GPI DMA mode. Reference the common schema YAML in the GENI I2C, SPI, and SERIAL YAML files. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20250911043256.3523057-2-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 1 + .../bindings/serial/qcom,serial-geni-qcom.yaml | 1 + .../bindings/soc/qcom/qcom,se-common-props.yaml | 26 ++++++++++++++++++++++ .../bindings/spi/qcom,spi-geni-qcom.yaml | 1 + 4 files changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 9f66a3bb1f80..51534953a69c 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -75,6 +75,7 @@ required: allOf: - $ref: /schemas/i2c/i2c-controller.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml index dd33794b3534..ed7b3909d87d 100644 --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml @@ -12,6 +12,7 @@ maintainers: allOf: - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml new file mode 100644 index 000000000000..6a34f05a07e8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,se-common-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QUP Peripheral-specific properties for I2C, SPI and SERIAL bus + +description: + The Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) is + a programmable module that supports a wide range of serial interfaces + such as UART, SPI, I2C, I3C, etc. This defines the common properties used + across QUP-supported peripherals. + +maintainers: + - Mukesh Kumar Savaliya + - Viken Dadhaniya + +properties: + qcom,enable-gsi-dma: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the Serial Engine (SE) to transfer data in QCOM GPI DMA mode. + By default, FIFO mode (PIO/CPU DMA) will be selected. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml index 2e20ca313ec1..d12c5a060ed0 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -25,6 +25,7 @@ description: allOf: - $ref: /schemas/spi/spi-controller.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# properties: compatible: -- cgit v1.2.3 From f9d803784f8dfea60f394d7fc94084c5f1eb4027 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 Sep 2025 14:11:18 -0700 Subject: dt-bindings: input: touchscreen: document Himax HX852x(ES) Himax HX852x(ES) is a touch panel controller with optional support for capacitive touch keys. Unfortunately, the model naming is quite unclear and confusing. There seems to be a distinction between models (e.g. HX8526) and the "series" suffix (e.g. -A, -B, -C, -D, -E, -ES). But this doesn't seem to be applied very consistently because e.g. HX8527-E(44) actually seems to belong to the -ES series. The compatible consists of the actual part number followed by the "series" as fallback compatible. Typically only the latter will be interesting for drivers as there is no relevant difference on the driver side. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250915-hx852x-v5-1-b938182f1056@linaro.org Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/himax,hx852es.yaml | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/himax,hx852es.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/himax,hx852es.yaml b/Documentation/devicetree/bindings/input/touchscreen/himax,hx852es.yaml new file mode 100644 index 000000000000..40a60880111d --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/himax,hx852es.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/himax,hx852es.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX852x(ES) touch panel controller + +maintainers: + - Stephan Gerhold + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + items: + - enum: + - himax,hx8525e + - himax,hx8526e + - himax,hx8527e + - const: himax,hx852es + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: Touch Screen Interrupt (TSIX), active low + + reset-gpios: + maxItems: 1 + description: External Reset (XRES), active low + + vcca-supply: + description: Analog power supply (VCCA) + + vccd-supply: + description: Digital power supply (VCCD) + + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + + linux,keycodes: + minItems: 1 + maxItems: 4 + +required: + - compatible + - reg + - interrupts + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@48 { + compatible = "himax,hx8527e", "himax,hx852es"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + vcca-supply = <®_ts_vcca>; + vccd-supply = <&pm8916_l6>; + linux,keycodes = ; + }; + }; + +... -- cgit v1.2.3 From c3a45c5fde95d319125812f629c579cc63c69941 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 12 Sep 2025 09:51:46 +0300 Subject: dt-bindings: power: supply: bq24190: document charge enable pin Document active low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE pin = Low. CE pin must be pulled high or low. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/bq24190.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.yaml b/Documentation/devicetree/bindings/power/supply/bq24190.yaml index ac9a76fc5876..938554a9fb02 100644 --- a/Documentation/devicetree/bindings/power/supply/bq24190.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq24190.yaml @@ -30,6 +30,12 @@ properties: interrupts: maxItems: 1 + ce-gpios: + description: + Active low Charge Enable pin. Battery charging is enabled when + REG01[5:4] = 01 and CE pin is Low. CE pin must be pulled high or low. + maxItems: 1 + usb-otg-vbus: $ref: /schemas/regulator/regulator.yaml# description: | -- cgit v1.2.3 From 7f8624af8e8c2c1a0169b46a23729a4cc614635c Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 17 Sep 2025 18:15:19 +0800 Subject: dt-bindings: soc: qcom,pmic-glink: Add charge limit nvmem properties Add nvmem properties to retrieve charge control configurations from the PMIC SDAM registers. Acked-by: Rob Herring (Arm) Signed-off-by: Fenglin Wu Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 48114bb0c927..7085bf88afab 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -56,6 +56,20 @@ properties: The array should contain a gpio entry for each PMIC Glink connector, in reg order. It is defined that GPIO active level means "CC2" or Reversed/Flipped orientation. + nvmem-cells: + minItems: 3 + maxItems: 3 + description: + The nvmem cells contain the charge control settings, including the charge control + enable status, the battery state of charge (SoC) threshold for stopping charging, + and the battery SoC delta required to restart charging. + + nvmem-cell-names: + items: + - const: charge_limit_en + - const: charge_limit_end + - const: charge_limit_delta + patternProperties: '^connector@\d$': $ref: /schemas/connector/usb-connector.yaml# -- cgit v1.2.3 From 458bb855f274e227618acfa8c098b8e4894d9cd9 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 17 Sep 2025 10:58:58 +0800 Subject: dt-bindings: arm: qcom: Document HAMOA-IOT-EVK board Document the device tree binding for the HAMOA-IOT-EVK board, which uses the Qualcomm X1E80100 SoC. The EVK consists of a carrier board and a modular System-on-Module (SoM). The SoM integrates the SoC, PMICs, and essential GPIOs, while the EVK carrier board provides additional peripherals such as UART and USB interfaces. Acked-by: Krzysztof Kozlowski Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20250917-hamoa_initial-v12-1-4ed39d17dfc5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 68cc458ca6bf..4f403b99c3fd 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1069,6 +1069,12 @@ properties: - qcom,x1e80100-qcp - const: qcom,x1e80100 + - items: + - enum: + - qcom,hamoa-iot-evk + - const: qcom,hamoa-iot-som + - const: qcom,x1e80100 + - items: - enum: - asus,zenbook-a14-ux3407qa -- cgit v1.2.3 From 1081eafa1bca16d3610bf44f515550d060526dd4 Mon Sep 17 00:00:00 2001 From: Eric Gonçalves Date: Tue, 16 Sep 2025 18:04:08 +0000 Subject: dt-bindings: arm: qcom: sort sm8450 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The bindings had samsung,r0q before sony,pdx*, which is out of alphabetical order, solve this issue by moving samsung,r0q before the pdx boards. Signed-off-by: Eric Gonçalves Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250916180409.157115-1-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 4f403b99c3fd..d89d1093cd15 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1005,9 +1005,9 @@ properties: - enum: - qcom,sm8450-hdk - qcom,sm8450-qrd + - samsung,r0q - sony,pdx223 - sony,pdx224 - - samsung,r0q - const: qcom,sm8450 - items: -- cgit v1.2.3 From 1b7d2e1742427527aac2b2d5cb92fb8f2f047cad Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 16 Sep 2025 13:13:26 -0400 Subject: dt-bindings: input: convert tca8418_keypad.txt to yaml format Convert tca8418_keypad.txt to yaml format. Signed-off-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250916171327.3773620-1-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov --- .../devicetree/bindings/input/tca8418_keypad.txt | 10 ---- .../devicetree/bindings/input/ti,tca8418.yaml | 61 ++++++++++++++++++++++ 2 files changed, 61 insertions(+), 10 deletions(-) delete mode 100644 Documentation/devicetree/bindings/input/tca8418_keypad.txt create mode 100644 Documentation/devicetree/bindings/input/ti,tca8418.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/tca8418_keypad.txt b/Documentation/devicetree/bindings/input/tca8418_keypad.txt deleted file mode 100644 index 255185009167..000000000000 --- a/Documentation/devicetree/bindings/input/tca8418_keypad.txt +++ /dev/null @@ -1,10 +0,0 @@ -This binding is based on the matrix-keymap binding with the following -changes: - -keypad,num-rows and keypad,num-columns are required. - -Required properties: -- compatible: "ti,tca8418" -- reg: the I2C address -- interrupts: IRQ line number, should trigger on falling edge -- linux,keymap: Keys definitions, see keypad-matrix. diff --git a/Documentation/devicetree/bindings/input/ti,tca8418.yaml b/Documentation/devicetree/bindings/input/ti,tca8418.yaml new file mode 100644 index 000000000000..624a1830d0b0 --- /dev/null +++ b/Documentation/devicetree/bindings/input/ti,tca8418.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/ti,tca8418.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI TCA8418 I2C/SMBus keypad scanner + +maintainers: + - Frank Li + +properties: + compatible: + enum: + - ti,tca8418 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: matrix-keymap.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + keypad@34 { + compatible = "ti,tca8418"; + reg = <0x34>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + keypad,num-rows = <4>; + keypad,num-columns = <4>; + linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0) + MATRIX_KEY(0x00, 0x00, BTN_1) + MATRIX_KEY(0x01, 0x01, BTN_2) + MATRIX_KEY(0x01, 0x00, BTN_3) + MATRIX_KEY(0x02, 0x00, BTN_4) + MATRIX_KEY(0x00, 0x03, BTN_5) + MATRIX_KEY(0x00, 0x02, BTN_6) + MATRIX_KEY(0x01, 0x03, BTN_7) + MATRIX_KEY(0x01, 0x02, BTN_8) + MATRIX_KEY(0x02, 0x02, BTN_9) + >; + }; + }; -- cgit v1.2.3 From 6e4a5154934f8c7283452651c4d398d34a46e952 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 10 Sep 2025 18:44:01 -0400 Subject: dt-bindings: touchscreen: resistive-adc-touch: change to unevaluatedProperties Change additionalProperties to unevaluatedProperties because it refs to touchscreen.yaml. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dtb: touchscreen (resistive-adc-touch): 'touchscreen-y-plate-ohms' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/input/touchscreen/resistive-adc-touch.yaml# Signed-off-by: Frank Li Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250910224402.994046-1-Frank.Li@nxp.com Signed-off-by: Dmitry Torokhov --- .../devicetree/bindings/input/touchscreen/resistive-adc-touch.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.yaml b/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.yaml index 7fc22a403d48..059d419f6c1c 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.yaml @@ -55,7 +55,7 @@ properties: touchscreen-min-pressure: true touchscreen-x-plate-ohms: true -additionalProperties: false +unevaluatedProperties: false required: - compatible -- cgit v1.2.3 From 28f94ed138c347504c1b1b94291da8a9a398e0d7 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:44 +0200 Subject: dt-bindings: arm: apple: Add t6020x compatibles This adds the following apple,t6020/t6021/t6022 platforms: - apple,j414s - MacBook Pro (14-inch, M2 Pro, 2023) - apple,j414c - MacBook Pro (14-inch, M2 Nax, 2023) - apple,j416s - MacBook Pro (16-inch, M2 Pro, 2023) - apple,j416c - MacBook Pro (16-inch, M2 Max, 2023) - apple,j474s - Mac mini (M2 Pro, 2023) - apple,j475c - Mac Studio (M2 Max, 2023) - apple,j475d - Mac Studio (M2 Ultra, 2023) - apple,j475d - Mac Pro (M2 Ultra, 2023) Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/arm/apple.yaml | 39 +++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 7073535b7c5b..5c2629ec3d4c 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -96,7 +96,7 @@ description: | - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) - And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: + Devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: - MacBook Pro (14-inch, M1 Pro, 2021) - MacBook Pro (14-inch, M1 Max, 2021) @@ -105,6 +105,17 @@ description: | - Mac Studio (M1 Max, 2022) - Mac Studio (M1 Ultra, 2022) + Devices based on the "M2 Pro", "M2 Max" and "M2 Ultra" SoCs: + + - MacBook Pro (14-inch, M2 Pro, 2023) + - MacBook Pro (14-inch, M2 Max, 2023) + - MacBook Pro (16-inch, M2 Pro, 2023) + - MacBook Pro (16-inch, M2 Max, 2023) + - Mac mini (M2 Pro, 2023) + - Mac Studio (M2 Max, 2023) + - Mac Studio (M2 Ultra, 2023) + - Mac Pro (M2 Ultra, 2023) + The compatible property should follow this format: compatible = "apple,", "apple,", "apple,arm-platform"; @@ -310,6 +321,32 @@ properties: - const: apple,t6002 - const: apple,arm-platform + - description: Apple M2 Pro SoC based platforms + items: + - enum: + - apple,j414s # MacBook Pro (14-inch, M2 Pro, 2023) + - apple,j416s # MacBook Pro (16-inch, M2 Pro, 2023) + - apple,j474s # Mac mini (M2 Pro, 2023) + - const: apple,t6020 + - const: apple,arm-platform + + - description: Apple M2 Max SoC based platforms + items: + - enum: + - apple,j414c # MacBook Pro (14-inch, M2 Max, 2023) + - apple,j416c # MacBook Pro (16-inch, M2 Max, 2023) + - apple,j475c # Mac Studio (M2 Max, 2023) + - const: apple,t6021 + - const: apple,arm-platform + + - description: Apple M2 Ultra SoC based platforms + items: + - enum: + - apple,j180d # Mac Pro (M2 Ultra, 2023) + - apple,j475d # Mac Studio (M2 Ultra, 2023) + - const: apple,t6022 + - const: apple,arm-platform + additionalProperties: true ... -- cgit v1.2.3 From f8cc02321bfca71967db1620d684aa3abab59612 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Thu, 21 Aug 2025 19:01:49 +0800 Subject: dt-bindings: perf: fsl-imx-ddr: Add a compatible string fsl,imx94-ddr-pmu for i.MX94 i.MX94 has a DDR Performance Monitor Unit which is compatible with i.MX93. This will add a compatible for i.MX94. Reviewed-by: Peng Fan Reviewed-by: Frank Li Acked-by: Conor Dooley Signed-off-by: Xu Yang Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml index 8597ea625edb..d2e578d6b83b 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml @@ -33,6 +33,7 @@ properties: - items: - enum: - fsl,imx91-ddr-pmu + - fsl,imx94-ddr-pmu - fsl,imx95-ddr-pmu - const: fsl,imx93-ddr-pmu -- cgit v1.2.3 From 0bb8d67611b59740f47ad57658a8d2986c43f8c1 Mon Sep 17 00:00:00 2001 From: Kaison Deng Date: Mon, 15 Sep 2025 10:22:04 +0800 Subject: dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT This documents Firefly ROC-RK3588-RT which is a SBC based on RK3588 SoC. Link: https://en.t-firefly.com/product/industry/rocrk3588rt Signed-off-by: Kaison Deng Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/27b2ce7950fdbf28c6c8404c3f8be3c1c35d6b3c.1757902513.git.dkx@t-chip.com.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index f9ee77f17ad7..6aceaa8acbb2 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -258,6 +258,11 @@ properties: - const: firefly,roc-rk3576-pc - const: rockchip,rk3576 + - description: Firefly ROC-RK3588-RT + items: + - const: firefly,roc-rk3588-rt + - const: rockchip,rk3588 + - description: Firefly Station M2 items: - const: firefly,rk3566-roc-pc -- cgit v1.2.3 From 4b167146ec051dce3e770052ddfe4689f41cfdd3 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Mon, 15 Sep 2025 09:52:24 +0800 Subject: dt-bindings: spmi: Add Apple A11 and T2 compatible The SPMI bus found on Apple A11 and T2 SoCs are compatible with the existing driver for t8103's spmi so add their compatibles. Signed-off-by: Nick Chan Acked-by: Rob Herring (Arm) Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/spmi/apple,spmi.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml index dbf09ad0ecde..ba524f1eb704 100644 --- a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml @@ -18,7 +18,10 @@ properties: compatible: oneOf: - items: - - const: apple,t6020-spmi + - enum: + - apple,t6020-spmi + - apple,t8012-spmi + - apple,t8015-spmi - const: apple,t8103-spmi - items: - enum: -- cgit v1.2.3 From 7e52794b88f8bce684ffd7081279ac4236131ae1 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 18 Sep 2025 17:36:06 +0200 Subject: dt-bindings: touchscreen: convert bu21013 bindings to json schema Convert Rohm BU21013 I2C touchscreen controller device tree binding to json-schema. Additional changes: - Replace -supply with avdd-supply to match example and existing DTS. - Add reset-gpios in the example because it is required. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250918153630.2535208-1-dario.binacchi@amarulasolutions.com Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/bu21013.txt | 43 ---------- .../bindings/input/touchscreen/rohm,bu21013.yaml | 95 ++++++++++++++++++++++ 2 files changed, 95 insertions(+), 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/bu21013.txt create mode 100644 Documentation/devicetree/bindings/input/touchscreen/rohm,bu21013.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt deleted file mode 100644 index da4c9d8b99b1..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Rohm BU21013 Touch Screen - -Required properties: - - compatible : "rohm,bu21013_tp" - - reg : I2C device address - - reset-gpios : GPIO pin enabling (selecting) chip (CS) - - interrupt-parent : the phandle for the gpio controller - - interrupts : (gpio) interrupt to which the chip is connected - -Optional properties: - - touch-gpios : GPIO pin registering a touch event - - -supply : Phandle to a regulator supply - - touchscreen-size-x : General touchscreen binding, see [1]. - - touchscreen-size-y : General touchscreen binding, see [1]. - - touchscreen-inverted-x : General touchscreen binding, see [1]. - - touchscreen-inverted-y : General touchscreen binding, see [1]. - - touchscreen-swapped-x-y : General touchscreen binding, see [1]. - -[1] All general touchscreen properties are described in - Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt. - -Deprecated properties: - - rohm,touch-max-x : Maximum outward permitted limit in the X axis - - rohm,touch-max-y : Maximum outward permitted limit in the Y axis - - rohm,flip-x : Flip touch coordinates on the X axis - - rohm,flip-y : Flip touch coordinates on the Y axis - -Example: - - i2c@80110000 { - bu21013_tp@5c { - compatible = "rohm,bu21013_tp"; - reg = <0x5c>; - interrupt-parent = <&gpio2>; - interrupts <&20 IRQ_TYPE_LEVEL_LOW>; - touch-gpio = <&gpio2 20 GPIO_ACTIVE_LOW>; - avdd-supply = <&ab8500_ldo_aux1_reg>; - - touchscreen-size-x = <384>; - touchscreen-size-y = <704>; - touchscreen-inverted-y; - }; - }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/rohm,bu21013.yaml b/Documentation/devicetree/bindings/input/touchscreen/rohm,bu21013.yaml new file mode 100644 index 000000000000..adea2c4edf1f --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/rohm,bu21013.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/rohm,bu21013.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rohm BU21013 touchscreen + +description: + Rohm BU21013 I2C driven touchscreen controller. + +maintainers: + - Dario Binacchi + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - rohm,bu21013_tp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + touch-gpios: + maxItems: 1 + description: GPIO registering a touch event. + + avdd-supply: + description: Analogic power supply + + rohm,touch-max-x: + deprecated: true + description: Maximum value on the X axis. + $ref: /schemas/types.yaml#/definitions/uint32 + + rohm,touch-max-y: + deprecated: true + description: Maximum value on the Y axis. + $ref: /schemas/types.yaml#/definitions/uint32 + + rohm,flip-x: + deprecated: true + description: Flip touch coordinates on the X axis + type: boolean + + rohm,flip-y: + deprecated: true + description: Flip touch coordinates on the Y axis + type: boolean + + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + +additionalProperties: false + +required: + - compatible + - reg + - reset-gpios + - interrupts + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@5c { + compatible = "rohm,bu21013_tp"; + reg = <0x5c>; + + interrupt-parent = <&gpio2>; + interrupts = <0x20 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + touch-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + + touchscreen-size-x = <384>; + touchscreen-size-y = <704>; + touchscreen-inverted-y; + }; + }; -- cgit v1.2.3 From 7ee0f793d00d586bf01017a0a24308659873975c Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 18 Sep 2025 17:36:09 +0200 Subject: dt-bindings: touchscreen: convert zet6223 bindings to json schema Convert Zeitec ZET6223 touchscreen controller device tree binding to json-schema. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250918153630.2535208-4-dario.binacchi@amarulasolutions.com Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/zeitec,zet6223.yaml | 62 ++++++++++++++++++++++ .../bindings/input/touchscreen/zet6223.txt | 30 ----------- 2 files changed, 62 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/zeitec,zet6223.yaml delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/zet6223.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/zeitec,zet6223.yaml b/Documentation/devicetree/bindings/input/touchscreen/zeitec,zet6223.yaml new file mode 100644 index 000000000000..d5e132ec0273 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/zeitec,zet6223.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/zeitec,zet6223.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zeitec ZET6223 touchscreen controller + +description: + Zeitec ZET6223 I2C driven touchscreen controller. + +maintainers: + - Dario Binacchi + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - zeitec,zet6223 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vio-supply: + description: 1.8V or 3.3V VIO supply. + + vcc-supply: + description: 3.3V VCC supply. + + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@76 { + compatible = "zeitec,zet6223"; + reg = <0x76>; + interrupt-parent = <&pio>; + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt b/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt deleted file mode 100644 index 27d55a506f18..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/zet6223.txt +++ /dev/null @@ -1,30 +0,0 @@ -Zeitec ZET6223 I2C touchscreen controller - -Required properties: -- compatible : "zeitec,zet6223" -- reg : I2C slave address of the chip (0x76) -- interrupts : interrupt specification for the zet6223 interrupt - -Optional properties: - -- vio-supply : Specification for VIO supply (1.8V or 3.3V, - depending on system interface needs). -- vcc-supply : Specification for 3.3V VCC supply. -- touchscreen-size-x : See touchscreen.txt -- touchscreen-size-y : See touchscreen.txt -- touchscreen-inverted-x : See touchscreen.txt -- touchscreen-inverted-y : See touchscreen.txt -- touchscreen-swapped-x-y : See touchscreen.txt - -Example: - -i2c@00000000 { - - zet6223: touchscreen@76 { - compatible = "zeitec,zet6223"; - reg = <0x76>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING> - }; - -}; -- cgit v1.2.3 From f79671dc87b6cea78dbe429969eb5549fca1bcc1 Mon Sep 17 00:00:00 2001 From: Aleksa Paunovic Date: Thu, 24 Jul 2025 17:23:25 +0200 Subject: dt-bindings: riscv: Add xmipsexectl ISA extension description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The xmipsexectl extension is described in the MIPS RV64 P8700/P8700-F Multiprocessing System Programmer’s Guide linked at [1]. Link: https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf Signed-off-by: Aleksa Paunovic Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-1-a6cbbe1c3412@htecgroup.com Signed-off-by: Paul Walmsley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf53..de41a6f074d3 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -662,6 +662,12 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + # MIPS + - const: xmipsexectl + description: + The MIPS extension for execution control as documented in + https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf + # SiFive - const: xsfvqmaccdod description: -- cgit v1.2.3 From f9d3206506b4db2711eca0f6b3d9dc621cc1e650 Mon Sep 17 00:00:00 2001 From: "J. Neuschäfer" Date: Thu, 18 Sep 2025 12:58:43 +0200 Subject: dt-bindings: arm: sunxi: Add Amediatech X96Q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The X96Q is a set-top box with an H313 SoC, AXP305 PMIC, 1 or 2 GiB RAM, 8 or 16 GiB eMMC flash, 2x USB A, Micro-SD, HDMI, Ethernet, audio/video output, and infrared input. https://x96mini.com/products/x96q-tv-box-android-10-set-top-box Reviewed-by: Andre Przywara Acked-by: Rob Herring (Arm) Signed-off-by: J. Neuschäfer Link: https://patch.msgid.link/20250918-x96q-v2-1-51bd39928806@posteo.net Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 72ef861a0b68..9e4627f97d7e 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -971,6 +971,11 @@ properties: - const: hechuang,x96-mate - const: allwinner,sun50i-h616 + - description: X96Q + items: + - const: amediatech,x96q + - const: allwinner,sun50i-h616 + - description: X96Q Pro+ items: - const: amediatech,x96q-pro-plus -- cgit v1.2.3 From 8a454c05632077e9bee51ddbf8a633739490e308 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 7 Aug 2025 16:42:21 -0500 Subject: dt-bindings: watchdog: Drop duplicate moxa,moxart-watchdog.txt "moxa,moxart-watchdog" is already documented in faraday,ftwdt010.yaml, so drop the old text binding. Reviewed-by: Guenter Roeck Fixes: 289660a4af0e ("dt-bindings: watchdog: convert faraday,ftwdt010 to yaml") Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250807214222.4170236-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/watchdog/moxa,moxart-watchdog.txt | 15 --------------- 1 file changed, 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt b/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt deleted file mode 100644 index 1169857d1d12..000000000000 --- a/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt +++ /dev/null @@ -1,15 +0,0 @@ -MOXA ART Watchdog timer - -Required properties: - -- compatible : Must be "moxa,moxart-watchdog" -- reg : Should contain registers location and length -- clocks : Should contain phandle for the clock that drives the counter - -Example: - - watchdog: watchdog@98500000 { - compatible = "moxa,moxart-watchdog"; - reg = <0x98500000 0x10>; - clocks = <&coreclk>; - }; -- cgit v1.2.3 From 72289f57b071b35fa4fe48382ce30ea5c7d60ebc Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 13:13:46 -0500 Subject: dt-bindings: mailbox: Convert rockchip,rk3368-mailbox to DT schema Convert the rockchip,rk3368-mailbox binding to DT schema format. Add the missing 'clocks' and 'clock-names' properties. Document that it's one interrupt per mailbox channel (and there are 4 channels). Link: https://lore.kernel.org/r/20250812181348.62137-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../bindings/mailbox/rockchip,rk3368-mailbox.yaml | 56 ++++++++++++++++++++++ .../bindings/mailbox/rockchip-mailbox.txt | 32 ------------- 2 files changed, 56 insertions(+), 32 deletions(-) create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml delete mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml new file mode 100644 index 000000000000..107bc96a8f3d --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/rockchip,rk3368-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3368 Mailbox Controller + +maintainers: + - Heiko Stuebner + +description: + The Rockchip mailbox is used by the Rockchip CPU cores to communicate + requests to MCU processor. + +properties: + compatible: + const: rockchip,rk3368-mailbox + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: pclk_mailbox + + interrupts: + description: One interrupt for each channel + maxItems: 4 + + '#mbox-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include + + mailbox@ff6b0000 { + compatible = "rockchip,rk3368-mailbox"; + reg = <0xff6b0000 0x1000>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt deleted file mode 100644 index b6bb84acf5be..000000000000 --- a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt +++ /dev/null @@ -1,32 +0,0 @@ -Rockchip mailbox - -The Rockchip mailbox is used by the Rockchip CPU cores to communicate -requests to MCU processor. - -Refer to ./mailbox.txt for generic information about mailbox device-tree -bindings. - -Required properties: - - - compatible: should be one of the following. - - "rockchip,rk3368-mbox" for rk3368 - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. - - #mbox-cells: Common mailbox binding property to identify the number - of cells required for the mailbox specifier. Should be 1 - -Example: --------- - -/* RK3368 */ -mbox: mbox@ff6b0000 { - compatible = "rockchip,rk3368-mailbox"; - reg = <0x0 0xff6b0000 0x0 0x1000>, - interrupts = , - , - , - ; - #mbox-cells = <1>; -}; -- cgit v1.2.3 From cae18692965571a3ccf7582b6b661cebbcd0ccae Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 13:13:53 -0500 Subject: dt-bindings: mailbox: Convert marvell,armada-3700-rwtm-mailbox to DT schema Convert the Marvell Armada 3700 rWTM mailbox binding to DT schema format. It's a straightforward conversion. Link: https://lore.kernel.org/r/20250812181357.63395-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../mailbox/marvell,armada-3700-rwtm-mailbox.txt | 16 --------- .../mailbox/marvell,armada-3700-rwtm-mailbox.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.txt create mode 100644 Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.txt b/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.txt deleted file mode 100644 index 282ab81a4ea6..000000000000 --- a/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.txt +++ /dev/null @@ -1,16 +0,0 @@ -* rWTM BIU Mailbox driver for Armada 37xx - -Required properties: -- compatible: must be "marvell,armada-3700-rwtm-mailbox" -- reg: physical base address of the mailbox and length of memory mapped - region -- interrupts: the IRQ line for the mailbox -- #mbox-cells: must be 1 - -Example: - rwtm: mailbox@b0000 { - compatible = "marvell,armada-3700-rwtm-mailbox"; - reg = <0xb0000 0x100>; - interrupts = ; - #mbox-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.yaml new file mode 100644 index 000000000000..0a07ed1b1beb --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/marvell,armada-3700-rwtm-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 3700 rWTM Mailbox + +maintainers: + - Marek Behún + +properties: + compatible: + const: marvell,armada-3700-rwtm-mailbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#mbox-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include + + mailbox@b0000 { + compatible = "marvell,armada-3700-rwtm-mailbox"; + reg = <0xb0000 0x100>; + interrupts = ; + #mbox-cells = <1>; + }; -- cgit v1.2.3 From bc4f25b5b7c5a8b0f85b2840421590ad9260eda5 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 13:14:04 -0500 Subject: dt-bindings: mailbox: Convert brcm,iproc-pdc-mbox to DT schema Convert the Broadcom iProc PDC mailbox binding to DT schema format. It's a straightforward conversion. Link: https://lore.kernel.org/r/20250812181406.65390-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../bindings/mailbox/brcm,iproc-pdc-mbox.txt | 25 -------- .../bindings/mailbox/brcm,iproc-pdc-mbox.yaml | 66 ++++++++++++++++++++++ 2 files changed, 66 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt deleted file mode 100644 index 9bcdf2087625..000000000000 --- a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt +++ /dev/null @@ -1,25 +0,0 @@ -The PDC driver manages data transfer to and from various offload engines -on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is -one device tree entry per block. On some chips, the PDC functionality is -handled by the FA2 (Northstar Plus). - -Required properties: -- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for - FA2/Northstar Plus. -- reg: Should contain PDC registers location and length. -- interrupts: Should contain the IRQ line for the PDC. -- #mbox-cells: 1 -- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. - -Optional properties: -- brcm,use-bcm-hdr: present if a BCM header precedes each frame. - -Example: - pdc0: iproc-pdc0@612c0000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ - interrupts = ; - #mbox-cells = <1>; /* one cell per mailbox channel */ - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.yaml b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.yaml new file mode 100644 index 000000000000..5534ae07c9fa --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/brcm,iproc-pdc-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc PDC mailbox + +maintainers: + - Ray Jui + - Scott Branden + +description: + The PDC driver manages data transfer to and from various offload engines on + some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is one + device tree entry per block. On some chips, the PDC functionality is handled + by the FA2 (Northstar Plus). + +properties: + compatible: + enum: + - brcm,iproc-pdc-mbox + - brcm,iproc-fa2-mbox + + reg: + maxItems: 1 + + dma-coherent: true + + interrupts: + maxItems: 1 + + '#mbox-cells': + const: 1 + + brcm,rx-status-len: + description: + Length of metadata preceding received frames, in bytes. + $ref: /schemas/types.yaml#/definitions/uint32 + + brcm,use-bcm-hdr: + type: boolean + description: + Present if a BCM header precedes each frame. + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + - brcm,rx-status-len + +additionalProperties: false + +examples: + - | + #include + + mailbox0@612c0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612c0000 0x445>; + interrupts = ; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; -- cgit v1.2.3 From 930c78583d350bedcaa8fc2302e9d3c37a7f0700 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 13:14:13 -0500 Subject: dt-bindings: mailbox: Convert brcm,iproc-flexrm-mbox to DT schema Convert the Broadcom FlexRM Ring Manager binding to DT schema format. It's a straightforward conversion. Link: https://lore.kernel.org/r/20250812181415.66923-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../bindings/mailbox/brcm,iproc-flexrm-mbox.txt | 59 -------------------- .../bindings/mailbox/brcm,iproc-flexrm-mbox.yaml | 63 ++++++++++++++++++++++ 2 files changed, 63 insertions(+), 59 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt deleted file mode 100644 index bf0c998b8603..000000000000 --- a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt +++ /dev/null @@ -1,59 +0,0 @@ -Broadcom FlexRM Ring Manager -============================ -The Broadcom FlexRM ring manager provides a set of rings which can be -used to submit work to offload engines. An SoC may have multiple FlexRM -hardware blocks. There is one device tree entry per FlexRM block. The -FlexRM driver will create a mailbox-controller instance for given FlexRM -hardware block where each mailbox channel is a separate FlexRM ring. - -Required properties: --------------------- -- compatible: Should be "brcm,iproc-flexrm-mbox" -- reg: Specifies base physical address and size of the FlexRM - ring registers -- msi-parent: Phandles (and potential Device IDs) to MSI controllers - The FlexRM engine will send MSIs (instead of wired - interrupts) to CPU. There is one MSI for each FlexRM ring. - Refer devicetree/bindings/interrupt-controller/msi.txt -- #mbox-cells: Specifies the number of cells needed to encode a mailbox - channel. This should be 3. - - The 1st cell is the mailbox channel number. - - The 2nd cell contains MSI completion threshold. This is the - number of completion messages for which FlexRM will inject - one MSI interrupt to CPU. - - The 3rd cell contains MSI timer value representing time for - which FlexRM will wait to accumulate N completion messages - where N is the value specified by 2nd cell above. If FlexRM - does not get required number of completion messages in time - specified by this cell then it will inject one MSI interrupt - to CPU provided at least one completion message is available. - -Optional properties: --------------------- -- dma-coherent: Present if DMA operations made by the FlexRM engine (such - as DMA descriptor access, access to buffers pointed by DMA - descriptors and read/write pointer updates to DDR) are - cache coherent with the CPU. - -Example: --------- -crypto_mbox: mbox@67000000 { - compatible = "brcm,iproc-flexrm-mbox"; - reg = <0x67000000 0x200000>; - msi-parent = <&gic_its 0x7f00>; - #mbox-cells = <3>; -}; - -crypto@672c0000 { - compatible = "brcm,spu2-v2-crypto"; - reg = <0x672c0000 0x1000>; - mboxes = <&crypto_mbox 0 0x1 0xffff>, - <&crypto_mbox 1 0x1 0xffff>, - <&crypto_mbox 16 0x1 0xffff>, - <&crypto_mbox 17 0x1 0xffff>, - <&crypto_mbox 30 0x1 0xffff>, - <&crypto_mbox 31 0x1 0xffff>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.yaml b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.yaml new file mode 100644 index 000000000000..c801bd2e95f3 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/brcm,iproc-flexrm-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom FlexRM Ring Manager + +maintainers: + - Ray Jui + - Scott Branden + +description: + The Broadcom FlexRM ring manager provides a set of rings which can be used to + submit work to offload engines. An SoC may have multiple FlexRM hardware + blocks. There is one device tree entry per FlexRM block. The FlexRM driver + will create a mailbox-controller instance for given FlexRM hardware block + where each mailbox channel is a separate FlexRM ring. + +properties: + compatible: + const: brcm,iproc-flexrm-mbox + + reg: + maxItems: 1 + + msi-parent: + maxItems: 1 + + '#mbox-cells': + description: > + The 1st cell is the mailbox channel number. + + The 2nd cell contains MSI completion threshold. This is the number of + completion messages for which FlexRM will inject one MSI interrupt to CPU. + + The 3rd cell contains MSI timer value representing time for which FlexRM + will wait to accumulate N completion messages where N is the value + specified by 2nd cell above. If FlexRM does not get required number of + completion messages in time specified by this cell then it will inject one + MSI interrupt to CPU provided at least one completion message is + available. + const: 3 + + dma-coherent: true + +required: + - compatible + - reg + - msi-parent + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + mailbox@67000000 { + compatible = "brcm,iproc-flexrm-mbox"; + reg = <0x67000000 0x200000>; + msi-parent = <&gic_its 0x7f00>; + #mbox-cells = <3>; + dma-coherent; + }; -- cgit v1.2.3 From 638f9174e4bf8036e9167f4ff6b937cc5b842da6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 15:32:57 -0500 Subject: dt-bindings: watchdog: Convert marvell,armada-3700-wdt to DT schema Convert the Marvell Armada 3700 watchdog binding to DT schema format. It's a straight-forward conversion. Acked-by: Guenter Roeck Link: https://lore.kernel.org/r/20250812203301.726374-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../bindings/watchdog/armada-37xx-wdt.txt | 23 ------------ .../bindings/watchdog/marvell,armada-3700-wdt.yaml | 41 ++++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 42 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt create mode 100644 Documentation/devicetree/bindings/watchdog/marvell,armada-3700-wdt.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt b/Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt deleted file mode 100644 index a8d00c31a1d8..000000000000 --- a/Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Armada 37xx CPU Watchdog Timer Controller - -Required properties: -- compatible : must be "marvell,armada-3700-wdt" -- reg : base physical address of the controller and length of memory mapped - region. -- clocks : the clock feeding the watchdog timer. See clock-bindings.txt -- marvell,system-controller : reference to syscon node for the CPU Miscellaneous - Registers - -Example: - - cpu_misc: system-controller@d000 { - compatible = "marvell,armada-3700-cpu-misc", "syscon"; - reg = <0xd000 0x1000>; - }; - - wdt: watchdog@8300 { - compatible = "marvell,armada-3700-wdt"; - reg = <0x8300 0x40>; - marvell,system-controller = <&cpu_misc>; - clocks = <&xtalclk>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/marvell,armada-3700-wdt.yaml b/Documentation/devicetree/bindings/watchdog/marvell,armada-3700-wdt.yaml new file mode 100644 index 000000000000..60d44d642fb5 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/marvell,armada-3700-wdt.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/marvell,armada-3700-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Armada 37xx CPU Watchdog Timer Controller + +maintainers: + - Marek Behún + +properties: + compatible: + const: marvell,armada-3700-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + marvell,system-controller: + description: Reference to syscon node for the CPU Miscellaneous Registers + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - clocks + - marvell,system-controller + +additionalProperties: false + +examples: + - | + watchdog@8300 { + compatible = "marvell,armada-3700-wdt"; + reg = <0x8300 0x40>; + marvell,system-controller = <&cpu_misc>; + clocks = <&xtalclk>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f3dcc2f64bc7..deb11270f20d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2623,7 +2623,7 @@ F: Documentation/devicetree/bindings/firmware/cznic,turris-mox-rwtm.txt F: Documentation/devicetree/bindings/firmware/cznic,turris-omnia-mcu.yaml F: Documentation/devicetree/bindings/interrupt-controller/marvell,mpic.yaml F: Documentation/devicetree/bindings/leds/cznic,turris-omnia-leds.yaml -F: Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt +F: Documentation/devicetree/bindings/watchdog/marvell,armada-3700-wdt.yaml F: drivers/bus/moxtet.c F: drivers/firmware/turris-mox-rwtm.c F: drivers/gpio/gpio-moxtet.c -- cgit v1.2.3 From c72504a22e1c4d87b3addc73db2f6e51a4b78b88 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 22 Aug 2025 17:56:44 -0500 Subject: dt-bindings: thermal: Convert marvell,armada370-thermal to DT schema Convert the Marvell Armada 3xx/XP thermal binding to schema. Drop the AP80x and CP110 as they have long been deprecated and have been replaced by a new binding. Reviewed-by: Miquel Raynal Link: https://lore.kernel.org/r/20250822225645.766397-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/thermal/armada-thermal.txt | 42 ---------------------- .../thermal/marvell,armada370-thermal.yaml | 37 +++++++++++++++++++ 2 files changed, 37 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/thermal/armada-thermal.txt create mode 100644 Documentation/devicetree/bindings/thermal/marvell,armada370-thermal.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt deleted file mode 100644 index ab8b8fccc7af..000000000000 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Marvell Armada 370/375/380/XP thermal management - -Required properties: - -- compatible: Should be set to one of the following: - * marvell,armada370-thermal - * marvell,armada375-thermal - * marvell,armada380-thermal - * marvell,armadaxp-thermal - * marvell,armada-ap806-thermal - * marvell,armada-ap807-thermal - * marvell,armada-cp110-thermal - -Note: these bindings are deprecated for AP806/CP110 and should instead -follow the rules described in: -Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt -Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt - -- reg: Device's register space. - Two entries are expected, see the examples below. The first one points - to the status register (4B). The second one points to the control - registers (8B). - Note: The compatibles marvell,armada370-thermal, - marvell,armada380-thermal, and marvell,armadaxp-thermal must point to - "control MSB/control 1", with size of 4 (deprecated binding), or point - to "control LSB/control 0" with size of 8 (current binding). All other - compatibles must point to "control LSB/control 0" with size of 8. - -Examples: - - /* Legacy bindings */ - thermal@d0018300 { - compatible = "marvell,armada370-thermal"; - reg = <0xd0018300 0x4 - 0xd0018304 0x4>; - }; - - ap_thermal: thermal@6f8084 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x6f808C 0x4>, - <0x6f8084 0x8>; - }; diff --git a/Documentation/devicetree/bindings/thermal/marvell,armada370-thermal.yaml b/Documentation/devicetree/bindings/thermal/marvell,armada370-thermal.yaml new file mode 100644 index 000000000000..337792859448 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/marvell,armada370-thermal.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/marvell,armada370-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 3xx/XP thermal management + +maintainers: + - Miquel Raynal + +properties: + compatible: + enum: + - marvell,armada370-thermal + - marvell,armada375-thermal + - marvell,armada380-thermal + - marvell,armadaxp-thermal + + reg: + items: + - description: status register (4B) + - description: control register (8B) + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + thermal@d0018300 { + compatible = "marvell,armada370-thermal"; + reg = <0xd0018300 0x4>, + <0xd0018304 0x8>; + }; -- cgit v1.2.3 From 047170ac08d6fa250209bed7c105d0443f1e0d81 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 22 Aug 2025 17:57:00 -0500 Subject: dt-binding: thermal: Convert marvell,armada-ap806-thermal to DT schema Convert the Marvell Armada AP80x/CP110 thermal binding to schema. It is a straight forward conversion. Reviewed-by: Miquel Raynal Link: https://lore.kernel.org/r/20250822225701.766947-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../arm/marvell/ap80x-system-controller.txt | 39 ------------------ .../arm/marvell/cp110-system-controller.txt | 43 -------------------- .../thermal/marvell,armada-ap806-thermal.yaml | 46 ++++++++++++++++++++++ 3 files changed, 46 insertions(+), 82 deletions(-) create mode 100644 Documentation/devicetree/bindings/thermal/marvell,armada-ap806-thermal.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt index c83245065d44..72de11bd2ef0 100644 --- a/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt @@ -115,45 +115,6 @@ ap_syscon: system-controller@6f4000 { SYSTEM CONTROLLER 1 =================== -Thermal: --------- - -For common binding part and usage, refer to -Documentation/devicetree/bindings/thermal/thermal*.yaml - -The thermal IP can probe the temperature all around the processor. It -may feature several channels, each of them wired to one sensor. - -It is possible to setup an overheat interrupt by giving at least one -critical point to any subnode of the thermal-zone node. - -Required properties: -- compatible: must be one of: - * marvell,armada-ap806-thermal -- reg: register range associated with the thermal functions. - -Optional properties: -- interrupts: overheat interrupt handle. Should point to line 18 of the - SEI irqchip. See interrupt-controller/interrupts.txt -- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer - to this IP and represents the channel ID. There is one sensor per - channel. O refers to the thermal IP internal channel, while positive - IDs refer to each CPU. - -Example: -ap_syscon1: system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - ap_thermal: thermal-sensor@80 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x80 0x10>; - interrupt-parent = <&sei>; - interrupts = <18>; - #thermal-sensor-cells = <1>; - }; -}; - Cluster clocks: --------------- diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt index 9d5d70c98058..54ff9f218328 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -189,46 +189,3 @@ CP110_LABEL(syscon0): system-controller@440000 { }; }; - -SYSTEM CONTROLLER 1 -=================== - -Thermal: --------- - -The thermal IP can probe the temperature all around the processor. It -may feature several channels, each of them wired to one sensor. - -It is possible to setup an overheat interrupt by giving at least one -critical point to any subnode of the thermal-zone node. - -For common binding part and usage, refer to -Documentation/devicetree/bindings/thermal/thermal*.yaml - -Required properties: -- compatible: must be one of: - * marvell,armada-cp110-thermal -- reg: register range associated with the thermal functions. - -Optional properties: -- interrupts-extended: overheat interrupt handle. Should point to - a line of the ICU-SEI irqchip (116 is what is usually used by the - firmware). The ICU-SEI will redirect towards interrupt line #37 of the - AP SEI which is shared across all CPs. - See interrupt-controller/interrupts.txt -- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer - to this IP and represents the channel ID. There is one sensor per - channel. O refers to the thermal IP internal channel. - -Example: -CP110_LABEL(syscon1): system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - CP110_LABEL(thermal): thermal-sensor@70 { - compatible = "marvell,armada-cp110-thermal"; - reg = <0x70 0x10>; - interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/marvell,armada-ap806-thermal.yaml b/Documentation/devicetree/bindings/thermal/marvell,armada-ap806-thermal.yaml new file mode 100644 index 000000000000..2c370317a40e --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/marvell,armada-ap806-thermal.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/marvell,armada-ap806-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada AP80x/CP110 thermal management + +maintainers: + - Miquel Raynal + +properties: + compatible: + enum: + - marvell,armada-ap806-thermal + - marvell,armada-ap807-thermal + - marvell,armada-cp110-thermal + + reg: + maxItems: 1 + + interrupts: + description: + Overheat interrupt. The interrupt is connected thru a System Error + Interrupt (SEI) controller. + maxItems: 1 + + '#thermal-sensor-cells': + description: Cell represents the channel ID. There is one sensor per + channel. O refers to the thermal IP internal channel. + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + thermal-sensor@80 { + compatible = "marvell,armada-ap806-thermal"; + reg = <0x80 0x10>; + interrupts = <18>; + #thermal-sensor-cells = <1>; + }; -- cgit v1.2.3 From d27ce63a31c3c9b221287844c41088e499042199 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 28 Aug 2025 17:30:21 -0500 Subject: dt-bindings: edac: Convert apm,xgene-edac to DT schema Convert the APM XGene EDAC binding to DT schema. Add the missing "apm,xgene-edac-soc" compatible, and drop the unused "apm,xgene-edac-pmd-v2" compatible. Link: https://lore.kernel.org/r/20250828223023.2409337-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/edac/apm,xgene-edac.yaml | 203 +++++++++++++++++++++ .../devicetree/bindings/edac/apm-xgene-edac.txt | 112 ------------ MAINTAINERS | 2 +- 3 files changed, 204 insertions(+), 113 deletions(-) create mode 100644 Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml delete mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml b/Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml new file mode 100644 index 000000000000..9afc78254cc0 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/apm,xgene-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC EDAC + +maintainers: + - Khuong Dinh + +description: > + EDAC node is defined to describe on-chip error detection and correction. + + The following error types are supported: + + memory controller - Memory controller + PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache + L3 - L3 cache controller + SoC - SoC IPs such as Ethernet, SATA, etc + +properties: + compatible: + const: apm,xgene-edac + + reg: + items: + - description: CPU bus (PCP) resource + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + ranges: true + + interrupts: + description: Interrupt-specifier for MCU, PMD, L3, or SoC error IRQ(s). + items: + - description: MCU error IRQ + - description: PMD error IRQ + - description: L3 error IRQ + - description: SoC error IRQ + minItems: 1 + + regmap-csw: + description: Regmap of the CPU switch fabric (CSW) resource. + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-mcba: + description: Regmap of the MCB-A (memory bridge) resource. + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-mcbb: + description: Regmap of the MCB-B (memory bridge) resource. + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-efuse: + description: Regmap of the PMD efuse resource. + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-rb: + description: Regmap of the register bus resource (optional for compatibility). + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - regmap-csw + - regmap-mcba + - regmap-mcbb + - regmap-efuse + - reg + - interrupts + +# Child-node bindings +patternProperties: + '^edacmc@': + description: Memory controller subnode + type: object + additionalProperties: false + + properties: + compatible: + const: apm,xgene-edac-mc + + reg: + maxItems: 1 + + memory-controller: + description: Instance number of the memory controller. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + required: + - compatible + - reg + - memory-controller + + + '^edacpmd@': + description: PMD subnode + type: object + additionalProperties: false + + properties: + compatible: + const: apm,xgene-edac-pmd + + reg: + maxItems: 1 + + pmd-controller: + description: Instance number of the PMD controller. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + required: + - compatible + - reg + - pmd-controller + + '^edacl3@': + description: L3 subnode + type: object + additionalProperties: false + + properties: + compatible: + enum: + - apm,xgene-edac-l3 + - apm,xgene-edac-l3-v2 + + reg: + maxItems: 1 + + required: + - compatible + - reg + + '^edacsoc@': + description: SoC subnode + type: object + additionalProperties: false + + properties: + compatible: + enum: + - apm,xgene-edac-soc + - apm,xgene-edac-soc-v1 + + reg: + maxItems: 1 + + required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + edac@78800000 { + compatible = "apm,xgene-edac"; + reg = <0x0 0x78800000 0x0 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupts = <0x0 0x20 0x4>, <0x0 0x21 0x4>, <0x0 0x27 0x4>; + + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + regmap-efuse = <&efuse>; + regmap-rb = <&rb>; + + edacmc@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e800000 0x0 0x1000>; + memory-controller = <0>; + }; + + edacpmd@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c000000 0x0 0x200000>; + pmd-controller = <0>; + }; + + edacl3@7e600000 { + compatible = "apm,xgene-edac-l3"; + reg = <0x0 0x7e600000 0x0 0x1000>; + }; + + edacsoc@7e930000 { + compatible = "apm,xgene-edac-soc-v1"; + reg = <0x0 0x7e930000 0x0 0x1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt deleted file mode 100644 index 1006b0489464..000000000000 --- a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt +++ /dev/null @@ -1,112 +0,0 @@ -* APM X-Gene SoC EDAC node - -EDAC node is defined to describe on-chip error detection and correction. -The follow error types are supported: - - memory controller - Memory controller - PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache - L3 - L3 cache controller - SoC - SoC IP's such as Ethernet, SATA, and etc - -The following section describes the EDAC DT node binding. - -Required properties: -- compatible : Shall be "apm,xgene-edac". -- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. -- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. -- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. -- regmap-efuse : Regmap of the PMD efuse resource. -- regmap-rb : Regmap of the register bus resource. This property - is optional only for compatibility. If the RB - error conditions are not cleared, it will - continuously generate interrupt. -- reg : First resource shall be the CPU bus (PCP) resource. -- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error - IRQ(s). - -Required properties for memory controller subnode: -- compatible : Shall be "apm,xgene-edac-mc". -- reg : First resource shall be the memory controller unit - (MCU) resource. -- memory-controller : Instance number of the memory controller. - -Required properties for PMD subnode: -- compatible : Shall be "apm,xgene-edac-pmd" or - "apm,xgene-edac-pmd-v2". -- reg : First resource shall be the PMD resource. -- pmd-controller : Instance number of the PMD controller. - -Required properties for L3 subnode: -- compatible : Shall be "apm,xgene-edac-l3" or - "apm,xgene-edac-l3-v2". -- reg : First resource shall be the L3 EDAC resource. - -Required properties for SoC subnode: -- compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or - "apm,xgene-edac-l3-soc" for general value reporting - only. -- reg : First resource shall be the SoC EDAC resource. - -Example: - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - efuse: efuse@1054a000 { - compatible = "apm,xgene-efuse", "syscon"; - reg = <0x0 0x1054a000 0x0 0x20>; - }; - - rb: rb@7e000000 { - compatible = "apm,xgene-rb", "syscon"; - reg = <0x0 0x7e000000 0x0 0x10>; - }; - - edac@78800000 { - compatible = "apm,xgene-edac"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - regmap-efuse = <&efuse>; - regmap-rb = <&rb>; - reg = <0x0 0x78800000 0x0 0x100>; - interrupts = <0x0 0x20 0x4>, - <0x0 0x21 0x4>, - <0x0 0x27 0x4>; - - edacmc@7e800000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e800000 0x0 0x1000>; - memory-controller = <0>; - }; - - edacpmd@7c000000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c000000 0x0 0x200000>; - pmd-controller = <0>; - }; - - edacl3@7e600000 { - compatible = "apm,xgene-edac-l3"; - reg = <0x0 0x7e600000 0x0 0x1000>; - }; - - edacsoc@7e930000 { - compatible = "apm,xgene-edac-soc-v1"; - reg = <0x0 0x7e930000 0x0 0x1000>; - }; - }; diff --git a/MAINTAINERS b/MAINTAINERS index deb11270f20d..2e1a079e24bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1872,7 +1872,7 @@ F: arch/arm64/boot/dts/apm/ APPLIED MICRO (APM) X-GENE SOC EDAC M: Khuong Dinh S: Supported -F: Documentation/devicetree/bindings/edac/apm-xgene-edac.txt +F: Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml F: drivers/edac/xgene_edac.c APPLIED MICRO (APM) X-GENE SOC ETHERNET (V2) DRIVER -- cgit v1.2.3 From 9b4bacf5d998a9222cab8f9cd3b851ccba0d9351 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Thu, 11 Sep 2025 12:09:54 -0300 Subject: dt-bindings: display: mediatek,od: Add mediatek,gce-client-reg property Currently, users of Mediatek OD (display overdrive) DT bindings set mediatek,gce-client-reg node property, which is missing from the DT schema. For example, device tree arch/arm64/boot/dts/mediatek/mt8173.dtsi is causing the following dtb check error: arch/arm64/boot/dts/mediatek/mt8173-elm.dtb: od@14023000 (mediatek,mt8173-disp-od): 'mediatek,gce-client-reg' does not match any of the regexes: '^pinctrl-[0-9]+$' This commit adds the missing node property in the DT schema and updates the example as well. Signed-off-by: Ariel D'Alessandro Link: https://lore.kernel.org/r/20250911151001.108744-6-ariel.dalessandro@collabora.com Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/mediatek/mediatek,od.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml index 71534febd49c..930c088a722a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml @@ -60,6 +60,18 @@ properties: - port@0 - port@1 + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: describes how to locate the GCE client register + items: + - items: + - description: Phandle reference to a Mediatek GCE Mailbox + - description: + GCE subsys id mapping to a client defined in header + include/dt-bindings/gce/-gce.h. + - description: offset for the GCE register offset + - description: size of the GCE register offset + required: - compatible - reg @@ -70,6 +82,7 @@ additionalProperties: false examples: - | #include + #include soc { #address-cells = <2>; @@ -79,5 +92,6 @@ examples: compatible = "mediatek,mt8173-disp-od"; reg = <0 0x14023000 0 0x1000>; clocks = <&mmsys CLK_MM_DISP_OD>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; }; }; -- cgit v1.2.3 From 2ad572d3a5b340770672aee9aa3c4941d3df737d Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Thu, 11 Sep 2025 12:09:55 -0300 Subject: dt-bindings: display: mediatek,ufoe: Add mediatek,gce-client-reg property Currently, users of Mediatek UFOe (Unified Frame Optimization engine) DT bindings set mediatek,gce-client-reg node property, which is missing from the DT schema. For example, device tree arch/arm64/boot/dts/mediatek/mt8173.dtsi is causing the following dtb check error: arch/arm64/boot/dts/mediatek/mt8173-elm.dtb: ufoe@1401a000 (mediatek,mt8173-disp-ufoe): 'mediatek,gce-client-reg' does not match any of the regexes: '^pinctrl-[0-9]+$' This commit adds the missing node property in the DT schema and updates the example as well. Signed-off-by: Ariel D'Alessandro Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250911151001.108744-7-ariel.dalessandro@collabora.com Signed-off-by: Rob Herring (Arm) --- .../bindings/display/mediatek/mediatek,ufoe.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml index 61a5e22effbf..036a66ed42e7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml @@ -64,6 +64,18 @@ properties: - port@0 - port@1 + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: describes how to locate the GCE client register + items: + - items: + - description: Phandle reference to a Mediatek GCE Mailbox + - description: + GCE subsys id mapping to a client defined in header + include/dt-bindings/gce/-gce.h. + - description: offset for the GCE register offset + - description: size of the GCE register offset + required: - compatible - reg @@ -77,7 +89,9 @@ examples: - | #include #include + #include #include + soc { #address-cells = <2>; #size-cells = <2>; @@ -88,5 +102,6 @@ examples: interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_UFOE>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; }; }; -- cgit v1.2.3 From 11f8652b7112ee2deba436045ef9b847cbb415a6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 21 Aug 2025 13:06:40 -0500 Subject: dt-bindings: arm: Add Arm C1 cores and PMUs Add the newly introduced Arm C1-Nano/Pro/Premium/Ultra core and PMU compatible strings. These cores are part of the Lumex CSS. The new names are replacing the long lived Cortex-A/X branding going forward. Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/cpus.yaml | 4 ++++ Documentation/devicetree/bindings/arm/pmu.yaml | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 41ad4ed0e74c..c1036dcfc912 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -123,6 +123,10 @@ properties: - arm,arm1176jzf-s - arm,arm11mpcore - arm,armv8 # Only for s/w models + - arm,c1-nano + - arm,c1-premium + - arm,c1-pro + - arm,c1-ultra - arm,cortex-a5 - arm,cortex-a7 - arm,cortex-a8 diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 9bb109e947dd..f47baaefcdac 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -28,6 +28,10 @@ properties: - arm,arm1136-pmu - arm,arm1176-pmu - arm,arm11mpcore-pmu + - arm,c1-nano-pmu + - arm,c1-premium-pmu + - arm,c1-pro-pmu + - arm,c1-ultra-pmu - arm,cortex-a5-pmu - arm,cortex-a7-pmu - arm,cortex-a8-pmu -- cgit v1.2.3 From 537e189f2708864e21c9be7109e1f454b956370c Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 9 Sep 2025 09:21:59 -0500 Subject: dt-bindings: watchdog: Convert nuvoton,npcm-wdt to DT schema Convert the Nuvoton watchdog binding to DT schema format. It's a straight-forward conversion. Acked-by: Guenter Roeck Link: https://lore.kernel.org/r/20250909142201.3209482-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) --- .../bindings/watchdog/nuvoton,npcm-wdt.txt | 30 ----------- .../bindings/watchdog/nuvoton,npcm750-wdt.yaml | 60 ++++++++++++++++++++++ 2 files changed, 60 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt create mode 100644 Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt deleted file mode 100644 index 866a958b8a2b..000000000000 --- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt +++ /dev/null @@ -1,30 +0,0 @@ -Nuvoton NPCM Watchdog - -Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog. -The watchdog supports a pre-timeout interrupt that fires 10ms before the -expiry. - -Required properties: -- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or - "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or - "nuvoton,npcm845-wdt" for NPCM845 (Arbel). -- reg : Offset and length of the register set for the device. -- interrupts : Contain the timer interrupt with flags for - falling edge. - -Required clocking property, have to be one of: -- clocks : phandle of timer reference clock. -- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx - timer (usually 25000000). - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - -timer@f000801c { - compatible = "nuvoton,npcm750-wdt"; - interrupts = ; - reg = <0xf000801c 0x4>; - clocks = <&clk NPCM7XX_CLK_TIMER>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml new file mode 100644 index 000000000000..7aa30f5b5c49 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/nuvoton,npcm750-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Watchdog + +maintainers: + - Joel Stanley + +description: + Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog. + The watchdog supports a pre-timeout interrupt that fires 10ms before the + expiry. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - enum: + - nuvoton,npcm750-wdt + - nuvoton,wpcm450-wdt + - items: + - enum: + - nuvoton,npcm845-wdt + - const: nuvoton,npcm750-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: Frequency in Hz of the clock that drives the NPCM timer. + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + watchdog@f000801c { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0xf000801c 0x4>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; -- cgit v1.2.3 From 4e4a4f58bed19e1a3a5a7c3a18ce3b927b76fcd3 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:35:32 +0800 Subject: dt-bindings: pci: Add Sophgo SG2042 PCIe host Add binding for Sophgo SG2042 PCIe host controller. Signed-off-by: Chen Wang Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/2755f145755b6096247c26852b63671a6fea4dbf.1757643388.git.unicorn_wang@outlook.com --- .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml new file mode 100644 index 000000000000..f8b7ca57fff1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) + +description: + Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. + +maintainers: + - Chen Wang + +properties: + compatible: + const: sophgo,sg2042-pcie-host + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: cfg + + vendor-id: + const: 0x1f1c + + device-id: + const: 0x2042 + + msi-parent: true + +allOf: + - $ref: cdns-pcie-host.yaml# + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + + pcie@62000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x62000000 0x00800000>, + <0x48000000 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + bus-range = <0x00 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + }; -- cgit v1.2.3 From b90d027afbdde5a0b640586f4cf91cc5cc97a5bc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 9 Sep 2025 08:49:02 +0300 Subject: dt-bindings: input: maxtouch: add common touchscreen properties Since atmel,maxtouch describes touchscreens too, it should include common touchscreen properties. Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250909054903.11519-2-clamor95@gmail.com Signed-off-by: Dmitry Torokhov --- Documentation/devicetree/bindings/input/atmel,maxtouch.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml b/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml index c40799355ed7..d79b254f1cde 100644 --- a/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml +++ b/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml @@ -16,6 +16,7 @@ description: | allOf: - $ref: input.yaml# + - $ref: touchscreen/touchscreen.yaml# properties: compatible: @@ -95,7 +96,7 @@ required: - reg - interrupts -additionalProperties: false +unevaluatedProperties: false examples: - | -- cgit v1.2.3 From ae28e0b895bb4fa78390ac9ad799a3fcd0ec11d2 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 5 Aug 2025 18:25:00 -0500 Subject: dt-bindings: arm: marvell: Convert marvell,armada-370-xp boards to DT schema Convert Marvell Armada 370/XP based boards to DT schema format. Acked-by: Gregory CLEMENT Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ------- .../bindings/arm/marvell/armada-370-xp.txt | 24 ------- .../arm/marvell/marvell,armada-370-xp.yaml | 78 ++++++++++++++++++++++ 3 files changed, 78 insertions(+), 47 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt delete mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,armada-370-xp.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt deleted file mode 100644 index 64e8c73fc5ab..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt +++ /dev/null @@ -1,23 +0,0 @@ -Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings ----------------------------------------------------------------------- - -Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx3236" - -In addition, boards using the Marvell 98DX3336 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx3336" - -In addition, boards using the Marvell 98DX4251 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx4251" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt deleted file mode 100644 index c6ed90ea6e17..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt +++ /dev/null @@ -1,24 +0,0 @@ -Marvell Armada 370 and Armada XP Platforms Device Tree Bindings ---------------------------------------------------------------- - -Boards with a SoC of the Marvell Armada 370 and Armada XP families -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,armada-370-xp" - -In addition, boards using the Marvell Armada 370 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armada370" - -In addition, boards using the Marvell Armada XP SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp" - diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,armada-370-xp.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,armada-370-xp.yaml new file mode 100644 index 000000000000..e65eadfbd097 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,armada-370-xp.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,armada-370-xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 370 and Armada XP platforms + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - ctera,c200-v2 + - dlink,dns327l + - globalscale,mirabox + - netgear,readynas-102 + - netgear,readynas-104 + - marvell,a370-db + - marvell,a370-rd + - seagate,dart-2 + - seagate,dart-4 + - seagate,cumulus-max + - seagate,cumulus + - synology,ds213j + - const: marvell,armada370 + - const: marvell,armada-370-xp + + - items: + - enum: + - mikrotik,crs305-1g-4s + - mikrotik,crs326-24g-2s + - mikrotik,crs328-4c-20s-4s + - const: marvell,armadaxp-98dx3236 + - const: marvell,armada-370-xp + + - items: + - const: marvell,db-xc3-24g4xg + - const: marvell,armadaxp-98dx3336 + - const: marvell,armada-370-xp + + - items: + - const: marvell,db-dxbc2 + - const: marvell,armadaxp-98dx4251 + - const: marvell,armada-370-xp + + - items: + - enum: + - lenovo,ix4-300d + - linksys,mamba + - marvell,rd-axpwifiap + - netgear,readynas-2120 + - synology,ds414 + - const: marvell,armadaxp-mv78230 + - const: marvell,armadaxp + - const: marvell,armada-370-xp + + - items: + - const: plathome,openblocks-ax3-4 + - const: marvell,armadaxp-mv78260 + - const: marvell,armadaxp + - const: marvell,armada-370-xp + + - items: + - enum: + - marvell,axp-db + - marvell,axp-gp + - marvell,axp-matrix + - const: marvell,armadaxp-mv78460 + - const: marvell,armadaxp + - const: marvell,armada-370-xp + +additionalProperties: true -- cgit v1.2.3 From abd4ac56f4af01a60922ccdfcbaa6b7dac994a32 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 5 Aug 2025 18:25:12 -0500 Subject: dt-bindings: arm: marvell: Convert marvell,armada375 boards to DT schema Convert Marvell Armada-375 based boards to DT schema format. Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/marvell/armada-375.txt | 9 --------- .../bindings/arm/marvell/marvell,armada375.yaml | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 9 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-375.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,armada375.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-375.txt b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt deleted file mode 100644 index 867d0b80cb8f..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-375.txt +++ /dev/null @@ -1,9 +0,0 @@ -Marvell Armada 375 Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 375 family shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armada375" diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,armada375.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,armada375.yaml new file mode 100644 index 000000000000..81c33e46fecc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,armada375.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,armada375.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 375 Platform + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + $nodename: + const: '/' + compatible: + items: + - const: marvell,a375-db + - const: marvell,armada375 + +additionalProperties: true -- cgit v1.2.3 From 3ef9017c373bba536d5e23d535d404525bdcfeb9 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 5 Aug 2025 18:25:17 -0500 Subject: dt-bindings: arm: marvell: Convert marvell,armada390 boards to DT schema Convert Marvell Armada-390 based boards to DT schema format. Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/marvell/armada-39x.txt | 31 --------------------- .../bindings/arm/marvell/marvell,armada390.yaml | 32 ++++++++++++++++++++++ 2 files changed, 32 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-39x.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,armada390.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt deleted file mode 100644 index 89468664f6ea..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt +++ /dev/null @@ -1,31 +0,0 @@ -Marvell Armada 39x Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 39x family shall have the -following property: - -Required root node property: - - - compatible: must contain "marvell,armada390" - -In addition, boards using the Marvell Armada 395 SoC shall have the -following property before the common "marvell,armada390" one: - -Required root node property: - -compatible: must contain "marvell,armada395" - -Example: - -compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390"; - -Boards using the Marvell Armada 398 SoC shall have the following -property before the common "marvell,armada390" one: - -Required root node property: - -compatible: must contain "marvell,armada398" - -Example: - -compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,armada390.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,armada390.yaml new file mode 100644 index 000000000000..5ff6a5439525 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,armada390.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,armada390.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 39x Platforms + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: marvell,a390-db + - const: marvell,armada390 + - items: + - enum: + - marvell,a398-db + - const: marvell,armada398 + - const: marvell,armada390 + - items: + - enum: + - marvell,a395-gp + - const: marvell,armada395 + - const: marvell,armada390 + +additionalProperties: true -- cgit v1.2.3 From 1c5f2ea8ce7f53f1c72980ac312ae1c0c29aa8a5 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 5 Aug 2025 18:25:25 -0500 Subject: dt-bindings: arm: marvell: Convert marvell,kirkwood boards to DT schema Convert Marvell Kirkwood based boards to DT schema format. Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/marvell/kirkwood.txt | 27 --- .../bindings/arm/marvell/marvell,kirkwood.txt | 105 -------- .../bindings/arm/marvell/marvell,kirkwood.yaml | 266 +++++++++++++++++++++ 3 files changed, 266 insertions(+), 132 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/marvell/kirkwood.txt delete mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt deleted file mode 100644 index 98cce9a653eb..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell Kirkwood Platforms Device Tree Bindings ------------------------------------------------ - -Boards with a SoC of the Marvell Kirkwood -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,kirkwood"; - -In order to support the kirkwood cpufreq driver, there must be a node -cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave", -where the "powersave" clock is a gating clock used to switch the CPU -between the "cpu_clk" and the "ddrclk". - -Example: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-88SV131"; - clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; - clock-names = "cpu_clk", "ddrclk", "powersave"; - }; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt deleted file mode 100644 index 7d28fe4bf654..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt +++ /dev/null @@ -1,105 +0,0 @@ -Marvell Kirkwood SoC Family Device Tree Bindings ------------------------------------------------- - -Boards with a SoC of the Marvell Kirkwook family, eg 88f6281 - -* Required root node properties: -compatible: must contain "marvell,kirkwood" - -In addition, the above compatible shall be extended with the specific -SoC. Currently known SoC compatibles are: - -"marvell,kirkwood-88f6192" -"marvell,kirkwood-88f6281" -"marvell,kirkwood-88f6282" -"marvell,kirkwood-88f6283" -"marvell,kirkwood-88f6702" -"marvell,kirkwood-98DX4122" - -And in addition, the compatible shall be extended with the specific -board. Currently known boards are: - -"buffalo,linkstation-lsqvl" -"buffalo,linkstation-lsvl" -"buffalo,linkstation-lswsxl" -"buffalo,linkstation-lswxl" -"buffalo,linkstation-lswvl" -"buffalo,lschlv2" -"buffalo,lsxhl" -"buffalo,lsxl" -"cloudengines,pogo02" -"cloudengines,pogoplugv4" -"dlink,dns-320" -"dlink,dns-320-a1" -"dlink,dns-325" -"dlink,dns-325-a1" -"dlink,dns-kirkwood" -"excito,b3" -"globalscale,dreamplug-003-ds2001" -"globalscale,guruplug" -"globalscale,guruplug-server-plus" -"globalscale,sheevaplug" -"globalscale,sheevaplug" -"globalscale,sheevaplug-esata" -"globalscale,sheevaplug-esata-rev13" -"iom,iconnect" -"iom,iconnect-1.1" -"iom,ix2-200" -"keymile,km_kirkwood" -"lacie,cloudbox" -"lacie,inetspace_v2" -"lacie,laplug" -"lacie,nas2big" -"lacie,netspace_lite_v2" -"lacie,netspace_max_v2" -"lacie,netspace_mini_v2" -"lacie,netspace_v2" -"marvell,db-88f6281-bp" -"marvell,db-88f6282-bp" -"marvell,mv88f6281gtw-ge" -"marvell,rd88f6281" -"marvell,rd88f6281" -"marvell,rd88f6281-a0" -"marvell,rd88f6281-a1" -"mpl,cec4" -"mpl,cec4-10" -"netgear,readynas" -"netgear,readynas" -"netgear,readynas-duo-v2" -"netgear,readynas-nv+-v2" -"plathome,openblocks-a6" -"plathome,openblocks-a7" -"raidsonic,ib-nas6210" -"raidsonic,ib-nas6210-b" -"raidsonic,ib-nas6220" -"raidsonic,ib-nas6220-b" -"raidsonic,ib-nas62x0" -"seagate,dockstar" -"seagate,goflexnet" -"synology,ds109" -"synology,ds110jv10" -"synology,ds110jv20" -"synology,ds110jv30" -"synology,ds111" -"synology,ds209" -"synology,ds210jv10" -"synology,ds210jv20" -"synology,ds212" -"synology,ds212jv10" -"synology,ds212jv20" -"synology,ds212pv10" -"synology,ds409" -"synology,ds409slim" -"synology,ds410j" -"synology,ds411" -"synology,ds411j" -"synology,ds411slim" -"synology,ds413jv10" -"synology,rs212" -"synology,rs409" -"synology,rs411" -"synology,rs812" -"usi,topkick" -"usi,topkick-1281P2" -"zyxel,nsa310" -"zyxel,nsa310a" diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.yaml new file mode 100644 index 000000000000..120784066833 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.yaml @@ -0,0 +1,266 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,kirkwood.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Kirkwood SoC Family + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - qnap,ts219 + - qnap,ts419 + - synology,ds110 + - synology,ds111 + - synology,ds209 + - synology,ds409slim + - synology,ds411j + - synology,ds411slim + - synology,rs212 + - synology,rs409 + - const: marvell,kirkwood + + - items: + - const: synology,ds109 + - const: synology,ds110jv20 + - const: synology,ds110 + - const: marvell,kirkwood + + - items: + - const: synology,ds110jv10 + - const: synology,ds110jv30 + - const: marvell,kirkwood + + - items: + - const: synology,ds210jv10 + - const: synology,ds210jv20 + - const: synology,ds210jv30 + - const: synology,ds211j + - const: marvell,kirkwood + + - items: + - const: synology,ds212jv10 + - const: synology,ds212jv20 + - const: marvell,kirkwood + + - items: + - const: synology,ds212 + - const: synology,ds212pv10 + - const: synology,ds212pv10 + - const: synology,ds212pv20 + - const: synology,ds213airv10 + - const: synology,ds213v10 + - const: marvell,kirkwood + + - items: + - const: synology,ds409 + - const: synology,ds410j + - const: marvell,kirkwood + + - items: + - const: synology,ds411 + - const: synology,ds413jv10 + - const: marvell,kirkwood + + - items: + - const: synology,rs411 + - const: synology,rs812 + - const: marvell,kirkwood + + - items: + - enum: + - cloudengines,pogoplugv4 + - lacie,laplug + - lacie,netspace_lite_v2 + - lacie,netspace_mini_v2 + - marvell,rd88f6192 + - seagate,blackarmor-nas220 + - enum: + - marvell,kirkwood-88f6192 + - const: marvell,kirkwood + + - items: + - enum: + - buffalo,lswsxl + - buffalo,lswxl + - checkpoint,l-50 + - cloudengines,pogoe02 + - ctera,c200-v1 + - dlink,dir-665 + - endian,4i-edge-200 + - excito,b3 + - globalscale,sheevaplug + - hp,t5325 + - iom,ix2-200 + - lacie,inetspace_v2 + - lacie,netspace_v2 + - lacie,netspace_max_v2 + - marvell,db-88f6281-bp + - marvell,mv88f6281gtw-ge + - seagate,dockstar + - seagate,goflexnet + - zyxel,nsa310 + - zyxel,nsa320 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - enum: + - buffalo,lschlv2 + - buffalo,lsxhl + - const: buffalo,lsxl + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: dlink,dns-320-a1 + - const: dlink,dns-320 + - const: dlink,dns-kirkwood + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: dlink,dns-325-a1 + - const: dlink,dns-325 + - const: dlink,dns-kirkwood + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: globalscale,dreamplug-003-ds2001 + - const: globalscale,dreamplug + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: globalscale,guruplug-server-plus + - const: globalscale,guruplug + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: globalscale,sheevaplug-esata-rev13 + - const: globalscale,sheevaplug-esata + - const: globalscale,sheevaplug + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: iom,iconnect-1.1 + - const: iom,iconnect + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: lacie,d2net_v2 + - const: lacie,netxbig + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + - items: + - enum: + - lacie,net2big_v2 + - lacie,net5big_v2 + - const: lacie,netxbig + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - enum: + - marvell,openrd-base + - marvell,openrd-client + - marvell,openrd-ultimate + - const: marvell,openrd + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - enum: + - marvell,rd88f6281-a + - marvell,rd88f6281-z0 + - const: marvell,rd88f6281 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: mpl,cec4-10 + - const: mpl,cec4 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: raidsonic,ib-nas6210-b + - const: raidsonic,ib-nas6220-b + - const: raidsonic,ib-nas6210 + - const: raidsonic,ib-nas6220 + - const: raidsonic,ib-nas62x0 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: zyxel,nsa310a + - const: zyxel,nsa310 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - enum: + - buffalo,lsqvl + - buffalo,lsvl + - buffalo,lswvl + - linksys,viper + - marvell,db-88f6282-bp + - zyxel,nsa325 + - const: marvell,kirkwood-88f6282 + - const: marvell,kirkwood + + - items: + - const: lacie,nas2big + - const: lacie,netxbig + - const: marvell,kirkwood-88f6282 + - const: marvell,kirkwood + + - items: + - enum: + - netgear,readynas-duo-v2 + - netgear,readynas-nv+-v2 + - const: netgear,readynas + - const: marvell,kirkwood-88f6282 + - const: marvell,kirkwood + + - items: + - const: usi,topkick-1281P2 + - const: usi,topkick + - const: marvell,kirkwood-88f6282 + - const: marvell,kirkwood + + - items: + - enum: + - plathome,openblocks-a6 + - plathome,openblocks-a7 + - const: marvell,kirkwood-88f6283 + - const: marvell,kirkwood + + - items: + - enum: + - lacie,cloudbox + - zyxel,nsa310s + - const: marvell,kirkwood-88f6702 + - const: marvell,kirkwood + + - items: + - enum: + - keymile,km_fixedeth + - keymile,km_kirkwood + - const: marvell,kirkwood-98DX4122 + - const: marvell,kirkwood + +additionalProperties: true -- cgit v1.2.3 From 573a8be749aed8d0744b78d6795cb2d7c20c14be Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 5 Aug 2025 18:25:31 -0500 Subject: dt-bindings: arm: marvell: Convert marvell,dove boards to DT schema Convert Marvell Dove based boards to DT schema format. Signed-off-by: Rob Herring (Arm) --- .../bindings/arm/marvell/marvell,dove.txt | 7 ----- .../bindings/arm/marvell/marvell,dove.yaml | 35 ++++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 36 insertions(+), 8 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt deleted file mode 100644 index e10e8525eabd..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt +++ /dev/null @@ -1,7 +0,0 @@ -Marvell Dove Platforms Device Tree Bindings ------------------------------------------------ - -Boards with a Marvell Dove SoC shall have the following properties: - -Required root node property: -- compatible: must contain "marvell,dove"; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml new file mode 100644 index 000000000000..a37804fb30c4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,dove.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Dove SoC + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - compulab,cm-a510 + - solidrun,cubox + - globalscale,d2plug + - globalscale,d3plug + - marvell,dove-db + - const: marvell,dove + - items: + - const: solidrun,cubox-es + - const: solidrun,cubox + - const: marvell,dove + - items: + - const: compulab,sbc-a510 + - const: compulab,cm-a510 + - const: marvell,dove + +additionalProperties: true diff --git a/MAINTAINERS b/MAINTAINERS index 2e1a079e24bc..d92d8f68e8cc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2831,7 +2831,7 @@ M: Gregory Clement L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git -F: Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt +F: Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt F: Documentation/devicetree/bindings/soc/dove/ F: arch/arm/boot/dts/marvell/dove* -- cgit v1.2.3 From 3e2518d8b646afe159170422c1c8e072ba7c0798 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 5 Aug 2025 18:25:51 -0500 Subject: dt-bindings: arm: marvell: Convert marvell,orion5x boards to DT schema Convert Marvell Orion5x based boards to DT schema format. Signed-off-by: Rob Herring (Arm) --- .../bindings/arm/marvell/marvell,orion5x.txt | 25 --------------- .../bindings/arm/marvell/marvell,orion5x.yaml | 37 ++++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 38 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt deleted file mode 100644 index 748a8f287462..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +++ /dev/null @@ -1,25 +0,0 @@ -Marvell Orion SoC Family Device Tree Bindings ---------------------------------------------- - -Boards with a SoC of the Marvell Orion family, eg 88f5181 - -* Required root node properties: -compatible: must contain "marvell,orion5x" - -In addition, the above compatible shall be extended with the specific -SoC. Currently known SoC compatibles are: - -"marvell,orion5x-88f5181" -"marvell,orion5x-88f5182" - -And in addition, the compatible shall be extended with the specific -board. Currently known boards are: - -"buffalo,lsgl" -"buffalo,lswsgl" -"buffalo,lswtgl" -"lacie,ethernet-disk-mini-v2" -"lacie,d2-network" -"marvell,rd-88f5182-nas" -"maxtor,shared-storage-2" -"netgear,wnr854t" diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml new file mode 100644 index 000000000000..c0417591b2be --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,orion5x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion5x SoC Family + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - netgear,wnr854t + - const: marvell,orion5x-88f5181 + - const: marvell,orion5x + - items: + - enum: + - buffalo,kurobox-pro + - buffalo,lschl + - buffalo,lsgl + - buffalo,lswsgl + - buffalo,lswtgl + - lacie,ethernet-disk-mini-v2 + - lacie,d2-network + - marvell,rd-88f5182-nas + - maxtor,shared-storage-2 + - const: marvell,orion5x-88f5182 + - const: marvell,orion5x + +additionalProperties: true diff --git a/MAINTAINERS b/MAINTAINERS index d92d8f68e8cc..4ee1f658c3c2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2832,7 +2832,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml -F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml F: Documentation/devicetree/bindings/soc/dove/ F: arch/arm/boot/dts/marvell/dove* F: arch/arm/boot/dts/marvell/orion5x* -- cgit v1.2.3 From ac28c7598611df3034c0f61d25da7b3377bbce87 Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Tue, 26 Aug 2025 09:39:34 +0200 Subject: dt-bindings: clock: mediatek: Add power-domains property The mt8183-mfgcfg node uses a power domain in its device tree node. To prevent schema validation warnings, add the optional `power-domains` property to the binding schema for mediatek syscon clocks. Fixes: 1781f2c46180 ("arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Julien Massot Acked-by: Rob Herring (Arm) Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/mediatek,syscon.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml index a86a64893c67..a52f90bfc9f9 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml @@ -76,6 +76,9 @@ properties: - const: mediatek,mt2701-vdecsys - const: syscon + power-domains: + maxItems: 1 + reg: maxItems: 1 @@ -86,6 +89,18 @@ required: - compatible - '#clock-cells' +if: + properties: + compatible: + contains: + const: mediatek,mt8183-mfgcfg +then: + properties: + power-domains: true +else: + properties: + power-domains: false + additionalProperties: false examples: -- cgit v1.2.3 From 24723d7c09ddac90bdd9e9864f92eb43ed70a083 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 15 Sep 2025 13:15:18 +0200 Subject: dt-bindings: remoteproc: qcom,milos-pas: Document remoteprocs Document the bindings for the ADSP, CDSP, MPSS and WPSS PAS on the Milos (e.g. SM7635) SoC. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250915-sm7635-remoteprocs-v5-1-96526cac59c6@fairphone.com Signed-off-by: Bjorn Andersson --- .../bindings/remoteproc/qcom,milos-pas.yaml | 198 +++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml new file mode 100644 index 000000000000..c47d97004b33 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,milos-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos SoC Peripheral Authentication Service + +maintainers: + - Luca Weiss + +description: + Qualcomm Milos SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,milos-adsp-pas + - qcom,milos-cdsp-pas + - qcom,milos-mpss-pas + - qcom,milos-wpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + interrupts: + minItems: 6 + maxItems: 6 + + interrupt-names: + minItems: 6 + maxItems: 6 + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + minItems: 1 + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + memory-region: + minItems: 1 + items: + - description: Memory region for core Firmware authentication + - description: Memory region for Devicetree Firmware authentication + +required: + - compatible + - reg + - memory-region + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,milos-adsp-pas + - qcom,milos-cdsp-pas + then: + properties: + memory-region: + minItems: 2 + firmware-name: + minItems: 2 + else: + properties: + memory-region: + maxItems: 1 + firmware-name: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - qcom,milos-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,milos-cdsp-pas + - qcom,milos-wpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MX power domain + power-domain-names: + items: + - const: cx + - const: mx + + - if: + properties: + compatible: + enum: + - qcom,milos-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + remoteproc@3000000 { + compatible = "qcom,milos-adsp-pas"; + reg = <0x03000000 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + firmware-name = "qcom/milos/vendor/device/adsp.mbn", + "qcom/milos/vendor/device/adsp_dtb.mbn"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; -- cgit v1.2.3 From dd240e95f1bee671f58148dea25e3be7cb39b50d Mon Sep 17 00:00:00 2001 From: Laura Nao Date: Mon, 15 Sep 2025 17:19:29 +0200 Subject: dt-bindings: clock: mediatek: Describe MT8196 clock controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce binding documentation for system clocks, functional clocks, and PEXTP0/1 and UFS reset controllers on MediaTek MT8196. This binding also includes a handle to the hardware voter, a fixed-function MCU designed to aggregate votes from the application processor and other remote processors to manage clocks and power domains. The HWV on MT8196/MT6991 is incomplete and requires software to manually enable power supplies, parent clocks, and FENC, as well as write to both the HWV MMIO and the controller registers. Because of these constraints, the HWV cannot be modeled using generic clock, power domain, or interconnect APIs. Instead, a custom phandle is exceptionally used to provide direct, syscon-like register access to drivers. Reviewed-by: Nícolas F. R. A. Prado Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd --- .../bindings/clock/mediatek,mt8196-clock.yaml | 112 +++ .../bindings/clock/mediatek,mt8196-sys-clock.yaml | 107 +++ include/dt-bindings/clock/mediatek,mt8196-clock.h | 803 +++++++++++++++++++++ include/dt-bindings/reset/mediatek,mt8196-resets.h | 26 + 4 files changed, 1048 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml create mode 100644 include/dt-bindings/clock/mediatek,mt8196-clock.h create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml new file mode 100644 index 000000000000..bfdbd2e4a167 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT8196 + +maintainers: + - Guangjie Song + - Laura Nao + +description: | + The clock architecture in MediaTek SoCs is structured like below: + PLLs --> + dividers --> + muxes + --> + clock gate + + The device nodes provide clock gate control in different IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8196-imp-iic-wrap-c + - mediatek,mt8196-imp-iic-wrap-e + - mediatek,mt8196-imp-iic-wrap-n + - mediatek,mt8196-imp-iic-wrap-w + - mediatek,mt8196-mdpsys0 + - mediatek,mt8196-mdpsys1 + - mediatek,mt8196-pericfg-ao + - mediatek,mt8196-pextp0cfg-ao + - mediatek,mt8196-pextp1cfg-ao + - mediatek,mt8196-ufscfg-ao + - mediatek,mt8196-vencsys + - mediatek,mt8196-vencsys-c1 + - mediatek,mt8196-vencsys-c2 + - mediatek,mt8196-vdecsys + - mediatek,mt8196-vdecsys-soc + - mediatek,mt8196-vdisp-ao + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + description: + Reset lines for PEXTP0/1 and UFS blocks. + + mediatek,hardware-voter: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the "Hardware Voter" (HWV), as named in the vendor + documentation for MT8196/MT6991. + + The HWV is a SoC-internal fixed-function MCU used to collect votes from + both the Application Processor and other remote processors within the SoC. + It is intended to transparently enable or disable hardware resources (such + as power domains or clocks) based on internal vote aggregation handled by + the MCU's internal state machine. + + However, in practice, this design is incomplete. While the HWV performs + some internal vote aggregation,software is still required to + - Manually enable power supplies externally, if present and if required + - Manually enable parent clocks via direct MMIO writes to clock controllers + - Enable the FENC after the clock has been ungated via direct MMIO + writes to clock controllers + + As such, the HWV behaves more like a hardware-managed clock reference + counter than a true voter. Furthermore, it is not a separate + controller. It merely serves as an alternative interface to the same + underlying clock or power controller. Actual control still requires + direct access to the controller's own MMIO register space, in + addition to writing to the HWV's MMIO region. + + For this reason, a custom phandle is used here - drivers need to directly + access the HWV MMIO region in a syscon-like fashion, due to how the + hardware is wired. This differs from true hardware voting systems, which + typically do not require custom phandles and rely instead on generic APIs + (clocks, power domains, interconnects). + + The name "hardware-voter" is retained to match vendor documentation, but + this should not be reused or misunderstood as a proper voting mechanism. + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + pericfg_ao: clock-controller@16640000 { + compatible = "mediatek,mt8196-pericfg-ao", "syscon"; + reg = <0x16640000 0x1000>; + mediatek,hardware-voter = <&scp_hwv>; + #clock-cells = <1>; + }; + - | + pextp0cfg_ao: clock-controller@169b0000 { + compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon"; + reg = <0x169b0000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml new file mode 100644 index 000000000000..660ab64f390d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT8196 + +maintainers: + - Guangjie Song + - Laura Nao + +description: | + The clock architecture in MediaTek SoCs is structured like below: + PLLs --> + dividers --> + muxes + --> + clock gate + + The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll + provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator. + The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which + provide the clock source to other IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8196-apmixedsys + - mediatek,mt8196-armpll-b-pll-ctrl + - mediatek,mt8196-armpll-bl-pll-ctrl + - mediatek,mt8196-armpll-ll-pll-ctrl + - mediatek,mt8196-apmixedsys-gp2 + - mediatek,mt8196-ccipll-pll-ctrl + - mediatek,mt8196-mfgpll-pll-ctrl + - mediatek,mt8196-mfgpll-sc0-pll-ctrl + - mediatek,mt8196-mfgpll-sc1-pll-ctrl + - mediatek,mt8196-ptppll-pll-ctrl + - mediatek,mt8196-topckgen + - mediatek,mt8196-topckgen-gp2 + - mediatek,mt8196-vlpckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + mediatek,hardware-voter: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the "Hardware Voter" (HWV), as named in the vendor + documentation for MT8196/MT6991. + + The HWV is a SoC-internal fixed-function MCU used to collect votes from + both the Application Processor and other remote processors within the SoC. + It is intended to transparently enable or disable hardware resources (such + as power domains or clocks) based on internal vote aggregation handled by + the MCU's internal state machine. + + However, in practice, this design is incomplete. While the HWV performs + some internal vote aggregation,software is still required to + - Manually enable power supplies externally, if present and if required + - Manually enable parent clocks via direct MMIO writes to clock controllers + - Enable the FENC after the clock has been ungated via direct MMIO + writes to clock controllers + + As such, the HWV behaves more like a hardware-managed clock reference + counter than a true voter. Furthermore, it is not a separate + controller. It merely serves as an alternative interface to the same + underlying clock or power controller. Actual control still requires + direct access to the controller's own MMIO register space, in + addition to writing to the HWV's MMIO region. + + For this reason, a custom phandle is used here - drivers need to directly + access the HWV MMIO region in a syscon-like fashion, due to how the + hardware is wired. This differs from true hardware voting systems, which + typically do not require custom phandles and rely instead on generic APIs + (clocks, power domains, interconnects). + + The name "hardware-voter" is retained to match vendor documentation, but + this should not be reused or misunderstood as a proper voting mechanism. + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + apmixedsys_clk: syscon@10000800 { + compatible = "mediatek,mt8196-apmixedsys", "syscon"; + reg = <0x10000800 0x1000>; + #clock-cells = <1>; + }; + - | + topckgen: syscon@10000000 { + compatible = "mediatek,mt8196-topckgen", "syscon"; + reg = <0x10000000 0x800>; + mediatek,hardware-voter = <&scp_hwv>; + #clock-cells = <1>; + }; + diff --git a/include/dt-bindings/clock/mediatek,mt8196-clock.h b/include/dt-bindings/clock/mediatek,mt8196-clock.h new file mode 100644 index 000000000000..ae0946ab7621 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8196-clock.h @@ -0,0 +1,803 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Guangjie Song + * Copyright (c) 2025 Collabora Ltd. + * Laura Nao + */ + +#ifndef _DT_BINDINGS_CLK_MT8196_H +#define _DT_BINDINGS_CLK_MT8196_H + +/* CKSYS */ +#define CLK_TOP_AXI 0 +#define CLK_TOP_MEM_SUB 1 +#define CLK_TOP_IO_NOC 2 +#define CLK_TOP_P_AXI 3 +#define CLK_TOP_UFS_PEXTP0_AXI 4 +#define CLK_TOP_PEXTP1_USB_AXI 5 +#define CLK_TOP_P_FMEM_SUB 6 +#define CLK_TOP_PEXPT0_MEM_SUB 7 +#define CLK_TOP_PEXTP1_USB_MEM_SUB 8 +#define CLK_TOP_P_NOC 9 +#define CLK_TOP_EMI_N 10 +#define CLK_TOP_EMI_S 11 +#define CLK_TOP_AP2CONN_HOST 12 +#define CLK_TOP_ATB 13 +#define CLK_TOP_CIRQ 14 +#define CLK_TOP_PBUS_156M 15 +#define CLK_TOP_EFUSE 16 +#define CLK_TOP_MCL3GIC 17 +#define CLK_TOP_MCINFRA 18 +#define CLK_TOP_DSP 19 +#define CLK_TOP_MFG_REF 20 +#define CLK_TOP_MFG_EB 21 +#define CLK_TOP_UART 22 +#define CLK_TOP_SPI0_BCLK 23 +#define CLK_TOP_SPI1_BCLK 24 +#define CLK_TOP_SPI2_BCLK 25 +#define CLK_TOP_SPI3_BCLK 26 +#define CLK_TOP_SPI4_BCLK 27 +#define CLK_TOP_SPI5_BCLK 28 +#define CLK_TOP_SPI6_BCLK 29 +#define CLK_TOP_SPI7_BCLK 30 +#define CLK_TOP_MSDC30_1 31 +#define CLK_TOP_MSDC30_2 32 +#define CLK_TOP_DISP_PWM 33 +#define CLK_TOP_USB_TOP_1P 34 +#define CLK_TOP_USB_XHCI_1P 35 +#define CLK_TOP_USB_FMCNT_P1 36 +#define CLK_TOP_I2C_P 37 +#define CLK_TOP_I2C_EAST 38 +#define CLK_TOP_I2C_WEST 39 +#define CLK_TOP_I2C_NORTH 40 +#define CLK_TOP_AES_UFSFDE 41 +#define CLK_TOP_UFS 42 +#define CLK_TOP_AUD_1 43 +#define CLK_TOP_AUD_2 44 +#define CLK_TOP_ADSP 45 +#define CLK_TOP_ADSP_UARTHUB_B 46 +#define CLK_TOP_DPMAIF_MAIN 47 +#define CLK_TOP_PWM 48 +#define CLK_TOP_MCUPM 49 +#define CLK_TOP_IPSEAST 50 +#define CLK_TOP_TL 51 +#define CLK_TOP_TL_P1 52 +#define CLK_TOP_TL_P2 53 +#define CLK_TOP_EMI_INTERFACE_546 54 +#define CLK_TOP_SDF 55 +#define CLK_TOP_UARTHUB_BCLK 56 +#define CLK_TOP_DPSW_CMP_26M 57 +#define CLK_TOP_SMAP 58 +#define CLK_TOP_SSR_PKA 59 +#define CLK_TOP_SSR_DMA 60 +#define CLK_TOP_SSR_KDF 61 +#define CLK_TOP_SSR_RNG 62 +#define CLK_TOP_SPU0 63 +#define CLK_TOP_SPU1 64 +#define CLK_TOP_DXCC 65 +#define CLK_TOP_APLL_I2SIN0 66 +#define CLK_TOP_APLL_I2SIN1 67 +#define CLK_TOP_APLL_I2SIN2 68 +#define CLK_TOP_APLL_I2SIN3 69 +#define CLK_TOP_APLL_I2SIN4 70 +#define CLK_TOP_APLL_I2SIN6 71 +#define CLK_TOP_APLL_I2SOUT0 72 +#define CLK_TOP_APLL_I2SOUT1 73 +#define CLK_TOP_APLL_I2SOUT2 74 +#define CLK_TOP_APLL_I2SOUT3 75 +#define CLK_TOP_APLL_I2SOUT4 76 +#define CLK_TOP_APLL_I2SOUT6 77 +#define CLK_TOP_APLL_FMI2S 78 +#define CLK_TOP_APLL_TDMOUT 79 +#define CLK_TOP_APLL12_DIV_TDMOUT_M 80 +#define CLK_TOP_APLL12_DIV_TDMOUT_B 81 +#define CLK_TOP_MAINPLL_D3 82 +#define CLK_TOP_MAINPLL_D4 83 +#define CLK_TOP_MAINPLL_D4_D2 84 +#define CLK_TOP_MAINPLL_D4_D4 85 +#define CLK_TOP_MAINPLL_D4_D8 86 +#define CLK_TOP_MAINPLL_D5 87 +#define CLK_TOP_MAINPLL_D5_D2 88 +#define CLK_TOP_MAINPLL_D5_D4 89 +#define CLK_TOP_MAINPLL_D5_D8 90 +#define CLK_TOP_MAINPLL_D6 91 +#define CLK_TOP_MAINPLL_D6_D2 92 +#define CLK_TOP_MAINPLL_D7 93 +#define CLK_TOP_MAINPLL_D7_D2 94 +#define CLK_TOP_MAINPLL_D7_D4 95 +#define CLK_TOP_MAINPLL_D7_D8 96 +#define CLK_TOP_MAINPLL_D9 97 +#define CLK_TOP_UNIVPLL_D4 98 +#define CLK_TOP_UNIVPLL_D4_D2 99 +#define CLK_TOP_UNIVPLL_D4_D4 100 +#define CLK_TOP_UNIVPLL_D4_D8 101 +#define CLK_TOP_UNIVPLL_D5 102 +#define CLK_TOP_UNIVPLL_D5_D2 103 +#define CLK_TOP_UNIVPLL_D5_D4 104 +#define CLK_TOP_UNIVPLL_D6 105 +#define CLK_TOP_UNIVPLL_D6_D2 106 +#define CLK_TOP_UNIVPLL_D6_D4 107 +#define CLK_TOP_UNIVPLL_D6_D8 108 +#define CLK_TOP_UNIVPLL_D6_D16 109 +#define CLK_TOP_UNIVPLL_192M 110 +#define CLK_TOP_UNIVPLL_192M_D4 111 +#define CLK_TOP_UNIVPLL_192M_D8 112 +#define CLK_TOP_UNIVPLL_192M_D16 113 +#define CLK_TOP_UNIVPLL_192M_D32 114 +#define CLK_TOP_UNIVPLL_192M_D10 115 +#define CLK_TOP_TVDPLL1_D2 116 +#define CLK_TOP_MSDCPLL_D2 117 +#define CLK_TOP_OSC_D2 118 +#define CLK_TOP_OSC_D3 119 +#define CLK_TOP_OSC_D4 120 +#define CLK_TOP_OSC_D5 121 +#define CLK_TOP_OSC_D7 122 +#define CLK_TOP_OSC_D8 123 +#define CLK_TOP_OSC_D10 124 +#define CLK_TOP_OSC_D14 125 +#define CLK_TOP_OSC_D20 126 +#define CLK_TOP_OSC_D32 127 +#define CLK_TOP_OSC_D40 128 +#define CLK_TOP_SFLASH 129 + +/* APMIXEDSYS */ +#define CLK_APMIXED_MAINPLL 0 +#define CLK_APMIXED_UNIVPLL 1 +#define CLK_APMIXED_MSDCPLL 2 +#define CLK_APMIXED_ADSPPLL 3 +#define CLK_APMIXED_EMIPLL 4 +#define CLK_APMIXED_EMIPLL2 5 +#define CLK_APMIXED_NET1PLL 6 +#define CLK_APMIXED_SGMIIPLL 7 + +/* CKSYS_GP2 */ +#define CLK_TOP2_SENINF0 0 +#define CLK_TOP2_SENINF1 1 +#define CLK_TOP2_SENINF2 2 +#define CLK_TOP2_SENINF3 3 +#define CLK_TOP2_SENINF4 4 +#define CLK_TOP2_SENINF5 5 +#define CLK_TOP2_IMG1 6 +#define CLK_TOP2_IPE 7 +#define CLK_TOP2_CAM 8 +#define CLK_TOP2_CAMTM 9 +#define CLK_TOP2_DPE 10 +#define CLK_TOP2_VDEC 11 +#define CLK_TOP2_CCUSYS 12 +#define CLK_TOP2_CCUTM 13 +#define CLK_TOP2_VENC 14 +#define CLK_TOP2_DP1 15 +#define CLK_TOP2_DP0 16 +#define CLK_TOP2_DISP 17 +#define CLK_TOP2_MDP 18 +#define CLK_TOP2_MMINFRA 19 +#define CLK_TOP2_MMINFRA_SNOC 20 +#define CLK_TOP2_MMUP 21 +#define CLK_TOP2_MMINFRA_AO 22 +#define CLK_TOP2_MAINPLL2_D2 23 +#define CLK_TOP2_MAINPLL2_D3 24 +#define CLK_TOP2_MAINPLL2_D4 25 +#define CLK_TOP2_MAINPLL2_D4_D2 26 +#define CLK_TOP2_MAINPLL2_D4_D4 27 +#define CLK_TOP2_MAINPLL2_D5 28 +#define CLK_TOP2_MAINPLL2_D5_D2 29 +#define CLK_TOP2_MAINPLL2_D6 30 +#define CLK_TOP2_MAINPLL2_D6_D2 31 +#define CLK_TOP2_MAINPLL2_D7 32 +#define CLK_TOP2_MAINPLL2_D7_D2 33 +#define CLK_TOP2_MAINPLL2_D9 34 +#define CLK_TOP2_UNIVPLL2_D3 35 +#define CLK_TOP2_UNIVPLL2_D4 36 +#define CLK_TOP2_UNIVPLL2_D4_D2 37 +#define CLK_TOP2_UNIVPLL2_D5 38 +#define CLK_TOP2_UNIVPLL2_D5_D2 39 +#define CLK_TOP2_UNIVPLL2_D6 40 +#define CLK_TOP2_UNIVPLL2_D6_D2 41 +#define CLK_TOP2_UNIVPLL2_D6_D4 42 +#define CLK_TOP2_UNIVPLL2_D7 43 +#define CLK_TOP2_IMGPLL_D2 44 +#define CLK_TOP2_IMGPLL_D4 45 +#define CLK_TOP2_IMGPLL_D5 46 +#define CLK_TOP2_IMGPLL_D5_D2 47 +#define CLK_TOP2_MMPLL2_D3 48 +#define CLK_TOP2_MMPLL2_D4 49 +#define CLK_TOP2_MMPLL2_D4_D2 50 +#define CLK_TOP2_MMPLL2_D5 51 +#define CLK_TOP2_MMPLL2_D5_D2 52 +#define CLK_TOP2_MMPLL2_D6 53 +#define CLK_TOP2_MMPLL2_D6_D2 54 +#define CLK_TOP2_MMPLL2_D7 55 +#define CLK_TOP2_MMPLL2_D9 56 +#define CLK_TOP2_TVDPLL1_D4 57 +#define CLK_TOP2_TVDPLL1_D8 58 +#define CLK_TOP2_TVDPLL1_D16 59 +#define CLK_TOP2_TVDPLL2_D2 60 +#define CLK_TOP2_TVDPLL2_D4 61 +#define CLK_TOP2_TVDPLL2_D8 62 +#define CLK_TOP2_TVDPLL2_D16 63 +#define CLK_TOP2_DVO 64 +#define CLK_TOP2_DVO_FAVT 65 +#define CLK_TOP2_TVDPLL3_D2 66 +#define CLK_TOP2_TVDPLL3_D4 67 +#define CLK_TOP2_TVDPLL3_D8 68 +#define CLK_TOP2_TVDPLL3_D16 69 + +/* APMIXEDSYS_GP2 */ +#define CLK_APMIXED2_MAINPLL2 0 +#define CLK_APMIXED2_UNIVPLL2 1 +#define CLK_APMIXED2_MMPLL2 2 +#define CLK_APMIXED2_IMGPLL 3 +#define CLK_APMIXED2_TVDPLL1 4 +#define CLK_APMIXED2_TVDPLL2 5 +#define CLK_APMIXED2_TVDPLL3 6 + +/* IMP_IIC_WRAP_E */ +#define CLK_IMPE_I2C5 0 + +/* IMP_IIC_WRAP_W */ +#define CLK_IMPW_I2C0 0 +#define CLK_IMPW_I2C3 1 +#define CLK_IMPW_I2C6 2 +#define CLK_IMPW_I2C10 3 + +/* IMP_IIC_WRAP_N */ +#define CLK_IMPN_I2C1 0 +#define CLK_IMPN_I2C2 1 +#define CLK_IMPN_I2C4 2 +#define CLK_IMPN_I2C7 3 +#define CLK_IMPN_I2C8 4 +#define CLK_IMPN_I2C9 5 + +/* IMP_IIC_WRAP_C */ +#define CLK_IMPC_I2C11 0 +#define CLK_IMPC_I2C12 1 +#define CLK_IMPC_I2C13 2 +#define CLK_IMPC_I2C14 3 + +/* PERICFG_AO */ +#define CLK_PERI_AO_UART0_BCLK 0 +#define CLK_PERI_AO_UART1_BCLK 1 +#define CLK_PERI_AO_UART2_BCLK 2 +#define CLK_PERI_AO_UART3_BCLK 3 +#define CLK_PERI_AO_UART4_BCLK 4 +#define CLK_PERI_AO_UART5_BCLK 5 +#define CLK_PERI_AO_PWM_X16W_HCLK 6 +#define CLK_PERI_AO_PWM_X16W_BCLK 7 +#define CLK_PERI_AO_PWM_PWM_BCLK0 8 +#define CLK_PERI_AO_PWM_PWM_BCLK1 9 +#define CLK_PERI_AO_PWM_PWM_BCLK2 10 +#define CLK_PERI_AO_PWM_PWM_BCLK3 11 +#define CLK_PERI_AO_SPI0_BCLK 12 +#define CLK_PERI_AO_SPI1_BCLK 13 +#define CLK_PERI_AO_SPI2_BCLK 14 +#define CLK_PERI_AO_SPI3_BCLK 15 +#define CLK_PERI_AO_SPI4_BCLK 16 +#define CLK_PERI_AO_SPI5_BCLK 17 +#define CLK_PERI_AO_SPI6_BCLK 18 +#define CLK_PERI_AO_SPI7_BCLK 19 +#define CLK_PERI_AO_AP_DMA_X32W_BCLK 20 +#define CLK_PERI_AO_MSDC1_MSDC_SRC 21 +#define CLK_PERI_AO_MSDC1_HCLK 22 +#define CLK_PERI_AO_MSDC1_AXI 23 +#define CLK_PERI_AO_MSDC1_HCLK_WRAP 24 +#define CLK_PERI_AO_MSDC2_MSDC_SRC 25 +#define CLK_PERI_AO_MSDC2_HCLK 26 +#define CLK_PERI_AO_MSDC2_AXI 27 +#define CLK_PERI_AO_MSDC2_HCLK_WRAP 28 +#define CLK_PERI_AO_FLASHIF_FLASH 29 +#define CLK_PERI_AO_FLASHIF_27M 30 +#define CLK_PERI_AO_FLASHIF_DRAM 31 +#define CLK_PERI_AO_FLASHIF_AXI 32 +#define CLK_PERI_AO_FLASHIF_BCLK 33 + +/* UFSCFG_AO */ +#define CLK_UFSAO_UNIPRO_TX_SYM 0 +#define CLK_UFSAO_UNIPRO_RX_SYM0 1 +#define CLK_UFSAO_UNIPRO_RX_SYM1 2 +#define CLK_UFSAO_UNIPRO_SYS 3 +#define CLK_UFSAO_UNIPRO_SAP 4 +#define CLK_UFSAO_PHY_SAP 5 +#define CLK_UFSAO_UFSHCI_UFS 6 +#define CLK_UFSAO_UFSHCI_AES 7 + +/* PEXTP0CFG_AO */ +#define CLK_PEXT_PEXTP_MAC_P0_TL 0 +#define CLK_PEXT_PEXTP_MAC_P0_REF 1 +#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS 2 +#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF 3 +#define CLK_PEXT_PEXTP_MAC_P0_AXI_250 4 +#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB 5 +#define CLK_PEXT_PEXTP_MAC_P0_PL_P 6 +#define CLK_PEXT_PEXTP_VLP_AO_P0_LP 7 + +/* PEXTP1CFG_AO */ +#define CLK_PEXT1_PEXTP_MAC_P1_TL 0 +#define CLK_PEXT1_PEXTP_MAC_P1_REF 1 +#define CLK_PEXT1_PEXTP_MAC_P2_TL 2 +#define CLK_PEXT1_PEXTP_MAC_P2_REF 3 +#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS 4 +#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF 5 +#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS 6 +#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF 7 +#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250 8 +#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB 9 +#define CLK_PEXT1_PEXTP_MAC_P1_PL_P 10 +#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250 11 +#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB 12 +#define CLK_PEXT1_PEXTP_MAC_P2_PL_P 13 +#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP 14 +#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP 15 + +/* VLP_CKSYS */ +#define CLK_VLP_APLL1 0 +#define CLK_VLP_APLL2 1 +#define CLK_VLP_SCP 2 +#define CLK_VLP_SCP_SPI 3 +#define CLK_VLP_SCP_IIC 4 +#define CLK_VLP_SCP_IIC_HS 5 +#define CLK_VLP_PWRAP_ULPOSC 6 +#define CLK_VLP_SPMI_M_TIA_32K 7 +#define CLK_VLP_APXGPT_26M_B 8 +#define CLK_VLP_DPSW 9 +#define CLK_VLP_DPSW_CENTRAL 10 +#define CLK_VLP_SPMI_M_MST 11 +#define CLK_VLP_DVFSRC 12 +#define CLK_VLP_PWM_VLP 13 +#define CLK_VLP_AXI_VLP 14 +#define CLK_VLP_SYSTIMER_26M 15 +#define CLK_VLP_SSPM 16 +#define CLK_VLP_SRCK 17 +#define CLK_VLP_CAMTG0 18 +#define CLK_VLP_CAMTG1 19 +#define CLK_VLP_CAMTG2 20 +#define CLK_VLP_CAMTG3 21 +#define CLK_VLP_CAMTG4 22 +#define CLK_VLP_CAMTG5 23 +#define CLK_VLP_CAMTG6 24 +#define CLK_VLP_CAMTG7 25 +#define CLK_VLP_SSPM_26M 26 +#define CLK_VLP_ULPOSC_SSPM 27 +#define CLK_VLP_VLP_PBUS_26M 28 +#define CLK_VLP_DEBUG_ERR_FLAG 29 +#define CLK_VLP_DPMSRDMA 30 +#define CLK_VLP_VLP_PBUS_156M 31 +#define CLK_VLP_SPM 32 +#define CLK_VLP_MMINFRA 33 +#define CLK_VLP_USB_TOP 34 +#define CLK_VLP_USB_XHCI 35 +#define CLK_VLP_NOC_VLP 36 +#define CLK_VLP_AUDIO_H 37 +#define CLK_VLP_AUD_ENGEN1 38 +#define CLK_VLP_AUD_ENGEN2 39 +#define CLK_VLP_AUD_INTBUS 40 +#define CLK_VLP_SPVLP_26M 41 +#define CLK_VLP_SPU0_VLP 42 +#define CLK_VLP_SPU1_VLP 43 +#define CLK_VLP_CLK26M 44 +#define CLK_VLP_APLL1_D4 45 +#define CLK_VLP_APLL1_D8 46 +#define CLK_VLP_APLL2_D4 47 +#define CLK_VLP_APLL2_D8 48 + +/* DISPSYS_CONFIG */ +#define CLK_MM_CONFIG 0 +#define CLK_MM_DISP_MUTEX0 1 +#define CLK_MM_DISP_AAL0 2 +#define CLK_MM_DISP_AAL1 3 +#define CLK_MM_DISP_C3D0 4 +#define CLK_MM_DISP_C3D1 5 +#define CLK_MM_DISP_C3D2 6 +#define CLK_MM_DISP_C3D3 7 +#define CLK_MM_DISP_CCORR0 8 +#define CLK_MM_DISP_CCORR1 9 +#define CLK_MM_DISP_CCORR2 10 +#define CLK_MM_DISP_CCORR3 11 +#define CLK_MM_DISP_CHIST0 12 +#define CLK_MM_DISP_CHIST1 13 +#define CLK_MM_DISP_COLOR0 14 +#define CLK_MM_DISP_COLOR1 15 +#define CLK_MM_DISP_DITHER0 16 +#define CLK_MM_DISP_DITHER1 17 +#define CLK_MM_DISP_DLI_ASYNC0 18 +#define CLK_MM_DISP_DLI_ASYNC1 19 +#define CLK_MM_DISP_DLI_ASYNC2 20 +#define CLK_MM_DISP_DLI_ASYNC3 21 +#define CLK_MM_DISP_DLI_ASYNC4 22 +#define CLK_MM_DISP_DLI_ASYNC5 23 +#define CLK_MM_DISP_DLI_ASYNC6 24 +#define CLK_MM_DISP_DLI_ASYNC7 25 +#define CLK_MM_DISP_DLI_ASYNC8 26 +#define CLK_MM_DISP_DLI_ASYNC9 27 +#define CLK_MM_DISP_DLI_ASYNC10 28 +#define CLK_MM_DISP_DLI_ASYNC11 29 +#define CLK_MM_DISP_DLI_ASYNC12 30 +#define CLK_MM_DISP_DLI_ASYNC13 31 +#define CLK_MM_DISP_DLI_ASYNC14 32 +#define CLK_MM_DISP_DLI_ASYNC15 33 +#define CLK_MM_DISP_DLO_ASYNC0 34 +#define CLK_MM_DISP_DLO_ASYNC1 35 +#define CLK_MM_DISP_DLO_ASYNC2 36 +#define CLK_MM_DISP_DLO_ASYNC3 37 +#define CLK_MM_DISP_DLO_ASYNC4 38 +#define CLK_MM_DISP_DLO_ASYNC5 39 +#define CLK_MM_DISP_DLO_ASYNC6 40 +#define CLK_MM_DISP_DLO_ASYNC7 41 +#define CLK_MM_DISP_DLO_ASYNC8 42 +#define CLK_MM_DISP_GAMMA0 43 +#define CLK_MM_DISP_GAMMA1 44 +#define CLK_MM_MDP_AAL0 45 +#define CLK_MM_MDP_AAL1 46 +#define CLK_MM_MDP_RDMA0 47 +#define CLK_MM_DISP_POSTMASK0 48 +#define CLK_MM_DISP_POSTMASK1 49 +#define CLK_MM_MDP_RSZ0 50 +#define CLK_MM_MDP_RSZ1 51 +#define CLK_MM_DISP_SPR0 52 +#define CLK_MM_DISP_TDSHP0 53 +#define CLK_MM_DISP_TDSHP1 54 +#define CLK_MM_DISP_WDMA0 55 +#define CLK_MM_DISP_Y2R0 56 +#define CLK_MM_SMI_SUB_COMM0 57 +#define CLK_MM_DISP_FAKE_ENG0 58 + +/* DISPSYS1_CONFIG */ +#define CLK_MM1_DISPSYS1_CONFIG 0 +#define CLK_MM1_DISPSYS1_S_CONFIG 1 +#define CLK_MM1_DISP_MUTEX0 2 +#define CLK_MM1_DISP_DLI_ASYNC20 3 +#define CLK_MM1_DISP_DLI_ASYNC21 4 +#define CLK_MM1_DISP_DLI_ASYNC22 5 +#define CLK_MM1_DISP_DLI_ASYNC23 6 +#define CLK_MM1_DISP_DLI_ASYNC24 7 +#define CLK_MM1_DISP_DLI_ASYNC25 8 +#define CLK_MM1_DISP_DLI_ASYNC26 9 +#define CLK_MM1_DISP_DLI_ASYNC27 10 +#define CLK_MM1_DISP_DLI_ASYNC28 11 +#define CLK_MM1_DISP_RELAY0 12 +#define CLK_MM1_DISP_RELAY1 13 +#define CLK_MM1_DISP_RELAY2 14 +#define CLK_MM1_DISP_RELAY3 15 +#define CLK_MM1_DISP_DP_INTF0 16 +#define CLK_MM1_DISP_DP_INTF1 17 +#define CLK_MM1_DISP_DSC_WRAP0 18 +#define CLK_MM1_DISP_DSC_WRAP1 19 +#define CLK_MM1_DISP_DSC_WRAP2 20 +#define CLK_MM1_DISP_DSC_WRAP3 21 +#define CLK_MM1_DISP_DSI0 22 +#define CLK_MM1_DISP_DSI1 23 +#define CLK_MM1_DISP_DSI2 24 +#define CLK_MM1_DISP_DVO0 25 +#define CLK_MM1_DISP_GDMA0 26 +#define CLK_MM1_DISP_MERGE0 27 +#define CLK_MM1_DISP_MERGE1 28 +#define CLK_MM1_DISP_MERGE2 29 +#define CLK_MM1_DISP_ODDMR0 30 +#define CLK_MM1_DISP_POSTALIGN0 31 +#define CLK_MM1_DISP_DITHER2 32 +#define CLK_MM1_DISP_R2Y0 33 +#define CLK_MM1_DISP_SPLITTER0 34 +#define CLK_MM1_DISP_SPLITTER1 35 +#define CLK_MM1_DISP_SPLITTER2 36 +#define CLK_MM1_DISP_SPLITTER3 37 +#define CLK_MM1_DISP_VDCM0 38 +#define CLK_MM1_DISP_WDMA1 39 +#define CLK_MM1_DISP_WDMA2 40 +#define CLK_MM1_DISP_WDMA3 41 +#define CLK_MM1_DISP_WDMA4 42 +#define CLK_MM1_MDP_RDMA1 43 +#define CLK_MM1_SMI_LARB0 44 +#define CLK_MM1_MOD1 45 +#define CLK_MM1_MOD2 46 +#define CLK_MM1_MOD3 47 +#define CLK_MM1_MOD4 48 +#define CLK_MM1_MOD5 49 +#define CLK_MM1_MOD6 50 +#define CLK_MM1_CG0 51 +#define CLK_MM1_CG1 52 +#define CLK_MM1_CG2 53 +#define CLK_MM1_CG3 54 +#define CLK_MM1_CG4 55 +#define CLK_MM1_CG5 56 +#define CLK_MM1_CG6 57 +#define CLK_MM1_CG7 58 +#define CLK_MM1_F26M 59 + +/* OVLSYS_CONFIG */ +#define CLK_OVLSYS_CONFIG 0 +#define CLK_OVL_FAKE_ENG0 1 +#define CLK_OVL_FAKE_ENG1 2 +#define CLK_OVL_MUTEX0 3 +#define CLK_OVL_EXDMA0 4 +#define CLK_OVL_EXDMA1 5 +#define CLK_OVL_EXDMA2 6 +#define CLK_OVL_EXDMA3 7 +#define CLK_OVL_EXDMA4 8 +#define CLK_OVL_EXDMA5 9 +#define CLK_OVL_EXDMA6 10 +#define CLK_OVL_EXDMA7 11 +#define CLK_OVL_EXDMA8 12 +#define CLK_OVL_EXDMA9 13 +#define CLK_OVL_BLENDER0 14 +#define CLK_OVL_BLENDER1 15 +#define CLK_OVL_BLENDER2 16 +#define CLK_OVL_BLENDER3 17 +#define CLK_OVL_BLENDER4 18 +#define CLK_OVL_BLENDER5 19 +#define CLK_OVL_BLENDER6 20 +#define CLK_OVL_BLENDER7 21 +#define CLK_OVL_BLENDER8 22 +#define CLK_OVL_BLENDER9 23 +#define CLK_OVL_OUTPROC0 24 +#define CLK_OVL_OUTPROC1 25 +#define CLK_OVL_OUTPROC2 26 +#define CLK_OVL_OUTPROC3 27 +#define CLK_OVL_OUTPROC4 28 +#define CLK_OVL_OUTPROC5 29 +#define CLK_OVL_MDP_RSZ0 30 +#define CLK_OVL_MDP_RSZ1 31 +#define CLK_OVL_DISP_WDMA0 32 +#define CLK_OVL_DISP_WDMA1 33 +#define CLK_OVL_UFBC_WDMA0 34 +#define CLK_OVL_MDP_RDMA0 35 +#define CLK_OVL_MDP_RDMA1 36 +#define CLK_OVL_BWM0 37 +#define CLK_OVL_DLI0 38 +#define CLK_OVL_DLI1 39 +#define CLK_OVL_DLI2 40 +#define CLK_OVL_DLI3 41 +#define CLK_OVL_DLI4 42 +#define CLK_OVL_DLI5 43 +#define CLK_OVL_DLI6 44 +#define CLK_OVL_DLI7 45 +#define CLK_OVL_DLI8 46 +#define CLK_OVL_DLO0 47 +#define CLK_OVL_DLO1 48 +#define CLK_OVL_DLO2 49 +#define CLK_OVL_DLO3 50 +#define CLK_OVL_DLO4 51 +#define CLK_OVL_DLO5 52 +#define CLK_OVL_DLO6 53 +#define CLK_OVL_DLO7 54 +#define CLK_OVL_DLO8 55 +#define CLK_OVL_DLO9 56 +#define CLK_OVL_DLO10 57 +#define CLK_OVL_DLO11 58 +#define CLK_OVL_DLO12 59 +#define CLK_OVLSYS_RELAY0 60 +#define CLK_OVL_INLINEROT0 61 +#define CLK_OVL_SMI 62 +#define CLK_OVL_SMI_SMI 63 + + +/* OVLSYS1_CONFIG */ +#define CLK_OVL1_OVLSYS_CONFIG 0 +#define CLK_OVL1_OVL_FAKE_ENG0 1 +#define CLK_OVL1_OVL_FAKE_ENG1 2 +#define CLK_OVL1_OVL_MUTEX0 3 +#define CLK_OVL1_OVL_EXDMA0 4 +#define CLK_OVL1_OVL_EXDMA1 5 +#define CLK_OVL1_OVL_EXDMA2 6 +#define CLK_OVL1_OVL_EXDMA3 7 +#define CLK_OVL1_OVL_EXDMA4 8 +#define CLK_OVL1_OVL_EXDMA5 9 +#define CLK_OVL1_OVL_EXDMA6 10 +#define CLK_OVL1_OVL_EXDMA7 11 +#define CLK_OVL1_OVL_EXDMA8 12 +#define CLK_OVL1_OVL_EXDMA9 13 +#define CLK_OVL1_OVL_BLENDER0 14 +#define CLK_OVL1_OVL_BLENDER1 15 +#define CLK_OVL1_OVL_BLENDER2 16 +#define CLK_OVL1_OVL_BLENDER3 17 +#define CLK_OVL1_OVL_BLENDER4 18 +#define CLK_OVL1_OVL_BLENDER5 19 +#define CLK_OVL1_OVL_BLENDER6 20 +#define CLK_OVL1_OVL_BLENDER7 21 +#define CLK_OVL1_OVL_BLENDER8 22 +#define CLK_OVL1_OVL_BLENDER9 23 +#define CLK_OVL1_OVL_OUTPROC0 24 +#define CLK_OVL1_OVL_OUTPROC1 25 +#define CLK_OVL1_OVL_OUTPROC2 26 +#define CLK_OVL1_OVL_OUTPROC3 27 +#define CLK_OVL1_OVL_OUTPROC4 28 +#define CLK_OVL1_OVL_OUTPROC5 29 +#define CLK_OVL1_OVL_MDP_RSZ0 30 +#define CLK_OVL1_OVL_MDP_RSZ1 31 +#define CLK_OVL1_OVL_DISP_WDMA0 32 +#define CLK_OVL1_OVL_DISP_WDMA1 33 +#define CLK_OVL1_OVL_UFBC_WDMA0 34 +#define CLK_OVL1_OVL_MDP_RDMA0 35 +#define CLK_OVL1_OVL_MDP_RDMA1 36 +#define CLK_OVL1_OVL_BWM0 37 +#define CLK_OVL1_DLI0 38 +#define CLK_OVL1_DLI1 39 +#define CLK_OVL1_DLI2 40 +#define CLK_OVL1_DLI3 41 +#define CLK_OVL1_DLI4 42 +#define CLK_OVL1_DLI5 43 +#define CLK_OVL1_DLI6 44 +#define CLK_OVL1_DLI7 45 +#define CLK_OVL1_DLI8 46 +#define CLK_OVL1_DLO0 47 +#define CLK_OVL1_DLO1 48 +#define CLK_OVL1_DLO2 49 +#define CLK_OVL1_DLO3 50 +#define CLK_OVL1_DLO4 51 +#define CLK_OVL1_DLO5 52 +#define CLK_OVL1_DLO6 53 +#define CLK_OVL1_DLO7 54 +#define CLK_OVL1_DLO8 55 +#define CLK_OVL1_DLO9 56 +#define CLK_OVL1_DLO10 57 +#define CLK_OVL1_DLO11 58 +#define CLK_OVL1_DLO12 59 +#define CLK_OVL1_OVLSYS_RELAY0 60 +#define CLK_OVL1_OVL_INLINEROT0 61 +#define CLK_OVL1_SMI 62 + + +/* VDEC_SOC_GCON_BASE */ +#define CLK_VDE1_LARB1_CKEN 0 +#define CLK_VDE1_LAT_CKEN 1 +#define CLK_VDE1_LAT_ACTIVE 2 +#define CLK_VDE1_LAT_CKEN_ENG 3 +#define CLK_VDE1_VDEC_CKEN 4 +#define CLK_VDE1_VDEC_ACTIVE 5 +#define CLK_VDE1_VDEC_CKEN_ENG 6 +#define CLK_VDE1_VDEC_SOC_APTV_EN 7 +#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN 8 +#define CLK_VDE1_VDEC_SOC_IPS_EN 9 + +/* VDEC_GCON_BASE */ +#define CLK_VDE2_LARB1_CKEN 0 +#define CLK_VDE2_LAT_CKEN 1 +#define CLK_VDE2_LAT_ACTIVE 2 +#define CLK_VDE2_LAT_CKEN_ENG 3 +#define CLK_VDE2_VDEC_CKEN 4 +#define CLK_VDE2_VDEC_ACTIVE 5 +#define CLK_VDE2_VDEC_CKEN_ENG 6 + +/* VENC_GCON */ +#define CLK_VEN1_CKE0_LARB 0 +#define CLK_VEN1_CKE1_VENC 1 +#define CLK_VEN1_CKE2_JPGENC 2 +#define CLK_VEN1_CKE3_JPGDEC 3 +#define CLK_VEN1_CKE4_JPGDEC_C1 4 +#define CLK_VEN1_CKE5_GALS 5 +#define CLK_VEN1_CKE29_VENC_ADAB_CTRL 6 +#define CLK_VEN1_CKE29_VENC_XPC_CTRL 7 +#define CLK_VEN1_CKE6_GALS_SRAM 8 +#define CLK_VEN1_RES_FLAT 9 + +/* VENC_GCON_CORE1 */ +#define CLK_VEN2_CKE0_LARB 0 +#define CLK_VEN2_CKE1_VENC 1 +#define CLK_VEN2_CKE2_JPGENC 2 +#define CLK_VEN2_CKE3_JPGDEC 3 +#define CLK_VEN2_CKE5_GALS 4 +#define CLK_VEN2_CKE29_VENC_XPC_CTRL 5 +#define CLK_VEN2_CKE6_GALS_SRAM 6 +#define CLK_VEN2_RES_FLAT 7 + +/* VENC_GCON_CORE2 */ +#define CLK_VEN_C2_CKE0_LARB 0 +#define CLK_VEN_C2_CKE1_VENC 1 +#define CLK_VEN_C2_CKE5_GALS 2 +#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL 3 +#define CLK_VEN_C2_CKE6_GALS_SRAM 4 +#define CLK_VEN_C2_RES_FLAT 5 + +/* MDPSYS_CONFIG */ +#define CLK_MDP_MDP_MUTEX0 0 +#define CLK_MDP_SMI0 1 +#define CLK_MDP_SMI0_SMI 2 +#define CLK_MDP_APB_BUS 3 +#define CLK_MDP_MDP_RDMA0 4 +#define CLK_MDP_MDP_RDMA1 5 +#define CLK_MDP_MDP_RDMA2 6 +#define CLK_MDP_MDP_BIRSZ0 7 +#define CLK_MDP_MDP_HDR0 8 +#define CLK_MDP_MDP_AAL0 9 +#define CLK_MDP_MDP_RSZ0 10 +#define CLK_MDP_MDP_RSZ2 11 +#define CLK_MDP_MDP_TDSHP0 12 +#define CLK_MDP_MDP_COLOR0 13 +#define CLK_MDP_MDP_WROT0 14 +#define CLK_MDP_MDP_WROT1 15 +#define CLK_MDP_MDP_WROT2 16 +#define CLK_MDP_MDP_FAKE_ENG0 17 +#define CLK_MDP_APB_DB 18 +#define CLK_MDP_MDP_DLI_ASYNC0 19 +#define CLK_MDP_MDP_DLI_ASYNC1 20 +#define CLK_MDP_MDP_DLO_ASYNC0 21 +#define CLK_MDP_MDP_DLO_ASYNC1 22 +#define CLK_MDP_MDP_DLI_ASYNC2 23 +#define CLK_MDP_MDP_DLO_ASYNC2 24 +#define CLK_MDP_MDP_DLO_ASYNC3 25 +#define CLK_MDP_IMG_DL_ASYNC0 26 +#define CLK_MDP_MDP_RROT0 27 +#define CLK_MDP_MDP_MERGE0 28 +#define CLK_MDP_MDP_C3D0 29 +#define CLK_MDP_MDP_FG0 30 +#define CLK_MDP_MDP_CLA2 31 +#define CLK_MDP_MDP_DLO_ASYNC4 32 +#define CLK_MDP_VPP_RSZ0 33 +#define CLK_MDP_VPP_RSZ1 34 +#define CLK_MDP_MDP_DLO_ASYNC5 35 +#define CLK_MDP_IMG0 36 +#define CLK_MDP_F26M 37 +#define CLK_MDP_IMG_DL_RELAY0 38 +#define CLK_MDP_IMG_DL_RELAY1 39 + +/* MDPSYS1_CONFIG */ +#define CLK_MDP1_MDP_MUTEX0 0 +#define CLK_MDP1_SMI0 1 +#define CLK_MDP1_SMI0_SMI 2 +#define CLK_MDP1_APB_BUS 3 +#define CLK_MDP1_MDP_RDMA0 4 +#define CLK_MDP1_MDP_RDMA1 5 +#define CLK_MDP1_MDP_RDMA2 6 +#define CLK_MDP1_MDP_BIRSZ0 7 +#define CLK_MDP1_MDP_HDR0 8 +#define CLK_MDP1_MDP_AAL0 9 +#define CLK_MDP1_MDP_RSZ0 10 +#define CLK_MDP1_MDP_RSZ2 11 +#define CLK_MDP1_MDP_TDSHP0 12 +#define CLK_MDP1_MDP_COLOR0 13 +#define CLK_MDP1_MDP_WROT0 14 +#define CLK_MDP1_MDP_WROT1 15 +#define CLK_MDP1_MDP_WROT2 16 +#define CLK_MDP1_MDP_FAKE_ENG0 17 +#define CLK_MDP1_APB_DB 18 +#define CLK_MDP1_MDP_DLI_ASYNC0 19 +#define CLK_MDP1_MDP_DLI_ASYNC1 20 +#define CLK_MDP1_MDP_DLO_ASYNC0 21 +#define CLK_MDP1_MDP_DLO_ASYNC1 22 +#define CLK_MDP1_MDP_DLI_ASYNC2 23 +#define CLK_MDP1_MDP_DLO_ASYNC2 24 +#define CLK_MDP1_MDP_DLO_ASYNC3 25 +#define CLK_MDP1_IMG_DL_ASYNC0 26 +#define CLK_MDP1_MDP_RROT0 27 +#define CLK_MDP1_MDP_MERGE0 28 +#define CLK_MDP1_MDP_C3D0 29 +#define CLK_MDP1_MDP_FG0 30 +#define CLK_MDP1_MDP_CLA2 31 +#define CLK_MDP1_MDP_DLO_ASYNC4 32 +#define CLK_MDP1_VPP_RSZ0 33 +#define CLK_MDP1_VPP_RSZ1 34 +#define CLK_MDP1_MDP_DLO_ASYNC5 35 +#define CLK_MDP1_IMG0 36 +#define CLK_MDP1_F26M 37 +#define CLK_MDP1_IMG_DL_RELAY0 38 +#define CLK_MDP1_IMG_DL_RELAY1 39 + +/* DISP_VDISP_AO_CONFIG */ +#define CLK_MM_V_DISP_VDISP_AO_CONFIG 0 +#define CLK_MM_V_DISP_DPC 1 +#define CLK_MM_V_SMI_SUB_SOMM0 2 + +/* MFGPLL_PLL_CTRL */ +#define CLK_MFG_AO_MFGPLL 0 + +/* MFGPLL_SC0_PLL_CTRL */ +#define CLK_MFGSC0_AO_MFGPLL_SC0 0 + +/* MFGPLL_SC1_PLL_CTRL */ +#define CLK_MFGSC1_AO_MFGPLL_SC1 0 + +/* CCIPLL_PLL_CTRL */ +#define CLK_CCIPLL 0 + +/* ARMPLL_LL_PLL_CTRL */ +#define CLK_CPLL_ARMPLL_LL 0 + +/* ARMPLL_BL_PLL_CTRL */ +#define CLK_CPBL_ARMPLL_BL 0 + +/* ARMPLL_B_PLL_CTRL */ +#define CLK_CPB_ARMPLL_B 0 + +/* PTPPLL_PLL_CTRL */ +#define CLK_PTPPLL 0 + +#endif /* _DT_BINDINGS_CLK_MT8196_H */ diff --git a/include/dt-bindings/reset/mediatek,mt8196-resets.h b/include/dt-bindings/reset/mediatek,mt8196-resets.h new file mode 100644 index 000000000000..46ced0850d91 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt8196-resets.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8196 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8196 + +/* PEXTP0 resets */ +#define MT8196_PEXTP0_RST0_PCIE0_MAC 0 +#define MT8196_PEXTP0_RST0_PCIE0_PHY 1 + +/* PEXTP1 resets */ +#define MT8196_PEXTP1_RST0_PCIE1_MAC 0 +#define MT8196_PEXTP1_RST0_PCIE1_PHY 1 +#define MT8196_PEXTP1_RST0_PCIE2_MAC 2 +#define MT8196_PEXTP1_RST0_PCIE2_PHY 3 + +/* UFS resets */ +#define MT8196_UFSAO_RST0_UFS_MPHY 0 +#define MT8196_UFSAO_RST1_UFS_UNIPRO 1 +#define MT8196_UFSAO_RST1_UFS_CRYPTO 2 +#define MT8196_UFSAO_RST1_UFSHCI 3 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8196 */ -- cgit v1.2.3 From b52297f6eb82e46ae5ecc34d270e7ed96eca0594 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 12 Sep 2025 13:36:12 +0200 Subject: dt-bindings: clock: st: flexgen: remove deprecated compatibles st/stih407-clock.dtsi file has been removed in commit 65322c1daf51 ("clk: st: flexgen: remove unused compatible"). This file has three compatibles which are now dangling. Remove them from documentation. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Brian Masney Reviewed-by: Patrice Chotard Acked-by: Rob Herring (Arm) Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/st/st,flexgen.txt | 3 --- 1 file changed, 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index c918075405ba..a9d1c19f30a3 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,12 +64,9 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) - "st,flexgen-stih407-a0" "st,flexgen-stih410-a0" - "st,flexgen-stih407-c0" "st,flexgen-stih410-c0" "st,flexgen-stih418-c0" - "st,flexgen-stih407-d0" "st,flexgen-stih410-d0" "st,flexgen-stih407-d2" "st,flexgen-stih418-d2" -- cgit v1.2.3 From 49f6c8b74d9a20c0dd16bd75c93b981a3d420a37 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 25 Jun 2025 11:07:24 +0200 Subject: dt-bindings: stm32: add STM32MP21 clocks and reset bindings Adds clock and reset binding entries for STM32MP21 SoC family. Signed-off-by: Nicolas Le Bayon Reviewed-by: Conor Dooley Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd --- .../bindings/clock/st,stm32mp21-rcc.yaml | 199 ++++++++++ include/dt-bindings/clock/st,stm32mp21-rcc.h | 426 +++++++++++++++++++++ include/dt-bindings/reset/st,stm32mp21-rcc.h | 138 +++++++ 3 files changed, 763 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml create mode 100644 include/dt-bindings/clock/st,stm32mp21-rcc.h create mode 100644 include/dt-bindings/reset/st,stm32mp21-rcc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml new file mode 100644 index 000000000000..4368063c6709 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP21 Reset Clock Controller + +maintainers: + - Gabriel Fernandez + +description: | + The RCC hardware block is both a reset and a clock controller. + RCC makes also power management (resume/suspend). + + See also: + include/dt-bindings/clock/st,stm32mp21-rcc.h + include/dt-bindings/reset/st,stm32mp21-rcc.h + +properties: + compatible: + enum: + - st,stm32mp21-rcc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + clocks: + items: + - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz) + - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz) + - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz) + - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz) + - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz) + - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated) + - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock + - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock + - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock + - description: CK_SCMI_ICN_DDR DDR interconnect bus clock + - description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock + - description: CK_SCMI_ICN_HSL HSL interconnect bus clock + - description: CK_SCMI_ICN_NIC NIC interconnect bus clock + - description: CK_SCMI_FLEXGEN_07 flexgen clock 7 + - description: CK_SCMI_FLEXGEN_08 flexgen clock 8 + - description: CK_SCMI_FLEXGEN_09 flexgen clock 9 + - description: CK_SCMI_FLEXGEN_10 flexgen clock 10 + - description: CK_SCMI_FLEXGEN_11 flexgen clock 11 + - description: CK_SCMI_FLEXGEN_12 flexgen clock 12 + - description: CK_SCMI_FLEXGEN_13 flexgen clock 13 + - description: CK_SCMI_FLEXGEN_14 flexgen clock 14 + - description: CK_SCMI_FLEXGEN_16 flexgen clock 16 + - description: CK_SCMI_FLEXGEN_17 flexgen clock 17 + - description: CK_SCMI_FLEXGEN_18 flexgen clock 18 + - description: CK_SCMI_FLEXGEN_19 flexgen clock 19 + - description: CK_SCMI_FLEXGEN_20 flexgen clock 20 + - description: CK_SCMI_FLEXGEN_21 flexgen clock 21 + - description: CK_SCMI_FLEXGEN_22 flexgen clock 22 + - description: CK_SCMI_FLEXGEN_23 flexgen clock 23 + - description: CK_SCMI_FLEXGEN_24 flexgen clock 24 + - description: CK_SCMI_FLEXGEN_25 flexgen clock 25 + - description: CK_SCMI_FLEXGEN_26 flexgen clock 26 + - description: CK_SCMI_FLEXGEN_27 flexgen clock 27 + - description: CK_SCMI_FLEXGEN_29 flexgen clock 29 + - description: CK_SCMI_FLEXGEN_30 flexgen clock 30 + - description: CK_SCMI_FLEXGEN_31 flexgen clock 31 + - description: CK_SCMI_FLEXGEN_33 flexgen clock 33 + - description: CK_SCMI_FLEXGEN_36 flexgen clock 36 + - description: CK_SCMI_FLEXGEN_37 flexgen clock 37 + - description: CK_SCMI_FLEXGEN_38 flexgen clock 38 + - description: CK_SCMI_FLEXGEN_39 flexgen clock 39 + - description: CK_SCMI_FLEXGEN_40 flexgen clock 40 + - description: CK_SCMI_FLEXGEN_41 flexgen clock 41 + - description: CK_SCMI_FLEXGEN_42 flexgen clock 42 + - description: CK_SCMI_FLEXGEN_43 flexgen clock 43 + - description: CK_SCMI_FLEXGEN_44 flexgen clock 44 + - description: CK_SCMI_FLEXGEN_45 flexgen clock 45 + - description: CK_SCMI_FLEXGEN_46 flexgen clock 46 + - description: CK_SCMI_FLEXGEN_47 flexgen clock 47 + - description: CK_SCMI_FLEXGEN_48 flexgen clock 48 + - description: CK_SCMI_FLEXGEN_50 flexgen clock 50 + - description: CK_SCMI_FLEXGEN_51 flexgen clock 51 + - description: CK_SCMI_FLEXGEN_52 flexgen clock 52 + - description: CK_SCMI_FLEXGEN_53 flexgen clock 53 + - description: CK_SCMI_FLEXGEN_54 flexgen clock 54 + - description: CK_SCMI_FLEXGEN_55 flexgen clock 55 + - description: CK_SCMI_FLEXGEN_56 flexgen clock 56 + - description: CK_SCMI_FLEXGEN_57 flexgen clock 57 + - description: CK_SCMI_FLEXGEN_58 flexgen clock 58 + - description: CK_SCMI_FLEXGEN_61 flexgen clock 61 + - description: CK_SCMI_FLEXGEN_62 flexgen clock 62 + - description: CK_SCMI_FLEXGEN_63 flexgen clock 63 + - description: CK_SCMI_ICN_APB1 Peripheral bridge 1 + - description: CK_SCMI_ICN_APB2 Peripheral bridge 2 + - description: CK_SCMI_ICN_APB3 Peripheral bridge 3 + - description: CK_SCMI_ICN_APB4 Peripheral bridge 4 + - description: CK_SCMI_ICN_APB5 Peripheral bridge 5 + - description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug + - description: CK_SCMI_TIMG1 Peripheral bridge for timer1 + - description: CK_SCMI_TIMG2 Peripheral bridge for timer2 + + access-controllers: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - clocks + +additionalProperties: false + +examples: + - | + #include + + clock-controller@44200000 { + compatible = "st,stm32mp21-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APB5>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>; + }; +... diff --git a/include/dt-bindings/clock/st,stm32mp21-rcc.h b/include/dt-bindings/clock/st,stm32mp21-rcc.h new file mode 100644 index 000000000000..054b785f2796 --- /dev/null +++ b/include/dt-bindings/clock/st,stm32mp21-rcc.h @@ -0,0 +1,426 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Gabriel Fernandez + */ + +#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_ +#define _DT_BINDINGS_STM32MP21_CLKS_H_ + +/* INTERNAL/EXTERNAL OSCILLATORS */ +#define HSI_CK 0 +#define HSE_CK 1 +#define MSI_CK 2 +#define LSI_CK 3 +#define LSE_CK 4 +#define I2S_CK 5 +#define RTC_CK 6 +#define SPDIF_CK_SYMB 7 + +/* PLL CLOCKS */ +#define PLL1_CK 8 +#define PLL2_CK 9 +#define PLL4_CK 10 +#define PLL5_CK 11 +#define PLL6_CK 12 +#define PLL7_CK 13 +#define PLL8_CK 14 + +#define CK_CPU1 15 + +/* APB DIV CLOCKS */ +#define CK_ICN_APB1 16 +#define CK_ICN_APB2 17 +#define CK_ICN_APB3 18 +#define CK_ICN_APB4 19 +#define CK_ICN_APB5 20 +#define CK_ICN_APBDBG 21 + +/* GLOBAL TIMER */ +#define TIMG1_CK 22 +#define TIMG2_CK 23 + +/* FLEXGEN CLOCKS */ +#define CK_ICN_HS_MCU 24 +#define CK_ICN_SDMMC 25 +#define CK_ICN_DDR 26 +#define CK_ICN_DISPLAY 27 +#define CK_ICN_HSL 28 +#define CK_ICN_NIC 29 +#define CK_ICN_VID 30 +#define CK_FLEXGEN_07 31 +#define CK_FLEXGEN_08 32 +#define CK_FLEXGEN_09 33 +#define CK_FLEXGEN_10 34 +#define CK_FLEXGEN_11 35 +#define CK_FLEXGEN_12 36 +#define CK_FLEXGEN_13 37 +#define CK_FLEXGEN_14 38 +#define CK_FLEXGEN_15 39 +#define CK_FLEXGEN_16 40 +#define CK_FLEXGEN_17 41 +#define CK_FLEXGEN_18 42 +#define CK_FLEXGEN_19 43 +#define CK_FLEXGEN_20 44 +#define CK_FLEXGEN_21 45 +#define CK_FLEXGEN_22 46 +#define CK_FLEXGEN_23 47 +#define CK_FLEXGEN_24 48 +#define CK_FLEXGEN_25 49 +#define CK_FLEXGEN_26 50 +#define CK_FLEXGEN_27 51 +#define CK_FLEXGEN_28 52 +#define CK_FLEXGEN_29 53 +#define CK_FLEXGEN_30 54 +#define CK_FLEXGEN_31 55 +#define CK_FLEXGEN_32 56 +#define CK_FLEXGEN_33 57 +#define CK_FLEXGEN_34 58 +#define CK_FLEXGEN_35 59 +#define CK_FLEXGEN_36 60 +#define CK_FLEXGEN_37 61 +#define CK_FLEXGEN_38 62 +#define CK_FLEXGEN_39 63 +#define CK_FLEXGEN_40 64 +#define CK_FLEXGEN_41 65 +#define CK_FLEXGEN_42 66 +#define CK_FLEXGEN_43 67 +#define CK_FLEXGEN_44 68 +#define CK_FLEXGEN_45 69 +#define CK_FLEXGEN_46 70 +#define CK_FLEXGEN_47 71 +#define CK_FLEXGEN_48 72 +#define CK_FLEXGEN_49 73 +#define CK_FLEXGEN_50 74 +#define CK_FLEXGEN_51 75 +#define CK_FLEXGEN_52 76 +#define CK_FLEXGEN_53 77 +#define CK_FLEXGEN_54 78 +#define CK_FLEXGEN_55 79 +#define CK_FLEXGEN_56 80 +#define CK_FLEXGEN_57 81 +#define CK_FLEXGEN_58 82 +#define CK_FLEXGEN_59 83 +#define CK_FLEXGEN_60 84 +#define CK_FLEXGEN_61 85 +#define CK_FLEXGEN_62 86 +#define CK_FLEXGEN_63 87 + +/* LOW SPEED MCU CLOCK */ +#define CK_ICN_LS_MCU 88 + +#define CK_BUS_STM 89 +#define CK_BUS_FMC 90 +#define CK_BUS_ETH1 91 +#define CK_BUS_ETH2 92 +#define CK_BUS_DDRPHYC 93 +#define CK_BUS_SYSCPU1 94 +#define CK_BUS_HPDMA1 95 +#define CK_BUS_HPDMA2 96 +#define CK_BUS_HPDMA3 97 +#define CK_BUS_ADC1 98 +#define CK_BUS_ADC2 99 +#define CK_BUS_IPCC1 100 +#define CK_BUS_DCMIPSSI 101 +#define CK_BUS_CRC 102 +#define CK_BUS_MDF1 103 +#define CK_BUS_BKPSRAM 104 +#define CK_BUS_HASH1 105 +#define CK_BUS_HASH2 106 +#define CK_BUS_RNG1 107 +#define CK_BUS_RNG2 108 +#define CK_BUS_CRYP1 109 +#define CK_BUS_CRYP2 110 +#define CK_BUS_SAES 111 +#define CK_BUS_PKA 112 +#define CK_BUS_GPIOA 113 +#define CK_BUS_GPIOB 114 +#define CK_BUS_GPIOC 115 +#define CK_BUS_GPIOD 116 +#define CK_BUS_GPIOE 117 +#define CK_BUS_GPIOF 118 +#define CK_BUS_GPIOG 119 +#define CK_BUS_GPIOH 120 +#define CK_BUS_GPIOI 121 +#define CK_BUS_GPIOZ 122 +#define CK_BUS_RTC 124 +#define CK_BUS_LPUART1 125 +#define CK_BUS_LPTIM3 126 +#define CK_BUS_LPTIM4 127 +#define CK_BUS_LPTIM5 128 +#define CK_BUS_TIM2 129 +#define CK_BUS_TIM3 130 +#define CK_BUS_TIM4 131 +#define CK_BUS_TIM5 132 +#define CK_BUS_TIM6 133 +#define CK_BUS_TIM7 134 +#define CK_BUS_TIM10 135 +#define CK_BUS_TIM11 136 +#define CK_BUS_TIM12 137 +#define CK_BUS_TIM13 138 +#define CK_BUS_TIM14 139 +#define CK_BUS_LPTIM1 140 +#define CK_BUS_LPTIM2 141 +#define CK_BUS_SPI2 142 +#define CK_BUS_SPI3 143 +#define CK_BUS_SPDIFRX 144 +#define CK_BUS_USART2 145 +#define CK_BUS_USART3 146 +#define CK_BUS_UART4 147 +#define CK_BUS_UART5 148 +#define CK_BUS_I2C1 149 +#define CK_BUS_I2C2 150 +#define CK_BUS_I2C3 151 +#define CK_BUS_I3C1 152 +#define CK_BUS_I3C2 153 +#define CK_BUS_I3C3 154 +#define CK_BUS_TIM1 155 +#define CK_BUS_TIM8 156 +#define CK_BUS_TIM15 157 +#define CK_BUS_TIM16 158 +#define CK_BUS_TIM17 159 +#define CK_BUS_SAI1 160 +#define CK_BUS_SAI2 161 +#define CK_BUS_SAI3 162 +#define CK_BUS_SAI4 163 +#define CK_BUS_USART1 164 +#define CK_BUS_USART6 165 +#define CK_BUS_UART7 166 +#define CK_BUS_FDCAN 167 +#define CK_BUS_SPI1 168 +#define CK_BUS_SPI4 169 +#define CK_BUS_SPI5 170 +#define CK_BUS_SPI6 171 +#define CK_BUS_BSEC 172 +#define CK_BUS_IWDG1 173 +#define CK_BUS_IWDG2 174 +#define CK_BUS_IWDG3 175 +#define CK_BUS_IWDG4 176 +#define CK_BUS_WWDG1 177 +#define CK_BUS_VREF 178 +#define CK_BUS_DTS 179 +#define CK_BUS_SERC 180 +#define CK_BUS_HDP 181 +#define CK_BUS_DDRPERFM 182 +#define CK_BUS_OTG 183 +#define CK_BUS_LTDC 184 +#define CK_BUS_CSI 185 +#define CK_BUS_DCMIPP 186 +#define CK_BUS_DDRC 187 +#define CK_BUS_DDRCFG 188 +#define CK_BUS_STGEN 189 +#define CK_SYSDBG 190 +#define CK_KER_TIM2 191 +#define CK_KER_TIM3 192 +#define CK_KER_TIM4 193 +#define CK_KER_TIM5 194 +#define CK_KER_TIM6 195 +#define CK_KER_TIM7 196 +#define CK_KER_TIM10 197 +#define CK_KER_TIM11 198 +#define CK_KER_TIM12 199 +#define CK_KER_TIM13 200 +#define CK_KER_TIM14 201 +#define CK_KER_TIM1 202 +#define CK_KER_TIM8 203 +#define CK_KER_TIM15 204 +#define CK_KER_TIM16 205 +#define CK_KER_TIM17 206 +#define CK_BUS_SYSRAM 207 +#define CK_BUS_RETRAM 208 +#define CK_BUS_OSPI1 209 +#define CK_BUS_OTFD1 210 +#define CK_BUS_SRAM1 211 +#define CK_BUS_SDMMC1 212 +#define CK_BUS_SDMMC2 213 +#define CK_BUS_SDMMC3 214 +#define CK_BUS_DDR 215 +#define CK_BUS_RISAF4 216 +#define CK_BUS_USBHOHCI 217 +#define CK_BUS_USBHEHCI 218 +#define CK_KER_LPTIM1 219 +#define CK_KER_LPTIM2 220 +#define CK_KER_USART2 221 +#define CK_KER_UART4 222 +#define CK_KER_USART3 223 +#define CK_KER_UART5 224 +#define CK_KER_SPI2 225 +#define CK_KER_SPI3 226 +#define CK_KER_SPDIFRX 227 +#define CK_KER_I2C1 228 +#define CK_KER_I2C2 229 +#define CK_KER_I3C1 230 +#define CK_KER_I3C2 231 +#define CK_KER_I2C3 232 +#define CK_KER_I3C3 233 +#define CK_KER_SPI1 234 +#define CK_KER_SPI4 235 +#define CK_KER_SPI5 236 +#define CK_KER_SPI6 237 +#define CK_KER_USART1 238 +#define CK_KER_USART6 239 +#define CK_KER_UART7 240 +#define CK_KER_MDF1 241 +#define CK_KER_SAI1 242 +#define CK_KER_SAI2 243 +#define CK_KER_SAI3 244 +#define CK_KER_SAI4 245 +#define CK_KER_FDCAN 246 +#define CK_KER_CSI 247 +#define CK_KER_CSITXESC 248 +#define CK_KER_CSIPHY 249 +#define CK_KER_STGEN 250 +#define CK_KER_USB2PHY2EN 251 +#define CK_KER_LPUART1 252 +#define CK_KER_LPTIM3 253 +#define CK_KER_LPTIM4 254 +#define CK_KER_LPTIM5 255 +#define CK_KER_TSDBG 256 +#define CK_KER_TPIU 257 +#define CK_BUS_ETR 258 +#define CK_BUS_SYSATB 259 +#define CK_KER_ADC1 260 +#define CK_KER_ADC2 261 +#define CK_KER_OSPI1 262 +#define CK_KER_FMC 263 +#define CK_KER_SDMMC1 264 +#define CK_KER_SDMMC2 265 +#define CK_KER_SDMMC3 266 +#define CK_KER_ETH1 267 +#define CK_KER_ETH2 268 +#define CK_KER_ETH1PTP 269 +#define CK_KER_ETH2PTP 270 +#define CK_KER_USB2PHY1 271 +#define CK_KER_USB2PHY2 272 +#define CK_MCO1 273 +#define CK_MCO2 274 +#define CK_KER_DTS 275 +#define CK_ETH1_RX 276 +#define CK_ETH1_TX 277 +#define CK_ETH1_MAC 278 +#define CK_ETH2_RX 279 +#define CK_ETH2_TX 280 +#define CK_ETH2_MAC 281 +#define CK_ETH1_STP 282 +#define CK_ETH2_STP 283 +#define CK_KER_LTDC 284 +#define HSE_DIV2_CK 285 +#define CK_DBGMCU 286 +#define CK_DAP 287 +#define CK_KER_ETR 288 +#define CK_KER_STM 289 + +#define CK_SCMI_ICN_HS_MCU 0 +#define CK_SCMI_ICN_SDMMC 1 +#define CK_SCMI_ICN_DDR 2 +#define CK_SCMI_ICN_DISPLAY 3 +#define CK_SCMI_ICN_HSL 4 +#define CK_SCMI_ICN_NIC 5 +#define CK_SCMI_FLEXGEN_07 7 +#define CK_SCMI_FLEXGEN_08 8 +#define CK_SCMI_FLEXGEN_09 9 +#define CK_SCMI_FLEXGEN_10 10 +#define CK_SCMI_FLEXGEN_11 11 +#define CK_SCMI_FLEXGEN_12 12 +#define CK_SCMI_FLEXGEN_13 13 +#define CK_SCMI_FLEXGEN_14 14 +#define CK_SCMI_FLEXGEN_15 15 +#define CK_SCMI_FLEXGEN_16 16 +#define CK_SCMI_FLEXGEN_17 17 +#define CK_SCMI_FLEXGEN_18 18 +#define CK_SCMI_FLEXGEN_19 19 +#define CK_SCMI_FLEXGEN_20 20 +#define CK_SCMI_FLEXGEN_21 21 +#define CK_SCMI_FLEXGEN_22 22 +#define CK_SCMI_FLEXGEN_23 23 +#define CK_SCMI_FLEXGEN_24 24 +#define CK_SCMI_FLEXGEN_25 25 +#define CK_SCMI_FLEXGEN_26 26 +#define CK_SCMI_FLEXGEN_27 27 +#define CK_SCMI_FLEXGEN_28 28 +#define CK_SCMI_FLEXGEN_29 29 +#define CK_SCMI_FLEXGEN_30 30 +#define CK_SCMI_FLEXGEN_31 31 +#define CK_SCMI_FLEXGEN_32 32 +#define CK_SCMI_FLEXGEN_33 33 +#define CK_SCMI_FLEXGEN_34 34 +#define CK_SCMI_FLEXGEN_35 35 +#define CK_SCMI_FLEXGEN_36 36 +#define CK_SCMI_FLEXGEN_37 37 +#define CK_SCMI_FLEXGEN_38 38 +#define CK_SCMI_FLEXGEN_39 39 +#define CK_SCMI_FLEXGEN_40 40 +#define CK_SCMI_FLEXGEN_41 41 +#define CK_SCMI_FLEXGEN_42 42 +#define CK_SCMI_FLEXGEN_43 43 +#define CK_SCMI_FLEXGEN_44 44 +#define CK_SCMI_FLEXGEN_45 45 +#define CK_SCMI_FLEXGEN_46 46 +#define CK_SCMI_FLEXGEN_47 47 +#define CK_SCMI_FLEXGEN_48 48 +#define CK_SCMI_FLEXGEN_49 49 +#define CK_SCMI_FLEXGEN_50 50 +#define CK_SCMI_FLEXGEN_51 51 +#define CK_SCMI_FLEXGEN_52 52 +#define CK_SCMI_FLEXGEN_53 53 +#define CK_SCMI_FLEXGEN_54 54 +#define CK_SCMI_FLEXGEN_55 55 +#define CK_SCMI_FLEXGEN_56 56 +#define CK_SCMI_FLEXGEN_57 57 +#define CK_SCMI_FLEXGEN_58 58 +#define CK_SCMI_FLEXGEN_59 59 +#define CK_SCMI_FLEXGEN_60 60 +#define CK_SCMI_FLEXGEN_61 61 +#define CK_SCMI_FLEXGEN_62 62 +#define CK_SCMI_FLEXGEN_63 63 +#define CK_SCMI_ICN_LS_MCU 64 +#define CK_SCMI_HSE 65 +#define CK_SCMI_LSE 66 +#define CK_SCMI_HSI 67 +#define CK_SCMI_LSI 68 +#define CK_SCMI_MSI 69 +#define CK_SCMI_HSE_DIV2 70 +#define CK_SCMI_CPU1 71 +#define CK_SCMI_SYSCPU1 72 +#define CK_SCMI_PLL2 73 +#define CK_SCMI_RTC 74 +#define CK_SCMI_RTCCK 75 +#define CK_SCMI_ICN_APB1 76 +#define CK_SCMI_ICN_APB2 77 +#define CK_SCMI_ICN_APB3 78 +#define CK_SCMI_ICN_APB4 79 +#define CK_SCMI_ICN_APB5 80 +#define CK_SCMI_ICN_APBDBG 81 +#define CK_SCMI_TIMG1 82 +#define CK_SCMI_TIMG2 83 +#define CK_SCMI_BKPSRAM 84 +#define CK_SCMI_BSEC 85 +#define CK_SCMI_BUS_ETR 86 +#define CK_SCMI_FMC 87 +#define CK_SCMI_GPIOA 88 +#define CK_SCMI_GPIOB 89 +#define CK_SCMI_GPIOC 90 +#define CK_SCMI_GPIOD 91 +#define CK_SCMI_GPIOE 92 +#define CK_SCMI_GPIOF 93 +#define CK_SCMI_GPIOG 94 +#define CK_SCMI_GPIOH 95 +#define CK_SCMI_GPIOI 96 +#define CK_SCMI_GPIOZ 97 +#define CK_SCMI_HPDMA1 98 +#define CK_SCMI_HPDMA2 99 +#define CK_SCMI_HPDMA3 100 +#define CK_SCMI_IPCC1 101 +#define CK_SCMI_RETRAM 102 +#define CK_SCMI_SRAM1 103 +#define CK_SCMI_SYSRAM 104 +#define CK_SCMI_OSPI1 105 +#define CK_SCMI_TPIU 106 +#define CK_SCMI_SYSDBG 107 +#define CK_SCMI_SYSATB 108 +#define CK_SCMI_TSDBG 109 +#define CK_SCMI_BUS_STM 110 +#define CK_SCMI_KER_STM 111 +#define CK_SCMI_KER_ETR 112 + +#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */ diff --git a/include/dt-bindings/reset/st,stm32mp21-rcc.h b/include/dt-bindings/reset/st,stm32mp21-rcc.h new file mode 100644 index 000000000000..6463bd73d025 --- /dev/null +++ b/include/dt-bindings/reset/st,stm32mp21-rcc.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Gabriel Fernandez + */ + +#ifndef _DT_BINDINGS_STM32MP21_RESET_H_ +#define _DT_BINDINGS_STM32MP21_RESET_H_ + +#define TIM1_R 0 +#define TIM2_R 1 +#define TIM3_R 2 +#define TIM4_R 3 +#define TIM5_R 4 +#define TIM6_R 5 +#define TIM7_R 6 +#define TIM8_R 7 +#define TIM10_R 8 +#define TIM11_R 9 +#define TIM12_R 10 +#define TIM13_R 11 +#define TIM14_R 12 +#define TIM15_R 13 +#define TIM16_R 14 +#define TIM17_R 15 +#define LPTIM1_R 16 +#define LPTIM2_R 17 +#define LPTIM3_R 18 +#define LPTIM4_R 19 +#define LPTIM5_R 20 +#define SPI1_R 21 +#define SPI2_R 22 +#define SPI3_R 23 +#define SPI4_R 24 +#define SPI5_R 25 +#define SPI6_R 26 +#define SPDIFRX_R 27 +#define USART1_R 28 +#define USART2_R 29 +#define USART3_R 30 +#define UART4_R 31 +#define UART5_R 32 +#define USART6_R 33 +#define UART7_R 34 +#define LPUART1_R 35 +#define I2C1_R 36 +#define I2C2_R 37 +#define I2C3_R 38 +#define SAI1_R 39 +#define SAI2_R 40 +#define SAI3_R 41 +#define SAI4_R 42 +#define MDF1_R 43 +#define FDCAN_R 44 +#define HDP_R 45 +#define ADC1_R 46 +#define ADC2_R 47 +#define ETH1_R 48 +#define ETH2_R 49 +#define USBH_R 50 +#define USB2PHY1_R 51 +#define USB2PHY2_R 52 +#define SDMMC1_R 53 +#define SDMMC1DLL_R 54 +#define SDMMC2_R 55 +#define SDMMC2DLL_R 56 +#define SDMMC3_R 57 +#define SDMMC3DLL_R 58 +#define LTDC_R 59 +#define CSI_R 60 +#define DCMIPP_R 61 +#define DCMIPSSI_R 62 +#define WWDG1_R 63 +#define VREF_R 64 +#define DTS_R 65 +#define CRC_R 66 +#define SERC_R 67 +#define I3C1_R 68 +#define I3C2_R 69 +#define I3C3_R 70 +#define IWDG2_KER_R 71 +#define IWDG4_KER_R 72 +#define RNG1_R 73 +#define RNG2_R 74 +#define PKA_R 75 +#define SAES_R 76 +#define HASH1_R 77 +#define HASH2_R 78 +#define CRYP1_R 79 +#define CRYP2_R 80 +#define OSPI1_R 81 +#define OSPI1DLL_R 82 +#define OTG_R 83 +#define FMC_R 84 +#define DBG_R 85 +#define GPIOA_R 86 +#define GPIOB_R 87 +#define GPIOC_R 88 +#define GPIOD_R 89 +#define GPIOE_R 90 +#define GPIOF_R 91 +#define GPIOG_R 92 +#define GPIOH_R 93 +#define GPIOI_R 94 +#define GPIOZ_R 95 +#define HPDMA1_R 96 +#define HPDMA2_R 97 +#define HPDMA3_R 98 +#define IPCC1_R 99 +#define C2_HOLDBOOT_R 100 +#define C1_HOLDBOOT_R 101 +#define C1_R 102 +#define C1P1POR_R 103 +#define C1P1_R 104 +#define C2_R 105 +#define SYS_R 106 +#define VSW_R 107 +#define C1MS_R 108 +#define DDRCP_R 109 +#define DDRCAPB_R 110 +#define DDRPHYCAPB_R 111 +#define DDRCFG_R 112 +#define DDR_R 113 +#define DDRPERFM_R 114 +#define IWDG1_SYS_R 116 +#define IWDG2_SYS_R 117 +#define IWDG3_SYS_R 118 +#define IWDG4_SYS_R 119 + +#define RST_SCMI_C1_R 0 +#define RST_SCMI_C2_R 1 +#define RST_SCMI_C1_HOLDBOOT_R 2 +#define RST_SCMI_C2_HOLDBOOT_R 3 +#define RST_SCMI_FMC 4 +#define RST_SCMI_OSPI1 5 +#define RST_SCMI_OSPI1DLL 6 + +#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */ -- cgit v1.2.3 From 099760708aa37737663086ce28145f8d386564f3 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 25 Jun 2025 11:07:26 +0200 Subject: dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings - drop minItems from access-controllers - remove rcc label from example - fixes typos - remove double '::' from 'See also::' Acked-by: Conor Dooley Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/st,stm32mp25-rcc.yaml | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml index 88e52f10d1ec..1e3b5d218bb0 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml @@ -11,9 +11,9 @@ maintainers: description: | The RCC hardware block is both a reset and a clock controller. - RCC makes also power management (resume/supend). + RCC makes also power management (resume/suspend). - See also:: + See also: include/dt-bindings/clock/st,stm32mp25-rcc.h include/dt-bindings/reset/st,stm32mp25-rcc.h @@ -38,7 +38,7 @@ properties: - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz) - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz) - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz) - - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated) + - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated) - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock @@ -108,15 +108,14 @@ properties: - description: CK_SCMI_ICN_APB2 Peripheral bridge 2 - description: CK_SCMI_ICN_APB3 Peripheral bridge 3 - description: CK_SCMI_ICN_APB4 Peripheral bridge 4 - - description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub + - description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug - description: CK_SCMI_TIMG1 Peripheral bridge for timer1 - description: CK_SCMI_TIMG2 Peripheral bridge for timer2 - description: CK_SCMI_PLL3 PLL3 clock - description: clk_dsi_txbyte DSI byte clock access-controllers: - minItems: 1 - maxItems: 2 + maxItems: 1 required: - compatible @@ -131,7 +130,7 @@ examples: - | #include - rcc: clock-controller@44200000 { + clock-controller@44200000 { compatible = "st,stm32mp25-rcc"; reg = <0x44200000 0x10000>; #clock-cells = <1>; -- cgit v1.2.3 From b92ef17f0c0b9ba8d913b092deee4d2914526007 Mon Sep 17 00:00:00 2001 From: André Draszik Date: Wed, 30 Jul 2025 10:31:34 +0100 Subject: dt-bindings: clock: samsung,s2mps11: add s2mpg10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Samsung S2MPG10 clock controller is similar to the existing clock controllers supported by this binding. Register offsets / layout are slightly different, so it needs its own compatible. Acked-by: Stephen Boyd Acked-by: Rob Herring (Arm) Signed-off-by: André Draszik Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml b/Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml index d5296e6053a1..91d455155a60 100644 --- a/Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml @@ -25,6 +25,7 @@ description: | properties: compatible: enum: + - samsung,s2mpg10-clk - samsung,s2mps11-clk - samsung,s2mps13-clk # S2MPS13 and S2MPS15 - samsung,s2mps14-clk -- cgit v1.2.3 From 793e6b74806eea39da26f2fb7e4b640608d9598d Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Fri, 19 Sep 2025 14:26:42 +0000 Subject: dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible Document the clock controller shipped in Loongson-2K0300 SoC, which generates various clock signals for SoC peripherals. Differing from previous generations of SoCs, LS2K0300 requires a 120MHz external clock input. Signed-off-by: Yao Zi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Yanteng Si Signed-off-by: Stephen Boyd --- .../bindings/clock/loongson,ls2k-clk.yaml | 18 +++++++++-- include/dt-bindings/clock/loongson,ls2k-clk.h | 36 ++++++++++++++++++++++ 2 files changed, 51 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml index 4f79cdb417ab..c07ad1f85857 100644 --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - loongson,ls2k0300-clk - loongson,ls2k0500-clk - loongson,ls2k-clk # This is for Loongson-2K1000 - loongson,ls2k2000-clk @@ -24,8 +25,7 @@ properties: maxItems: 1 clocks: - items: - - description: 100m ref + maxItems: 1 clock-names: items: @@ -38,11 +38,23 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h for the full list of Loongson-2 SoC clock IDs. +allOf: + - if: + properties: + compatible: + contains: + const: loongson,ls2k0300-clk + then: + properties: + clock-names: false + else: + required: + - clock-names + required: - compatible - reg - clocks - - clock-names - '#clock-cells' additionalProperties: false diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h index 4279ba595f1e..8cbb86b2cf1e 100644 --- a/include/dt-bindings/clock/loongson,ls2k-clk.h +++ b/include/dt-bindings/clock/loongson,ls2k-clk.h @@ -43,4 +43,40 @@ #define LOONGSON2_I2S_CLK 33 #define LOONGSON2_MISC_CLK 34 +#define LS2K0300_CLK_STABLE 0 +#define LS2K0300_NODE_PLL 1 +#define LS2K0300_DDR_PLL 2 +#define LS2K0300_PIX_PLL 3 +#define LS2K0300_CLK_THSENS 4 +#define LS2K0300_CLK_NODE_DIV 5 +#define LS2K0300_CLK_NODE_PLL_GATE 6 +#define LS2K0300_CLK_NODE_SCALE 7 +#define LS2K0300_CLK_NODE_GATE 8 +#define LS2K0300_CLK_GMAC_DIV 9 +#define LS2K0300_CLK_GMAC_GATE 10 +#define LS2K0300_CLK_I2S_DIV 11 +#define LS2K0300_CLK_I2S_SCALE 12 +#define LS2K0300_CLK_I2S_GATE 13 +#define LS2K0300_CLK_DDR_DIV 14 +#define LS2K0300_CLK_DDR_GATE 15 +#define LS2K0300_CLK_NET_DIV 16 +#define LS2K0300_CLK_NET_GATE 17 +#define LS2K0300_CLK_DEV_DIV 18 +#define LS2K0300_CLK_DEV_GATE 19 +#define LS2K0300_CLK_PIX_DIV 20 +#define LS2K0300_CLK_PIX_PLL_GATE 21 +#define LS2K0300_CLK_PIX_SCALE 22 +#define LS2K0300_CLK_PIX_GATE 23 +#define LS2K0300_CLK_GMACBP_DIV 24 +#define LS2K0300_CLK_GMACBP_GATE 25 +#define LS2K0300_CLK_USB_SCALE 26 +#define LS2K0300_CLK_USB_GATE 27 +#define LS2K0300_CLK_APB_SCALE 28 +#define LS2K0300_CLK_APB_GATE 29 +#define LS2K0300_CLK_BOOT_SCALE 30 +#define LS2K0300_CLK_BOOT_GATE 31 +#define LS2K0300_CLK_SDIO_SCALE 32 +#define LS2K0300_CLK_SDIO_GATE 33 +#define LS2K0300_CLK_GMAC_IN 34 + #endif -- cgit v1.2.3 From 9cf5b8b69bfccf3d98d31f640244437a452daa80 Mon Sep 17 00:00:00 2001 From: Baojun Xu Date: Sat, 20 Sep 2025 14:20:44 +0800 Subject: ASoC: tas2781: Correct the wrong description and register address on tas2781 Correct the wrong description for TAS257X. Combined TAS5825 with TAS2563, as they use the same register address and number. Correct the register address and number for TAS5827. Fixes: 7095d688de38 ("ASoC: tas2781: Add tas2118, tas2x20, tas5825 support") Signed-off-by: Baojun Xu Acked-by: Mark Brown Signed-off-by: Takashi Iwai --- .../devicetree/bindings/sound/ti,tas2781.yaml | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ti,tas2781.yaml b/Documentation/devicetree/bindings/sound/ti,tas2781.yaml index 011211112be4..bd00afa47d62 100644 --- a/Documentation/devicetree/bindings/sound/ti,tas2781.yaml +++ b/Documentation/devicetree/bindings/sound/ti,tas2781.yaml @@ -11,11 +11,13 @@ maintainers: - Shenghao Ding description: | - The TAS2118/TAS2X20/TAS257x is mono, digital input Class-D audio + The TAS2118/TAS2X20 is mono, digital input Class-D audio amplifier optimized for efficiently driving high peak power into small loudspeakers. - Integrated speaker voltage and current sense provides for - real time monitoring of loudspeaker behavior. + The TAS257x is mono, digital input Class-D audio amplifier optimized + for efficiently driving high peak power into small loudspeakers. + Integrated speaker voltage and current sense provides for real time + monitoring of loudspeaker behavior. The TAS2563/TAS2781 is a mono, digital input Class-D audio amplifier optimized for efficiently driving high peak power into small loudspeakers. An integrated on-chip DSP supports Texas @@ -25,9 +27,7 @@ description: | The TAS5825/TAS5827 is a stereo, digital input Class-D audio amplifier optimized for efficiently driving high peak power into small loudspeakers. An integrated on-chip DSP supports Texas - Instruments Smart Amp speaker protection algorithm. The - integrated speaker voltage and current sense provides for real time - monitoring of loudspeaker behavior. + Instruments Smart Amp speaker protection algorithm. Specifications about the audio amplifier can be found at: https://www.ti.com/lit/gpn/tas2120 @@ -131,6 +131,7 @@ allOf: contains: enum: - ti,tas2563 + - ti,tas5825 then: properties: reg: @@ -181,15 +182,14 @@ allOf: compatible: contains: enum: - - ti,tas5825 - ti,tas5827 then: properties: reg: - maxItems: 4 + maxItems: 6 items: - minimum: 0x4c - maximum: 0x4f + minimum: 0x60 + maximum: 0x65 additionalProperties: false -- cgit v1.2.3 From f8673e4069b2032bf9f854bae818a7bdbdca7520 Mon Sep 17 00:00:00 2001 From: Stefan Binding Date: Wed, 17 Sep 2025 16:37:11 +0100 Subject: ASoC: dt-bindings: cirrus,cs35l41: Document the cirrus,subsystem-id property Add new property: cirrus,subsystem-id This new property is used to uniquely identify the system if device tree is used, to allow the driver to select the correct firmware and tuning for the system. The DSP driver searches for a compatible firmware (and tuning) based on what it is able to read from the hardware. However, the SSID is based on the system, and cannot be read from the hardware, therefore it needs to be read from the Device Tree. On ACPI-based systems, it is able to read this from the ACPI _SUB property, and to maintain compatibility with the driver between ACPI and Device Tree systems we need an equivalent property. Signed-off-by: Stefan Binding Link: https://patch.msgid.link/20250917153722.94978-2-sbinding@opensource.cirrus.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml index 14dea1feefc5..e6cf2ebcd777 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml @@ -151,6 +151,12 @@ properties: minimum: 0 maximum: 5 + cirrus,subsystem-id: + $ref: /schemas/types.yaml#/definitions/string + description: + Subsystem ID. If this property is present, it sets the system name, + used to identify the firmware and tuning to load. + required: - compatible - reg -- cgit v1.2.3 From f145845d8348c9b6288df41cb7904fd9fde566dc Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 19 Sep 2025 17:35:31 -0500 Subject: dt-bindings: ata: apm,xgene-ahci: Add apm,xgene-ahci-v2 support The "apm,xgene-ahci-v2" compatible has been in use for a long time, but was undocumented. It doesn't require clocks or phys. Remove the "apm,xgene-ahci-pcie" compatible which isn't used anywhere while we're here. Signed-off-by: Rob Herring (Arm) Signed-off-by: Damien Le Moal --- .../devicetree/bindings/ata/apm,xgene-ahci.yaml | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml b/Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml index 7dc942808656..dc631381f9e1 100644 --- a/Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml +++ b/Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml @@ -9,14 +9,11 @@ title: APM X-Gene 6.0 Gb/s SATA host controller maintainers: - Rob Herring -allOf: - - $ref: ahci-common.yaml# - properties: compatible: enum: - apm,xgene-ahci - - apm,xgene-ahci-pcie + - apm,xgene-ahci-v2 reg: minItems: 4 @@ -35,12 +32,22 @@ properties: required: - compatible - - clocks - - phys - - phy-names unevaluatedProperties: false +allOf: + - $ref: ahci-common.yaml# + - if: + properties: + compatible: + contains: + const: apm,xgene-ahci + then: + required: + - clocks + - phys + - phy-names + examples: - | sata@1a400000 { -- cgit v1.2.3 From 6bd5b7297c95e6982cf0aee192431156681a1cdd Mon Sep 17 00:00:00 2001 From: "Bastien Curutchet (Schneider Electric)" Date: Thu, 18 Sep 2025 10:33:50 +0200 Subject: dt-bindings: net: dsa: microchip: Group if clause under allOf tag Upcoming patch adds a new if/then clause. It requires to be grouped with the already existing if/then clause under an 'allOf:' tag. Move the if/then clause under the already existing 'allOf:' tag to prepare next patch. Acked-by: Rob Herring (Arm) Signed-off-by: Bastien Curutchet (Schneider Electric) Link: https://patch.msgid.link/20250918-ksz-strap-pins-v3-1-16662e881728@bootlin.com Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/dsa/microchip,ksz.yaml | 68 +++++++++++----------- 1 file changed, 34 insertions(+), 34 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index eb4607460db7..db8175b4ced6 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -10,9 +10,6 @@ maintainers: - Marek Vasut - Woojung Huh -allOf: - - $ref: /schemas/spi/spi-peripheral-props.yaml# - properties: # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional # required and optional properties. @@ -107,38 +104,41 @@ required: - compatible - reg -if: - not: - properties: - compatible: - enum: - - microchip,ksz8863 - - microchip,ksz8873 -then: - $ref: dsa.yaml#/$defs/ethernet-ports -else: - patternProperties: - "^(ethernet-)?ports$": +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + + - if: + not: + properties: + compatible: + enum: + - microchip,ksz8863 + - microchip,ksz8873 + then: + $ref: dsa.yaml#/$defs/ethernet-ports + else: patternProperties: - "^(ethernet-)?port@[0-2]$": - $ref: dsa-port.yaml# - unevaluatedProperties: false - properties: - microchip,rmii-clk-internal: - $ref: /schemas/types.yaml#/definitions/flag - description: - When ksz88x3 is acting as clock provier (via REFCLKO) it - can select between internal and external RMII reference - clock. Internal reference clock means that the clock for - the RMII of ksz88x3 is provided by the ksz88x3 internally - and the REFCLKI pin is unconnected. For the external - reference clock, the clock needs to be fed back to ksz88x3 - via REFCLKI. - If microchip,rmii-clk-internal is set, ksz88x3 will provide - rmii reference clock internally, otherwise reference clock - should be provided externally. - dependencies: - microchip,rmii-clk-internal: [ethernet] + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-2]$": + $ref: dsa-port.yaml# + unevaluatedProperties: false + properties: + microchip,rmii-clk-internal: + $ref: /schemas/types.yaml#/definitions/flag + description: + When ksz88x3 is acting as clock provier (via REFCLKO) it + can select between internal and external RMII reference + clock. Internal reference clock means that the clock for + the RMII of ksz88x3 is provided by the ksz88x3 internally + and the REFCLKI pin is unconnected. For the external + reference clock, the clock needs to be fed back to ksz88x3 + via REFCLKI. + If microchip,rmii-clk-internal is set, ksz88x3 will provide + rmii reference clock internally, otherwise reference clock + should be provided externally. + dependencies: + microchip,rmii-clk-internal: [ethernet] unevaluatedProperties: false -- cgit v1.2.3 From e469b87e0fb0d1209edb6c291474b1a1afa45bd5 Mon Sep 17 00:00:00 2001 From: "Bastien Curutchet (Schneider Electric)" Date: Thu, 18 Sep 2025 10:33:51 +0200 Subject: dt-bindings: net: dsa: microchip: Add strap description to set SPI mode At reset, KSZ8463 uses a strap-based configuration to set SPI as interface bus. If the required pull-ups/pull-downs are missing (by mistake or by design to save power) the pins may float and the configuration can go wrong preventing any communication with the switch. Add a 'reset' pinmux state Add a KSZ8463 specific strap description that can be used by the driver to drive the strap pins during reset. Two GPIOs are used. Users must describe either both of them or none of them. Signed-off-by: Bastien Curutchet (Schneider Electric) Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250918-ksz-strap-pins-v3-2-16662e881728@bootlin.com Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/dsa/microchip,ksz.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index db8175b4ced6..a8c8009414ae 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -34,6 +34,13 @@ properties: - microchip,ksz8567 - microchip,lan9646 + pinctrl-names: + items: + - const: default + - const: reset + description: + Used during reset for strap configuration. + reset-gpios: description: Should be a gpio specifier for a reset line. @@ -139,6 +146,18 @@ allOf: should be provided externally. dependencies: microchip,rmii-clk-internal: [ethernet] + - if: + properties: + compatible: + contains: + const: microchip,ksz8463 + then: + properties: + straps-rxd-gpios: + description: + RXD0 and RXD1 pins, used to select SPI as bus interface. + minItems: 2 + maxItems: 2 unevaluatedProperties: false -- cgit v1.2.3 From bee278e18e641a4bc11513b0fa8f5eb2667b8a32 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 18 Sep 2025 23:20:26 +0200 Subject: dt-bindings: embedded-controller: Add Lenovo Thinkpad T14s EC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add binding for the EC found in the Thinkpad T14s Gen6 Snapdragon, which is based on the Qualcomm X1 Elite. Some of the system LEDs and extra keys are only accessible via the EC. Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sebastian Reichel Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250918-thinkpad-t14s-ec-v5-1-ac0bc6382c5c@collabora.com Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen --- .../lenovo,thinkpad-t14s-ec.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/embedded-controller/lenovo,thinkpad-t14s-ec.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/embedded-controller/lenovo,thinkpad-t14s-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/lenovo,thinkpad-t14s-ec.yaml new file mode 100644 index 000000000000..c87ccb5b3086 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/lenovo,thinkpad-t14s-ec.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/lenovo,thinkpad-t14s-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lenovo Thinkpad T14s Embedded Controller + +maintainers: + - Sebastian Reichel + +description: + The Qualcomm Snapdragon-based Lenovo Thinkpad T14s has an Embedded Controller + (EC) which handles things such as keyboard backlight, LEDs or non-standard + keys. + +properties: + compatible: + const: lenovo,thinkpad-t14s-ec + + reg: + const: 0x28 + + interrupts: + maxItems: 1 + + wakeup-source: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - |+ + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@28 { + compatible = "lenovo,thinkpad-t14s-ec"; + reg = <0x28>; + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; + }; +... -- cgit v1.2.3 From ef0e000cd162a58dba10608ef6959f172d1bc5f4 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 11 Jun 2025 18:26:20 -0500 Subject: dt-bindings: timer: Convert faraday,fttmr010 to DT schema Convert the Faraday fttmr010 Timer binding to DT schema format. Adjust the compatible string values to match what's in use. The number of interrupts can also be anywhere from 1 to 8. The clock-names order was reversed compared to what's used. Signed-off-by: Rob Herring (Arm) Signed-off-by: Daniel Lezcano Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20250611232621.1508116-1-robh@kernel.org --- .../devicetree/bindings/timer/faraday,fttmr010.txt | 38 --------- .../bindings/timer/faraday,fttmr010.yaml | 89 ++++++++++++++++++++++ 2 files changed, 89 insertions(+), 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/faraday,fttmr010.txt create mode 100644 Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt deleted file mode 100644 index 3cb2f4c98d64..000000000000 --- a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt +++ /dev/null @@ -1,38 +0,0 @@ -Faraday Technology timer - -This timer is a generic IP block from Faraday Technology, embedded in the -Cortina Systems Gemini SoCs and other designs. - -Required properties: - -- compatible : Must be one of - "faraday,fttmr010" - "cortina,gemini-timer", "faraday,fttmr010" - "moxa,moxart-timer", "faraday,fttmr010" - "aspeed,ast2400-timer" - "aspeed,ast2500-timer" - "aspeed,ast2600-timer" - -- reg : Should contain registers location and length -- interrupts : Should contain the three timer interrupts usually with - flags for falling edge - -Optionally required properties: - -- clocks : a clock to provide the tick rate for "faraday,fttmr010" -- clock-names : should be "EXTCLK" and "PCLK" for the external tick timer - and peripheral clock respectively, for "faraday,fttmr010" -- syscon : a phandle to the global Gemini system controller if the compatible - type is "cortina,gemini-timer" - -Example: - -timer@43000000 { - compatible = "faraday,fttmr010"; - reg = <0x43000000 0x1000>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ - <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ - <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ - clocks = <&extclk>, <&pclk>; - clock-names = "EXTCLK", "PCLK"; -}; diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml b/Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml new file mode 100644 index 000000000000..39506323556c --- /dev/null +++ b/Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/faraday,fttmr010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday FTTMR010 timer + +maintainers: + - Joel Stanley + - Linus Walleij + +description: + This timer is a generic IP block from Faraday Technology, embedded in the + Cortina Systems Gemini SoCs and other designs. + +properties: + compatible: + oneOf: + - items: + - const: moxa,moxart-timer + - const: faraday,fttmr010 + - enum: + - aspeed,ast2400-timer + - aspeed,ast2500-timer + - aspeed,ast2600-timer + - cortina,gemini-timer + - faraday,fttmr010 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 8 + description: One interrupt per timer + + clocks: + minItems: 1 + items: + - description: Peripheral clock + - description: External tick clock + + clock-names: + minItems: 1 + items: + - const: PCLK + - const: EXTCLK + + resets: + maxItems: 1 + + syscon: + description: System controller phandle for Gemini systems + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: cortina,gemini-timer + then: + required: + - syscon + else: + properties: + syscon: false + +additionalProperties: false + +examples: + - | + #include + + timer@43000000 { + compatible = "faraday,fttmr010"; + reg = <0x43000000 0x1000>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ + <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ + <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ + clocks = <&pclk>, <&extclk>; + clock-names = "PCLK", "EXTCLK"; + }; -- cgit v1.2.3 From bb7bf8b44de1b13b8b7b10ca166b545ff22edac9 Mon Sep 17 00:00:00 2001 From: Max Shevchenko Date: Wed, 2 Jul 2025 13:50:40 +0300 Subject: dt-bindings: timer: mediatek: add MT6572 Add a compatible string for timer on the MT6572 SoC. Signed-off-by: Max Shevchenko Signed-off-by: Daniel Lezcano Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250702-mt6572-v4-3-bde75b7ed445@proton.me --- Documentation/devicetree/bindings/timer/mediatek,timer.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml index f68fc7050c56..d5b574bfd2ca 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml +++ b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - mediatek,mt2701-timer + - mediatek,mt6572-timer - mediatek,mt6580-timer - mediatek,mt6582-timer - mediatek,mt6589-timer -- cgit v1.2.3 From c1ff9e919addb8cf0414b08bd996f11a4a2e7297 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 23 May 2025 10:14:37 -0400 Subject: dt-bindings: timer: fsl,ftm-timer: use items for reg The original txt binding doc is: reg : Specifies base physical address and size of the register sets for the clock event device and clock source device. And existed dts provide two reg MMIO spaces. So change to use items to descript reg property. Update examples. Fixes: 8fc30d8f8e86 ("dt-bindings: timer: fsl,ftm-timer: Convert to dtschema") Signed-off-by: Frank Li Signed-off-by: Daniel Lezcano Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250523141437.533643-1-Frank.Li@nxp.com --- Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml index 0e4a8ddc3de3..e3b61b62521e 100644 --- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml @@ -14,7 +14,9 @@ properties: const: fsl,ftm-timer reg: - maxItems: 1 + items: + - description: clock event device + - description: clock source device interrupts: maxItems: 1 @@ -50,7 +52,8 @@ examples: ftm@400b8000 { compatible = "fsl,ftm-timer"; - reg = <0x400b8000 0x1000>; + reg = <0x400b8000 0x1000>, + <0x400b9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clock-names = "ftm-evt", "ftm-src", "ftm-evt-counter-en", "ftm-src-counter-en"; clocks = <&clks VF610_CLK_FTM2>, <&clks VF610_CLK_FTM3>, -- cgit v1.2.3 From ffc5870fc4e0ea72bf73ad5ab1d648aa0b4f7cbf Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 28 May 2025 12:53:50 -0400 Subject: dt-bindings: timer: Add fsl,timrot.yaml Add fsl,timrot.yaml for i.MX23/i.MX28 timer. Also add a generic fallback compatible string "fsl,timrot" for legacy devices, which have existed for over 15 years. Signed-off-by: Frank Li Signed-off-by: Daniel Lezcano Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250528165351.691848-1-Frank.Li@nxp.com --- .../devicetree/bindings/timer/fsl,timrot.yaml | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/fsl,timrot.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/fsl,timrot.yaml b/Documentation/devicetree/bindings/timer/fsl,timrot.yaml new file mode 100644 index 000000000000..d181f274ef9f --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,timrot.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,timrot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MXS Timer + +maintainers: + - Frank Li + +properties: + compatible: + items: + - enum: + - fsl,imx23-timrot + - fsl,imx28-timrot + - const: fsl,timrot + + reg: + maxItems: 1 + + interrupts: + items: + - description: irq for timer0 + - description: irq for timer1 + - description: irq for timer2 + - description: irq for timer3 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer: timer@80068000 { + compatible = "fsl,imx28-timrot", "fsl,timrot"; + reg = <0x80068000 0x2000>; + interrupts = <48>, <49>, <50>, <51>; + clocks = <&clks 26>; + }; -- cgit v1.2.3 From 99d19715daf5553a28452a4ef95e9692277e2787 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 11 Jun 2025 13:07:58 +0200 Subject: dt-bindings: timer: mediatek,timer: Add MediaTek MT8196 compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new compatible for the MediaTek MT8196 SoC, fully compatible with MT6765. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Daniel Lezcano Reviewed-by: Nícolas F. R. A. Prado Acked-by: Rob Herring (Arm) Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250611110800.458164-2-angelogioacchino.delregno@collabora.com --- Documentation/devicetree/bindings/timer/mediatek,timer.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml index d5b574bfd2ca..e3e38066c2cb 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml +++ b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml @@ -45,6 +45,7 @@ properties: - mediatek,mt8188-timer - mediatek,mt8192-timer - mediatek,mt8195-timer + - mediatek,mt8196-timer - mediatek,mt8365-systimer - const: mediatek,mt6765-timer -- cgit v1.2.3 From 5fa7d739f811bdffb5fc99696c2e821344fe0b88 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:17 +0300 Subject: regulator: dt-bindings: qcom,sdm845-refgen-regulator: document more platforms Document refgen block being present on SDM670, Lemans and QCS8300 platforms. It should be used to provide reference voltage to DSI controller. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250921-refgen-v1-1-9d93e64133ea@oss.qualcomm.com Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml index f02f97d4fdd2..40f9223d4c27 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml @@ -23,11 +23,14 @@ properties: - enum: - qcom,sc7180-refgen-regulator - qcom,sc8180x-refgen-regulator + - qcom,sdm670-refgen-regulator - qcom,sm8150-refgen-regulator - const: qcom,sdm845-refgen-regulator - items: - enum: + - qcom,qcs8300-refgen-regulator + - qcom,sa8775p-refgen-regulator - qcom,sc7280-refgen-regulator - qcom,sc8280xp-refgen-regulator - qcom,sm6350-refgen-regulator -- cgit v1.2.3 From e609438851928381e39b5393f17156955a84122a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:17 +0300 Subject: regulator: dt-bindings: qcom,sdm845-refgen-regulator: document more platforms Document refgen block being present on SDM670, Lemans and QCS8300 platforms. It should be used to provide reference voltage to DSI controller. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250921-refgen-v1-1-9d93e64133ea@oss.qualcomm.com Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml index f02f97d4fdd2..40f9223d4c27 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml @@ -23,11 +23,14 @@ properties: - enum: - qcom,sc7180-refgen-regulator - qcom,sc8180x-refgen-regulator + - qcom,sdm670-refgen-regulator - qcom,sm8150-refgen-regulator - const: qcom,sdm845-refgen-regulator - items: - enum: + - qcom,qcs8300-refgen-regulator + - qcom,sa8775p-refgen-regulator - qcom,sc7280-refgen-regulator - qcom,sc8280xp-refgen-regulator - qcom,sm6350-refgen-regulator -- cgit v1.2.3 From adaf5b248ff38f98ea1b3696b9a793db270f8c3e Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Mon, 4 Aug 2025 17:23:37 +0200 Subject: dt: bindings: fsl,vf610-pit: Add compatible for s32g2 and s32g3 The Vybrid Family is a NXP (formerly Freescale) platform having a Programmable Interrupt Timer (PIT). This timer is an IP found also on the NXP Automotive platform S32G2 and S32G3. Add the compatible for those platforms to describe the timer. Signed-off-by: Daniel Lezcano Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250804152344.1109310-20-daniel.lezcano@linaro.org --- Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml index bee2c35bd0e2..42e130654d58 100644 --- a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml @@ -15,8 +15,13 @@ description: properties: compatible: - enum: - - fsl,vf610-pit + oneOf: + - enum: + - fsl,vf610-pit + - nxp,s32g2-pit + - items: + - const: nxp,s32g3-pit + - const: nxp,s32g2-pit reg: maxItems: 1 -- cgit v1.2.3 From 1ad38ef4dbccee28b9b50e315a2d4d9ca5f7ee09 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Sat, 16 Aug 2025 00:25:28 -0700 Subject: dt-bindings: arm: Add label in the coresight components Current name of coresight component's folder consists of prefix of the device and the id in the device list. When run 'ls' command, we can get the register address of the device. Take CTI for example, if we want to set the config for modem CTI, but we can't know which CTI is modem CTI from all current information. cti_sys0 -> ../../../devices/platform/soc@0/138f0000.cti/cti_sys0 cti_sys1 -> ../../../devices/platform/soc@0/13900000.cti/cti_sys1 Add label to show hardware context information of each coresight device. There will be a sysfs node label in each device folder. cat /sys/bus/coresight/devices/cti_sys0/label Signed-off-by: Mao Jinlong Reviewed-by: Krzysztof Kozlowski Reviewed-by: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20250816072529.3716968-2-quic_jinlmao@quicinc.com --- Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml | 4 ++++ Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml | 4 ++++ Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml | 4 ++++ .../devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml | 4 ++++ .../devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml | 4 ++++ Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml | 4 ++++ Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml | 4 ++++ .../devicetree/bindings/arm/arm,coresight-static-funnel.yaml | 4 ++++ .../devicetree/bindings/arm/arm,coresight-static-replicator.yaml | 4 ++++ Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml | 4 ++++ Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml | 4 ++++ Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 4 ++++ Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml | 4 ++++ Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml | 4 ++++ Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 4 ++++ 15 files changed, 60 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml index 2d5545a2b49c..2a91670ccb8c 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml @@ -98,6 +98,10 @@ properties: power-domains: maxItems: 1 + label: + description: + Description of a coresight device. + arm,cti-ctm-id: $ref: /schemas/types.yaml#/definitions/uint32 description: diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml index 08b89b62c505..ed091dc0c10a 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml @@ -39,6 +39,10 @@ properties: enum: - arm,coresight-dummy-sink + label: + description: + Description of a coresight device. + in-ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml index 742dc4e25d3b..78337be42b55 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml @@ -38,6 +38,10 @@ properties: enum: - arm,coresight-dummy-source + label: + description: + Description of a coresight device. + arm,static-trace-id: description: If dummy source needs static id support, use this to set trace id. $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml index 44a1041cb0fc..b74db15e5f8a 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml @@ -57,6 +57,10 @@ properties: power-domains: maxItems: 1 + label: + description: + Description of a coresight device. + in-ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml index 03792e9bd97a..17ea936b796f 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml @@ -54,6 +54,10 @@ properties: - const: apb_pclk - const: atclk + label: + description: + Description of a coresight device. + power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml index 90679788e0bf..892df7aca1ac 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml @@ -54,6 +54,10 @@ properties: - const: apb_pclk - const: atclk + label: + description: + Description of a coresight device. + power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml index 01200f67504a..71f2e1ed27e5 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml @@ -85,6 +85,10 @@ properties: CPU powers down the coresight component also powers down and loses its context. + label: + description: + Description of a coresight device. + arm,cp14: type: boolean description: diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml index cc8c3baa79b4..9598a3d0a95b 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml @@ -30,6 +30,10 @@ properties: power-domains: maxItems: 1 + label: + description: + Description of a coresight device. + in-ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml index 0c1017affbad..b81851b26c74 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml @@ -43,6 +43,10 @@ properties: - const: dbg_trc - const: dbg_apb + label: + description: + Description of a coresight device. + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml index 4787d7c6bac2..96dd5b5f771a 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -55,6 +55,10 @@ properties: - const: apb_pclk - const: atclk + label: + description: + Description of a coresight device. + iommus: maxItems: 1 diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml index 61a0cdc27745..a207f6899e67 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml @@ -54,6 +54,10 @@ properties: - const: apb_pclk - const: atclk + label: + description: + Description of a coresight device. + power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..c969c16c21ef 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -39,6 +39,10 @@ properties: items: - const: apb + label: + description: + Description of a coresight device. + in-ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml index 4fd5752978cd..ffe613efeabe 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml @@ -20,6 +20,10 @@ properties: compatible: const: qcom,coresight-remote-etm + label: + description: + Description of a coresight device. + out-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml index 5ed40f21b8eb..a48c9ac3eaa9 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml @@ -64,6 +64,10 @@ properties: items: - const: apb_pclk + label: + description: + Description of a coresight device. + in-ports: description: | Input connections from TPDM to TPDA diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 07d21a3617f5..4edc47483851 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -76,6 +76,10 @@ properties: minimum: 0 maximum: 32 + label: + description: + Description of a coresight device. + clocks: maxItems: 1 -- cgit v1.2.3 From 7aada81cd75ad844c84fb1dcdce2d67ec41763f8 Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 14 Sep 2025 16:18:48 +0300 Subject: dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatible for exynos8890 Add samsung,exynos8890-dw-mshc-smu specific compatible to the bindings documentation. Since Samsung, as usual, likes reusing devices from older designs, use the samsung,exynos7-dw-mshc-smu compatible. Signed-off-by: Ivaylo Ivanov Acked-by: Rob Herring (Arm) Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index e8bd49d46794..27c4060f2f91 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -31,6 +31,7 @@ properties: - samsung,exynos5433-dw-mshc-smu - samsung,exynos7885-dw-mshc-smu - samsung,exynos850-dw-mshc-smu + - samsung,exynos8890-dw-mshc-smu - samsung,exynos8895-dw-mshc-smu - const: samsung,exynos7-dw-mshc-smu -- cgit v1.2.3 From 8d13f91d7fce4e842dfc7edbcba0690f7ed11c18 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 17 Sep 2025 11:38:13 +0800 Subject: dt-bindings: i2c: spacemit: extend and validate all properties Extend the K1 I2C properties by including generic i2c-controller schema. and this will enable it to do the DT validation check later. Signed-off-by: Yixun Lan Reviewed-by: Troy Mitchell Tested-by: Alex Elder Acked-by: Conor Dooley Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml index 3d6aefb0d0f1..226c600deae1 100644 --- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml @@ -9,6 +9,9 @@ title: I2C controller embedded in SpacemiT's K1 SoC maintainers: - Troy Mitchell +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + properties: compatible: const: spacemit,k1-i2c -- cgit v1.2.3 From 8ab3bd59f9fc210a1a88b509f6931cf3f5ea229a Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 14 Sep 2025 16:16:20 +0300 Subject: dt-bindings: i2c: exynos5: add samsung,exynos8890-hsi2c compatible Add samsung,exynos8890-hsi2c compatible, reusing the 8895 support since it's compatible with exynos8890's i2c controllers. Signed-off-by: Ivaylo Ivanov Acked-by: Rob Herring (Arm) Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index 6fc03281a8f8..32269239bae4 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -33,6 +33,10 @@ properties: - samsung,exynos7870-hsi2c - tesla,fsd-hsi2c - const: samsung,exynos7-hsi2c + - items: + - enum: + - samsung,exynos8890-hsi2c + - const: samsung,exynos8895-hsi2c - items: - enum: - google,gs101-hsi2c -- cgit v1.2.3 From 958e55f90a01451de77e22063d37b60388219b96 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 21 Aug 2025 10:32:06 +0200 Subject: dt-bindings: i2c: spacemit,k1-i2c: Minor whitespace cleanup in example The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Troy Mitchell Acked-by: Rob Herring (Arm) Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml index 3d6aefb0d0f1..c1a3004df71d 100644 --- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml @@ -53,7 +53,7 @@ examples: reg = <0xd4010800 0x38>; interrupt-parent = <&plic>; interrupts = <36>; - clocks =<&ccu 32>, <&ccu 84>; + clocks = <&ccu 32>, <&ccu 84>; clock-names = "func", "bus"; clock-frequency = <100000>; }; -- cgit v1.2.3 From 492263fd564c882a7170a58d3dffb4574de042d4 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 18 Aug 2025 09:38:57 +0530 Subject: dt-bindings: mailbox: Add bindings for RPMI shared memory transport Add device tree bindings for the common RISC-V Platform Management Interface (RPMI) shared memory transport as a mailbox controller. Reviewed-by: Conor Dooley Signed-off-by: Anup Patel Acked-by: Jassi Brar Link: https://lore.kernel.org/r/20250818040920.272664-2-apatel@ventanamicro.com Signed-off-by: Paul Walmsley --- .../bindings/mailbox/riscv,rpmi-shmem-mbox.yaml | 124 +++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml new file mode 100644 index 000000000000..3aabc52a0c03 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Platform Management Interface (RPMI) shared memory mailbox + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a common shared + memory based RPMI transport. This RPMI shared memory transport integrates as + mailbox controller in the SBI implementation or supervisor software whereas + each RPMI service group is mailbox client in the SBI implementation and + supervisor software. + + =========================================== + References + =========================================== + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + +properties: + compatible: + const: riscv,rpmi-shmem-mbox + + reg: + minItems: 2 + items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + - description: P2A request queue base address + - description: A2P acknowledgment queue base address + - description: A2P doorbell address + + reg-names: + minItems: 2 + items: + - const: a2p-req + - const: p2a-ack + - enum: [ p2a-req, a2p-doorbell ] + - const: a2p-ack + - const: a2p-doorbell + + interrupts: + maxItems: 1 + description: + The RPMI shared memory transport supports P2A doorbell as a wired + interrupt and this property specifies the interrupt source. + + msi-parent: + description: + The RPMI shared memory transport supports P2A doorbell as a system MSI + and this property specifies the target MSI controller. + + riscv,slot-size: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 64 + description: + Power-of-2 RPMI slot size of the RPMI shared memory transport. + + riscv,a2p-doorbell-value: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x1 + description: + Value written to the 32-bit A2P doorbell register. + + riscv,p2a-doorbell-sysmsi-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The RPMI shared memory transport supports P2A doorbell as a system MSI + and this property specifies system MSI index to be used for configuring + the P2A doorbell MSI. + + "#mbox-cells": + const: 1 + description: + The first cell specifies RPMI service group ID. + +required: + - compatible + - reg + - reg-names + - riscv,slot-size + - "#mbox-cells" + +anyOf: + - required: + - interrupts + - required: + - msi-parent + +additionalProperties: false + +examples: + - | + // Example 1 (RPMI shared memory with only 2 queues): + mailbox@10080000 { + compatible = "riscv,rpmi-shmem-mbox"; + reg = <0x10080000 0x10000>, + <0x10090000 0x10000>; + reg-names = "a2p-req", "p2a-ack"; + msi-parent = <&imsic_mlevel>; + riscv,slot-size = <64>; + #mbox-cells = <1>; + }; + - | + // Example 2 (RPMI shared memory with only 4 queues): + mailbox@10001000 { + compatible = "riscv,rpmi-shmem-mbox"; + reg = <0x10001000 0x800>, + <0x10001800 0x800>, + <0x10002000 0x800>, + <0x10002800 0x800>, + <0x10003000 0x4>; + reg-names = "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "a2p-doorbell"; + msi-parent = <&imsic_mlevel>; + riscv,slot-size = <64>; + riscv,a2p-doorbell-value = <0x00008000>; + #mbox-cells = <1>; + }; -- cgit v1.2.3 From 52aefc1e3c5fbdfdd216796fbe78443ae67e447f Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Tue, 26 Aug 2025 09:39:35 +0200 Subject: ASoC: dt-binding: Convert mt8183-afe-pcm to dt-schema Convert the MediaTek MT8183 AFE PCM Device Tree binding from the old .txt format to dt-schema format to improve validation. While converting, also document all clock inputs and memory-region used by the AFE block. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Julien Massot Link: https://patch.msgid.link/20250826-mtk-dtb-warnings-v3-2-20e89886a20e@collabora.com Signed-off-by: Mark Brown --- .../bindings/sound/mediatek,mt8183-audio.yaml | 228 +++++++++++++++++++++ .../devicetree/bindings/sound/mt8183-afe-pcm.txt | 42 ---- 2 files changed, 228 insertions(+), 42 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml delete mode 100644 Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml new file mode 100644 index 000000000000..031b0fa7b4dc --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8183-audio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek AFE PCM controller for mt8183 + +maintainers: + - Julien Massot + +properties: + compatible: + const: mediatek,mt8183-audio + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: audiosys + + power-domains: + maxItems: 1 + + memory-region: + maxItems: 1 + + clocks: + items: + - description: AFE clock + - description: ADDA DAC clock + - description: ADDA DAC pre-distortion clock + - description: ADDA ADC clock + - description: ADDA6 ADC clock + - description: Audio low-jitter 22.5792m clock + - description: Audio low-jitter 24.576m clock + - description: Audio PLL1 tuner clock + - description: Audio PLL2 tuner clock + - description: I2S1 bit clock + - description: I2S2 bit clock + - description: I2S3 bit clock + - description: I2S4 bit clock + - description: Audio Time-Division Multiplexing interface clock + - description: Powerdown Audio test model clock + - description: Audio infra sys clock + - description: Audio infra 26M clock + - description: Mux for audio clock + - description: Mux for audio internal bus clock + - description: Mux main divider by 4 + - description: Primary audio mux + - description: Primary audio PLL + - description: Secondary audio mux + - description: Secondary audio PLL + - description: Primary audio en-generator clock + - description: Primary PLL divider by 4 for IEC + - description: Secondary audio en-generator clock + - description: Secondary PLL divider by 8 for IEC + - description: Mux selector for I2S port 0 + - description: Mux selector for I2S port 1 + - description: Mux selector for I2S port 2 + - description: Mux selector for I2S port 3 + - description: Mux selector for I2S port 4 + - description: Mux selector for I2S port 5 + - description: APLL1 and APLL2 divider for I2S port 0 + - description: APLL1 and APLL2 divider for I2S port 1 + - description: APLL1 and APLL2 divider for I2S port 2 + - description: APLL1 and APLL2 divider for I2S port 3 + - description: APLL1 and APLL2 divider for I2S port 4 + - description: APLL1 and APLL2 divider for IEC + - description: 26MHz clock for audio subsystem + + clock-names: + items: + - const: aud_afe_clk + - const: aud_dac_clk + - const: aud_dac_predis_clk + - const: aud_adc_clk + - const: aud_adc_adda6_clk + - const: aud_apll22m_clk + - const: aud_apll24m_clk + - const: aud_apll1_tuner_clk + - const: aud_apll2_tuner_clk + - const: aud_i2s1_bclk_sw + - const: aud_i2s2_bclk_sw + - const: aud_i2s3_bclk_sw + - const: aud_i2s4_bclk_sw + - const: aud_tdm_clk + - const: aud_tml_clk + - const: aud_infra_clk + - const: mtkaif_26m_clk + - const: top_mux_audio + - const: top_mux_aud_intbus + - const: top_syspll_d2_d4 + - const: top_mux_aud_1 + - const: top_apll1_ck + - const: top_mux_aud_2 + - const: top_apll2_ck + - const: top_mux_aud_eng1 + - const: top_apll1_d8 + - const: top_mux_aud_eng2 + - const: top_apll2_d8 + - const: top_i2s0_m_sel + - const: top_i2s1_m_sel + - const: top_i2s2_m_sel + - const: top_i2s3_m_sel + - const: top_i2s4_m_sel + - const: top_i2s5_m_sel + - const: top_apll12_div0 + - const: top_apll12_div1 + - const: top_apll12_div2 + - const: top_apll12_div3 + - const: top_apll12_div4 + - const: top_apll12_divb + - const: top_clk26m_clk + +required: + - compatible + - interrupts + - resets + - reset-names + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + audio-controller { + compatible = "mediatek,mt8183-audio"; + interrupts = ; + resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + power-domains = <&spm MT8183_POWER_DOMAIN_AUDIO>; + clocks = <&audiosys CLK_AUDIO_AFE>, + <&audiosys CLK_AUDIO_DAC>, + <&audiosys CLK_AUDIO_DAC_PREDIS>, + <&audiosys CLK_AUDIO_ADC>, + <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, + <&audiosys CLK_AUDIO_22M>, + <&audiosys CLK_AUDIO_24M>, + <&audiosys CLK_AUDIO_APLL_TUNER>, + <&audiosys CLK_AUDIO_APLL2_TUNER>, + <&audiosys CLK_AUDIO_I2S1>, + <&audiosys CLK_AUDIO_I2S2>, + <&audiosys CLK_AUDIO_I2S3>, + <&audiosys CLK_AUDIO_I2S4>, + <&audiosys CLK_AUDIO_TDM>, + <&audiosys CLK_AUDIO_TML>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_AUDIO>, + <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&topckgen CLK_TOP_SYSPLL_D2_D4>, + <&topckgen CLK_TOP_MUX_AUD_1>, + <&topckgen CLK_TOP_APLL1_CK>, + <&topckgen CLK_TOP_MUX_AUD_2>, + <&topckgen CLK_TOP_APLL2_CK>, + <&topckgen CLK_TOP_MUX_AUD_ENG1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_MUX_AUD_ENG2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_MUX_APLL_I2S0>, + <&topckgen CLK_TOP_MUX_APLL_I2S1>, + <&topckgen CLK_TOP_MUX_APLL_I2S2>, + <&topckgen CLK_TOP_MUX_APLL_I2S3>, + <&topckgen CLK_TOP_MUX_APLL_I2S4>, + <&topckgen CLK_TOP_MUX_APLL_I2S5>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + <&clk26m>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adc_adda6_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_i2s1_bclk_sw", + "aud_i2s2_bclk_sw", + "aud_i2s3_bclk_sw", + "aud_i2s4_bclk_sw", + "aud_tdm_clk", + "aud_tml_clk", + "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_syspll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + "top_clk26m_clk"; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt deleted file mode 100644 index 1f1cba4152ce..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt +++ /dev/null @@ -1,42 +0,0 @@ -Mediatek AFE PCM controller for mt8183 - -Required properties: -- compatible = "mediatek,mt68183-audio"; -- reg: register location and size -- interrupts: should contain AFE interrupt -- resets: Must contain an entry for each entry in reset-names - See ../reset/reset.txt for details. -- reset-names: should have these reset names: - "audiosys"; -- power-domains: should define the power domain -- clocks: Must contain an entry for each entry in clock-names -- clock-names: should have these clock names: - "infra_sys_audio_clk", - "mtkaif_26m_clk", - "top_mux_audio", - "top_mux_aud_intbus", - "top_sys_pll3_d4", - "top_clk26m_clk"; - -Example: - - afe: mt8183-afe-pcm@11220000 { - compatible = "mediatek,mt8183-audio"; - reg = <0 0x11220000 0 0x1000>; - interrupts = ; - resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; - reset-names = "audiosys"; - power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>; - clocks = <&infrasys CLK_INFRA_AUDIO>, - <&infrasys CLK_INFRA_AUDIO_26M_BCLK>, - <&topckgen CLK_TOP_MUX_AUDIO>, - <&topckgen CLK_TOP_MUX_AUD_INTBUS>, - <&topckgen CLK_TOP_SYSPLL_D2_D4>, - <&clk26m>; - clock-names = "infra_sys_audio_clk", - "mtkaif_26m_clk", - "top_mux_audio", - "top_mux_aud_intbus", - "top_sys_pll_d2_d4", - "top_clk26m_clk"; - }; -- cgit v1.2.3 From cf5be90ee4dfa3c38dc64fbcc4fb70fa0180b7b7 Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Tue, 26 Aug 2025 09:39:38 +0200 Subject: ASoC: Convert MT8183 DA7219 sound card to DT schema Convert the Device Tree binding for MT8183-based boards using the DA7219 headset codec and optional MAX98357, RT1015 or RT1015P speaker amplifiers from the legacy .txt format to DT schema. This improves binding validation and removes DT schema warnings for boards using these audio components. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Julien Massot Link: https://patch.msgid.link/20250826-mtk-dtb-warnings-v3-5-20e89886a20e@collabora.com Signed-off-by: Mark Brown --- .../bindings/sound/mediatek,mt8183_da7219.yaml | 49 ++++++++++++++++++++++ .../bindings/sound/mt8183-da7219-max98357.txt | 21 ---------- 2 files changed, 49 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8183_da7219.yaml delete mode 100644 Documentation/devicetree/bindings/sound/mt8183-da7219-max98357.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8183_da7219.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8183_da7219.yaml new file mode 100644 index 000000000000..b526e8123182 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8183_da7219.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8183_da7219.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8183 sound card with external codecs + +maintainers: + - Julien Massot + +description: + MediaTek MT8183 SoC-based sound cards with DA7219 as headset codec, + and MAX98357A, RT1015 or RT1015P as speaker amplifiers. Optionally includes HDMI codec. + +properties: + compatible: + enum: + - mediatek,mt8183_da7219_max98357 + - mediatek,mt8183_da7219_rt1015 + - mediatek,mt8183_da7219_rt1015p + + mediatek,headset-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the DA7219 headset codec. + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the MT8183 ASoC platform (e.g., AFE node). + + mediatek,hdmi-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Optional phandle to the HDMI codec (e.g., IT6505). + +required: + - compatible + - mediatek,headset-codec + - mediatek,platform + +additionalProperties: false + +examples: + - | + sound { + compatible = "mediatek,mt8183_da7219_max98357"; + mediatek,headset-codec = <&da7219>; + mediatek,hdmi-codec = <&it6505dptx>; + mediatek,platform = <&afe>; + }; diff --git a/Documentation/devicetree/bindings/sound/mt8183-da7219-max98357.txt b/Documentation/devicetree/bindings/sound/mt8183-da7219-max98357.txt deleted file mode 100644 index f276dfc74b46..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8183-da7219-max98357.txt +++ /dev/null @@ -1,21 +0,0 @@ -MT8183 with MT6358, DA7219, MAX98357, and RT1015 CODECS - -Required properties: -- compatible : "mediatek,mt8183_da7219_max98357" for MAX98357A codec - "mediatek,mt8183_da7219_rt1015" for RT1015 codec - "mediatek,mt8183_da7219_rt1015p" for RT1015P codec -- mediatek,headset-codec: the phandles of da7219 codecs -- mediatek,platform: the phandle of MT8183 ASoC platform - -Optional properties: -- mediatek,hdmi-codec: the phandles of HDMI codec - -Example: - - sound { - compatible = "mediatek,mt8183_da7219_max98357"; - mediatek,headset-codec = <&da7219>; - mediatek,hdmi-codec = <&it6505dptx>; - mediatek,platform = <&afe>; - }; - -- cgit v1.2.3 From 82fd5dc99d63f948c59ac3b08137ef49125938bc Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Tue, 26 Aug 2025 09:39:39 +0200 Subject: ASoC: dt-binding: Convert MediaTek mt8183-mt6358 to DT schema Convert the existing text-based DT binding for MT8183 sound cards using MT6358 and various other codecs to a DT schema. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Julien Massot Link: https://patch.msgid.link/20250826-mtk-dtb-warnings-v3-6-20e89886a20e@collabora.com Signed-off-by: Mark Brown --- .../sound/mediatek,mt8183_mt6358_ts3a227.yaml | 59 ++++++++++++++++++++++ .../sound/mt8183-mt6358-ts3a227-max98357.txt | 25 --------- 2 files changed, 59 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8183_mt6358_ts3a227.yaml delete mode 100644 Documentation/devicetree/bindings/sound/mt8183-mt6358-ts3a227-max98357.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8183_mt6358_ts3a227.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8183_mt6358_ts3a227.yaml new file mode 100644 index 000000000000..43a6f9d40644 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8183_mt6358_ts3a227.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8183_mt6358_ts3a227.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8183 sound card with MT6358, TS3A227, and MAX98357/RT1015 codecs + +maintainers: + - Julien Massot + +description: + MediaTek MT8183 SoC-based sound cards using the MT6358 codec, + with optional TS3A227 headset codec, EC codec (via Chrome EC), and HDMI audio. + Speaker amplifier can be one of MAX98357A/B, RT1015, or RT1015P. + +properties: + compatible: + enum: + - mediatek,mt8183_mt6358_ts3a227_max98357 + - mediatek,mt8183_mt6358_ts3a227_max98357b + - mediatek,mt8183_mt6358_ts3a227_rt1015 + - mediatek,mt8183_mt6358_ts3a227_rt1015p + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the MT8183 ASoC platform node (e.g., AFE). + + mediatek,headset-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the TS3A227 headset codec. + + mediatek,ec-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Optional phandle to a ChromeOS EC codec node. + See bindings in google,cros-ec-codec.yaml. + + mediatek,hdmi-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Optional phandle to an HDMI audio codec node. + +required: + - compatible + - mediatek,platform + +additionalProperties: false + +examples: + - | + sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_max98357"; + mediatek,headset-codec = <&ts3a227>; + mediatek,ec-codec = <&ec_codec>; + mediatek,hdmi-codec = <&it6505dptx>; + mediatek,platform = <&afe>; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mt8183-mt6358-ts3a227-max98357.txt b/Documentation/devicetree/bindings/sound/mt8183-mt6358-ts3a227-max98357.txt deleted file mode 100644 index ecd46ed8eb98..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8183-mt6358-ts3a227-max98357.txt +++ /dev/null @@ -1,25 +0,0 @@ -MT8183 with MT6358, TS3A227, MAX98357, and RT1015 CODECS - -Required properties: -- compatible : "mediatek,mt8183_mt6358_ts3a227_max98357" for MAX98357A codec - "mediatek,mt8183_mt6358_ts3a227_max98357b" for MAX98357B codec - "mediatek,mt8183_mt6358_ts3a227_rt1015" for RT1015 codec - "mediatek,mt8183_mt6358_ts3a227_rt1015p" for RT1015P codec -- mediatek,platform: the phandle of MT8183 ASoC platform - -Optional properties: -- mediatek,headset-codec: the phandles of ts3a227 codecs -- mediatek,ec-codec: the phandle of EC codecs. - See google,cros-ec-codec.txt for more details. -- mediatek,hdmi-codec: the phandles of HDMI codec - -Example: - - sound { - compatible = "mediatek,mt8183_mt6358_ts3a227_max98357"; - mediatek,headset-codec = <&ts3a227>; - mediatek,ec-codec = <&ec_codec>; - mediatek,hdmi-codec = <&it6505dptx>; - mediatek,platform = <&afe>; - }; - -- cgit v1.2.3 From 45d78cd0bf2c40e74c31f70340484e20aae45b07 Mon Sep 17 00:00:00 2001 From: SungMin Park Date: Wed, 17 Sep 2025 12:43:11 +0530 Subject: dt-bindings: timer: exynos4210-mct: Add compatible for ARTPEC-9 SoC Add Axis ARTPEC-9 mct compatible to the bindings documentation. The design for the timer is reused from previous Samsung SoCs like exynos4210 and ARTPEC-8. Signed-off-by: SungMin Park Signed-off-by: Ravi Patel Signed-off-by: Daniel Lezcano Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250917071311.1404-1-ravi.patel@samsung.com --- Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 10578f544581..a4b229e0e78a 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - axis,artpec8-mct + - axis,artpec9-mct - google,gs101-mct - samsung,exynos2200-mct-peris - samsung,exynos3250-mct @@ -131,6 +132,7 @@ allOf: contains: enum: - axis,artpec8-mct + - axis,artpec9-mct - google,gs101-mct - samsung,exynos2200-mct-peris - samsung,exynos5260-mct -- cgit v1.2.3 From bca9b6633fb92ff37247442d08f3889a2e87881c Mon Sep 17 00:00:00 2001 From: Cosmo Chou Date: Tue, 16 Sep 2025 17:50:25 +0800 Subject: dt-bindings: trivial-devices: add mps,mp5998 Add dt-bindings for MPS mp5998 hot-swap controller. Signed-off-by: Cosmo Chou Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250916095026.800164-1-chou.cosmo@gmail.com Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index edaba5cd8434..12cb7f64b988 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -315,6 +315,8 @@ properties: - mps,mp5920 # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990 - mps,mp5990 + # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5998 + - mps,mp5998 # Monolithic Power Systems Inc. digital step-down converter mp9941 - mps,mp9941 # Temperature sensor with integrated fan control -- cgit v1.2.3 From cf6f234d7dfbbb13197eb71e7716412d4e30988d Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 23 Sep 2025 16:37:34 +0200 Subject: dt-bindings: touchscreen: add debounce-delay-us property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for glitch delay configuration. A detected signal is valid only if it remains stable longer than the configured delay; otherwise, it is considered a glitch. This property was introduced for the i.MX6UL touchscreen controller (TSC), which provides a hardware deglitch filter with four thresholds depending on the IPG clock frequency. In this use case, the IPG clock rate is 66 MHz, resulting in thresholds of 124 µs, 62 µs, 31 µs, and 15 µs, which requires a property with microsecond-level resolution. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250923143746.2857292-4-dario.binacchi@amarulasolutions.com Signed-off-by: Dmitry Torokhov --- Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml index 3e3572aa483a..7023e8c73a7b 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml @@ -206,6 +206,10 @@ properties: unevaluatedProperties: false + debounce-delay-us: + description: Minimum duration in microseconds a signal must remain stable + to be considered valid. + dependencies: touchscreen-size-x: [ touchscreen-size-y ] touchscreen-size-y: [ touchscreen-size-x ] -- cgit v1.2.3 From 3fccd1f9552dd073915b0a69d43cc03c582ce79b Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 23 Sep 2025 16:37:35 +0200 Subject: dt-bindings: touchscreen: fsl,imx6ul-tsc: support glitch thresold Support the debounce-delay-us property. Drivers must convert this value to IPG clock cycles and map it to one of the four discrete thresholds exposed by the TSC_DEBUG_MODE2 register: 0: 8191 IPG cycles 1: 4095 IPG cycles 2: 2047 IPG cycles 3: 1023 IPG cycles Signed-off-by: Dario Binacchi Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250923143746.2857292-5-dario.binacchi@amarulasolutions.com Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/fsl,imx6ul-tsc.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.yaml b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.yaml index 678756ad0f92..a99280aefcbe 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.yaml @@ -62,6 +62,20 @@ properties: description: Number of data samples which are averaged for each read. enum: [ 1, 4, 8, 16, 32 ] + debounce-delay-us: + description: | + Minimum duration in microseconds a signal must remain stable + to be considered valid. + + Drivers must convert this value to IPG clock cycles and map + it to one of the four discrete thresholds exposed by the + TSC_DEBUG_MODE2 register: + + 0: 8191 IPG cycles + 1: 4095 IPG cycles + 2: 2047 IPG cycles + 3: 1023 IPG cycles + required: - compatible - reg -- cgit v1.2.3 From 581b4da1f73c9e0caf9b7d0a46d1b5a0b36fbe20 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 18 Aug 2025 09:38:58 +0530 Subject: dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Add device tree bindings for the RISC-V SBI Message Proxy (MPXY) extension as a mailbox controller. Reviewed-by: Conor Dooley Signed-off-by: Anup Patel Acked-by: Jassi Brar Link: https://lore.kernel.org/r/20250818040920.272664-3-apatel@ventanamicro.com Signed-off-by: Paul Walmsley --- .../bindings/mailbox/riscv,sbi-mpxy-mbox.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml b/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml new file mode 100644 index 000000000000..061437a0b45a --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/riscv,sbi-mpxy-mbox.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/riscv,sbi-mpxy-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V SBI Message Proxy (MPXY) extension based mailbox + +maintainers: + - Anup Patel + +description: | + The RISC-V SBI Message Proxy (MPXY) extension [1] allows supervisor + software to send messages through the SBI implementation (M-mode + firmware or HS-mode hypervisor). The underlying message protocol + and message format used by the supervisor software could be some + other standard protocol compatible with the SBI MPXY extension + (such as RISC-V Platform Management Interface (RPMI) [2]). + + =========================================== + References + =========================================== + + [1] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + + [2] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + +properties: + compatible: + const: riscv,sbi-mpxy-mbox + + "#mbox-cells": + const: 2 + description: + The first cell specifies channel_id of the SBI MPXY channel, + the second cell specifies MSG_PROT_ID of the SBI MPXY channel + +required: + - compatible + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + mailbox { + compatible = "riscv,sbi-mpxy-mbox"; + #mbox-cells = <2>; + }; -- cgit v1.2.3 From 1d7e08325090045b6b08ecda6f9eaa471d309880 Mon Sep 17 00:00:00 2001 From: "J. Neuschäfer" Date: Tue, 23 Sep 2025 01:10:01 +0200 Subject: dt-bindings: net: ethernet-controller: Fix grammar in comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "difference" is a noun, so "sufficient" is an adjective without "ly". Signed-off-by: J. Neuschäfer Reviewed-by: Andrew Lunn Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250923-dt-net-typo-v1-1-08e1bdd14c74@posteo.net Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 2c924d296a8f..e4b6e9c92994 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -279,7 +279,7 @@ additionalProperties: true # specified. # # One option is to make the clock traces on the PCB longer than the -# data traces. A sufficiently difference in length can provide the 2ns +# data traces. A sufficient difference in length can provide the 2ns # delay. If both the RX and TX delays are implemented in this manner, # 'rgmii' should be used, so indicating the PCB adds the delays. # -- cgit v1.2.3 From 25aab8f3ce56fd3cdf921c206ce42d1cdede5259 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 12:36:03 +0200 Subject: dt-bindings: i2c: samsung,s3c2410-i2c: Drop S3C2410 Samsung S3C2410 SoC was removed from the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of "samsung,s3c2410-i2c" compatible. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Reviewed-by: Andi Shyti Signed-off-by: Andi Shyti Link: https://lore.kernel.org/r/20250830103601.82046-4-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml index 6ba7d793504c..a2ddc6803617 100644 --- a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml @@ -13,7 +13,6 @@ properties: compatible: oneOf: - enum: - - samsung,s3c2410-i2c - samsung,s3c2440-i2c # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs: - samsung,s3c2440-hdmiphy-i2c @@ -93,7 +92,6 @@ allOf: compatible: contains: enum: - - samsung,s3c2410-i2c - samsung,s3c2440-i2c - samsung,s3c2440-hdmiphy-i2c then: -- cgit v1.2.3 From 217f92d91c9faeb6b78bd6205b3585944cbcb433 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Sat, 20 Sep 2025 19:22:52 +0200 Subject: dt-bindings: i2c: i2c-mt65xx: Document MediaTek MT6878 I2C Document the I2C controllers found in the MediaTek MT6878 SoC, by adding a new compatible string for the controllers. Their design is compatible with the design from the MediaTek MT8188 SoC. Signed-off-by: Igor Belwon Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250920-mt6878-i2c-bringup-v2-1-70a951f10be9@mentallysanemainliners.org Signed-off-by: Andi Shyti --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index 23fe8ff76645..bd6811cbde70 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -50,6 +50,10 @@ properties: - enum: - mediatek,mt6795-i2c - const: mediatek,mt8173-i2c + - items: + - enum: + - mediatek,mt6878-i2c + - const: mediatek,mt8188-i2c - items: - enum: - mediatek,mt6893-i2c -- cgit v1.2.3 From 91945660ac29341710b0914db200f6eacf251513 Mon Sep 17 00:00:00 2001 From: Ram Kumar Dwivedi Date: Wed, 17 Sep 2025 19:39:30 +0530 Subject: scsi: ufs: dt-bindings: Document gear and rate limit properties Add optional "limit-hs-gear" and "limit-rate" properties to the UFS controller common binding. These properties allow limiting the maximum HS gear and rate. This is useful in cases where the customer board may have signal integrity, clock configuration or layout issues that prevent reliable operation at higher gears. Such limitations are especially critical in those platforms, where stability is prioritized over peak performance. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Ram Kumar Dwivedi Reviewed-by: Alim Akhtar Signed-off-by: Martin K. Petersen --- Documentation/devicetree/bindings/ufs/ufs-common.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Documentation/devicetree/bindings/ufs/ufs-common.yaml index 31fe7f30ff5b..9f04f34d8c5a 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml @@ -89,6 +89,22 @@ properties: msi-parent: true + limit-hs-gear: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 6 + default: 6 + description: + Restricts the maximum HS gear used in both TX and RX directions. + + limit-gear-rate: + $ref: /schemas/types.yaml#/definitions/string + enum: [rate-a, rate-b] + default: rate-b + description: + Restricts the UFS controller to rate-a or rate-b for both TX and + RX directions. + dependencies: freq-table-hz: [ clocks ] operating-points-v2: [ clocks, clock-names ] -- cgit v1.2.3 From 67c9b685c7f8f19b2f449fdd5fb6a0a0c39f429a Mon Sep 17 00:00:00 2001 From: Oleh Kuzhylnyi Date: Wed, 24 Sep 2025 21:42:47 -0700 Subject: dt-bindings: input: touchscreen: add hynitron cst816x series Add documentation for Hynitron CST816x series touchscreen bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Oleh Kuzhylnyi Link: https://lore.kernel.org/r/20250921125939.249788-1-kuzhylol@gmail.com Signed-off-by: Dmitry Torokhov --- .../input/touchscreen/hynitron,cst816x.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/hynitron,cst816x.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/hynitron,cst816x.yaml b/Documentation/devicetree/bindings/input/touchscreen/hynitron,cst816x.yaml new file mode 100644 index 000000000000..72d4da636881 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/hynitron,cst816x.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/hynitron,cst816x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hynitron CST816x Series Capacitive Touch controller + +maintainers: + - Oleh Kuzhylnyi + +description: | + Bindings for CST816x high performance self-capacitance touch chip series + with single point gesture and real two-point operation. + +properties: + compatible: + enum: + - hynitron,cst816s + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + linux,keycodes: + minItems: 1 + items: + - description: Slide up gesture + - description: Slide down gesture + - description: Slide left gesture + - description: Slide right gesture + - description: Long press gesture + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + touchscreen@15 { + compatible = "hynitron,cst816s"; + reg = <0x15>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + linux,keycodes = , , , , + ; + }; + }; + +... -- cgit v1.2.3 From 95e6b0af80525d14cb35fc664dd3ce5d5756dac1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 9 Sep 2025 07:59:51 -0700 Subject: dt-bindings: input: pm8941-pwrkey: Document wakeup-source property The 'resin' keys (usually connected to a volume-down button) are generally not supposed to wake up the device from suspend, so explicitly document a wakeup-source property to enable this wakeup behavior. For 'pwrkey' the default stays that pressing the button does wake up the device from suspend. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250909-resin-wakeup-v1-1-46159940e02b@lucaweiss.eu Signed-off-by: Dmitry Torokhov --- .../bindings/input/qcom,pm8941-pwrkey.yaml | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml index 72006a14fd41..f978cf965a4d 100644 --- a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml +++ b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.yaml @@ -10,9 +10,6 @@ maintainers: - Courtney Cavin - Vinod Koul -allOf: - - $ref: input.yaml# - properties: compatible: enum: @@ -36,12 +33,30 @@ properties: configured for pull up. $ref: /schemas/types.yaml#/definitions/flag + wakeup-source: + description: + Button can wake-up the system. Only applicable for 'resin', 'pwrkey' + always wakes the system by default. + linux,code: description: The input key-code associated with the power key. Use the linux event codes defined in include/dt-bindings/input/linux-event-codes.h. When property is omitted KEY_POWER is assumed. +allOf: + - $ref: input.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8941-pwrkey + - qcom,pmk8350-pwrkey + then: + properties: + wakeup-source: false + required: - compatible - interrupts -- cgit v1.2.3 From b9607ff0f86ad310f4a5e6ac985b1e89d78fd3ec Mon Sep 17 00:00:00 2001 From: Darshan Prajapati Date: Mon, 25 Aug 2025 18:54:22 +0530 Subject: dt-bindings: riscv: Add SiFive P550 CPU compatible Update Documentation for supporting SiFive P550 based CPU Signed-off-by: Darshan Prajapati Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250825132427.1618089-2-pinkesh.vaghela@einfochips.com Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 1a0cf0702a45..153d0dac57fb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -52,6 +52,7 @@ properties: - sifive,e5 - sifive,e7 - sifive,e71 + - sifive,p550 - sifive,rocket0 - sifive,s7 - sifive,u5 -- cgit v1.2.3 From 3e907d0faa798f612747cbeacb6185e9a4ee4db1 Mon Sep 17 00:00:00 2001 From: Pritesh Patel Date: Mon, 25 Aug 2025 18:54:24 +0530 Subject: dt-bindings: riscv: Add SiFive HiFive Premier P550 board Add DT binding documentation for the ESWIN EIC7700 SoC and HiFive Premier P550 Board Signed-off-by: Pritesh Patel Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Reviewed-by: Matthias Brugger Reviewed-by: Rob Herring (Arm) Acked-by: Min Lin Link: https://lore.kernel.org/r/20250825132427.1618089-4-pinkesh.vaghela@einfochips.com Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/riscv/eswin.yaml | 29 ++++++++++++++++++++++ MAINTAINERS | 7 ++++++ 2 files changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/eswin.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/riscv/eswin.yaml b/Documentation/devicetree/bindings/riscv/eswin.yaml new file mode 100644 index 000000000000..c603c45eef22 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/eswin.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/eswin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN SoC-based boards + +maintainers: + - Min Lin + - Pinkesh Vaghela + - Pritesh Patel + +description: + ESWIN SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - sifive,hifive-premier-p550 + - const: eswin,eic7700 + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 6dcfbd11efef..7d3bd754eadb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9074,6 +9074,13 @@ L: linux-can@vger.kernel.org S: Maintained F: drivers/net/can/usb/esd_usb.c +ESWIN DEVICETREES +M: Min Lin +M: Pinkesh Vaghela +M: Pritesh Patel +S: Maintained +F: Documentation/devicetree/bindings/riscv/eswin.yaml + ET131X NETWORK DRIVER M: Mark Einon S: Odd Fixes -- cgit v1.2.3 From 21b5a7ace6b2fc2fdee1eda4a802e0abfe192262 Mon Sep 17 00:00:00 2001 From: Darshan Prajapati Date: Mon, 25 Aug 2025 18:54:25 +0530 Subject: dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC Add compatible string for ESWIN EIC7700 PLIC. Signed-off-by: Darshan Prajapati Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250825132427.1618089-5-pinkesh.vaghela@einfochips.com Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 5b827bc24301..f683d696909b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -59,6 +59,7 @@ properties: - items: - enum: - canaan,k210-plic + - eswin,eic7700-plic - sifive,fu540-c000-plic - spacemit,k1-plic - starfive,jh7100-plic -- cgit v1.2.3 From 64826db1e2e177b58dcbc7cf1e1379527be2185a Mon Sep 17 00:00:00 2001 From: Harrison Carter Date: Tue, 16 Sep 2025 16:11:01 +0100 Subject: dt-bindings: leds: as3645: Convert to DT schema Convert the ams,as3645a.txt to DT Schema format. Signed-off-by: Harrison Carter Reviewed-by: "Rob Herring (Arm)" Signed-off-by: Lee Jones --- .../devicetree/bindings/leds/ams,as3645a.txt | 85 -------------- .../devicetree/bindings/leds/ams,as3645a.yaml | 130 +++++++++++++++++++++ 2 files changed, 130 insertions(+), 85 deletions(-) delete mode 100644 Documentation/devicetree/bindings/leds/ams,as3645a.txt create mode 100644 Documentation/devicetree/bindings/leds/ams,as3645a.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/leds/ams,as3645a.txt b/Documentation/devicetree/bindings/leds/ams,as3645a.txt deleted file mode 100644 index 4af2987b25e9..000000000000 --- a/Documentation/devicetree/bindings/leds/ams,as3645a.txt +++ /dev/null @@ -1,85 +0,0 @@ -Analog devices AS3645A device tree bindings - -The AS3645A flash LED controller can drive two LEDs, one high current -flash LED and one indicator LED. The high current flash LED can be -used in torch mode as well. - -Ranges below noted as [a, b] are closed ranges between a and b, i.e. a -and b are included in the range. - -Please also see common.txt in the same directory. - - -Required properties -=================== - -compatible : Must be "ams,as3645a". -reg : The I2C address of the device. Typically 0x30. -#address-cells : 1 -#size-cells : 0 - - -Required properties of the flash child node (0) -=============================================== - -reg: 0 -flash-timeout-us: Flash timeout in microseconds. The value must be in - the range [100000, 850000] and divisible by 50000. -flash-max-microamp: Maximum flash current in microamperes. Has to be - in the range between [200000, 500000] and - divisible by 20000. -led-max-microamp: Maximum torch (assist) current in microamperes. The - value must be in the range between [20000, 160000] and - divisible by 20000. -ams,input-max-microamp: Maximum flash controller input current. The - value must be in the range [1250000, 2000000] - and divisible by 50000. - - -Optional properties of the flash child node -=========================================== - -function : See Documentation/devicetree/bindings/leds/common.txt. -color : See Documentation/devicetree/bindings/leds/common.txt. -label : See Documentation/devicetree/bindings/leds/common.txt (deprecated). - - -Required properties of the indicator child node (1) -=================================================== - -reg: 1 -led-max-microamp: Maximum indicator current. The allowed values are - 2500, 5000, 7500 and 10000. - -Optional properties of the indicator child node -=============================================== - -function : See Documentation/devicetree/bindings/leds/common.txt. -color : See Documentation/devicetree/bindings/leds/common.txt. -label : See Documentation/devicetree/bindings/leds/common.txt (deprecated). - - -Example -======= - -#include - - as3645a@30 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30>; - compatible = "ams,as3645a"; - led@0 { - reg = <0x0>; - flash-timeout-us = <150000>; - flash-max-microamp = <320000>; - led-max-microamp = <60000>; - ams,input-max-microamp = <1750000>; - function = LED_FUNCTION_FLASH; - }; - led@1 { - reg = <0x1>; - led-max-microamp = <10000>; - function = LED_FUNCTION_INDICATOR; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/ams,as3645a.yaml b/Documentation/devicetree/bindings/leds/ams,as3645a.yaml new file mode 100644 index 000000000000..250a4b275d8a --- /dev/null +++ b/Documentation/devicetree/bindings/leds/ams,as3645a.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/ams,as3645a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AS3645A LED Controller + +maintainers: + - Sakari Ailus + +description: + The AS3645A flash LED controller can drive two LEDs, one + high current flash LED and one indicator LED. The high + current flash LED can be used in torch mode as well. + +properties: + compatible: + const: ams,as3645a + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + led@0: + description: led0 describes the 'flash' feature + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + const: 0 + + flash-timeout-us: + minimum: 100000 + maximum: 850000 + multipleOf: 50000 + + flash-max-microamp: + minimum: 200000 + maximum: 500000 + multipleOf: 20000 + + led-max-microamp: + minimum: 20000 + maximum: 160000 + multipleOf: 20000 + description: + Maximum current when in torch (assist) mode. + + ams,input-max-microamp: + minimum: 1250000 + maximum: 2000000 + multipleOf: 50000 + + required: + - reg + - flash-timeout-us + - flash-max-microamp + - led-max-microamp + - ams,input-max-microamp + + led@1: + description: led1 describes the 'indicator' feature + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + const: 1 + + led-max-microamp: + enum: + - 2500 + - 5000 + - 7500 + - 10000 + description: + Maximum indicator current. + + required: + - reg + - led-max-microamp + +required: + - compatible + - reg + - "#size-cells" + - "#address-cells" + +additionalProperties: false + +examples: + - | + #include + + i2c{ + #address-cells = <1>; + #size-cells = <0>; + + led-controller@30 { + compatible = "ams,as3645a"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30>; + + led@0 { + reg = <0>; + flash-timeout-us = <150000>; + flash-max-microamp = <320000>; + led-max-microamp = <60000>; + ams,input-max-microamp = <1750000>; + function = LED_FUNCTION_FLASH; + }; + + led@1 { + reg = <1>; + led-max-microamp = <10000>; + function = LED_FUNCTION_INDICATOR; + }; + }; + }; +... -- cgit v1.2.3 From 0f6eae86e626e0561d2f545a3183be2e12108410 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 12 Sep 2025 14:07:42 +0200 Subject: dt-bindings: hwmon: sl28cpld: add sa67mcu compatible The Kontron SMARC-sAM67 module features an on-board house keeping uC. It is designed to be compatible with the older sl28cpld implementation, but has different sensors, like voltage and temperature monitoring. Add a new compatible for that board. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250912120745.2295115-5-mwalle@kernel.org Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml index 010333cb25c0..ec20625db454 100644 --- a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml +++ b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - kontron,sa67mcu-hwmon - kontron,sl28cpld-fan reg: -- cgit v1.2.3 From b0b255d6b86dd1f2618a1402d6cbdcec1be0c589 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 25 Sep 2025 17:31:33 +0200 Subject: dt-bindings: touchscreen: convert eeti bindings to json schema Convert EETI touchscreen controller device tree binding to json-schema. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250925153144.4082786-1-dario.binacchi@amarulasolutions.com Signed-off-by: Dmitry Torokhov --- .../bindings/input/touchscreen/eeti,exc3000.yaml | 16 ++++++++++-- .../devicetree/bindings/input/touchscreen/eeti.txt | 30 ---------------------- 2 files changed, 14 insertions(+), 32 deletions(-) delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/eeti.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/eeti,exc3000.yaml b/Documentation/devicetree/bindings/input/touchscreen/eeti,exc3000.yaml index d19b07d4cfd4..930c70104b3f 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/eeti,exc3000.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/eeti,exc3000.yaml @@ -16,12 +16,14 @@ properties: - const: eeti,exc80h60 - const: eeti,exc80h84 - const: eeti,egalax_ts # Do NOT use for new binding + - const: eeti,exc3000-i2c + deprecated: true - items: - enum: - eeti,exc81w32 - const: eeti,exc80h84 reg: - enum: [0x4, 0x2a] + enum: [0x4, 0xa, 0x2a] interrupts: maxItems: 1 reset-gpios: @@ -30,6 +32,12 @@ properties: maxItems: 1 vdd-supply: description: Power supply regulator for the chip + attn-gpios: + deprecated: true + maxItems: 1 + description: Phandle to a GPIO to check whether interrupt is still + latched. This is necessary for platforms that lack + support for level-triggered IRQs. touchscreen-size-x: true touchscreen-size-y: true touchscreen-inverted-x: true @@ -51,7 +59,9 @@ allOf: compatible: not: contains: - const: eeti,egalax_ts + enum: + - eeti,egalax_ts + - eeti,exc3000-i2c then: properties: reg: @@ -59,6 +69,8 @@ allOf: wakeup-gpios: false + attn-gpios: false + required: - touchscreen-size-x - touchscreen-size-y diff --git a/Documentation/devicetree/bindings/input/touchscreen/eeti.txt b/Documentation/devicetree/bindings/input/touchscreen/eeti.txt deleted file mode 100644 index 32b3712c916e..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/eeti.txt +++ /dev/null @@ -1,30 +0,0 @@ -Bindings for EETI touchscreen controller - -Required properties: -- compatible: should be "eeti,exc3000-i2c" -- reg: I2C address of the chip. Should be set to <0xa> -- interrupts: interrupt to which the chip is connected - -Optional properties: -- attn-gpios: A handle to a GPIO to check whether interrupt is still - latched. This is necessary for platforms that lack - support for level-triggered IRQs. - -The following optional properties described in touchscreen.txt are -also supported: - -- touchscreen-inverted-x -- touchscreen-inverted-y -- touchscreen-swapped-x-y - -Example: - -i2c-master { - touchscreen@a { - compatible = "eeti,exc3000-i2c"; - reg = <0xa>; - interrupt-parent = <&gpio>; - interrupts = <123 IRQ_TYPE_EDGE_RISING>; - attn-gpios = <&gpio 123 GPIO_ACTIVE_HIGH>; - }; -}; -- cgit v1.2.3 From 6b4896e404c7053cf09a6f58fd09684262fab6dd Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 25 Sep 2025 17:31:34 +0200 Subject: dt-bindings: arm: bcm: raspberrypi,bcm2835-firmware: Add touchscreen child node Convert Raspberry Pi firmware 7" touchscreen controller device tree binding to json-schema. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250925153144.4082786-2-dario.binacchi@amarulasolutions.com Signed-off-by: Dmitry Torokhov --- .../arm/bcm/raspberrypi,bcm2835-firmware.yaml | 28 ++++++++++++++++++++++ .../input/touchscreen/raspberrypi,firmware-ts.txt | 26 -------------------- 2 files changed, 28 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/raspberrypi,firmware-ts.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml index 1f84407a73e4..8349c0a854d9 100644 --- a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml @@ -103,6 +103,28 @@ properties: - compatible - "#pwm-cells" + touchscreen: + type: object + $ref: /schemas/input/touchscreen/touchscreen.yaml# + additionalProperties: false + + properties: + compatible: + const: raspberrypi,firmware-ts + + firmware: + deprecated: true + description: Phandle to RPi's firmware device node. + + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-swapped-x-y: true + + required: + - compatible + required: - compatible - mboxes @@ -135,5 +157,11 @@ examples: compatible = "raspberrypi,firmware-poe-pwm"; #pwm-cells = <2>; }; + + ts: touchscreen { + compatible = "raspberrypi,firmware-ts"; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; }; ... diff --git a/Documentation/devicetree/bindings/input/touchscreen/raspberrypi,firmware-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/raspberrypi,firmware-ts.txt deleted file mode 100644 index 2a1af240ccc3..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/raspberrypi,firmware-ts.txt +++ /dev/null @@ -1,26 +0,0 @@ -Raspberry Pi firmware based 7" touchscreen -===================================== - -Required properties: - - compatible: "raspberrypi,firmware-ts" - -Optional properties: - - firmware: Reference to RPi's firmware device node - - touchscreen-size-x: See touchscreen.txt - - touchscreen-size-y: See touchscreen.txt - - touchscreen-inverted-x: See touchscreen.txt - - touchscreen-inverted-y: See touchscreen.txt - - touchscreen-swapped-x-y: See touchscreen.txt - -Example: - -firmware: firmware-rpi { - compatible = "raspberrypi,bcm2835-firmware"; - mboxes = <&mailbox>; - - ts: touchscreen { - compatible = "raspberrypi,firmware-ts"; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; -- cgit v1.2.3 From 2728e71ad67810fea8346fb800c647b66a25162d Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 25 Sep 2025 17:31:35 +0200 Subject: dt-bindings: touchscreen: remove touchscreen.txt With commit 1d6204e2f51f ("dt-bindings: touchscreen: Add touchscreen schema") touchscreen.txt is no longer needed, and since no other file refers to it, it can be safely removed. Signed-off-by: Dario Binacchi Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250925153144.4082786-3-dario.binacchi@amarulasolutions.com Signed-off-by: Dmitry Torokhov --- Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt | 1 - 1 file changed, 1 deletion(-) delete mode 100644 Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt deleted file mode 100644 index e1adb902d503..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt +++ /dev/null @@ -1 +0,0 @@ -See touchscreen.yaml -- cgit v1.2.3 From 54e184f0f5f34b0cd18623117150b52444ab6433 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 18 Aug 2025 09:39:04 +0530 Subject: dt-bindings: clock: Add RPMI clock service message proxy bindings Add device tree bindings for the RPMI clock service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley Signed-off-by: Anup Patel Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20250818040920.272664-9-apatel@ventanamicro.com Signed-off-by: Paul Walmsley --- .../bindings/clock/riscv,rpmi-mpxy-clock.yaml | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml b/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml new file mode 100644 index 000000000000..76f2a1b3d30d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/riscv,rpmi-mpxy-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/riscv,rpmi-mpxy-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI clock service group based message proxy + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines clock service group for accessing + system clocks managed by a platform microcontroller. The SBI implementation + (machine mode firmware or hypervisor) can implement an SBI MPXY channel + to allow RPMI clock service group access to the supervisor software. + + =========================================== + References + =========================================== + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the SBI implementation. + const: riscv,rpmi-mpxy-clock + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport. + + riscv,sbi-mpxy-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The SBI MPXY channel id to be used for providing RPMI access to + the supervisor software. + +required: + - compatible + - mboxes + - riscv,sbi-mpxy-channel-id + +additionalProperties: false + +examples: + - | + clock-service { + compatible = "riscv,rpmi-mpxy-clock"; + mboxes = <&rpmi_shmem_mbox 0x8>; + riscv,sbi-mpxy-channel-id = <0x1000>; + }; +... -- cgit v1.2.3 From b385830290b417c7708e2db7c0e34a0b3e7297bf Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 18 Aug 2025 09:39:05 +0530 Subject: dt-bindings: clock: Add RPMI clock service controller bindings Add device tree bindings for the RPMI clock service group based controller for the supervisor software. The RPMI clock service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Conor Dooley Reviewed-by: Stephen Boyd Signed-off-by: Anup Patel Acked-by: Jassi Brar Link: https://lore.kernel.org/r/20250818040920.272664-10-apatel@ventanamicro.com Signed-off-by: Paul Walmsley --- .../bindings/clock/riscv,rpmi-clock.yaml | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml b/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml new file mode 100644 index 000000000000..5d62bf8215c8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/riscv,rpmi-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/riscv,rpmi-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI clock service group based clock controller + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines clock service group for accessing + system clocks managed by a platform microcontroller. The supervisor + software can access RPMI clock service group via SBI MPXY channel or + some dedicated supervisor-mode RPMI transport. + + =========================================== + References + =========================================== + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the supervisor software. + const: riscv,rpmi-clock + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport or SBI message proxy channel. + + "#clock-cells": + const: 1 + description: + Platform specific CLOCK_ID as defined by the RISC-V Platform Management + Interface (RPMI) specification. + +required: + - compatible + - mboxes + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "riscv,rpmi-clock"; + mboxes = <&mpxy_mbox 0x1000 0x0>; + #clock-cells = <1>; + }; +... -- cgit v1.2.3 From 4ae50c82a5ab9071b928648da8723153004170bb Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 24 Jun 2025 12:19:44 +0530 Subject: dt-bindings: thermal: tsens: Add QCS615 compatible Add compatibility string for the thermal sensors on QCS615 platform. Acked-by: Rob Herring (Arm) Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20250624064945.764245-2-quic_gkohli@quicinc.com Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 94311ebd7652..f65dc829574c 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -54,6 +54,7 @@ properties: - qcom,msm8996-tsens - qcom,msm8998-tsens - qcom,qcm2290-tsens + - qcom,qcs615-tsens - qcom,sa8255p-tsens - qcom,sa8775p-tsens - qcom,sar2130p-tsens -- cgit v1.2.3 From aa0025154855b10b68ada4e60fd99623d51252cc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 28 Aug 2025 08:51:00 +0300 Subject: dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System Document SOCTHERM Thermal Management System found in the Tegra 4 SoC. Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250828055104.8073-3-clamor95@gmail.com Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml index cf47a1f3b384..25efedced584 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml @@ -18,6 +18,7 @@ description: The SOCTHERM IP block contains thermal sensors, support for properties: compatible: enum: + - nvidia,tegra114-soctherm - nvidia,tegra124-soctherm - nvidia,tegra132-soctherm - nvidia,tegra210-soctherm @@ -206,6 +207,7 @@ allOf: compatible: contains: enum: + - nvidia,tegra114-soctherm - nvidia,tegra124-soctherm - nvidia,tegra210-soctherm - nvidia,tegra210b01-soctherm -- cgit v1.2.3 From a3152e5c742ca2557c5cd0e5a9e6ca6b9a92df93 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Sun, 10 Aug 2025 15:21:22 +0300 Subject: dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit The Renesas RZ/G3S SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The temperature is measured using the RZ/G3S ADC, with a dedicated ADC channel directly connected to the TSU. Add documentation for it. Reviewed-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang Link: https://lore.kernel.org/r/20250810122125.792966-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Daniel Lezcano --- .../bindings/thermal/renesas,r9a08g045-tsu.yaml | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml new file mode 100644 index 000000000000..573e2b9d3752 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a08g045-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S Thermal Sensor Unit + +description: + The thermal sensor unit (TSU) measures the temperature(Tj) inside + the LSI. + +maintainers: + - Claudiu Beznea + +$ref: thermal-sensor.yaml# + +properties: + compatible: + const: renesas,r9a08g045-tsu + + reg: + maxItems: 1 + + clocks: + items: + - description: TSU module clock + + power-domains: + maxItems: 1 + + resets: + items: + - description: TSU module reset + + io-channels: + items: + - description: ADC channel which reports the TSU temperature + + io-channel-names: + items: + - const: tsu + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + - io-channels + - io-channel-names + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + #include + + tsu: thermal@10059000 { + compatible = "renesas,r9a08g045-tsu"; + reg = <0x10059000 0x1000>; + clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets = <&cpg R9A08G045_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + io-channels = <&adc 8>; + io-channel-names = "tsu"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu>; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; -- cgit v1.2.3 From e881662aa06af65021c2fa255dd7530235a3d195 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 20 Aug 2025 19:40:49 +0200 Subject: dt-bindings: thermal: rockchip: Tighten grf requirements Instead of having an optional rockchip,grf property, forbid using it on platforms without registers in a GRF being needed for thermal monitoring and make it mandatory on the platforms actually needing it. Signed-off-by: Sebastian Reichel Reviewed-by: Dragan Simic Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250820-thermal-rockchip-grf-warning-v2-3-c7e2d35017b8@kernel.org Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/thermal/rockchip-thermal.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index 573f447cc26e..9fa5c4c49d76 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -119,6 +119,21 @@ required: - resets allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-tsadc + - rockchip,rk3366-tsadc + - rockchip,rk3399-tsadc + - rockchip,rk3568-tsadc + then: + required: + - rockchip,grf + else: + properties: + rockchip,grf: false - if: not: properties: -- cgit v1.2.3 From caf41eb4575ddac61dd0f6d4a6108bb7ab9fc408 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Wed, 17 Sep 2025 19:01:55 +0200 Subject: dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit The Renesas RZ/G3E SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel (channel 1) for temperature sensing. Reviewed-by: Rob Herring (Arm) Signed-off-by: John Madieu Link: https://lore.kernel.org/r/20250917170202.197929-2-john.madieu.xa@bp.renesas.com Signed-off-by: Daniel Lezcano --- .../bindings/thermal/renesas,r9a09g047-tsu.yaml | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml new file mode 100644 index 000000000000..8d3f3c24f0f2 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E Temperature Sensor Unit (TSU) + +maintainers: + - John Madieu + +description: + The Temperature Sensor Unit (TSU) is an integrated thermal sensor that + monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides + real-time temperature measurements for thermal management. + +properties: + compatible: + const: renesas,r9a09g047-tsu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + interrupts: + items: + - description: Conversion complete interrupt signal (pulse) + - description: Comparison result interrupt signal (level) + + interrupt-names: + items: + - const: adi + - const: adcmpi + + "#thermal-sensor-cells": + const: 0 + + renesas,tsu-trim: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of trim registers + description: + Phandle and offset to the system controller containing the TSU + calibration trim values. The offset points to the first trim register + (OTPTSU1TRMVAL0), with the second trim register (OTPTSU1TRMVAL1) located + at offset + 4. + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + - renesas,tsu-trim + +additionalProperties: false + +examples: + - | + #include + #include + + thermal-sensor@14002000 { + compatible = "renesas,r9a09g047-tsu"; + reg = <0x14002000 0x1000>; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; -- cgit v1.2.3 From a72ab2514b7c8e8203c551310166f4c72262ff43 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 18 Aug 2025 09:39:07 +0530 Subject: dt-bindings: Add RPMI system MSI message proxy bindings Add device tree bindings for the RPMI system MSI service group based message proxy implemented by the SBI implementation (machine mode firmware or hypervisor). The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Atish Patra Reviewed-by: Conor Dooley Signed-off-by: Anup Patel Acked-by: Jassi Brar Link: https://lore.kernel.org/r/20250818040920.272664-12-apatel@ventanamicro.com Signed-off-by: Paul Walmsley --- .../riscv,rpmi-mpxy-system-msi.yaml | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml new file mode 100644 index 000000000000..1991f5c7446a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-mpxy-system-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI system MSI service group based message proxy + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines system MSI service group which + allow application processors to receive MSIs upon system events + such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug + event, memory hotplug event, etc from the platform microcontroller. + The SBI implementation (machine mode firmware or hypervisor) can + implement an SBI MPXY channel to allow RPMI system MSI service + group access to the supervisor software. + + =========================================== + References + =========================================== + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +properties: + compatible: + description: + Intended for use by the SBI implementation. + const: riscv,rpmi-mpxy-system-msi + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport. + + riscv,sbi-mpxy-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The SBI MPXY channel id to be used for providing RPMI access to + the supervisor software. + +required: + - compatible + - mboxes + - riscv,sbi-mpxy-channel-id + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "riscv,rpmi-mpxy-system-msi"; + mboxes = <&rpmi_shmem_mbox 0x2>; + riscv,sbi-mpxy-channel-id = <0x2000>; + }; +... -- cgit v1.2.3 From 3e6cf38486005831e063fd0d943a46bc8434e732 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 18 Aug 2025 09:39:08 +0530 Subject: dt-bindings: Add RPMI system MSI interrupt controller bindings Add device tree bindings for the RPMI system MSI service group based interrupt controller for the supervisor software. The RPMI system MSI service group is defined by the RISC-V platform management interface (RPMI) specification. Reviewed-by: Atish Patra Reviewed-by: Conor Dooley Signed-off-by: Anup Patel Acked-by: Jassi Brar Link: https://lore.kernel.org/r/20250818040920.272664-13-apatel@ventanamicro.com Signed-off-by: Paul Walmsley --- .../riscv,rpmi-system-msi.yaml | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml new file mode 100644 index 000000000000..b10a0532e586 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-system-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V RPMI system MSI service group based interrupt controller + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a + messaging protocol which is modular and extensible. The supervisor + software can send/receive RPMI messages via SBI MPXY extension [2] + or some dedicated supervisor-mode RPMI transport. + + The RPMI specification [1] defines system MSI service group which + allow application processors to receive MSIs upon system events + such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug + event, memory hotplug event, etc from the platform microcontroller. + The supervisor software can access RPMI system MSI service group via + SBI MPXY channel or some dedicated supervisor-mode RPMI transport. + + =========================================== + References + =========================================== + + [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) + https://github.com/riscv-non-isa/riscv-rpmi/releases + + [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) + https://github.com/riscv-non-isa/riscv-sbi-doc/releases + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + description: + Intended for use by the supervisor software. + const: riscv,rpmi-system-msi + + mboxes: + maxItems: 1 + description: + Mailbox channel of the underlying RPMI transport or SBI message proxy channel. + + msi-parent: true + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - mboxes + - msi-parent + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible = "riscv,rpmi-system-msi"; + mboxes = <&mpxy_mbox 0x2000 0x0>; + msi-parent = <&imsic_slevel>; + interrupt-controller; + #interrupt-cells = <1>; + }; +... -- cgit v1.2.3 From 76bb6969a8cfc5e00ca142fdad86ffd0a6ed9ecd Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 25 Sep 2025 15:22:19 -0400 Subject: dt-bindings: hwmon: (lm75) allow interrupt for ti,tmp75 Allow interrupt for ti,tmp75 because chip has open drain ALERT signal. Signed-off-by: Frank Li Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250925192219.303825-1-Frank.Li@nxp.com Signed-off-by: Guenter Roeck --- Documentation/devicetree/bindings/hwmon/lm75.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/hwmon/lm75.yaml b/Documentation/devicetree/bindings/hwmon/lm75.yaml index ecdd09a032e5..0b9fda81e3ec 100644 --- a/Documentation/devicetree/bindings/hwmon/lm75.yaml +++ b/Documentation/devicetree/bindings/hwmon/lm75.yaml @@ -70,6 +70,7 @@ allOf: - ti,tmp100 - ti,tmp101 - ti,tmp112 + - ti,tmp75 then: properties: interrupts: false -- cgit v1.2.3 From 79428e60897916401c9ed326f6ada4d7c7c997a3 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Sat, 20 Sep 2025 18:06:31 +0530 Subject: dt-bindings: thermal: qcom-tsens: Document the Glymur temperature Sensor Document the Temperature Sensor (TSENS) on Glymur Platform. Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Pankaj Patil Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250920123631.281153-1-pankaj.patil@oss.qualcomm.com Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index f65dc829574c..78e2f6573b96 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -49,6 +49,7 @@ properties: - description: v2 of TSENS items: - enum: + - qcom,glymur-tsens - qcom,milos-tsens - qcom,msm8953-tsens - qcom,msm8996-tsens -- cgit v1.2.3 From ad9a8291b13b985852ad617827a4c5265a8836f5 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 30 Apr 2025 13:27:35 -0500 Subject: dt-bindings: edac: Convert aspeed,ast2400-sdram-edac to DT schema Convert the ASpeed SDRAM EDAC binding to DT schema. It's a straight-forward conversion. Reviewed-by: Andrew Jeffery Reviewed-by: Stefan Schaeckeler Signed-off-by: Rob Herring (Arm) --- .../bindings/edac/aspeed,ast2400-sdram-edac.yaml | 48 ++++++++++++++++++++++ .../devicetree/bindings/edac/aspeed-sdram-edac.txt | 28 ------------- MAINTAINERS | 2 +- 3 files changed, 49 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml delete mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml new file mode 100644 index 000000000000..09735826d707 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/aspeed,ast2400-sdram-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed BMC SoC SDRAM EDAC controller + +maintainers: + - Stefan Schaeckeler + +description: > + The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error + correction check). + + The memory controller supports SECDED (single bit error correction, double bit + error detection) and single bit error auto scrubbing by reserving 8 bits for + every 64 bit word (effectively reducing available memory to 8/9). + + Note, the bootloader must configure ECC mode in the memory controller. + +properties: + compatible: + enum: + - aspeed,ast2400-sdram-edac + - aspeed,ast2500-sdram-edac + - aspeed,ast2600-sdram-edac + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + }; diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt deleted file mode 100644 index 8ca9e0a049d8..000000000000 --- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt +++ /dev/null @@ -1,28 +0,0 @@ -Aspeed BMC SoC EDAC node - -The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error -correction check). - -The memory controller supports SECDED (single bit error correction, double bit -error detection) and single bit error auto scrubbing by reserving 8 bits for -every 64 bit word (effectively reducing available memory to 8/9). - -Note, the bootloader must configure ECC mode in the memory controller. - - -Required properties: -- compatible: should be one of - - "aspeed,ast2400-sdram-edac" - - "aspeed,ast2500-sdram-edac" - - "aspeed,ast2600-sdram-edac" -- reg: sdram controller register set should be <0x1e6e0000 0x174> -- interrupts: should be AVIC interrupt #0 - - -Example: - - edac: sdram@1e6e0000 { - compatible = "aspeed,ast2500-sdram-edac"; - reg = <0x1e6e0000 0x174>; - interrupts = <0>; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 4ee1f658c3c2..85eca954284d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8695,7 +8695,7 @@ F: drivers/edac/armada_xp_* EDAC-AST2500 M: Stefan Schaeckeler S: Supported -F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt +F: Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml F: drivers/edac/aspeed_edac.c EDAC-BLUEFIELD -- cgit v1.2.3 From b518ec73cc62fe3f921ea6c009628a40c927d92c Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Sun, 14 Sep 2025 16:14:52 +0300 Subject: dt-bindings: gpu: arm,mali-midgard: add exynos8890-mali compatible The exynos8890 uses the ARM Mali T880 GPU, document its compatible string with the appropriate fallback. Signed-off-by: Ivaylo Ivanov Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 48daba21a890..a7192622e120 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -53,8 +53,10 @@ properties: - enum: - rockchip,rk3399-mali - const: arm,mali-t860 - - # "arm,mali-t880" + - items: + - enum: + - samsung,exynos8890-mali + - const: arm,mali-t880 reg: maxItems: 1 -- cgit v1.2.3 From 60042a6ff2348fd2edca2f31e79fe80548d1a75d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 15 Sep 2025 11:51:23 -0400 Subject: dt-bindings: display: simple: Add innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 Add innolux,n133hse-ea1 13.3" TFT LCD panel and nlt,nl12880bc20-spwg-24 12.1" WXGA (1280 x 800) LVDS TFT LCD panel. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-novena.dtb: /panel: failed to match any schema with compatible: ['innolux,n133hse-ea1'] arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dtb: /lvds0-panel: failed to match any schema with compatible: ['nlt,nl12880bc20-spwg-24'] Signed-off-by: Frank Li Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 1ac1f0219079..42d9080e8b83 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -178,6 +178,8 @@ properties: - innolux,g121xce-l01 # InnoLux 15.6" FHD (1920x1080) TFT LCD panel - innolux,g156hce-l01 + # InnoLux 13.3" FHD (1920x1080) TFT LCD panel + - innolux,n133hse-ea1 # InnoLux 15.6" WXGA TFT LCD panel - innolux,n156bge-l21 # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel @@ -228,6 +230,8 @@ properties: - netron-dy,e231732 # Newhaven Display International 480 x 272 TFT LCD panel - newhaven,nhd-4.3-480272ef-atxl + # NLT Technologies, Ltd. 12.1" WXGA (1280 x 800) LVDS TFT LCD panel + - nlt,nl12880bc20-spwg-24 # NLT Technologies, Ltd. 15.6" WXGA (1366×768) LVDS TFT LCD panel - nlt,nl13676bc25-03f # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel -- cgit v1.2.3 From c502ca1ea1b9a7ed4b9665bed48bc1d8887639b3 Mon Sep 17 00:00:00 2001 From: sheetal Date: Thu, 18 Sep 2025 15:50:08 +0530 Subject: dt-bindings: interrupt-controller: arm,gic: Add tegra264-agic Add nvidia,tegra264-agic to the arm,gic binding for tegra264 audio interrupt controller support. Signed-off-by: sheetal Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index 7173c4b5a228..ee4c77dac201 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -59,6 +59,7 @@ properties: - nvidia,tegra186-agic - nvidia,tegra194-agic - nvidia,tegra234-agic + - nvidia,tegra264-agic - const: nvidia,tegra210-agic interrupt-controller: true -- cgit v1.2.3 From 4379fbb9b06c8c17dac63652cfc2a7ada96c5074 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 18 Sep 2025 19:32:49 +0530 Subject: dt-bindings: interrupt-controller: qcom,pdc: Document Glymur PDC Document compatible for the Power Domain Controller(PDC) block on Glymur.PDC acts as interrupt controller in SoC states where GIC is non-operational. Signed-off-by: Pankaj Patil Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index f06b40f88778..38d0c2d57dd6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,glymur-pdc - qcom,qcs615-pdc - qcom,qcs8300-pdc - qcom,qdu1000-pdc -- cgit v1.2.3 From 069862313db33a2b68ebf9e92ac13b73ef12f2af Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:37 +0200 Subject: dt-bindings: display: mediatek: dpi: Allow specifying resets Even though the DPI IP has a reset bit on all MediaTek SoCs, it is optional, and has always been unused until MT8195; specifically: on older SoCs, like MT8173, the reset bit is located in MMSYS, and on newer SoCs, like MT8195, it is located in VDOSYS. For this reason, allow specifying the resets and reset-names on all MediaTek SoCs. Those properties are optional because there are multiple ways to reset this IP and the reset lines in MM/VDO are used only if the IP cannot perform warm-reset. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index b659d79393a8..eb4f276e8dc4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -102,6 +102,13 @@ properties: - port@0 - port@1 + resets: + maxItems: 1 + + reset-names: + items: + - const: dpi + required: - compatible - reg -- cgit v1.2.3 From c1f7800c9c70c67d5feea2d9acaac004086d41d2 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:42 +0200 Subject: dt-bindings: timer: mediatek: Add compatible for MT6795 GP Timer Add a compatible for the General Purpose Timer (GPT) found on the MediaTek Helio X10 MT6795 SoC which is fully compatible with the one found in MT6577. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Acked-by: Rob Herring (Arm) Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/timer/mediatek,timer.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml index f68fc7050c56..42d81073a49d 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml +++ b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt6580-timer - mediatek,mt6582-timer - mediatek,mt6589-timer + - mediatek,mt6795-timer - mediatek,mt7623-timer - mediatek,mt8127-timer - mediatek,mt8135-timer -- cgit v1.2.3 From 8d200dff1e8e0cb521dd48ba1d5424be400cd9bc Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:43 +0200 Subject: dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2 The MT7622 SoC has a PWM channel 7-2 group for the pwm7 IP: add the missing pwm_ch7_2 group. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 9acca85184fa..57b19031925d 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -204,7 +204,7 @@ patternProperties: pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0, pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1, pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3, - pwm_ch7_0, pwm_0, pwm_1] + pwm_ch7_0, pwm_ch7_2, pwm_0, pwm_1] - if: properties: function: -- cgit v1.2.3 From 8e0118a79bda64aad3ae72dd80c814c1978460ea Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:44 +0200 Subject: dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg The pin controller for both MT7622 and MT7629 need both a "base" and an "eint" MMIO like the ones found on other MediaTek SoCs: while devicetrees have always been correct, the binding is not, as it only allows an "eint" reg. Add "base" to reg-names and increment maxItems for reg to two. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 57b19031925d..6b925c5099cc 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -19,10 +19,11 @@ properties: - mediatek,mt7629-pinctrl reg: - maxItems: 1 + maxItems: 2 reg-names: items: + - const: base - const: eint gpio-controller: true @@ -367,7 +368,8 @@ examples: pio: pinctrl@10211000 { compatible = "mediatek,mt7622-pinctrl"; - reg = <0 0x10211000 0 0x1000>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10005000 0 0x1000>; gpio-controller; #gpio-cells = <2>; -- cgit v1.2.3 From 41663b33cda3a70c719f82f4f62c2f54b16fad5b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:46 +0200 Subject: dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible This binding had no compatible and for this reason would not be applied to anything: add the missing "mediatek,mt6332-regulator" compatible. Fixes: e22943e32e1f regulator: ("Add bindings for MT6332 regulator") Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml index 2eb512c29a0d..475f18d4f261 100644 --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml @@ -15,6 +15,10 @@ description: | buck- and ldo-. MT6332 regulators node should be sub node of the MT6397 MFD node. +properties: + compatible: + const: mediatek,mt6332-regulator + patternProperties: "^buck-v(dram|dvfs2|pa|rf18a|rf18b|sbst)$": type: object @@ -36,6 +40,9 @@ patternProperties: unevaluatedProperties: false +required: + - compatible + additionalProperties: false examples: -- cgit v1.2.3 From e29e64fb9c58ce92cb8316cd6a939bd3e49b7f63 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:47 +0200 Subject: dt-bindings: regulator: mediatek,mt6331: Fix various regulator names This binding was never applied to anything because it misses the compatible, hence any mistake in it got unnoticed. Before adding the compatible to let it apply, fix the names and the node names of various regulators. Fixes: 6385e21692bb ("regulator: Add bindings for MT6331 regulator") Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Rob Herring (Arm) --- .../bindings/regulator/mediatek,mt6331-regulator.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml index 79e5198e1c73..6006a973b865 100644 --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml @@ -26,23 +26,23 @@ patternProperties: unevaluatedProperties: false - "^ldo-v(avdd32aud|auxa32)$": + "^ldo-(avdd32aud|vauxa32)$": type: object $ref: regulator.yaml# properties: regulator-name: - pattern: "^v(avdd32aud|auxa32)$" + pattern: "^(avdd32_aud|vauxa32)$" unevaluatedProperties: false - "^ldo-v(dig18|emc33|ibr|mc|mch|mipi|rtc|sram|usb10)$": + "^ldo-v(dig18|emc33|ibr|mc|mch|mipi|rtc|sim1|sim2|sram|usb10)$": type: object $ref: regulator.yaml# properties: regulator-name: - pattern: "^v(dig18|emc33|ibr|mc|mch|mipi|rtc|sram|usb10)$" + pattern: "^v(dig18|emc33|ibr|mc|mch|mipi|rtc|sim1|sim2|sram|usb)$" unevaluatedProperties: false @@ -52,7 +52,7 @@ patternProperties: properties: regulator-name: - pattern: "^vcam(a|af|d|io)$" + pattern: "^vcam(a|_af|d|io)$" unevaluatedProperties: false @@ -75,7 +75,7 @@ patternProperties: properties: regulator-name: - pattern: "^vgp[12]$" + pattern: "^vgp[1234]$" required: - regulator-name -- cgit v1.2.3 From 1a8493e06b854b05263071a5db77488cb9c07972 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:48 +0200 Subject: dt-bindings: regulator: mediatek,mt6331: Add missing compatible This binding had no compatible and for this reason would not be applied to anything: add the missing "mediatek,mt6331-regulator" comaptible. Fixes: 6385e21692bb ("regulator: Add bindings for MT6331 regulator") Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml index 6006a973b865..c654acf13768 100644 --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml @@ -15,6 +15,10 @@ description: | buck- and ldo-. MT6331 regulators node should be sub node of the MT6397 MFD node. +properties: + compatible: + const: mediatek,mt6331-regulator + patternProperties: "^buck-v(core2|io18|dvfs11|dvfs12|dvfs13|dvfs14)$": type: object @@ -82,6 +86,9 @@ patternProperties: unevaluatedProperties: false +required: + - compatible + additionalProperties: false examples: -- cgit v1.2.3 From a31c2f8e2b6af2e45d5e8016e5055b2b00b4d6c5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:39 +0200 Subject: dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional The GCE Mailbox needs only one clock and the clock-names can be used only by the driver (which, for instance, does not use it), and this is true for all of the currently supported MediaTek SoCs. Stop requiring to specify clock-names on all non-MT8195 GCEs. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Acked-by: Rob Herring (Arm) Reviewed-by: Chen-Yu Tsai Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml index 73d6db34d64a..587126d03fc6 100644 --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml @@ -60,17 +60,6 @@ required: - interrupts - clocks -allOf: - - if: - not: - properties: - compatible: - contains: - const: mediatek,mt8195-gce - then: - required: - - clock-names - additionalProperties: false examples: -- cgit v1.2.3 From 37020f865aa3c4049266cb34cf83ef299184ae80 Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Tue, 26 Aug 2025 09:39:36 +0200 Subject: dt-bindings: arm: mediatek: Support mt8183-audiosys variant Update the mediatek,audsys binding to support the mt8183-audiosys compatible, which uses a different audio controller (mediatek,mt8183-audio.yaml) compared to the legacy mt2701-audio controller. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Julien Massot Signed-off-by: Rob Herring (Arm) --- .../bindings/arm/mediatek/mediatek,audsys.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml index 45d4a6620041..f3a761cbd0fd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt7622-audsys - mediatek,mt8167-audsys - mediatek,mt8173-audsys + - mediatek,mt8183-audiosys - mediatek,mt8183-audsys - mediatek,mt8186-audsys - mediatek,mt8192-audsys @@ -41,13 +42,26 @@ properties: const: 1 audio-controller: - $ref: /schemas/sound/mediatek,mt2701-audio.yaml# type: object required: - compatible - '#clock-cells' +if: + properties: + compatible: + contains: + const: mediatek,mt8183-audiosys +then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt8183-audio.yaml# +else: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + additionalProperties: false examples: -- cgit v1.2.3 From 49ceb031b6c139e17e069b25506a4c283fd22595 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Thu, 11 Sep 2025 12:09:51 -0300 Subject: dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema Convert the existing text-based DT bindings for Mediatek MT8173 Video Processor Unit to a DT schema. Signed-off-by: Ariel D'Alessandro Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski [robh: update MAINTAINERS and mediatek-mdp.txt references] Signed-off-by: Rob Herring (Arm) --- .../bindings/media/mediatek,mt8173-vpu.yaml | 74 ++++++++++++++++++++++ .../devicetree/bindings/media/mediatek-mdp.txt | 3 +- .../devicetree/bindings/media/mediatek-vpu.txt | 31 --------- MAINTAINERS | 2 +- 4 files changed, 77 insertions(+), 33 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml delete mode 100644 Documentation/devicetree/bindings/media/mediatek-vpu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml new file mode 100644 index 000000000000..8a47761f1e6b --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8173-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8173 Video Processor Unit + +maintainers: + - Ariel D'Alessandro + +description: + Video Processor Unit is a HW video controller. It controls HW Codec including + H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color + convert). + +properties: + compatible: + const: mediatek,mt8173-vpu + + reg: + maxItems: 2 + + reg-names: + items: + - const: tcm + - const: cfg_reg + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: main + + memory-region: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - memory-region + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + vpu: vpu@10020000 { + compatible = "mediatek,mt8173-vpu"; + reg = <0 0x10020000 0 0x30000>, + <0 0x10050000 0 0x100>; + reg-names = "tcm", "cfg_reg"; + interrupts = ; + clocks = <&topckgen CLK_TOP_SCP_SEL>; + clock-names = "main"; + memory-region = <&vpu_dma_reserved>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/mediatek-mdp.txt b/Documentation/devicetree/bindings/media/mediatek-mdp.txt index 53ef26e2c857..253a93eabb5e 100644 --- a/Documentation/devicetree/bindings/media/mediatek-mdp.txt +++ b/Documentation/devicetree/bindings/media/mediatek-mdp.txt @@ -5,7 +5,8 @@ Media Data Path is used for scaling and color space conversion. Required properties (controller node): - compatible: "mediatek,mt8173-mdp" - mediatek,vpu: the node of video processor unit, see - Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. + Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml for + details. Required properties (all function blocks, child node): - compatible: Should be one of diff --git a/Documentation/devicetree/bindings/media/mediatek-vpu.txt b/Documentation/devicetree/bindings/media/mediatek-vpu.txt deleted file mode 100644 index 2a5bac37f9a2..000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-vpu.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Mediatek Video Processor Unit - -Video Processor Unit is a HW video controller. It controls HW Codec including -H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert). - -Required properties: - - compatible: "mediatek,mt8173-vpu" - - reg: Must contain an entry for each entry in reg-names. - - reg-names: Must include the following entries: - "tcm": tcm base - "cfg_reg": Main configuration registers base - - interrupts: interrupt number to the cpu. - - clocks : clock name from clock manager - - clock-names: must be main. It is the main clock of VPU - -Optional properties: - - memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) - to be used for VPU extended memory; if not present, VPU may be located - anywhere in the memory - -Example: - vpu: vpu@10020000 { - compatible = "mediatek,mt8173-vpu"; - reg = <0 0x10020000 0 0x30000>, - <0 0x10050000 0 0x100>; - reg-names = "tcm", "cfg_reg"; - interrupts = ; - clocks = <&topckgen TOP_SCP_SEL>; - clock-names = "main"; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 85eca954284d..3c1970f96d99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15540,7 +15540,7 @@ M: Andrew-CT Chen M: Yunfei Dong S: Supported F: Documentation/devicetree/bindings/media/mediatek,vcodec*.yaml -F: Documentation/devicetree/bindings/media/mediatek-vpu.txt +F: Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml F: drivers/media/platform/mediatek/vcodec/ F: drivers/media/platform/mediatek/vpu/ -- cgit v1.2.3 From d0b5a39acd079bccaebbb0d94bfd4649359951c2 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Thu, 11 Sep 2025 12:09:57 -0300 Subject: dt-bindings: pinctrl: mt65xx: Allow gpio-line-names Current, the DT bindings for MediaTek's MT65xx Pin controller is missing the gpio-line-names property, add it to the associated schema. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Linus Walleij Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index b9680b896f12..aa71398cf522 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -43,6 +43,8 @@ properties: the amount of cells must be specified as 2. See the below mentioned gpio binding representation for description of particular cells. + gpio-line-names: true + mediatek,pctl-regmap: $ref: /schemas/types.yaml#/definitions/phandle-array items: -- cgit v1.2.3 From 18b26b15178386eb82bca4b23b03e96ca9317d36 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Thu, 11 Sep 2025 12:10:00 -0300 Subject: dt-bindings: soc: mediatek: pwrap: Add power-domains property Currently, the DT bindings for Mediatek PMIC Wrapper is missing the power-domains property, which is used in the MT8173 E1 evaluation board as it needs USB power domain. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index 4737e5f45d54..54c0cd64d309 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -98,6 +98,9 @@ properties: - const: pwrap - const: pwrap-bridge + power-domains: + maxItems: 1 + pmic: type: object @@ -126,6 +129,18 @@ allOf: clock-names: minItems: 4 + - if: + properties: + compatible: + contains: + const: mediatek,mt8173-pwrap + then: + properties: + power-domains: true + else: + properties: + power-domains: false + additionalProperties: false examples: -- cgit v1.2.3 From 4fea3336ef57295b989a6b2db4a6946a06e4c787 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 23 Sep 2025 16:41:18 -0400 Subject: dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c Add compatible string synaptics,synaptics_i2c for synaptics touch pad. It match existed driver drivers/input/mouse/synaptics_i2c.c. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ Documentation/devicetree/bindings/vendor-prefixes.yaml | 3 +++ 2 files changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index f3dd18681aa6..8db4596c616b 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -395,6 +395,8 @@ properties: - sparkfun,qwiic-joystick # Sierra Wireless mangOH Green SPI IoT interface - swir,mangoh-iotport-spi + # Synaptics I2C touchpad + - synaptics,synaptics_i2c # Ambient Light Sensor with SMBUS/Two Wire Serial Interface - taos,tsl2550 # Digital PWM System Controller PMBus diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 0f5273123650..699560820fdf 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1552,6 +1552,9 @@ patternProperties: description: Sierra Wireless "^syna,.*": description: Synaptics Inc. + "^synaptics,.*": + description: Synaptics Inc. + deprecated: true "^synology,.*": description: Synology, Inc. "^synopsys,.*": -- cgit v1.2.3 From 86eedc669a56e5607c253253d7b466a5b8d70fc8 Mon Sep 17 00:00:00 2001 From: Markus Heidelberg Date: Fri, 26 Sep 2025 12:57:47 +0200 Subject: docs: dt: fix grammar and spelling Signed-off-by: Markus Heidelberg Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/of_unittest.rst | 4 ++-- Documentation/devicetree/overlay-notes.rst | 6 +++--- Documentation/devicetree/usage-model.rst | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/of_unittest.rst b/Documentation/devicetree/of_unittest.rst index a6c05962add3..8b557acd29d1 100644 --- a/Documentation/devicetree/of_unittest.rst +++ b/Documentation/devicetree/of_unittest.rst @@ -56,7 +56,7 @@ drivers/of/unittest.c. See the content of the folder:: for the Device Tree Source Include files (.dtsi) included in testcases.dts. -When the kernel is build with CONFIG_OF_UNITTEST enabled, then the following make +When the kernel is built with CONFIG_OF_UNITTEST enabled, then the following make rule:: $(obj)/%.dtb: $(src)/%.dts FORCE @@ -133,7 +133,7 @@ via the following kernel symbols:: __dtb_testcases_end - address marking the end of test data blob Secondly, it calls of_fdt_unflatten_tree() to unflatten the flattened -blob. And finally, if the machine's device tree (i.e live tree) is present, +blob. And finally, if the machine's device tree (i.e. live tree) is present, then it attaches the unflattened test data tree to the live tree, else it attaches itself as a live device tree. diff --git a/Documentation/devicetree/overlay-notes.rst b/Documentation/devicetree/overlay-notes.rst index 35e79242af9a..ba401ef850e7 100644 --- a/Documentation/devicetree/overlay-notes.rst +++ b/Documentation/devicetree/overlay-notes.rst @@ -14,11 +14,11 @@ How overlays work A Devicetree's overlay purpose is to modify the kernel's live tree, and have the modification affecting the state of the kernel in a way that is reflecting the changes. -Since the kernel mainly deals with devices, any new device node that result +Since the kernel mainly deals with devices, any new device node that results in an active device should have it created while if the device node is either disabled or removed all together, the affected device should be deregistered. -Lets take an example where we have a foo board with the following base tree:: +Let's take an example where we have a foo board with the following base tree:: ---- foo.dts --------------------------------------------------------------- /* FOO platform */ @@ -111,7 +111,7 @@ The API is quite easy to use. 1) Call of_overlay_fdt_apply() to create and apply an overlay changeset. The return value is an error or a cookie identifying this overlay. -2) Call of_overlay_remove() to remove and cleanup the overlay changeset +2) Call of_overlay_remove() to remove and clean up the overlay changeset previously created via the call to of_overlay_fdt_apply(). Removal of an overlay changeset that is stacked by another will not be permitted. diff --git a/Documentation/devicetree/usage-model.rst b/Documentation/devicetree/usage-model.rst index 0717426856b2..c6146c96ac56 100644 --- a/Documentation/devicetree/usage-model.rst +++ b/Documentation/devicetree/usage-model.rst @@ -46,7 +46,7 @@ The DT was originally created by Open Firmware as part of the communication method for passing data from Open Firmware to a client program (like to an operating system). An operating system used the Device Tree to discover the topology of the hardware at runtime, and -thereby support a majority of available hardware without hard coded +thereby supported a majority of available hardware without hard coded information (assuming drivers were available for all devices). Since Open Firmware is commonly used on PowerPC and SPARC platforms, @@ -128,7 +128,7 @@ successor, the BeagleBoard xM board might look like, respectively:: compatible = "ti,omap3-beagleboard-xm", "ti,omap3450", "ti,omap3"; Where "ti,omap3-beagleboard-xm" specifies the exact model, it also -claims that it compatible with the OMAP 3450 SoC, and the omap3 family +claims that it is compatible with the OMAP 3450 SoC, and the omap3 family of SoCs in general. You'll notice that the list is sorted from most specific (exact board) to least specific (SoC family). @@ -205,7 +205,7 @@ platform-specific configuration data. During early boot, the architecture setup code calls of_scan_flat_dt() several times with different helper callbacks to parse device tree -data before paging is setup. The of_scan_flat_dt() code scans through +data before paging is set up. The of_scan_flat_dt() code scans through the device tree and uses the helpers to extract information required during early boot. Typically the early_init_dt_scan_chosen() helper is used to parse the chosen node including kernel parameters, -- cgit v1.2.3 From d6f57d8c5a5aede34c72382cdbd5b35616e171e6 Mon Sep 17 00:00:00 2001 From: Markus Heidelberg Date: Fri, 26 Sep 2025 12:57:48 +0200 Subject: dt-bindings: fix spelling, typos, grammar, duplicated words Signed-off-by: Markus Heidelberg Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 2 +- Documentation/devicetree/bindings/example-schema.yaml | 2 +- Documentation/devicetree/bindings/gpio/gpio.txt | 12 ++++++------ Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +- Documentation/devicetree/bindings/leds/common.yaml | 2 +- Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml | 2 +- Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml | 2 +- Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml | 2 +- .../devicetree/bindings/mmc/mmc-controller-common.yaml | 4 ++-- .../devicetree/bindings/net/amlogic,meson-dwmac.yaml | 2 +- .../devicetree/bindings/net/ethernet-controller.yaml | 2 +- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 2 +- Documentation/devicetree/bindings/net/micrel-ksz90x1.txt | 4 ++-- Documentation/devicetree/bindings/net/micrel.txt | 2 +- Documentation/devicetree/bindings/submitting-patches.rst | 2 +- 15 files changed, 22 insertions(+), 22 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 89298b39903f..4cdca5320544 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -140,7 +140,7 @@ patternProperties: the connection between the motherboard and any tiles. Sometimes the compatible is placed directly under this node, sometimes it is placed in a subnode named "motherboard-bus". Sometimes the compatible includes - "arm,vexpress,v2?-p1" sometimes (on software models) is is just + "arm,vexpress,v2?-p1" sometimes (on software models) it is just "simple-bus". If the compatible is placed in the "motherboard-bus" node, it is stricter and always has two compatibles. type: object diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index c731d5045e80..b04f3cc4312c 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -223,7 +223,7 @@ required: # # For multiple 'if' schema, group them under an 'allOf'. # -# If the conditionals become too unweldy, then it may be better to just split +# If the conditionals become too unwieldy, then it may be better to just split # the binding into separate schema documents. allOf: - if: diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index d82c32217fff..b37dbb1edc62 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -35,8 +35,8 @@ and bit-banged data signals: <&gpio1 15 0>; In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is -a local offset to the GPIO line and the second cell represent consumer flags, -such as if the consumer desire the line to be active low (inverted) or open +a local offset to the GPIO line and the second cell represents consumer flags, +such as if the consumer desires the line to be active low (inverted) or open drain. This is the recommended practice. The exact meaning of each specifier cell is controller specific, and must be @@ -59,7 +59,7 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. Optional standard bitfield specifiers for the last cell: - Bit 0: 0 means active high, 1 means active low -- Bit 1: 0 mean push-pull wiring, see: +- Bit 1: 0 means push-pull wiring, see: https://en.wikipedia.org/wiki/Push-pull_output 1 means single-ended wiring, see: https://en.wikipedia.org/wiki/Single-ended_triode @@ -176,7 +176,7 @@ example of a name from an SoC's reference manual) would not be desirable. In either case placeholders are discouraged: rather use the "" (blank string) if the use of the GPIO line is undefined in your design. Ideally, -try to add comments to the dts file describing the naming the convention +try to add comments to the dts file describing the naming convention you have chosen, and specifying from where the names are derived. The names are assigned starting from line offset 0, from left to right, @@ -304,7 +304,7 @@ pins 50..69. It is also possible to use pin groups for gpio ranges when pin groups are the easiest and most convenient mapping. -Both both and must set to 0 when using named pin groups +Both and must be set to 0 when using named pin groups names. The property gpio-ranges-group-names must contain exactly one string for each @@ -313,7 +313,7 @@ range. Elements of gpio-ranges-group-names must contain the name of a pin group defined in the respective pin controller. The number of pins/GPIO lines in the range is the number of pins in that pin group. The number of pins of that -group is defined int the implementation and not in the device tree. +group is defined in the implementation and not in the device tree. If numerical and named pin groups are mixed, the string corresponding to a numerical pin range in gpio-ranges-group-names must be empty. diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 75750c64157c..f49ed8ac4776 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -52,7 +52,7 @@ description: |+ As above, The Multimedia HW will go through SMI and M4U while it access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain smi local arbiter and smi common. It will control whether the Multimedia - HW should go though the m4u for translation or bypass it and talk + HW should go through the m4u for translation or bypass it and talk directly with EMI. And also SMI help control the power domain and clocks for each local arbiter. diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml index 3e8319e44339..274f83288a92 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -62,7 +62,7 @@ properties: default-state: description: The initial state of the LED. If the LED is already on or off and the - default-state property is set the to same value, then no glitch should be + default-state property is set to the same value, then no glitch should be produced where the LED momentarily turns off (or on). The "keep" setting will keep the LED at whatever its current state is, without producing a glitch. diff --git a/Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml b/Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml index ae149eb8593d..ca72786b0e0d 100644 --- a/Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml @@ -26,7 +26,7 @@ properties: '#gpio-cells': description: The first cell is the pin number. - The second cell is is used to specify flags. + The second cell is used to specify flags. See ../gpio/gpio.txt for more information. const: 2 diff --git a/Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml b/Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml index 5167d6eb904a..885e33276b1b 100644 --- a/Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml @@ -26,7 +26,7 @@ properties: '#gpio-cells': description: The first cell is the pin number. - The second cell is is used to specify flags. + The second cell is used to specify flags. See ../gpio/gpio.txt for more information. const: 2 diff --git a/Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml b/Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml index eca430edf608..2b5b54aa6c73 100644 --- a/Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml @@ -28,7 +28,7 @@ properties: '#gpio-cells': description: The first cell is the pin number. - The second cell is is used to specify flags. + The second cell is used to specify flags. See ../gpio/gpio.txt for more information. const: 2 diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml index 9a7235439759..1e601da0339a 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -57,7 +57,7 @@ properties: # latter case. We choose to use the XOR logic for GPIO CD and WP # lines. This means, the two properties are "superimposed," for # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the - # respective *-inverted property property results in a + # respective *-inverted property results in a # double-inversion and actually means the "normal" line polarity is # in effect. wp-inverted: @@ -264,7 +264,7 @@ properties: mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay waiting for I/O signalling and card power supply to be stable, regardless of whether pwrseq-simple is used. Default to 10ms if - no available. + not available. default: 10 supports-cqe: diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index 0cd78d71768c..5c91716d1f21 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -149,7 +149,7 @@ properties: - description: The first register range should be the one of the DWMAC controller - description: - The second range is is for the Amlogic specific configuration + The second range is for the Amlogic specific configuration (for example the PRG_ETHERNET register range on Meson8b and newer) interrupts: diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 66b1cfbbfe22..341f4938c956 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -222,7 +222,7 @@ properties: reg: maxItems: 1 description: - This define the LED index in the PHY or the MAC. It's really + This defines the LED index in the PHY or the MAC. It's really driver dependent and required for ports that define multiple LED for the same port. diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 71e2cd32580f..2ec2d9fda7e3 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -266,7 +266,7 @@ properties: reg: maxItems: 1 description: - This define the LED index in the PHY or the MAC. It's really + This defines the LED index in the PHY or the MAC. It's really driver dependent and required for ports that define multiple LED for the same port. diff --git a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt index 2681168777a1..6f7b907d5a04 100644 --- a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt +++ b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt @@ -13,7 +13,7 @@ KSZ9021: All skew control options are specified in picoseconds. The minimum value is 0, the maximum value is 3000, and it can be specified in 200ps - steps, *but* these values are in not fact what you get because this chip's + steps, *but* these values are in no way what you get because this chip's skew values actually increase in 120ps steps, starting from -840ps. The incorrect values came from an error in the original KSZ9021 datasheet before it was corrected in revision 1.2 (Feb 2014), but it is too late to @@ -153,7 +153,7 @@ KSZ9031: - micrel,force-master: Boolean, force phy to master mode. Only set this option if the phy reference clock provided at CLK125_NDO pin is used as MAC reference - clock because the clock jitter in slave mode is to high (errata#2). + clock because the clock jitter in slave mode is too high (errata#2). Attention: The link partner must be configurable as slave otherwise no link will be established. diff --git a/Documentation/devicetree/bindings/net/micrel.txt b/Documentation/devicetree/bindings/net/micrel.txt index a407dd1b4614..01622ce58112 100644 --- a/Documentation/devicetree/bindings/net/micrel.txt +++ b/Documentation/devicetree/bindings/net/micrel.txt @@ -26,7 +26,7 @@ Optional properties: Setting the RMII Reference Clock Select bit enables 25 MHz rather than 50 MHz clock mode. - Note that this option in only needed for certain PHY revisions with a + Note that this option is only needed for certain PHY revisions with a non-standard, inverted function of this configuration bit. Specifically, a clock reference ("rmii-ref" below) is always needed to actually select a mode. diff --git a/Documentation/devicetree/bindings/submitting-patches.rst b/Documentation/devicetree/bindings/submitting-patches.rst index 46d0b036c97e..5f24570f72e9 100644 --- a/Documentation/devicetree/bindings/submitting-patches.rst +++ b/Documentation/devicetree/bindings/submitting-patches.rst @@ -95,7 +95,7 @@ II. For kernel maintainers For subsystem bindings (anything affecting more than a single device), getting a devicetree maintainer to review it is required. - 3) For a series going though multiple trees, the binding patch should be + 3) For a series going through multiple trees, the binding patch should be kept with the driver using the binding. 4) The DTS files should however never be applied via driver subsystem tree, -- cgit v1.2.3 From 74459b0dacced28542b631abf89bc24456c7f789 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 23 Sep 2025 16:55:48 -0400 Subject: dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml Convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml format. Additional changes: - Only keep one example. Signed-off-by: Frank Li Signed-off-by: Rob Herring (Arm) --- .../bridge/megachips,stdp2690-ge-b850v3-fw.yaml | 111 +++++++++++++++++++++ .../bridge/megachips-stdpxxxx-ge-b850v3-fw.txt | 91 ----------------- 2 files changed, 111 insertions(+), 91 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml delete mode 100644 Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml b/Documentation/devicetree/bindings/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml new file mode 100644 index 000000000000..dfa6ff6f115e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GE B850v3 video bridge + +maintainers: + - Frank Li + +description: | + STDP4028-ge-b850v3-fw bridges (LVDS-DP) + STDP2690-ge-b850v3-fw bridges (DP-DP++) + + The video processing pipeline on the second output on the GE B850v3: + + Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output + + Each bridge has a dedicated flash containing firmware for supporting the custom + design. The result is that, in this design, neither the STDP4028 nor the + STDP2690 behave as the stock bridges would. The compatible strings include the + suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with + the firmware specific for the GE B850v3. + + The hardware do not provide control over the video processing pipeline, as the + two bridges behaves as a single one. The only interfaces exposed by the + hardware are EDID, HPD, and interrupts. + +properties: + compatible: + enum: + - megachips,stdp4028-ge-b850v3-fw + - megachips,stdp2690-ge-b850v3-fw + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + description: sink port + $ref: /schemas/graph.yaml#/properties/port + + port@1: + description: source port + $ref: /schemas/graph.yaml#/properties/port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: megachips,stdp4028-ge-b850v3-fw + then: + required: + - interrupts + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@73 { + compatible = "megachips,stdp4028-ge-b850v3-fw"; + reg = <0x73>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&lvds0_out>; + }; + + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&stdp2690_in>; + }; + }; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt b/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt deleted file mode 100644 index 09e0a21f705e..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt +++ /dev/null @@ -1,91 +0,0 @@ -Drivers for the second video output of the GE B850v3: - STDP4028-ge-b850v3-fw bridges (LVDS-DP) - STDP2690-ge-b850v3-fw bridges (DP-DP++) - -The video processing pipeline on the second output on the GE B850v3: - - Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output - -Each bridge has a dedicated flash containing firmware for supporting the custom -design. The result is that, in this design, neither the STDP4028 nor the -STDP2690 behave as the stock bridges would. The compatible strings include the -suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with -the firmware specific for the GE B850v3. - -The hardware do not provide control over the video processing pipeline, as the -two bridges behaves as a single one. The only interfaces exposed by the -hardware are EDID, HPD, and interrupts. - -stdp4028-ge-b850v3-fw required properties: - - compatible : "megachips,stdp4028-ge-b850v3-fw" - - reg : I2C bus address - - interrupts : one interrupt should be described here, as in - <0 IRQ_TYPE_LEVEL_HIGH> - - ports : One input port(reg = <0>) and one output port(reg = <1>) - -stdp2690-ge-b850v3-fw required properties: - compatible : "megachips,stdp2690-ge-b850v3-fw" - - reg : I2C bus address - - ports : One input port(reg = <0>) and one output port(reg = <1>) - -Example: - -&mux2_i2c2 { - clock-frequency = <100000>; - - stdp4028@73 { - compatible = "megachips,stdp4028-ge-b850v3-fw"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0x73>; - - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - stdp4028_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - port@1 { - reg = <1>; - stdp4028_out: endpoint { - remote-endpoint = <&stdp2690_in>; - }; - }; - }; - }; - - stdp2690@72 { - compatible = "megachips,stdp2690-ge-b850v3-fw"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0x72>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - stdp2690_in: endpoint { - remote-endpoint = <&stdp4028_out>; - }; - }; - - port@1 { - reg = <1>; - stdp2690_out: endpoint { - /* Connector for external display */ - }; - }; - }; - }; -}; -- cgit v1.2.3 From 33b6c8ed1ddd6118fbc150269cd2201462fbd7e6 Mon Sep 17 00:00:00 2001 From: Kael D'Alcamo Date: Wed, 24 Sep 2025 16:09:22 +0200 Subject: dt-bindings: vendor-prefixes: update regex for properties without a prefix Update vendor-prefixes.yaml to allow property names without a prefix to contain '#' character in all positions Signed-off-by: Kael D'Alcamo Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 699560820fdf..6ce9de649f4b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1862,7 +1862,7 @@ patternProperties: # Normal property name match without a comma # These should catch all node/property names without a prefix - "^[a-zA-Z0-9#_][a-zA-Z0-9+\\-._@]{0,63}$": true + "^[a-zA-Z0-9#_][a-zA-Z0-9#+\\-._@]{0,63}$": true "^[a-zA-Z0-9+\\-._]*@[0-9a-zA-Z,]*$": true "^#.*": true -- cgit v1.2.3 From 532a94352fca6b51f49d1cd9f0e4250ade49b8b2 Mon Sep 17 00:00:00 2001 From: Kael D'Alcamo Date: Wed, 24 Sep 2025 16:09:20 +0200 Subject: dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema Convert the Devicetree binding documentation for: * SUNW,n2-rng * SUNW,vf-rng * SUNW,kt-rng * ORCL,m4-rng * ORCL,m7-rng from plain text to YAML. Signed-off-by: Kael D'Alcamo Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/rng/SUNW,n2-rng.yaml | 50 ++++++++++++++++++++++ .../bindings/rng/sparc_sun_oracle_rng.txt | 30 ------------- 2 files changed, 50 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/rng/SUNW,n2-rng.yaml delete mode 100644 Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/SUNW,n2-rng.yaml b/Documentation/devicetree/bindings/rng/SUNW,n2-rng.yaml new file mode 100644 index 000000000000..6eafc532dc76 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/SUNW,n2-rng.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/SUNW,n2-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SUN UltraSPARC HWRNG + +maintainers: + - David S. Miller + +properties: + compatible: + enum: + - SUNW,n2-rng # for Niagara 2 Platform (SUN UltraSPARC T2 CPU) + - SUNW,vf-rng # for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU) + # for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), + # (UltraSPARC KT/Niagara 3 - development names) + # more recent systems (after Oracle acquisition of SUN) + - SUNW,kt-rng + - ORCL,m4-rng # for SPARC T5/M5 + - ORCL,m7-rng # for SPARC T7/M7 + + reg: + maxItems: 1 + + "rng-#units": + description: Number of RNG units + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + +required: + - compatible + - reg + +additionalProperties: false + +# PS: see as well prtconfs.git by DaveM +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + rng@e { + compatible = "ORCL,m4-rng"; + reg = <0xe>; + rng-#units = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt b/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt deleted file mode 100644 index b0b211194c71..000000000000 --- a/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt +++ /dev/null @@ -1,30 +0,0 @@ -HWRNG support for the n2_rng driver - -Required properties: -- reg : base address to sample from -- compatible : should contain one of the following - RNG versions: - - 'SUNW,n2-rng' for Niagara 2 Platform (SUN UltraSPARC T2 CPU) - - 'SUNW,vf-rng' for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU) - - 'SUNW,kt-rng' for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), (UltraSPARC KT/Niagara 3 - development names) - more recent systems (after Oracle acquisition of SUN) - - 'ORCL,m4-rng' for SPARC T5/M5 - - 'ORCL,m7-rng' for SPARC T7/M7 - -Examples: -/* linux LDOM on SPARC T5-2 */ -Node 0xf029a4f4 - .node: f029a4f4 - rng-#units: 00000002 - compatible: 'ORCL,m4-rng' - reg: 0000000e - name: 'random-number-generator' - -/* solaris on SPARC M7-8 */ -Node 0xf028c08c - rng-#units: 00000003 - compatible: 'ORCL,m7-rng' - reg: 0000000e - name: 'random-number-generator' - -PS: see as well prtconfs.git by DaveM -- cgit v1.2.3 From 267bca002c504b6c656c23dc973a34ddaededbce Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 25 Sep 2025 15:19:49 +0200 Subject: dt-bindings: net: sparx5: correct LAN969x register space windows LAN969x needs only 2 register space windows as GCB is already covered by the "devices" register space window, so expect only 2 "reg" and "reg-names" properties. Fixes: 41c6439fdc2b ("dt-bindings: net: add compatible strings for lan969x targets") Signed-off-by: Robert Marko Acked-by: Conor Dooley Link: https://patch.msgid.link/20250925132109.583984-1-robert.marko@sartura.hr Signed-off-by: Jakub Kicinski --- .../bindings/net/microchip,sparx5-switch.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index 082982c59a55..5caa3779660d 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -55,12 +55,14 @@ properties: - const: microchip,lan9691-switch reg: + minItems: 2 items: - description: cpu target - description: devices target - description: general control block target reg-names: + minItems: 2 items: - const: cpu - const: devices @@ -168,6 +170,26 @@ required: - interrupt-names - ethernet-ports +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,lan9691-switch + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + additionalProperties: false examples: -- cgit v1.2.3 From 96a17ed17b369109b662b40345df961b412c1cd3 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Fri, 19 Sep 2025 19:53:25 +0530 Subject: dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller On the Qualcomm Glymur platform, the fifth PCIe host is compatible with the DWC controller present on the X1E80100 platform, but does not have cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six. Signed-off-by: Qiang Yu Signed-off-by: Pankaj Patil Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250919142325.1090059-1-pankaj.patil@oss.qualcomm.com --- Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index 257068a18264..61581ffbfb24 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -32,10 +32,11 @@ properties: - const: mhi # MHI registers clocks: - minItems: 7 + minItems: 6 maxItems: 7 clock-names: + minItems: 6 items: - const: aux # Auxiliary clock - const: cfg # Configuration clock -- cgit v1.2.3 From d1a7be736ca9b89c32023185fa95c0df02f6db27 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 24 Sep 2025 17:35:49 -0500 Subject: dt-bindings: gpu: Convert nvidia,gk20a to DT schema Convert the NVIDIA GPU binding to DT schema format. Add undocumented "interconnects" and "interconnect-names" properties for gp10b and gv11b. Drop all but one example. Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/gpu/nvidia,gk20a.txt | 115 -------------- .../devicetree/bindings/gpu/nvidia,gk20a.yaml | 171 +++++++++++++++++++++ 2 files changed, 171 insertions(+), 115 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt create mode 100644 Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt deleted file mode 100644 index cc6ce5221a38..000000000000 --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt +++ /dev/null @@ -1,115 +0,0 @@ -NVIDIA Tegra Graphics Processing Units - -Required properties: -- compatible: "nvidia," - Currently recognized values: - - nvidia,gk20a - - nvidia,gm20b - - nvidia,gp10b - - nvidia,gv11b -- reg: Physical base address and length of the controller's registers. - Must contain two entries: - - first entry for bar0 - - second entry for bar1 -- interrupts: Must contain an entry for each entry in interrupt-names. - See ../interrupt-controller/interrupts.txt for details. -- interrupt-names: Must include the following entries: - - stall - - nonstall -- vdd-supply: regulator for supply voltage. Only required for GPUs not using - power domains. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - gpu - - pwr -If the compatible string is "nvidia,gm20b", then the following clock -is also required: - - ref -If the compatible string is "nvidia,gv11b", then the following clock is also -required: - - fuse -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - gpu -- power-domains: GPUs that make use of power domains can define this property - instead of vdd-supply. Currently "nvidia,gp10b" makes use of this. - -Optional properties: -- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details. - -Example for GK20A: - - gpu@57000000 { - compatible = "nvidia,gk20a"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - vdd-supply = <&vdd_gpu>; - clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - iommus = <&mc TEGRA_SWGROUP_GPU>; - }; - -Example for GM20B: - - gpu@57000000 { - compatible = "nvidia,gm20b"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA210_CLK_GPU>, - <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, - <&tegra_car TEGRA210_CLK_PLL_G_REF>; - clock-names = "gpu", "pwr", "ref"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - iommus = <&mc TEGRA_SWGROUP_GPU>; - }; - -Example for GP10B: - - gpu@17000000 { - compatible = "nvidia,gp10b"; - reg = <0x0 0x17000000 0x0 0x1000000>, - <0x0 0x18000000 0x0 0x1000000>; - interrupts = ; - interrupt-names = "stall", "nonstall"; - clocks = <&bpmp TEGRA186_CLK_GPCCLK>, - <&bpmp TEGRA186_CLK_GPU>; - clock-names = "gpu", "pwr"; - resets = <&bpmp TEGRA186_RESET_GPU>; - reset-names = "gpu"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; - iommus = <&smmu TEGRA186_SID_GPU>; - }; - -Example for GV11B: - - gpu@17000000 { - compatible = "nvidia,gv11b"; - reg = <0x17000000 0x1000000>, - <0x18000000 0x1000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&bpmp TEGRA194_CLK_GPCCLK>, - <&bpmp TEGRA194_CLK_GPU_PWR>, - <&bpmp TEGRA194_CLK_FUSE>; - clock-names = "gpu", "pwr", "fuse"; - resets = <&bpmp TEGRA194_RESET_GPU>; - reset-names = "gpu"; - dma-coherent; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; - iommus = <&smmu TEGRA194_SID_GPU>; - }; diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml new file mode 100644 index 000000000000..4d856a8b674c --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/nvidia,gk20a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Graphics Processing Units + +maintainers: + - Alexandre Courbot + - Jon Hunter + - Thierry Reding + +properties: + compatible: + enum: + - nvidia,gk20a + - nvidia,gm20b + - nvidia,gp10b + - nvidia,gv11b + + reg: + items: + - description: Bar0 register window + - description: Bar1 register window + + interrupts: + items: + - description: Stall interrupt + - description: Nonstall interrupt + + interrupt-names: + items: + - const: stall + - const: nonstall + + vdd-supply: + description: + Regulator for GPU supply voltage + + clocks: + minItems: 2 + items: + - description: GPU clock + - description: Power clock + - description: Reference or fuse clock + + clock-names: + minItems: 2 + items: + - const: gpu + - const: pwr + - enum: [ ref, fuse ] + + resets: + maxItems: 1 + + reset-names: + items: + - const: gpu + + power-domains: + maxItems: 1 + + interconnects: + minItems: 4 + maxItems: 12 + + interconnect-names: + minItems: 4 + maxItems: 12 + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,gp10b + - nvidia,gv11b + then: + required: + - power-domains + else: + properties: + interconnects: false + interconnect-names: false + + required: + - vdd-supply + - if: + properties: + compatible: + contains: + enum: + - nvidia,gp10b + then: + properties: + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: dma-mem + - const: write-0 + - const: read-1 + - const: write-1 + - if: + properties: + compatible: + contains: + enum: + - nvidia,gv11b + then: + properties: + interconnects: + minItems: 12 + + interconnect-names: + items: + - const: dma-mem + - const: read-0-hp + - const: write-0 + - const: read-1 + - const: read-1-hp + - const: write-1 + - const: read-2 + - const: read-2-hp + - const: write-2 + - const: read-3 + - const: read-3-hp + - const: write-3 + +additionalProperties: false + +examples: + - | + #include + #include + #include + + gpu@57000000 { + compatible = "nvidia,gk20a"; + reg = <0x57000000 0x01000000>, + <0x58000000 0x01000000>; + interrupts = , + ; + interrupt-names = "stall", "nonstall"; + vdd-supply = <&vdd_gpu>; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + clock-names = "gpu", "pwr"; + resets = <&tegra_car 184>; + reset-names = "gpu"; + iommus = <&mc TEGRA_SWGROUP_GPU>; + }; -- cgit v1.2.3 From 8d5868f8c1b27e99b35d200b5ed2dfe12586e936 Mon Sep 17 00:00:00 2001 From: Jonas Rebmann Date: Wed, 24 Sep 2025 10:34:12 +0200 Subject: dt-bindings: net: dsa: nxp,sja1105: Add reset-gpios property Both the nxp,sja1105 and the nxp,sja1110 series feature an active-low reset pin, rendering reset-gpios a valid property for all of the nxp,sja1105 family. Acked-by: Vladimir Oltean Reviewed-by: Rob Herring (Arm) Reviewed-by: Frank Li Signed-off-by: Jonas Rebmann Link: https://patch.msgid.link/20250924-imx8mp-prt8ml-v3-1-f498d7f71a94@pengutronix.de Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml index 9432565f4f5d..e9dd914b0734 100644 --- a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml +++ b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml @@ -32,6 +32,15 @@ properties: reg: maxItems: 1 + reset-gpios: + description: + A GPIO connected to the active-low RST_N pin of the SJA1105. Note that + reset of this chip is performed via SPI and the RST_N pin must be wired + to satisfy the power-up sequence documented in "SJA1105PQRS Application + Hints" (AH1704) sec. 2.4.4. Connecting the SJA1105 RST_N pin to a GPIO is + therefore discouraged. + maxItems: 1 + spi-cpha: true spi-cpol: true -- cgit v1.2.3 From 9665aa15ef8bdf1fa596f9ff8162e9c5e00ac036 Mon Sep 17 00:00:00 2001 From: Théo Lebrun Date: Tue, 23 Sep 2025 18:00:23 +0200 Subject: dt-bindings: net: cdns,macb: allow tsu_clk without tx_clk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow providing tsu_clk without a tx_clk as both are optional. This is about relaxing unneeded constraints. It so happened that in the past HW that needed a tsu_clk always needed a tx_clk. Fixes: 4e5b6de1f46d ("dt-bindings: net: cdns,macb: Convert to json-schema") Reviewed-by: Krzysztof Kozlowski Acked-by: Nicolas Ferre Signed-off-by: Théo Lebrun Link: https://patch.msgid.link/20250923-macb-fixes-v6-1-772d655cdeb6@bootlin.com Signed-off-by: Jakub Kicinski --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index 559d0f733e7e..6e20d67e7628 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -85,7 +85,7 @@ properties: items: - enum: [ ether_clk, hclk, pclk ] - enum: [ hclk, pclk ] - - const: tx_clk + - enum: [ tx_clk, tsu_clk ] - enum: [ rx_clk, tsu_clk ] - const: tsu_clk -- cgit v1.2.3 From ec67ef0a501d7dc915d84c0ada4ab3697adfa1d9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 11 Jun 2025 13:08:00 +0200 Subject: dt-bindings: i2c: i2c-mt65xx: Add MediaTek MT8196/6991 compatibles Add support for the MediaTek MT8196 Chromebook SoC and for its close relative, the MediaTek Dimensity 9400 MT6991 SoC. Those chips' multiple I2C controller instances are compatible with the ones found in the MT8188 SoC. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley [wsa: rebased] Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index bd6811cbde70..3562ce0c0f7e 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -53,6 +53,8 @@ properties: - items: - enum: - mediatek,mt6878-i2c + - mediatek,mt6991-i2c + - mediatek,mt8196-i2c - const: mediatek,mt8188-i2c - items: - enum: -- cgit v1.2.3 From 166c83f7789ed02dc1f25bc7bed4a1beb25343aa Mon Sep 17 00:00:00 2001 From: Kael D'Alcamo Date: Sun, 21 Sep 2025 18:11:34 +0200 Subject: dt-bindings: rng: hisi-rng: convert to DT schema Convert the Devicetree binding documentation for hisilicon,hip04-rng and hisilicon,hip05-rng from plain text to YAML. Signed-off-by: Kael D'Alcamo Reviewed-by: Rob Herring (Arm) Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/rng/hisi-rng.txt | 12 -------- .../devicetree/bindings/rng/hisi-rng.yaml | 32 ++++++++++++++++++++++ 2 files changed, 32 insertions(+), 12 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rng/hisi-rng.txt create mode 100644 Documentation/devicetree/bindings/rng/hisi-rng.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/hisi-rng.txt b/Documentation/devicetree/bindings/rng/hisi-rng.txt deleted file mode 100644 index d04d55a6c2f5..000000000000 --- a/Documentation/devicetree/bindings/rng/hisi-rng.txt +++ /dev/null @@ -1,12 +0,0 @@ -Hisilicon Random Number Generator - -Required properties: -- compatible : Should be "hisilicon,hip04-rng" or "hisilicon,hip05-rng" -- reg : Offset and length of the register set of this block - -Example: - -rng@d1010000 { - compatible = "hisilicon,hip05-rng"; - reg = <0xd1010000 0x100>; -}; diff --git a/Documentation/devicetree/bindings/rng/hisi-rng.yaml b/Documentation/devicetree/bindings/rng/hisi-rng.yaml new file mode 100644 index 000000000000..5406b2596f42 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/hisi-rng.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/hisi-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Random Number Generator + +maintainers: + - Kefeng Wang + +properties: + compatible: + enum: + - hisilicon,hip04-rng + - hisilicon,hip05-rng + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rng@d1010000 { + compatible = "hisilicon,hip05-rng"; + reg = <0xd1010000 0x100>; + }; -- cgit v1.2.3 From 9fbad55d6f9db98ab9f1d48ac5e5f8f72fbac0cc Mon Sep 17 00:00:00 2001 From: Griffin Kroah-Hartman Date: Sat, 27 Sep 2025 21:11:55 -0700 Subject: dt-bindings: input: Add Awinic AW86927 Add bindings for the Awinic AW86927 haptic chip which can be found in smartphones. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Griffin Kroah-Hartman Link: https://lore.kernel.org/r/20250925-aw86927-v3-1-1fc6265b42de@fairphone.com Signed-off-by: Dmitry Torokhov --- .../devicetree/bindings/input/awinic,aw86927.yaml | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/awinic,aw86927.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/awinic,aw86927.yaml b/Documentation/devicetree/bindings/input/awinic,aw86927.yaml new file mode 100644 index 000000000000..b7252916bd72 --- /dev/null +++ b/Documentation/devicetree/bindings/input/awinic,aw86927.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/awinic,aw86927.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW86927 LRA Haptic IC + +maintainers: + - Griffin Kroah-Hartman + +properties: + compatible: + const: awinic,aw86927 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + vibrator@5a { + compatible = "awinic,aw86927"; + reg = <0x5a>; + interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; + }; + }; -- cgit v1.2.3 From 064a97a29e3ba0e5d75b3b8ad5b762962aaad8ab Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 12 Sep 2025 14:07:43 +0200 Subject: dt-bindings: watchdog: add SMARC-sAM67 support The SMARC-sAM67 board has an on-board uC which has the same register interface as the older CPLD implementation on the SMARC-sAL28 board. Although the MCU emulates the same behavior, be prepared for any quirks and add a board specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Reviewed-by: Guenter Roeck Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- .../devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml index 179272f74de5..b5b624e85468 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -18,7 +18,12 @@ allOf: properties: compatible: - const: kontron,sl28cpld-wdt + oneOf: + - items: + - enum: + - kontron,sa67mcu-wdt + - const: kontron,sl28cpld-wdt + - const: kontron,sl28cpld-wdt reg: maxItems: 1 -- cgit v1.2.3 From 129b91fc329604e05f794dc1a18a6da3eb518b4e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 26 Sep 2025 16:47:37 -0500 Subject: dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt The contents of arm/altera/socfpga-sdram-edac.txt are already covered by edac/altr,socfpga-ecc-manager.yaml except for the "altr,sdram-edac" compatible string. Add the compatible and drop the old .txt binding doc. Acked-by: Matthew Gerlach Signed-off-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/altera/socfpga-sdram-edac.txt | 15 --------------- .../bindings/edac/altr,socfpga-ecc-manager.yaml | 1 + 2 files changed, 1 insertion(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt deleted file mode 100644 index f5ad0ff69fae..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt +++ /dev/null @@ -1,15 +0,0 @@ -Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] -The EDAC accesses a range of registers in the SDRAM controller. - -Required properties: -- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10" -- altr,sdr-syscon : phandle of the sdr module -- interrupts : Should contain the SDRAM ECC IRQ in the - appropriate format for the IRQ controller. - -Example: - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; - }; diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml index ec4634c5fa89..3d787dea0f14 100644 --- a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml +++ b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml @@ -53,6 +53,7 @@ properties: properties: compatible: enum: + - altr,sdram-edac - altr,sdram-edac-a10 - altr,sdram-edac-s10 -- cgit v1.2.3 From 12bfcb84dc0852c97baff9ac1c0292a9db90c367 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Fri, 19 Sep 2025 03:52:00 -0400 Subject: dt-bindings: mtd: Add realtek,rtl9301-ecc Add a dtschema for the ECC engine on the Realtek RTL93xx SoCs. The engine supports BCH6 and BCH12 parity for 512 byte blocks. The hardware can make use of interrupts but this is not yet supported by the driver. From the known datasheets it is connected to the LXB (lexra bus) and propably depends on its clock. Provide an optional clock property that can describe the relation. Signed-off-by: Markus Stockhausen Reviewed-by: Rob Herring (Arm) Signed-off-by: Miquel Raynal --- .../bindings/mtd/realtek,rtl9301-ecc.yaml | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/realtek,rtl9301-ecc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/realtek,rtl9301-ecc.yaml b/Documentation/devicetree/bindings/mtd/realtek,rtl9301-ecc.yaml new file mode 100644 index 000000000000..55b35c3db0ff --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/realtek,rtl9301-ecc.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/realtek,rtl9301-ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek SoCs NAND ECC engine + +maintainers: + - Markus Stockhausen + +properties: + compatible: + const: realtek,rtl9301-ecc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + ecc0: ecc@1a600 { + compatible = "realtek,rtl9301-ecc"; + reg = <0x1a600 0x54>; + }; + }; -- cgit v1.2.3 From d9fcb34f8b3bf793fadb591aafc76f27ecb48ff0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 26 Sep 2025 03:15:58 +0800 Subject: dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Reviewed-by: Rob Herring (Arm) Acked-by: Conor Dooley Signed-off-by: Chen-Yu Tsai Link: https://patch.msgid.link/20250925191600.3306595-2-wens@kernel.org Signed-off-by: Paolo Abeni --- .../bindings/net/allwinner,sun8i-a83t-emac.yaml | 95 +++++++++++++++++++++- 1 file changed, 93 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 2ac709a4c472..fc62fb2a68ac 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -10,6 +10,21 @@ maintainers: - Chen-Yu Tsai - Maxime Ripard +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-emac + - allwinner,sun8i-h3-emac + - allwinner,sun8i-r40-gmac + - allwinner,sun8i-v3s-emac + - allwinner,sun50i-a64-emac + - allwinner,sun55i-a523-gmac200 + required: + - compatible + properties: compatible: oneOf: @@ -26,6 +41,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a reg: maxItems: 1 @@ -37,14 +55,21 @@ properties: const: macirq clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 clock-names: - const: stmmaceth + minItems: 1 + items: + - const: stmmaceth + - const: mbus phy-supply: description: PHY regulator + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -191,6 +216,42 @@ allOf: - mdio-parent-bus - mdio@1 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 700 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 3100 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + power-domains: false + + unevaluatedProperties: false examples: @@ -323,4 +384,34 @@ examples: }; }; + - | + ethernet@4510000 { + compatible = "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg = <0x04510000 0x10000>; + clocks = <&ccu 117>, <&ccu 79>; + clock-names = "stmmaceth", "mbus"; + resets = <&ccu 43>; + reset-names = "stmmaceth"; + interrupts = <0 47 4>; + interrupt-names = "macirq"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins>; + power-domains = <&pck600 4>; + syscon = <&syscon>; + phy-handle = <&ext_rgmii_phy_1>; + phy-mode = "rgmii-id"; + snps,fixed-burst; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; ... -- cgit v1.2.3 From 9d602da0c9919f36d55b051951c1fd4f3dc24593 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 30 Jul 2025 19:34:22 +0200 Subject: dt-bindings: mfd: qnap,ts433-mcu: Add qnap,ts233-mcu compatible The same MCU is used on other devices of the series with a slightly different set of features, like the number of LEDs. Add a compatible for the MCU used in the TS233 variant. Signed-off-by: Heiko Stuebner Acked-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250730173423.1878599-2-heiko@sntech.de Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml b/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml index 877078ac172f..fe9e06cfb933 100644 --- a/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml +++ b/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qnap,ts233-mcu - qnap,ts433-mcu patternProperties: -- cgit v1.2.3 From 597b398bc27c84f3998c2169ad7ce74e8404533a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 30 Jul 2025 19:22:47 +0200 Subject: dt-bindings: mfd: qnap,ts433-mcu: Allow nvmem-layout child node The MCU has an eeprom memory connected internally, that for example contains some mac-addresses for the soc gmac controllers. Therefore allow defining the nvmem-layout for the eeprom. Signed-off-by: Heiko Stuebner Acked-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250730172248.1875122-2-heiko@sntech.de Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml b/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml index fe9e06cfb933..5454d9403cad 100644 --- a/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml +++ b/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml @@ -19,6 +19,9 @@ properties: - qnap,ts233-mcu - qnap,ts433-mcu + nvmem-layout: + $ref: /schemas/nvmem/layouts/nvmem-layout.yaml + patternProperties: "^fan-[0-9]+$": $ref: /schemas/hwmon/fan-common.yaml# -- cgit v1.2.3 From 58091331b59eebc9bf725178be87021d20e4ec2d Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 7 Aug 2025 08:29:08 -0500 Subject: dt-bindings: mfd: aspeed-lpc: Add missing "clocks" property on lpc-snoop node The ASpeed lpc-snoop nodes have a "clocks" property which isn't documented. It looks like all the LPC child devices have the same clock source. Perhaps it is the parent device that should have the clock, but it's too late for that. The driver for lpc-snoop requires a clock to be present. Signed-off-by: "Rob Herring (Arm)" Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/20250807132909.3291770-1-robh@kernel.org Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml index d88854e60b7f..f329223cec07 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml @@ -137,6 +137,9 @@ patternProperties: reg: maxItems: 1 + clocks: + maxItems: 1 + interrupts: maxItems: 1 -- cgit v1.2.3 From c1c8ed81e200126b711ee5b012e1fa9a0da2cbe1 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 12 Aug 2025 15:33:18 -0500 Subject: dt-bindings: mfd: syscon: Add "marvell,armada-3700-usb2-host-device-misc" compatible Add the "marvell,armada-3700-usb2-host-device-misc" compatible which is already in use. Signed-off-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250812203319.729300-1-robh@kernel.org Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 27672adeb1fe..1f381d159af8 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -79,6 +79,7 @@ select: - marvell,armada-3700-cpu-misc - marvell,armada-3700-nb-pm - marvell,armada-3700-avs + - marvell,armada-3700-usb2-host-device-misc - marvell,armada-3700-usb2-host-misc - marvell,dove-global-config - mediatek,mt2701-pctl-a-syscfg @@ -185,6 +186,7 @@ properties: - marvell,armada-3700-cpu-misc - marvell,armada-3700-nb-pm - marvell,armada-3700-avs + - marvell,armada-3700-usb2-host-device-misc - marvell,armada-3700-usb2-host-misc - marvell,dove-global-config - mediatek,mt2701-pctl-a-syscfg -- cgit v1.2.3 From 3d6a17fccc2832d8bc84420a634330941509d6e1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Aug 2025 10:12:02 +0200 Subject: dt-bindings: mfd: Move embedded controllers to own directory Move several embedded controller bindings (like ChromeOS EC, Gateworks System Controller and Kontron sl28cpld Board Management) to new subdirectory "embedded-controller" matching their purpose. An embedded controller (EC) is a discrete component that contains a microcontroller (i.e. a small CPU running a small firmware without operating system) mounted into a larger computer system running a fully fledged operating system that needs to utilize the embedded controller as part of its operation. So far the EC bindings were split between "mfd" and "platform" directory. MFD name comes from Linux, not hardware, and "platform" is a bit too generic. Rename Gateworks GSC and Huawei Gaokun filenames to match compatible, as preferred for bindings. Acked-by: Michael Walle # for sl28cpld Reviewed-by: Linus Walleij Signed-off-by: Krzysztof Kozlowski Acked-by: Mark Brown Reviewed-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250825081201.9775-2-krzysztof.kozlowski@linaro.org Signed-off-by: Lee Jones --- .../embedded-controller/acer,aspire1-ec.yaml | 60 ++++ .../embedded-controller/google,cros-ec.yaml | 326 +++++++++++++++++++++ .../bindings/embedded-controller/gw,gsc.yaml | 193 ++++++++++++ .../embedded-controller/huawei,gaokun3-ec.yaml | 124 ++++++++ .../embedded-controller/kontron,sl28cpld.yaml | 153 ++++++++++ .../embedded-controller/lenovo,yoga-c630-ec.yaml | 83 ++++++ .../embedded-controller/microsoft,surface-sam.yaml | 47 +++ .../bindings/gpio/kontron,sl28cpld-gpio.yaml | 2 +- .../bindings/hwmon/kontron,sl28cpld-hwmon.yaml | 2 +- .../kontron,sl28cpld-intc.yaml | 2 +- .../devicetree/bindings/mfd/gateworks-gsc.yaml | 193 ------------ .../devicetree/bindings/mfd/google,cros-ec.yaml | 326 --------------------- .../devicetree/bindings/mfd/kontron,sl28cpld.yaml | 153 ---------- .../bindings/platform/acer,aspire1-ec.yaml | 60 ---- .../bindings/platform/huawei,gaokun-ec.yaml | 124 -------- .../bindings/platform/lenovo,yoga-c630-ec.yaml | 83 ------ .../bindings/platform/microsoft,surface-sam.yaml | 47 --- .../bindings/pwm/google,cros-ec-pwm.yaml | 2 +- .../bindings/pwm/kontron,sl28cpld-pwm.yaml | 2 +- .../devicetree/bindings/remoteproc/mtk,scp.yaml | 4 +- .../bindings/sound/google,cros-ec-codec.yaml | 2 +- .../bindings/watchdog/kontron,sl28cpld-wdt.yaml | 2 +- MAINTAINERS | 6 +- 23 files changed, 998 insertions(+), 998 deletions(-) create mode 100644 Documentation/devicetree/bindings/embedded-controller/acer,aspire1-ec.yaml create mode 100644 Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml create mode 100644 Documentation/devicetree/bindings/embedded-controller/gw,gsc.yaml create mode 100644 Documentation/devicetree/bindings/embedded-controller/huawei,gaokun3-ec.yaml create mode 100644 Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml create mode 100644 Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-c630-ec.yaml create mode 100644 Documentation/devicetree/bindings/embedded-controller/microsoft,surface-sam.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/google,cros-ec.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml delete mode 100644 Documentation/devicetree/bindings/platform/acer,aspire1-ec.yaml delete mode 100644 Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml delete mode 100644 Documentation/devicetree/bindings/platform/lenovo,yoga-c630-ec.yaml delete mode 100644 Documentation/devicetree/bindings/platform/microsoft,surface-sam.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/embedded-controller/acer,aspire1-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/acer,aspire1-ec.yaml new file mode 100644 index 000000000000..01ee61768527 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/acer,aspire1-ec.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/acer,aspire1-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Acer Aspire 1 Embedded Controller + +maintainers: + - Nikita Travkin + +description: + The Acer Aspire 1 laptop uses an embedded controller to control battery + and charging as well as to provide a set of misc features such as the + laptop lid status and HPD events for the USB Type-C DP alt mode. + +properties: + compatible: + const: acer,aspire1-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + + connector: + $ref: /schemas/connector/usb-connector.yaml# + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@76 { + compatible = "acer,aspire1-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 30 IRQ_TYPE_LEVEL_LOW>; + + connector { + compatible = "usb-c-connector"; + + port { + ec_dp_in: endpoint { + remote-endpoint = <&mdss_dp_out>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml new file mode 100644 index 000000000000..3ab5737c9a8f --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml @@ -0,0 +1,326 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/google,cros-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ChromeOS Embedded Controller + +maintainers: + - Benson Leung + - Guenter Roeck + +description: + Google's ChromeOS EC is a microcontroller which talks to the AP and + implements various functions such as keyboard and battery charging. + The EC can be connected through various interfaces (I2C, SPI, and others) + and the compatible string specifies which interface is being used. + +properties: + compatible: + oneOf: + - description: + For implementations of the EC connected through I2C. + const: google,cros-ec-i2c + - description: + For implementations of the EC connected through SPI. + const: google,cros-ec-spi + - description: + For implementations of the FPMCU connected through SPI. + items: + - const: google,cros-ec-fp + - const: google,cros-ec-spi + - description: + For implementations of the EC connected through RPMSG. + const: google,cros-ec-rpmsg + - description: + For implementations of the EC connected through UART. + const: google,cros-ec-uart + + controller-data: true + + google,cros-ec-spi-pre-delay: + description: + This property specifies the delay in usecs between the + assertion of the CS and the first clock pulse. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + google,cros-ec-spi-msg-delay: + description: + This property specifies the delay in usecs between messages. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + google,has-vbc-nvram: + description: + Some implementations of the EC include a small nvram space used to + store verified boot context data. This boolean flag is used to specify + whether this nvram is present or not. + type: boolean + + mediatek,rpmsg-name: + description: + Must be defined if the cros-ec is a rpmsg device for a Mediatek + ARM Cortex M4 Co-processor. Contains the name of the rpmsg + device. Used to match the subnode to the rpmsg device announced by + the SCP. + $ref: /schemas/types.yaml#/definitions/string + + spi-max-frequency: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + boot0-gpios: + maxItems: 1 + description: Assert for bootloader mode. + + vdd-supply: true + + wakeup-source: + description: Button can wake-up the system. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#gpio-cells': + const: 2 + + gpio-controller: true + + typec: + $ref: /schemas/chrome/google,cros-ec-typec.yaml# + + ec-pwm: + $ref: /schemas/pwm/google,cros-ec-pwm.yaml# + deprecated: true + + pwm: + $ref: /schemas/pwm/google,cros-ec-pwm.yaml# + + keyboard-controller: + $ref: /schemas/input/google,cros-ec-keyb.yaml# + + proximity: + $ref: /schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml# + + codecs: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 2 + + '#size-cells': + const: 1 + + patternProperties: + "^ec-codec@[a-f0-9]+$": + type: object + $ref: /schemas/sound/google,cros-ec-codec.yaml# + + required: + - "#address-cells" + - "#size-cells" + + cbas: + type: object + + description: + This device is used to signal when a detachable base is attached + to a Chrome OS tablet. This device cannot be detected at runtime. + + properties: + compatible: + const: google,cros-cbas + + required: + - compatible + + additionalProperties: false + +patternProperties: + "^i2c-tunnel[0-9]*$": + type: object + $ref: /schemas/i2c/google,cros-ec-i2c-tunnel.yaml# + + "^regulator@[0-9]+$": + type: object + $ref: /schemas/regulator/google,cros-ec-regulator.yaml# + + "^extcon[0-9]*$": + type: object + $ref: /schemas/extcon/extcon-usbc-cros-ec.yaml# + +required: + - compatible + +allOf: + - if: + properties: + compatible: + not: + contains: + const: google,cros-ec-spi + then: + properties: + controller-data: false + google,cros-ec-spi-pre-delay: false + google,cros-ec-spi-msg-delay: false + spi-max-frequency: false + else: + $ref: /schemas/spi/spi-peripheral-props.yaml + + - if: + properties: + compatible: + not: + contains: + const: google,cros-ec-rpmsg + then: + properties: + mediatek,rpmsg-name: false + + - if: + properties: + compatible: + not: + contains: + enum: + - google,cros-ec-rpmsg + - google,cros-ec-uart + then: + required: + - reg + - interrupts + + - if: + properties: + compatible: + contains: + const: google,cros-ec-fp + then: + properties: + '#address-cells': false + '#size-cells': false + typec: false + ec-pwm: false + kbd-led-backlight: false + keyboard-controller: false + proximity: false + codecs: false + cbas: false + + patternProperties: + "^i2c-tunnel[0-9]*$": false + "^regulator@[0-9]+$": false + "^extcon[0-9]*$": false + + # Using additionalProperties: false here and + # listing true properties doesn't work + + required: + - reset-gpios + - boot0-gpios + - vdd-supply + else: + properties: + reset-gpios: false + boot0-gpios: false + vdd-supply: false + +additionalProperties: false + +examples: + # Example for I2C + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + cros-ec@1e { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; + interrupts = <6 0>; + interrupt-parent = <&gpio0>; + }; + }; + + # Example for SPI + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + cros-ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0x0>; + google,cros-ec-spi-msg-delay = <30>; + google,cros-ec-spi-pre-delay = <10>; + interrupts = <99 0>; + interrupt-parent = <&gpio7>; + spi-max-frequency = <5000000>; + #gpio-cells = <2>; + gpio-controller; + + proximity { + compatible = "google,cros-ec-mkbp-proximity"; + }; + + cbas { + compatible = "google,cros-cbas"; + }; + }; + }; + + # Example for RPMSG + - | + scp0 { + cros-ec { + compatible = "google,cros-ec-rpmsg"; + }; + }; + + # Example for FPMCU + - | + spi { + #address-cells = <0x1>; + #size-cells = <0x0>; + + ec@0 { + compatible = "google,cros-ec-fp", "google,cros-ec-spi"; + reg = <0x0>; + interrupt-parent = <&gpio_controller>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <3000000>; + reset-gpios = <&gpio_controller 5 GPIO_ACTIVE_LOW>; + boot0-gpios = <&gpio_controller 10 GPIO_ACTIVE_HIGH>; + vdd-supply = <&pp3300_fp_mcu>; + }; + }; + + # Example for UART + - | + serial { + cros-ec { + compatible = "google,cros-ec-uart"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/embedded-controller/gw,gsc.yaml b/Documentation/devicetree/bindings/embedded-controller/gw,gsc.yaml new file mode 100644 index 000000000000..82d4b2dadbae --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/gw,gsc.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/gw,gsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gateworks System Controller + +description: | + The Gateworks System Controller (GSC) is a device present across various + Gateworks product families that provides a set of system related features + such as the following (refer to the board hardware user manuals to see what + features are present) + - Watchdog Timer + - GPIO + - Pushbutton controller + - Hardware monitor with ADC's for temperature and voltage rails and + fan controller + +maintainers: + - Tim Harvey + +properties: + $nodename: + pattern: "gsc@[0-9a-f]{1,2}" + compatible: + const: gw,gsc + + reg: + description: I2C device address + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + adc: + type: object + additionalProperties: false + description: Optional hardware monitoring module + + properties: + compatible: + const: gw,gsc-adc + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^channel@[0-9a-f]+$": + type: object + additionalProperties: false + description: | + Properties for a single ADC which can report cooked values + (i.e. temperature sensor based on thermister), raw values + (i.e. voltage rail with a pre-scaling resistor divider). + + properties: + reg: + description: Register of the ADC + maxItems: 1 + + label: + description: Name of the ADC input + + gw,mode: + description: | + conversion mode: + 0 - temperature, in C*10 + 1 - pre-scaled 24-bit voltage value + 2 - scaled voltage based on an optional resistor divider + and optional offset + 3 - pre-scaled 16-bit voltage value + 4 - fan tach input to report RPM's + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4] + + gw,voltage-divider-ohms: + description: Values of resistors for divider on raw ADC input + maxItems: 2 + items: + minimum: 1000 + maximum: 1000000 + + gw,voltage-offset-microvolt: + description: | + A positive voltage offset to apply to a raw ADC + (i.e. to compensate for a diode drop). + minimum: 0 + maximum: 1000000 + + required: + - gw,mode + - reg + - label + + required: + - compatible + - "#address-cells" + - "#size-cells" + +patternProperties: + "^fan-controller@[0-9a-f]+$": + type: object + additionalProperties: false + description: Optional fan controller + + properties: + compatible: + const: gw,gsc-fan + + reg: + description: The fan controller base address + maxItems: 1 + + required: + - compatible + - reg + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* A0: Board Temperature */ + reg = <0x00>; + label = "temp"; + gw,mode = <0>; + }; + + channel@2 { /* A1: Input Voltage (raw ADC) */ + reg = <0x02>; + label = "vdd_vin"; + gw,mode = <1>; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <800000>; + }; + + channel@b { /* A2: Battery voltage */ + reg = <0x0b>; + label = "vdd_bat"; + gw,mode = <1>; + }; + }; + + fan-controller@2c { + compatible = "gw,gsc-fan"; + reg = <0x2c>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/embedded-controller/huawei,gaokun3-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/huawei,gaokun3-ec.yaml new file mode 100644 index 000000000000..cd9e65b6c2ea --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/huawei,gaokun3-ec.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/huawei,gaokun3-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Huawei Matebook E Go Embedded Controller + +maintainers: + - Pengyu Luo + +description: + Different from other Qualcomm Snapdragon sc8180x and sc8280xp-based + machines, the Huawei Matebook E Go tablets use embedded controllers + while others use a system called PMIC GLink which handles battery, + UCSI, USB Type-C DP Alt Mode. In addition, Huawei's implementation + also handles additional features, such as charging thresholds, FN + lock, smart charging, tablet lid status, thermal sensors, and more. + +properties: + compatible: + enum: + - huawei,gaokun3-ec + + reg: + const: 0x38 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + +patternProperties: + '^connector@[01]$': + $ref: /schemas/connector/usb-connector.yaml# + + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@38 { + compatible = "huawei,gaokun3-ec"; + reg = <0x38>; + + interrupts-extended = <&tlmm 107 IRQ_TYPE_LEVEL_LOW>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi0_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + + port@1 { + reg = <1>; + + ucsi0_sbu: endpoint { + remote-endpoint = <&usb0_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi1_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@1 { + reg = <1>; + + ucsi1_sbu: endpoint { + remote-endpoint = <&usb1_sbu_mux>; + }; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml new file mode 100644 index 000000000000..0b752f3baaa9 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/kontron,sl28cpld.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kontron's sl28cpld board management controller + +maintainers: + - Michael Walle + +description: | + The board management controller may contain different IP blocks like + watchdog, fan monitoring, PWM controller, interrupt controller and a + GPIO controller. + +properties: + compatible: + const: kontron,sl28cpld + + reg: + description: + I2C device address. + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + +patternProperties: + "^gpio(@[0-9a-f]+)?$": + $ref: /schemas/gpio/kontron,sl28cpld-gpio.yaml + + "^hwmon(@[0-9a-f]+)?$": + $ref: /schemas/hwmon/kontron,sl28cpld-hwmon.yaml + + "^interrupt-controller(@[0-9a-f]+)?$": + $ref: /schemas/interrupt-controller/kontron,sl28cpld-intc.yaml + + "^pwm(@[0-9a-f]+)?$": + $ref: /schemas/pwm/kontron,sl28cpld-pwm.yaml + + "^watchdog(@[0-9a-f]+)?$": + $ref: /schemas/watchdog/kontron,sl28cpld-wdt.yaml + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sl28cpld@4a { + compatible = "kontron,sl28cpld"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + + watchdog@4 { + compatible = "kontron,sl28cpld-wdt"; + reg = <0x4>; + kontron,assert-wdt-timeout-pin; + }; + + hwmon@b { + compatible = "kontron,sl28cpld-fan"; + reg = <0xb>; + }; + + pwm@c { + compatible = "kontron,sl28cpld-pwm"; + reg = <0xc>; + #pwm-cells = <2>; + }; + + pwm@e { + compatible = "kontron,sl28cpld-pwm"; + reg = <0xe>; + #pwm-cells = <2>; + }; + + gpio@10 { + compatible = "kontron,sl28cpld-gpio"; + reg = <0x10>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "a", "b", "c"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@15 { + compatible = "kontron,sl28cpld-gpio"; + reg = <0x15>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@1a { + compatible = "kontron,sl28cpld-gpo"; + reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@1b { + compatible = "kontron,sl28cpld-gpi"; + reg = <0x1b>; + + gpio-controller; + #gpio-cells = <2>; + }; + + interrupt-controller@1c { + compatible = "kontron,sl28cpld-intc"; + reg = <0x1c>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-c630-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-c630-ec.yaml new file mode 100644 index 000000000000..a029b38e8dc0 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-c630-ec.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/lenovo,yoga-c630-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lenovo Yoga C630 Embedded Controller. + +maintainers: + - Bjorn Andersson + +description: + The Qualcomm Snapdragon-based Lenovo Yoga C630 has an Embedded Controller + (EC) which handles things such as battery and USB Type-C. This binding + describes the interface, on an I2C bus, to this EC. + +properties: + compatible: + const: lenovo,yoga-c630-ec + + reg: + const: 0x70 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + +patternProperties: + '^connector@[01]$': + $ref: /schemas/connector/usb-connector.yaml# + + properties: + reg: + maxItems: 1 + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - |+ + #include + i2c1 { + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@70 { + compatible = "lenovo,yoga-c630-ec"; + reg = <0x70>; + + interrupts-extended = <&tlmm 20 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "source"; + data-role = "host"; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "source"; + data-role = "host"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-sam.yaml b/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-sam.yaml new file mode 100644 index 000000000000..9202cfca0b35 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-sam.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/microsoft,surface-sam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Surface System Aggregator Module (SAM, SSAM) + +maintainers: + - Konrad Dybcio + +description: | + Surface devices use a standardized embedded controller to let the + operating system interface with various hardware functions. The + specific functionalities are modeled as subdevices and matched on + five levels: domain, category, target, instance and function. + +properties: + compatible: + const: microsoft,surface-sam + + interrupts: + maxItems: 1 + + current-speed: true + +required: + - compatible + - interrupts + +additionalProperties: false + +examples: + - | + #include + uart { + embedded-controller { + compatible = "microsoft,surface-sam"; + + interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>; + + pinctrl-0 = <&ssam_state>; + pinctrl-names = "default"; + + current-speed = <4000000>; + }; + }; diff --git a/Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml b/Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml index b032471831e7..02663d67eac7 100644 --- a/Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml @@ -11,7 +11,7 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. There are three flavors of the GPIO controller, one full featured input/output with interrupt support (kontron,sl28cpld-gpio), one diff --git a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml index 010333cb25c0..5803a1770cad 100644 --- a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml +++ b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml @@ -11,7 +11,7 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. properties: compatible: diff --git a/Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml index e8dfa6507f64..87df07beda59 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml @@ -11,7 +11,7 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. The following interrupts are available. All types and levels are fixed and handled by the board management controller. diff --git a/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml b/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml deleted file mode 100644 index dc379f3ebf24..000000000000 --- a/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml +++ /dev/null @@ -1,193 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Gateworks System Controller - -description: | - The Gateworks System Controller (GSC) is a device present across various - Gateworks product families that provides a set of system related features - such as the following (refer to the board hardware user manuals to see what - features are present) - - Watchdog Timer - - GPIO - - Pushbutton controller - - Hardware monitor with ADC's for temperature and voltage rails and - fan controller - -maintainers: - - Tim Harvey - -properties: - $nodename: - pattern: "gsc@[0-9a-f]{1,2}" - compatible: - const: gw,gsc - - reg: - description: I2C device address - maxItems: 1 - - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#interrupt-cells": - const: 1 - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - - adc: - type: object - additionalProperties: false - description: Optional hardware monitoring module - - properties: - compatible: - const: gw,gsc-adc - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - - patternProperties: - "^channel@[0-9a-f]+$": - type: object - additionalProperties: false - description: | - Properties for a single ADC which can report cooked values - (i.e. temperature sensor based on thermister), raw values - (i.e. voltage rail with a pre-scaling resistor divider). - - properties: - reg: - description: Register of the ADC - maxItems: 1 - - label: - description: Name of the ADC input - - gw,mode: - description: | - conversion mode: - 0 - temperature, in C*10 - 1 - pre-scaled 24-bit voltage value - 2 - scaled voltage based on an optional resistor divider - and optional offset - 3 - pre-scaled 16-bit voltage value - 4 - fan tach input to report RPM's - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3, 4] - - gw,voltage-divider-ohms: - description: Values of resistors for divider on raw ADC input - maxItems: 2 - items: - minimum: 1000 - maximum: 1000000 - - gw,voltage-offset-microvolt: - description: | - A positive voltage offset to apply to a raw ADC - (i.e. to compensate for a diode drop). - minimum: 0 - maximum: 1000000 - - required: - - gw,mode - - reg - - label - - required: - - compatible - - "#address-cells" - - "#size-cells" - -patternProperties: - "^fan-controller@[0-9a-f]+$": - type: object - additionalProperties: false - description: Optional fan controller - - properties: - compatible: - const: gw,gsc-fan - - reg: - description: The fan controller base address - maxItems: 1 - - required: - - compatible - - reg - -required: - - compatible - - reg - - interrupts - - interrupt-controller - - "#interrupt-cells" - - "#address-cells" - - "#size-cells" - -additionalProperties: false - -examples: - - | - #include - #include - i2c { - #address-cells = <1>; - #size-cells = <0>; - - gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { /* A0: Board Temperature */ - reg = <0x00>; - label = "temp"; - gw,mode = <0>; - }; - - channel@2 { /* A1: Input Voltage (raw ADC) */ - reg = <0x02>; - label = "vdd_vin"; - gw,mode = <1>; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <800000>; - }; - - channel@b { /* A2: Battery voltage */ - reg = <0x0b>; - label = "vdd_bat"; - gw,mode = <1>; - }; - }; - - fan-controller@2c { - compatible = "gw,gsc-fan"; - reg = <0x2c>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml deleted file mode 100644 index 50f457090066..000000000000 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ /dev/null @@ -1,326 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: ChromeOS Embedded Controller - -maintainers: - - Benson Leung - - Guenter Roeck - -description: - Google's ChromeOS EC is a microcontroller which talks to the AP and - implements various functions such as keyboard and battery charging. - The EC can be connected through various interfaces (I2C, SPI, and others) - and the compatible string specifies which interface is being used. - -properties: - compatible: - oneOf: - - description: - For implementations of the EC connected through I2C. - const: google,cros-ec-i2c - - description: - For implementations of the EC connected through SPI. - const: google,cros-ec-spi - - description: - For implementations of the FPMCU connected through SPI. - items: - - const: google,cros-ec-fp - - const: google,cros-ec-spi - - description: - For implementations of the EC connected through RPMSG. - const: google,cros-ec-rpmsg - - description: - For implementations of the EC connected through UART. - const: google,cros-ec-uart - - controller-data: true - - google,cros-ec-spi-pre-delay: - description: - This property specifies the delay in usecs between the - assertion of the CS and the first clock pulse. - $ref: /schemas/types.yaml#/definitions/uint32 - default: 0 - - google,cros-ec-spi-msg-delay: - description: - This property specifies the delay in usecs between messages. - $ref: /schemas/types.yaml#/definitions/uint32 - default: 0 - - google,has-vbc-nvram: - description: - Some implementations of the EC include a small nvram space used to - store verified boot context data. This boolean flag is used to specify - whether this nvram is present or not. - type: boolean - - mediatek,rpmsg-name: - description: - Must be defined if the cros-ec is a rpmsg device for a Mediatek - ARM Cortex M4 Co-processor. Contains the name of the rpmsg - device. Used to match the subnode to the rpmsg device announced by - the SCP. - $ref: /schemas/types.yaml#/definitions/string - - spi-max-frequency: true - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - reset-gpios: - maxItems: 1 - - boot0-gpios: - maxItems: 1 - description: Assert for bootloader mode. - - vdd-supply: true - - wakeup-source: - description: Button can wake-up the system. - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - '#gpio-cells': - const: 2 - - gpio-controller: true - - typec: - $ref: /schemas/chrome/google,cros-ec-typec.yaml# - - ec-pwm: - $ref: /schemas/pwm/google,cros-ec-pwm.yaml# - deprecated: true - - pwm: - $ref: /schemas/pwm/google,cros-ec-pwm.yaml# - - keyboard-controller: - $ref: /schemas/input/google,cros-ec-keyb.yaml# - - proximity: - $ref: /schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml# - - codecs: - type: object - additionalProperties: false - - properties: - '#address-cells': - const: 2 - - '#size-cells': - const: 1 - - patternProperties: - "^ec-codec@[a-f0-9]+$": - type: object - $ref: /schemas/sound/google,cros-ec-codec.yaml# - - required: - - "#address-cells" - - "#size-cells" - - cbas: - type: object - - description: - This device is used to signal when a detachable base is attached - to a Chrome OS tablet. This device cannot be detected at runtime. - - properties: - compatible: - const: google,cros-cbas - - required: - - compatible - - additionalProperties: false - -patternProperties: - "^i2c-tunnel[0-9]*$": - type: object - $ref: /schemas/i2c/google,cros-ec-i2c-tunnel.yaml# - - "^regulator@[0-9]+$": - type: object - $ref: /schemas/regulator/google,cros-ec-regulator.yaml# - - "^extcon[0-9]*$": - type: object - $ref: /schemas/extcon/extcon-usbc-cros-ec.yaml# - -required: - - compatible - -allOf: - - if: - properties: - compatible: - not: - contains: - const: google,cros-ec-spi - then: - properties: - controller-data: false - google,cros-ec-spi-pre-delay: false - google,cros-ec-spi-msg-delay: false - spi-max-frequency: false - else: - $ref: /schemas/spi/spi-peripheral-props.yaml - - - if: - properties: - compatible: - not: - contains: - const: google,cros-ec-rpmsg - then: - properties: - mediatek,rpmsg-name: false - - - if: - properties: - compatible: - not: - contains: - enum: - - google,cros-ec-rpmsg - - google,cros-ec-uart - then: - required: - - reg - - interrupts - - - if: - properties: - compatible: - contains: - const: google,cros-ec-fp - then: - properties: - '#address-cells': false - '#size-cells': false - typec: false - ec-pwm: false - kbd-led-backlight: false - keyboard-controller: false - proximity: false - codecs: false - cbas: false - - patternProperties: - "^i2c-tunnel[0-9]*$": false - "^regulator@[0-9]+$": false - "^extcon[0-9]*$": false - - # Using additionalProperties: false here and - # listing true properties doesn't work - - required: - - reset-gpios - - boot0-gpios - - vdd-supply - else: - properties: - reset-gpios: false - boot0-gpios: false - vdd-supply: false - -additionalProperties: false - -examples: - # Example for I2C - - | - #include - #include - - i2c { - #address-cells = <1>; - #size-cells = <0>; - - cros-ec@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 0>; - interrupt-parent = <&gpio0>; - }; - }; - - # Example for SPI - - | - #include - #include - - spi { - #address-cells = <1>; - #size-cells = <0>; - - cros-ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0x0>; - google,cros-ec-spi-msg-delay = <30>; - google,cros-ec-spi-pre-delay = <10>; - interrupts = <99 0>; - interrupt-parent = <&gpio7>; - spi-max-frequency = <5000000>; - #gpio-cells = <2>; - gpio-controller; - - proximity { - compatible = "google,cros-ec-mkbp-proximity"; - }; - - cbas { - compatible = "google,cros-cbas"; - }; - }; - }; - - # Example for RPMSG - - | - scp0 { - cros-ec { - compatible = "google,cros-ec-rpmsg"; - }; - }; - - # Example for FPMCU - - | - spi { - #address-cells = <0x1>; - #size-cells = <0x0>; - - ec@0 { - compatible = "google,cros-ec-fp", "google,cros-ec-spi"; - reg = <0x0>; - interrupt-parent = <&gpio_controller>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <3000000>; - reset-gpios = <&gpio_controller 5 GPIO_ACTIVE_LOW>; - boot0-gpios = <&gpio_controller 10 GPIO_ACTIVE_HIGH>; - vdd-supply = <&pp3300_fp_mcu>; - }; - }; - - # Example for UART - - | - serial { - cros-ec { - compatible = "google,cros-ec-uart"; - }; - }; -... diff --git a/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml b/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml deleted file mode 100644 index 37207a97e06c..000000000000 --- a/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml +++ /dev/null @@ -1,153 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/mfd/kontron,sl28cpld.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Kontron's sl28cpld board management controller - -maintainers: - - Michael Walle - -description: | - The board management controller may contain different IP blocks like - watchdog, fan monitoring, PWM controller, interrupt controller and a - GPIO controller. - -properties: - compatible: - const: kontron,sl28cpld - - reg: - description: - I2C device address. - maxItems: 1 - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - - "#interrupt-cells": - const: 2 - - interrupts: - maxItems: 1 - - interrupt-controller: true - -patternProperties: - "^gpio(@[0-9a-f]+)?$": - $ref: /schemas/gpio/kontron,sl28cpld-gpio.yaml - - "^hwmon(@[0-9a-f]+)?$": - $ref: /schemas/hwmon/kontron,sl28cpld-hwmon.yaml - - "^interrupt-controller(@[0-9a-f]+)?$": - $ref: /schemas/interrupt-controller/kontron,sl28cpld-intc.yaml - - "^pwm(@[0-9a-f]+)?$": - $ref: /schemas/pwm/kontron,sl28cpld-pwm.yaml - - "^watchdog(@[0-9a-f]+)?$": - $ref: /schemas/watchdog/kontron,sl28cpld-wdt.yaml - -required: - - "#address-cells" - - "#size-cells" - - compatible - - reg - -additionalProperties: false - -examples: - - | - #include - i2c { - #address-cells = <1>; - #size-cells = <0>; - - sl28cpld@4a { - compatible = "kontron,sl28cpld"; - reg = <0x4a>; - #address-cells = <1>; - #size-cells = <0>; - - watchdog@4 { - compatible = "kontron,sl28cpld-wdt"; - reg = <0x4>; - kontron,assert-wdt-timeout-pin; - }; - - hwmon@b { - compatible = "kontron,sl28cpld-fan"; - reg = <0xb>; - }; - - pwm@c { - compatible = "kontron,sl28cpld-pwm"; - reg = <0xc>; - #pwm-cells = <2>; - }; - - pwm@e { - compatible = "kontron,sl28cpld-pwm"; - reg = <0xe>; - #pwm-cells = <2>; - }; - - gpio@10 { - compatible = "kontron,sl28cpld-gpio"; - reg = <0x10>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "a", "b", "c"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio@15 { - compatible = "kontron,sl28cpld-gpio"; - reg = <0x15>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio@1a { - compatible = "kontron,sl28cpld-gpo"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; - }; - - gpio@1b { - compatible = "kontron,sl28cpld-gpi"; - reg = <0x1b>; - - gpio-controller; - #gpio-cells = <2>; - }; - - interrupt-controller@1c { - compatible = "kontron,sl28cpld-intc"; - reg = <0x1c>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/platform/acer,aspire1-ec.yaml b/Documentation/devicetree/bindings/platform/acer,aspire1-ec.yaml deleted file mode 100644 index 7cb0134134ff..000000000000 --- a/Documentation/devicetree/bindings/platform/acer,aspire1-ec.yaml +++ /dev/null @@ -1,60 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/platform/acer,aspire1-ec.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Acer Aspire 1 Embedded Controller - -maintainers: - - Nikita Travkin - -description: - The Acer Aspire 1 laptop uses an embedded controller to control battery - and charging as well as to provide a set of misc features such as the - laptop lid status and HPD events for the USB Type-C DP alt mode. - -properties: - compatible: - const: acer,aspire1-ec - - reg: - const: 0x76 - - interrupts: - maxItems: 1 - - connector: - $ref: /schemas/connector/usb-connector.yaml# - -required: - - compatible - - reg - - interrupts - -additionalProperties: false - -examples: - - | - #include - i2c { - #address-cells = <1>; - #size-cells = <0>; - - embedded-controller@76 { - compatible = "acer,aspire1-ec"; - reg = <0x76>; - - interrupts-extended = <&tlmm 30 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - - port { - ec_dp_in: endpoint { - remote-endpoint = <&mdss_dp_out>; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml b/Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml deleted file mode 100644 index 4a03b0ee3149..000000000000 --- a/Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml +++ /dev/null @@ -1,124 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/platform/huawei,gaokun-ec.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Huawei Matebook E Go Embedded Controller - -maintainers: - - Pengyu Luo - -description: - Different from other Qualcomm Snapdragon sc8180x and sc8280xp-based - machines, the Huawei Matebook E Go tablets use embedded controllers - while others use a system called PMIC GLink which handles battery, - UCSI, USB Type-C DP Alt Mode. In addition, Huawei's implementation - also handles additional features, such as charging thresholds, FN - lock, smart charging, tablet lid status, thermal sensors, and more. - -properties: - compatible: - enum: - - huawei,gaokun3-ec - - reg: - const: 0x38 - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - interrupts: - maxItems: 1 - -patternProperties: - '^connector@[01]$': - $ref: /schemas/connector/usb-connector.yaml# - - properties: - reg: - maxItems: 1 - -required: - - compatible - - reg - - interrupts - -additionalProperties: false - -examples: - - | - #include - i2c { - #address-cells = <1>; - #size-cells = <0>; - - embedded-controller@38 { - compatible = "huawei,gaokun3-ec"; - reg = <0x38>; - - interrupts-extended = <&tlmm 107 IRQ_TYPE_LEVEL_LOW>; - - #address-cells = <1>; - #size-cells = <0>; - - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ucsi0_ss_in: endpoint { - remote-endpoint = <&usb_0_qmpphy_out>; - }; - }; - - port@1 { - reg = <1>; - - ucsi0_sbu: endpoint { - remote-endpoint = <&usb0_sbu_mux>; - }; - }; - }; - }; - - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ucsi1_ss_in: endpoint { - remote-endpoint = <&usb_1_qmpphy_out>; - }; - }; - - port@1 { - reg = <1>; - - ucsi1_sbu: endpoint { - remote-endpoint = <&usb1_sbu_mux>; - }; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/platform/lenovo,yoga-c630-ec.yaml b/Documentation/devicetree/bindings/platform/lenovo,yoga-c630-ec.yaml deleted file mode 100644 index 3180ce1a22d4..000000000000 --- a/Documentation/devicetree/bindings/platform/lenovo,yoga-c630-ec.yaml +++ /dev/null @@ -1,83 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/platform/lenovo,yoga-c630-ec.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Lenovo Yoga C630 Embedded Controller. - -maintainers: - - Bjorn Andersson - -description: - The Qualcomm Snapdragon-based Lenovo Yoga C630 has an Embedded Controller - (EC) which handles things such as battery and USB Type-C. This binding - describes the interface, on an I2C bus, to this EC. - -properties: - compatible: - const: lenovo,yoga-c630-ec - - reg: - const: 0x70 - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - interrupts: - maxItems: 1 - -patternProperties: - '^connector@[01]$': - $ref: /schemas/connector/usb-connector.yaml# - - properties: - reg: - maxItems: 1 - - unevaluatedProperties: false - -required: - - compatible - - reg - - interrupts - -additionalProperties: false - -examples: - - |+ - #include - i2c1 { - clock-frequency = <400000>; - - #address-cells = <1>; - #size-cells = <0>; - - embedded-controller@70 { - compatible = "lenovo,yoga-c630-ec"; - reg = <0x70>; - - interrupts-extended = <&tlmm 20 IRQ_TYPE_LEVEL_HIGH>; - - #address-cells = <1>; - #size-cells = <0>; - - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "source"; - data-role = "host"; - }; - - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "source"; - data-role = "host"; - }; - }; - }; -... diff --git a/Documentation/devicetree/bindings/platform/microsoft,surface-sam.yaml b/Documentation/devicetree/bindings/platform/microsoft,surface-sam.yaml deleted file mode 100644 index b33d26f15b2a..000000000000 --- a/Documentation/devicetree/bindings/platform/microsoft,surface-sam.yaml +++ /dev/null @@ -1,47 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/platform/microsoft,surface-sam.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Surface System Aggregator Module (SAM, SSAM) - -maintainers: - - Konrad Dybcio - -description: | - Surface devices use a standardized embedded controller to let the - operating system interface with various hardware functions. The - specific functionalities are modeled as subdevices and matched on - five levels: domain, category, target, instance and function. - -properties: - compatible: - const: microsoft,surface-sam - - interrupts: - maxItems: 1 - - current-speed: true - -required: - - compatible - - interrupts - -additionalProperties: false - -examples: - - | - #include - uart { - embedded-controller { - compatible = "microsoft,surface-sam"; - - interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>; - - pinctrl-0 = <&ssam_state>; - pinctrl-names = "default"; - - current-speed = <4000000>; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index f7bc84b05a87..8f5a468cfb91 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -14,7 +14,7 @@ description: | Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller (EC) and controlled via a host-command interface. An EC PWM node should be only found as a sub-node of the EC node (see - Documentation/devicetree/bindings/mfd/google,cros-ec.yaml). + Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml). allOf: - $ref: pwm.yaml# diff --git a/Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml b/Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml index 981cfec53f37..19a9d2e15a96 100644 --- a/Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml @@ -11,7 +11,7 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. The controller supports one PWM channel and supports only four distinct frequencies (250Hz, 500Hz, 1kHz, 2kHz). diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index adc6b3f36fde..179c98b33b4d 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -58,7 +58,7 @@ properties: maxItems: 1 cros-ec-rpmsg: - $ref: /schemas/mfd/google,cros-ec.yaml + $ref: /schemas/embedded-controller/google,cros-ec.yaml description: This subnode represents the rpmsg device. The properties of this node are defined by the individual bindings for @@ -126,7 +126,7 @@ patternProperties: maxItems: 1 cros-ec-rpmsg: - $ref: /schemas/mfd/google,cros-ec.yaml + $ref: /schemas/embedded-controller/google,cros-ec.yaml description: This subnode represents the rpmsg device. The properties of this node are defined by the individual bindings for diff --git a/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml index 1434f4433738..dd51e8c5b8c2 100644 --- a/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml +++ b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml @@ -15,7 +15,7 @@ description: | Embedded Controller (EC) and is controlled via a host-command interface. An EC codec node should only be found inside the "codecs" subnode of a cros-ec node. - (see Documentation/devicetree/bindings/mfd/google,cros-ec.yaml). + (see Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml). allOf: - $ref: dai-common.yaml# diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml index 179272f74de5..872a8471ef65 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -11,7 +11,7 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. allOf: - $ref: watchdog.yaml# diff --git a/MAINTAINERS b/MAINTAINERS index cf2f09782499..6e3961562d29 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10128,7 +10128,7 @@ F: drivers/media/i2c/gc2145.c GATEWORKS SYSTEM CONTROLLER (GSC) DRIVER M: Tim Harvey S: Maintained -F: Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml +F: Documentation/devicetree/bindings/embedded-controller/gw,gsc.yaml F: Documentation/hwmon/gsc-hwmon.rst F: drivers/hwmon/gsc-hwmon.c F: drivers/mfd/gateworks-gsc.c @@ -11299,7 +11299,7 @@ F: drivers/net/ethernet/huawei/hinic3/ HUAWEI MATEBOOK E GO EMBEDDED CONTROLLER DRIVER M: Pengyu Luo S: Maintained -F: Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml +F: Documentation/devicetree/bindings/embedded-controller/huawei,gaokun3-ec.yaml F: drivers/platform/arm64/huawei-gaokun-ec.c F: drivers/power/supply/huawei-gaokun-battery.c F: drivers/usb/typec/ucsi/ucsi_huawei_gaokun.c @@ -23210,10 +23210,10 @@ F: drivers/usb/misc/sisusbvga/ SL28 CPLD MFD DRIVER M: Michael Walle S: Maintained +F: Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml F: Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml F: Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml F: Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml -F: Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml F: Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml F: Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml F: drivers/gpio/gpio-sl28cpld.c -- cgit v1.2.3 From a598ae45f48d7d5a17f8290f2f5bd46046fd0b9b Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 22 Aug 2025 15:15:26 +0200 Subject: dt-bindings: mfd: sl28cpld: Add sa67mcu compatible The Kontron SMARC-sAM67 module features an on-board house keeping uC. It's designed to be compatible with the older on-board CPLD used on the SMARC-sAL28 board. To be prepared for any board specific quirks, add a specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822131531.1366437-3-mwalle@kernel.org Signed-off-by: Lee Jones --- .../devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml index 0b752f3baaa9..a77e67f6cb82 100644 --- a/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml @@ -16,7 +16,12 @@ description: | properties: compatible: - const: kontron,sl28cpld + oneOf: + - items: + - enum: + - kontron,sa67mcu + - const: kontron,sl28cpld + - const: kontron,sl28cpld reg: description: -- cgit v1.2.3 From 8566de1cf6892647c034c576caec772e6cf2c952 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:50 -0500 Subject: dt-bindings: mfd: Add support the SpacemiT P1 PMIC Enable the SpacemiT P1, which is an I2C-controlled PMIC. Initially only the RTC and regulators will be supported. Signed-off-by: Alex Elder Reviewed-by: "Rob Herring (Arm)" Acked-by: Troy Mitchell Link: https://lore.kernel.org/r/20250825172057.163883-2-elder@riscstar.com Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/spacemit,p1.yaml | 86 ++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/spacemit,p1.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml new file mode 100644 index 000000000000..c6593ac6ef6a --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/spacemit,p1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT P1 Power Management Integrated Circuit + +maintainers: + - Troy Mitchell + +description: + P1 is an I2C-controlled PMIC produced by SpacemiT. It implements six + constant-on-time buck converters and twelve low-dropout regulators. + It also contains a load switch, watchdog timer, real-time clock, eight + 12-bit ADC channels, and six GPIOs. Additional details are available + in the "Power Stone/P1" section at the following link. + https://developer.spacemit.com/documentation + +properties: + compatible: + const: spacemit,p1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vin-supply: + description: Input supply phandle. + + regulators: + type: object + + patternProperties: + "^(buck[1-6]|aldo[1-4]|dldo[1-7])$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + + regulators { + buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-name = "aldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo1 { + regulator-name = "dldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + }; + }; + }; -- cgit v1.2.3 From 8a498184e2e8aac24db0faf295b7d0fb62dfe90d Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 1 Sep 2025 12:04:13 +0100 Subject: dt-bindings: mfd: syscon: Document the control-scb syscon on PolarFire SoC The "control-scb" region, contains the "tvs" temperature and voltage sensors and the control/status registers for the system controller's mailbox. The mailbox has a dedicated node, so there's no need for a child node describing it, looking the syscon up by compatible is sufficient. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20250901-shorten-yahoo-223aeaecd290@spud Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 1f381d159af8..657c38175fba 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -91,6 +91,7 @@ select: - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy @@ -199,6 +200,7 @@ properties: - mediatek,mt8365-infracfg-nao - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy -- cgit v1.2.3 From 1160f9f88be2a911a8d7a27a896b24360a1763c9 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 29 Aug 2025 20:15:15 +0000 Subject: dt-bindings: mfd: fsl,mc13xxx: Convert txt to DT schema Convert the txt mc13xxx bindings to DT schema attempting to keep most information. The nodes codec and touchscreen are not part of the new schema since it was only briefly mentioned before. Following the convention, rename led-control to fsl,led-control. Signed-off-by: Alexander Kurz Reviewed-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250829201517.15374-6-akurz@blala.de Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/fsl,mc13xxx.yaml | 218 +++++++++++++++++++++ Documentation/devicetree/bindings/mfd/mc13xxx.txt | 156 --------------- 2 files changed, 218 insertions(+), 156 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/mc13xxx.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml b/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml new file mode 100644 index 000000000000..007c2e3eee91 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml @@ -0,0 +1,218 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/fsl,mc13xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MC13xxx Power Management Integrated Circuits (PMIC) + +maintainers: + - Alexander Kurz + +description: > + The MC13xxx PMIC series consists of the three models MC13783, MC13892 + and MC34708 and provide regulators and other features like RTC, ADC, + LED, touchscreen, codec and input buttons. + + Link to datasheets + https://www.nxp.com/docs/en/data-sheet/MC13783.pdf + https://www.nxp.com/docs/en/data-sheet/MC13892.pdf + https://www.nxp.com/docs/en/data-sheet/MC34708.pdf + +properties: + compatible: + enum: + - fsl,mc13783 + - fsl,mc13892 + - fsl,mc34708 + + reg: + description: I2C slave address or SPI chip select number. + maxItems: 1 + + spi-max-frequency: true + + spi-cs-high: true + + system-power-controller: true + + interrupts: + maxItems: 1 + + leds: + type: object + $ref: /schemas/leds/common.yaml# + + properties: + reg: + description: | + One of + MC13783 LED IDs + 0: Main display + 1: AUX display + 2: Keypad + 3: Red 1 + 4: Green 1 + 5: Blue 1 + 6: Red 2 + 7: Green 2 + 8: Blue 2 + 9: Red 3 + 10: Green 3 + 11: Blue 3 + + MC13892 LED IDs + 0: Main display + 1: AUX display + 2: Keypad + 3: Red + 4: Green + 5: Blue + + MC34708 LED IDs + 0: Charger Red + 1: Charger Green + maxItems: 1 + + led-control: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Setting for LED-Control register array length depends on model, + mc13783: 6, mc13892: 4, mc34708: 1 + + regulators: + type: object + + additionalProperties: + type: object + + description: | + List of child nodes specifying the regulators, depending on chip variant. + Each child node is defined using the standard binding for regulators and + the optional regulator properties defined below. + + fsl,mc13xxx-uses-adc: + type: boolean + description: Indicate the ADC is being used + + fsl,mc13xxx-uses-codec: + type: boolean + description: Indicate the Audio Codec is being used + + fsl,mc13xxx-uses-rtc: + type: boolean + description: Indicate the RTC is being used + + fsl,mc13xxx-uses-touch: + type: boolean + description: Indicate the touchscreen controller is being used + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,mc13783 + then: + properties: + leds: + properties: + led-control: + minItems: 6 + maxItems: 6 + regulators: + patternProperties: + "^gpo[1-4]|pwgt[12]spi|sw[12][ab]|sw3|vaudio|vcam|vdig|vesim|vgen|viohi|violo|vmmc[12]|vrf[12]|vrfbg|vrfcp|vrfdig|vrfref|vsim|vvib$": + type: object + $ref: /schemas/regulator/regulator.yaml# + + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + const: fsl,mc13892 + then: + properties: + leds: + properties: + led-control: + minItems: 4 + maxItems: 4 + regulators: + patternProperties: + "^gpo[1-4]|pwgt[12]spi|sw[1-4]|swbst|vaudio|vcam|vcoincell|vdig|vgen[1-3]|viohi|vpll|vsd|vusb|vusb2|vvideo$": + type: object + $ref: /schemas/regulator/regulator.yaml# + + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + const: fsl,mc34708 + then: + properties: + leds: + properties: + led-control: + minItems: 1 + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + pmic: mc13892@0 { + compatible = "fsl,mc13892"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cs-high; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-rtc; + fsl,mc13xxx-uses-adc; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x000 0x000 0x0e0 0x000>; + + sysled@3 { + reg = <3>; + label = "system:red:live"; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt deleted file mode 100644 index 8261ea73278a..000000000000 --- a/Documentation/devicetree/bindings/mfd/mc13xxx.txt +++ /dev/null @@ -1,156 +0,0 @@ -* Freescale MC13783/MC13892 Power Management Integrated Circuit (PMIC) - -Required properties: -- compatible : Should be "fsl,mc13783" or "fsl,mc13892" - -Optional properties: -- fsl,mc13xxx-uses-adc : Indicate the ADC is being used -- fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used -- fsl,mc13xxx-uses-rtc : Indicate the RTC is being used -- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used - -Sub-nodes: -- codec: Contain the Audio Codec node. - - adc-port: Contain PMIC SSI port number used for ADC. - - dac-port: Contain PMIC SSI port number used for DAC. -- leds : Contain the led nodes and initial register values in property - "led-control". Number of register depends of used IC, for MC13783 is 6, - for MC13892 is 4, for MC34708 is 1. See datasheet for bits definitions of - these registers. - - #address-cells: Must be 1. - - #size-cells: Must be 0. - Each led node should contain "reg", which used as LED ID (described below). - Optional properties "label" and "linux,default-trigger" is described in - Documentation/devicetree/bindings/leds/common.txt. -- regulators : Contain the regulator nodes. The regulators are bound using - their names as listed below with their registers and bits for enabling. - -MC13783 LED IDs: - 0 : Main display - 1 : AUX display - 2 : Keypad - 3 : Red 1 - 4 : Green 1 - 5 : Blue 1 - 6 : Red 2 - 7 : Green 2 - 8 : Blue 2 - 9 : Red 3 - 10 : Green 3 - 11 : Blue 3 - -MC13892 LED IDs: - 0 : Main display - 1 : AUX display - 2 : Keypad - 3 : Red - 4 : Green - 5 : Blue - -MC34708 LED IDs: - 0 : Charger Red - 1 : Charger Green - -MC13783 regulators: - sw1a : regulator SW1A (register 24, bit 0) - sw1b : regulator SW1B (register 25, bit 0) - sw2a : regulator SW2A (register 26, bit 0) - sw2b : regulator SW2B (register 27, bit 0) - sw3 : regulator SW3 (register 29, bit 20) - vaudio : regulator VAUDIO (register 32, bit 0) - viohi : regulator VIOHI (register 32, bit 3) - violo : regulator VIOLO (register 32, bit 6) - vdig : regulator VDIG (register 32, bit 9) - vgen : regulator VGEN (register 32, bit 12) - vrfdig : regulator VRFDIG (register 32, bit 15) - vrfref : regulator VRFREF (register 32, bit 18) - vrfcp : regulator VRFCP (register 32, bit 21) - vsim : regulator VSIM (register 33, bit 0) - vesim : regulator VESIM (register 33, bit 3) - vcam : regulator VCAM (register 33, bit 6) - vrfbg : regulator VRFBG (register 33, bit 9) - vvib : regulator VVIB (register 33, bit 11) - vrf1 : regulator VRF1 (register 33, bit 12) - vrf2 : regulator VRF2 (register 33, bit 15) - vmmc1 : regulator VMMC1 (register 33, bit 18) - vmmc2 : regulator VMMC2 (register 33, bit 21) - gpo1 : regulator GPO1 (register 34, bit 6) - gpo2 : regulator GPO2 (register 34, bit 8) - gpo3 : regulator GPO3 (register 34, bit 10) - gpo4 : regulator GPO4 (register 34, bit 12) - pwgt1spi : regulator PWGT1SPI (register 34, bit 15) - pwgt2spi : regulator PWGT2SPI (register 34, bit 16) - -MC13892 regulators: - vcoincell : regulator VCOINCELL (register 13, bit 23) - sw1 : regulator SW1 (register 24, bit 0) - sw2 : regulator SW2 (register 25, bit 0) - sw3 : regulator SW3 (register 26, bit 0) - sw4 : regulator SW4 (register 27, bit 0) - swbst : regulator SWBST (register 29, bit 20) - vgen1 : regulator VGEN1 (register 32, bit 0) - viohi : regulator VIOHI (register 32, bit 3) - vdig : regulator VDIG (register 32, bit 9) - vgen2 : regulator VGEN2 (register 32, bit 12) - vpll : regulator VPLL (register 32, bit 15) - vusb2 : regulator VUSB2 (register 32, bit 18) - vgen3 : regulator VGEN3 (register 33, bit 0) - vcam : regulator VCAM (register 33, bit 6) - vvideo : regulator VVIDEO (register 33, bit 12) - vaudio : regulator VAUDIO (register 33, bit 15) - vsd : regulator VSD (register 33, bit 18) - gpo1 : regulator GPO1 (register 34, bit 6) - gpo2 : regulator GPO2 (register 34, bit 8) - gpo3 : regulator GPO3 (register 34, bit 10) - gpo4 : regulator GPO4 (register 34, bit 12) - pwgt1spi : regulator PWGT1SPI (register 34, bit 15) - pwgt2spi : regulator PWGT2SPI (register 34, bit 16) - vusb : regulator VUSB (register 50, bit 3) - - The bindings details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - -Examples: - -ecspi@70010000 { /* ECSPI1 */ - cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */ - <&gpio4 25 0>; /* GPIO4_25 */ - - pmic: mc13892@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mc13892"; - spi-max-frequency = <6000000>; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <8>; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x000 0x000 0x0e0 0x000>; - - sysled@3 { - reg = <3>; - label = "system:red:live"; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - sw1_reg: mc13892__sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: mc13892__sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; -- cgit v1.2.3 From 5872dcccc5ade97bc27aafe13e361bb8e7c73da1 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 29 Aug 2025 20:15:16 +0000 Subject: dt-bindings: mfd: fsl,mc13xxx: Add buttons node Add a buttons node and properties describing the "ONOFD" (MC13783) and "PWRON" (MC13892/MC34708) buttons available in the fsl,mc13xxx PMIC ICs. Signed-off-by: Alexander Kurz Reviewed-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250829201517.15374-7-akurz@blala.de Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/fsl,mc13xxx.yaml | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml b/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml index 007c2e3eee91..d2886f2686a8 100644 --- a/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml +++ b/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml @@ -39,6 +39,58 @@ properties: interrupts: maxItems: 1 + buttons: + type: object + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^onkey@[0-2]$": + $ref: /schemas/input/input.yaml# + unevaluatedProperties: false + type: object + + properties: + reg: + description: | + One of + MC13783 BUTTON IDs: + 0: ONOFD1 + 1: ONOFD2 + 2: ONOFD3 + + MC13892 BUTTON IDs: + 0: PWRON1 + 1: PWRON2 + 2: PWRON3 + + MC34708 BUTTON IDs: + 0: PWRON1 + 1: PWRON2 + maximum: 2 + + debounce-delay-ms: + enum: [0, 30, 150, 750] + default: 30 + description: + Sets the debouncing delay in milliseconds. + + active-low: + description: Set active when pin is pulled low. + + linux,code: true + + fsl,enable-reset: + description: + Setting of the global reset option. + type: boolean + + unevaluatedProperties: false + leds: type: object $ref: /schemas/leds/common.yaml# @@ -159,6 +211,12 @@ allOf: const: fsl,mc34708 then: properties: + buttons: + patternProperties: + "^onkey@[0-2]$": + properties: + reg: + maximum: 1 leds: properties: led-control: @@ -187,6 +245,18 @@ examples: fsl,mc13xxx-uses-rtc; fsl,mc13xxx-uses-adc; + buttons { + #address-cells = <1>; + #size-cells = <0>; + + onkey@0 { + reg = <0>; + debounce-delay-ms = <30>; + active-low; + fsl,enable-reset; + }; + }; + leds { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 99e2f00cf418c2e12fc934ae2ba790870e98fd67 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 29 Aug 2025 18:04:49 -0500 Subject: dt-bindings: mfd: Convert aspeed,ast2400-p2a-ctrl to DT schema Convert the aspeed,ast2x00-p2a-ctrl binding to DT schema format. The schema is simple enough to just add it to the parent aspeed,ast2x00-scu binding. Signed-off-by: "Rob Herring (Arm)" Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/20250829230450.1496151-1-robh@kernel.org Signed-off-by: Lee Jones --- .../bindings/mfd/aspeed,ast2x00-scu.yaml | 33 +++++++++++++++- .../devicetree/bindings/misc/aspeed-p2a-ctrl.txt | 46 ---------------------- 2 files changed, 32 insertions(+), 47 deletions(-) delete mode 100644 Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index 5eccd10d95ce..5adb7f6aca45 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -48,8 +48,34 @@ properties: patternProperties: '^p2a-control@[0-9a-f]+$': - description: See Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt + description: > + PCI-to-AHB Bridge Control + + The bridge is available on platforms with the VGA enabled on the Aspeed + device. In this case, the host has access to a 64KiB window into all of + the BMC's memory. The BMC can disable this bridge. If the bridge is + enabled, the host has read access to all the regions of memory, however + the host only has read and write access depending on a register + controlled by the BMC. type: object + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2400-p2a-ctrl + - aspeed,ast2500-p2a-ctrl + reg: + maxItems: 1 + + memory-region: + maxItems: 1 + description: + A reserved_memory region to be used for the PCI to AHB mapping + + required: + - compatible + - reg '^pinctrl(@[0-9a-f]+)?$': type: object @@ -123,6 +149,11 @@ examples: #size-cells = <1>; ranges = <0x0 0x1e6e2000 0x1000>; + p2a-control@2c { + compatible = "aspeed,ast2400-p2a-ctrl"; + reg = <0x2c 0x4>; + }; + silicon-id@7c { compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; reg = <0x7c 0x4>, <0x150 0x8>; diff --git a/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt b/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt deleted file mode 100644 index f2e2e28b317c..000000000000 --- a/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt +++ /dev/null @@ -1,46 +0,0 @@ -====================================================================== -Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver -====================================================================== - -The bridge is available on platforms with the VGA enabled on the Aspeed device. -In this case, the host has access to a 64KiB window into all of the BMC's -memory. The BMC can disable this bridge. If the bridge is enabled, the host -has read access to all the regions of memory, however the host only has read -and write access depending on a register controlled by the BMC. - -Required properties: -=================== - - - compatible: must be one of: - - "aspeed,ast2400-p2a-ctrl" - - "aspeed,ast2500-p2a-ctrl" - -Optional properties: -=================== - -- reg: A hint for the memory regions associated with the P2A controller -- memory-region: A phandle to a reserved_memory region to be used for the PCI - to AHB mapping - -The p2a-control node should be the child of a syscon node with the required -property: - -- compatible : Should be one of the following: - "aspeed,ast2400-scu", "syscon", "simple-mfd" - "aspeed,ast2500-scu", "syscon", "simple-mfd" - -Example -=================== - -g4 Example ----------- - -syscon: scu@1e6e2000 { - compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - - p2a: p2a-control { - compatible = "aspeed,ast2400-p2a-ctrl"; - memory-region = <&reserved_memory>; - }; -}; -- cgit v1.2.3 From b445c14ac7eb39447a364c142aa85b6487b30c67 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Sun, 31 Aug 2025 10:14:36 +0800 Subject: dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles Add SCU interrupt controller compatible strings for the AST2700 SoC: scu-ic0 to 3. This extends the MFD binding to support AST2700-based platforms. Signed-off-by: Ryan Chen Acked-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250831021438.976893-3-ryan_chen@aspeedtech.com Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index 5adb7f6aca45..da1887d7a8fe 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -101,6 +101,10 @@ patternProperties: - aspeed,ast2500-scu-ic - aspeed,ast2600-scu-ic0 - aspeed,ast2600-scu-ic1 + - aspeed,ast2700-scu-ic0 + - aspeed,ast2700-scu-ic1 + - aspeed,ast2700-scu-ic2 + - aspeed,ast2700-scu-ic3 '^silicon-id@[0-9a-f]+$': description: Unique hardware silicon identifiers within the SoC -- cgit v1.2.3 From 59863239e09f435e4dd3393637adc4d657772de5 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 12 Sep 2025 14:07:40 +0200 Subject: dt-bindings: mfd: tps6594: Allow gpio-line-names Setting the signal names in the device tree was already possible, but it will lead to a warning. Allow the gpio-line-names property to fix that. Signed-off-by: Michael Walle Acked-by: "Rob Herring (Arm)" Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/ti,tps6594.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml index a48cb00afe43..ca17fbdea691 100644 --- a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml @@ -41,6 +41,7 @@ properties: system-power-controller: true gpio-controller: true + gpio-line-names: true '#gpio-cells': const: 2 -- cgit v1.2.3 From 354f31e9d2a3e4799d3d057a9e1c9f7ae7348bba Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 12 Sep 2025 14:07:43 +0200 Subject: dt-bindings: watchdog: Add SMARC-sAM67 support The SMARC-sAM67 board has an on-board uC which has the same register interface as the older CPLD implementation on the SMARC-sAL28 board. Although the MCU emulates the same behavior, be prepared for any quirks and add a board specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Reviewed-by: Guenter Roeck Signed-off-by: Lee Jones --- .../devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml index 872a8471ef65..0821ba0e84a3 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -18,7 +18,12 @@ allOf: properties: compatible: - const: kontron,sl28cpld-wdt + oneOf: + - items: + - enum: + - kontron,sa67mcu-wdt + - const: kontron,sl28cpld-wdt + - const: kontron,sl28cpld-wdt reg: maxItems: 1 -- cgit v1.2.3 From 02dde2c4c32e8c8404a890d6092a66dbe0f36564 Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Sun, 14 Sep 2025 21:25:14 +0200 Subject: dt-bindings: mfd: twl: Add missing sub-nodes for TWL4030 & TWL603x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the main TI TWL-family binding to be self-contained and to fix pre-existing validation errors. To ensure future patches are bisectable, child nodes whose bindings are in other patches (audio, keypad, usb, etc.) are now defined using a flexible 'additionalProperties: true' pattern. This removes hard dependencies between the MFD and subsystem bindings. The complete dtbs_check for this binding is clean except for two warnings originating from pre-existing bugs in the OMAP DTS files, for which fixes have already been submitted separately [1][2]. Reviewed-by: Rob Herring Acked-by: Uwe Kleine-König Signed-off-by: Jihed Chaibi Reviewed-by: Andreas Kemnade Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/ti,twl.yaml | 319 ++++++++++++++++++--- .../devicetree/bindings/mfd/twl4030-power.txt | 48 ---- .../devicetree/bindings/pwm/ti,twl-pwm.txt | 17 -- .../devicetree/bindings/pwm/ti,twl-pwmled.txt | 17 -- 4 files changed, 273 insertions(+), 128 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/twl4030-power.txt delete mode 100644 Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt delete mode 100644 Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/ti,twl.yaml b/Documentation/devicetree/bindings/mfd/ti,twl.yaml index f162ab60c09b..776b04e182cb 100644 --- a/Documentation/devicetree/bindings/mfd/ti,twl.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,twl.yaml @@ -11,9 +11,9 @@ maintainers: description: | The TWLs are Integrated Power Management Chips. - Some version might contain much more analog function like + Some versions might contain much more analog functions like USB transceiver or Audio amplifier. - These chips are connected to an i2c bus. + These chips are connected to an I2C bus. allOf: - if: @@ -49,33 +49,14 @@ allOf: ti,retain-on-reset: false properties: - madc: - type: object - $ref: /schemas/iio/adc/ti,twl4030-madc.yaml - unevaluatedProperties: false - charger: - type: object $ref: /schemas/power/supply/twl4030-charger.yaml unevaluatedProperties: false - pwrbutton: - type: object - additionalProperties: false - properties: - compatible: - const: ti,twl4030-pwrbutton - interrupts: - items: - - items: - const: 8 - - watchdog: - type: object - additionalProperties: false - properties: - compatible: - const: ti,twl4030-wdt + gpadc: false + + usb-comparator: false + - if: properties: compatible: @@ -106,15 +87,30 @@ allOf: properties: charger: - type: object - properties: - compatible: - const: ti,twl6030-charger + $ref: /schemas/power/supply/ti,twl6030-charger.yaml + unevaluatedProperties: false + gpadc: - type: object properties: compatible: const: ti,twl6030-gpadc + + pwrbutton: false + + madc: false + + watchdog: false + + audio: false + + keypad: false + + twl4030-usb: false + + gpio: false + + power: false + - if: properties: compatible: @@ -142,23 +138,36 @@ allOf: properties: charger: - type: object - properties: - compatible: - items: - - const: ti,twl6032-charger - - const: ti,twl6030-charger + $ref: /schemas/power/supply/ti,twl6030-charger.yaml + unevaluatedProperties: false + gpadc: - type: object properties: compatible: const: ti,twl6032-gpadc + pwrbutton: false + + madc: false + + watchdog: false + + audio: false + + keypad: false + + twl4030-usb: false + + gpio: false + + power: false + properties: compatible: - description: - TWL4030 for integrated power-management/audio CODEC device used in OMAP3 - based boards + description: > + TWL4030 for integrated power-management/audio CODEC device used in + OMAP3 based boards. + TWL6030/32 for integrated power-management used in OMAP4 based boards enum: - ti,twl4030 @@ -181,28 +190,221 @@ properties: "#clock-cells": const: 1 + clocks: + maxItems: 1 + + clock-names: + const: fck + charger: type: object - additionalProperties: true + properties: compatible: true + required: - compatible rtc: type: object additionalProperties: false + properties: compatible: const: ti,twl4030-rtc interrupts: maxItems: 1 + madc: + type: object + $ref: /schemas/iio/adc/ti,twl4030-madc.yaml + unevaluatedProperties: false + + pwrbutton: + type: object + additionalProperties: false + + properties: + compatible: + const: ti,twl4030-pwrbutton + interrupts: + items: + - items: + const: 8 + + watchdog: + type: object + additionalProperties: false + + properties: + compatible: + const: ti,twl4030-wdt + + audio: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl4030-audio + + required: + - compatible + + keypad: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl4030-keypad + + required: + - compatible + + twl4030-usb: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl4030-usb + + required: + - compatible + + gpio: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl4030-gpio + + required: + - compatible + + power: + type: object + additionalProperties: false + description: > + The power management module inside the TWL4030 provides several + facilities to control the power resources, including power scripts. + + For now, the binding only supports the complete shutdown of the + system after poweroff. + + Board-specific compatible strings may be used for platform-specific + power configurations. + + A board-specific compatible string (e.g., ti,twl4030-power-omap3-evm) + may be paired with a generic fallback (generally for power saving mode). + + properties: + compatible: + oneOf: + # Case 1: A single compatible string is provided. + - enum: + - ti,twl4030-power + - ti,twl4030-power-reset + - ti,twl4030-power-idle + - ti,twl4030-power-idle-osc-off + - ti,twl4030-power-omap3-sdp + - ti,twl4030-power-omap3-ldp + - ti,twl4030-power-omap3-evm + + # Case 2: The specific, valid fallback for 'idle-osc-off'. + - items: + - const: ti,twl4030-power-idle-osc-off + - const: ti,twl4030-power-idle + + # Case 3: The specific, valid fallback for 'omap3-evm'. + - items: + - const: ti,twl4030-power-omap3-evm + - const: ti,twl4030-power-idle + + ti,system-power-controller: + type: boolean + deprecated: true + description: > + DEPRECATED. The standard 'system-power-controller' + property on the parent node should be used instead. + + ti,use_poweroff: + type: boolean + deprecated: true + description: DEPRECATED, to be removed. + + required: + - compatible + + gpadc: + type: object + $ref: /schemas/iio/adc/ti,twl6030-gpadc.yaml + unevaluatedProperties: false + + properties: + compatible: true + + usb-comparator: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl6030-usb + + required: + - compatible + + pwm: + type: object + $ref: /schemas/pwm/pwm.yaml# + unevaluatedProperties: false + description: + PWM controllers (PWM1 and PWM2 on TWL4030, PWM0 and PWM1 on TWL6030/32). + + properties: + compatible: + enum: + - ti,twl4030-pwm + - ti,twl6030-pwm + + '#pwm-cells': + const: 2 + + required: + - compatible + - '#pwm-cells' + + pwmled: + type: object + $ref: /schemas/pwm/pwm.yaml# + unevaluatedProperties: false + description: > + PWM controllers connected to LED terminals (PWMA and PWMB on TWL4030. + + LED PWM on TWL6030/32, mainly used as charging indicator LED). + + properties: + compatible: + enum: + - ti,twl4030-pwmled + - ti,twl6030-pwmled + + '#pwm-cells': + const: 2 + + required: + - compatible + - '#pwm-cells' + patternProperties: "^regulator-": type: object unevaluatedProperties: false $ref: /schemas/regulator/regulator.yaml + properties: compatible: true regulator-initial-mode: @@ -211,12 +413,13 @@ patternProperties: # with low power consumption with low load current capability - 0x0e # Active mode, the regulator can deliver its nominal output # voltage with full-load current capability + ti,retain-on-reset: - description: - Does not turn off the supplies during warm - reset. Could be needed for VMMC, as TWL6030 - reset sequence for this signal does not comply - with the SD specification. + description: > + Does not turn off the supplies during warm reset. + + Could be needed for VMMC, as TWL6030 reset sequence for + this signal does not comply with the SD specification. type: boolean unevaluatedProperties: false @@ -271,6 +474,16 @@ examples: compatible = "ti,twl6030-vmmc"; ti,retain-on-reset; }; + + pwm { + compatible = "ti,twl6030-pwm"; + #pwm-cells = <2>; + }; + + pwmled { + compatible = "ti,twl6030-pwmled"; + #pwm-cells = <2>; + }; }; }; @@ -325,6 +538,20 @@ examples: watchdog { compatible = "ti,twl4030-wdt"; }; + + power { + compatible = "ti,twl4030-power"; + }; + + pwm { + compatible = "ti,twl4030-pwm"; + #pwm-cells = <2>; + }; + + pwmled { + compatible = "ti,twl4030-pwmled"; + #pwm-cells = <2>; + }; }; }; ... diff --git a/Documentation/devicetree/bindings/mfd/twl4030-power.txt b/Documentation/devicetree/bindings/mfd/twl4030-power.txt deleted file mode 100644 index 3d19963312ce..000000000000 --- a/Documentation/devicetree/bindings/mfd/twl4030-power.txt +++ /dev/null @@ -1,48 +0,0 @@ -Texas Instruments TWL family (twl4030) reset and power management module - -The power management module inside the TWL family provides several facilities -to control the power resources, including power scripts. For now, the -binding only supports the complete shutdown of the system after poweroff. - -Required properties: -- compatible : must be one of the following - "ti,twl4030-power" - "ti,twl4030-power-reset" - "ti,twl4030-power-idle" - "ti,twl4030-power-idle-osc-off" - -The use of ti,twl4030-power-reset is recommended at least on -3530 that needs a special configuration for warm reset to work. - -When using ti,twl4030-power-idle, the TI recommended configuration -for idle modes is loaded to the tlw4030 PMIC. - -When using ti,twl4030-power-idle-osc-off, the TI recommended -configuration is used with the external oscillator being shut -down during off-idle. Note that this does not work on all boards -depending on how the external oscillator is wired. - -Optional properties: - -- ti,system-power-controller: This indicates that TWL4030 is the - power supply master of the system. With this flag, the chip will - initiate an ACTIVE-to-OFF or SLEEP-to-OFF transition when the - system poweroffs. - -- ti,use_poweroff: Deprecated name for ti,system-power-controller - -Example: -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_power: power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt deleted file mode 100644 index d97ca1964e94..000000000000 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt +++ /dev/null @@ -1,17 +0,0 @@ -Texas Instruments TWL series PWM drivers - -Supported PWMs: -On TWL4030 series: PWM1 and PWM2 -On TWL6030 series: PWM0 and PWM1 - -Required properties: -- compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm" -- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of - the cells format. - -Example: - -twl_pwm: pwm { - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt deleted file mode 100644 index 31ca1b032ef0..000000000000 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt +++ /dev/null @@ -1,17 +0,0 @@ -Texas Instruments TWL series PWM drivers connected to LED terminals - -Supported PWMs: -On TWL4030 series: PWMA and PWMB (connected to LEDA and LEDB terminals) -On TWL6030 series: LED PWM (mainly used as charging indicator LED) - -Required properties: -- compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled" -- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of - the cells format. - -Example: - -twl_pwmled: pwmled { - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; -}; -- cgit v1.2.3 From f9a68cf7b9afeb1780527f840995fc4292a2202a Mon Sep 17 00:00:00 2001 From: Akiyoshi Kurita Date: Tue, 30 Sep 2025 22:45:47 +0900 Subject: dt-bindings: mmc: Correct typo "upto" to "up to" The word "upto" is a typo for "up to". Correct this typo in the mmc-controller-common binding documentation. Signed-off-by: Akiyoshi Kurita Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml index 1e601da0339a..9a369c8e9cb8 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -85,7 +85,7 @@ properties: - for eMMC, the maximum supported frequency is 200MHz, - for SD/SDIO cards the SDR104 mode has a max supported frequency of 208MHz, - - some mmc host controllers do support a max frequency upto + - some mmc host controllers do support a max frequency up to 384MHz. So, lets keep the maximum supported value here. -- cgit v1.2.3 From b8ef623f18da24ee9e1cf9bef66dacd2e8574902 Mon Sep 17 00:00:00 2001 From: Christian Bruel Date: Wed, 20 Aug 2025 09:54:05 +0200 Subject: dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings STM32MP25 PCIe Controller is based on the DesignWare core configured as endpoint mode from the SYSCFG register. Signed-off-by: Christian Bruel Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250820075411.1178729-6-christian.bruel@foss.st.com --- .../devicetree/bindings/pci/st,stm32-pcie-ep.yaml | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml new file mode 100644 index 000000000000..b076ada4f332 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 PCIe Endpoint + +maintainers: + - Christian Bruel + +description: + PCIe endpoint controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: Data Bus Interface (DBI) shadow registers. + - description: Internal Address Translation Unit (iATU) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: addr_space + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + phys: + maxItems: 1 + +required: + - phys + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pcie-ep@48400000 { + compatible = "st,stm32mp25-pcie-ep"; + reg = <0x48400000 0x400000>, + <0x48500000 0x100000>, + <0x48700000 0x80000>, + <0x10000000 0x10000000>; + reg-names = "dbi", "dbi2", "atu", "addr_space"; + clocks = <&rcc CK_BUS_PCIE>; + phys = <&combophy PHY_TYPE_PCIE>; + resets = <&rcc PCIE_R>; + pinctrl-names = "default", "init"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + }; -- cgit v1.2.3 From 0395a5e8fd07645df6743fd2a6883708196d9d75 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Sat, 27 Sep 2025 10:19:24 +0000 Subject: dt-bindings: i2c: realtek,rtl9301-i2c: fix wording and typos Fix wording of binding description to use plural because there is not only a single RTL9300 SoC. RTL9300 describes a whole family of Realtek SoCs. Add missing word 'of' in description of reg property. Change 'SDA pin' to 'SDA line number' because the property must contain the SDA (channel) number ranging from 0-7 instead of a real pin number. Signed-off-by: Jonas Jelonek Reviewed-by: Rob Herring (Arm) Reviewed-by: Chris Packham Tested-by: Chris Packham # On RTL9302C based board Tested-by: Markus Stockhausen Signed-off-by: Andi Shyti Link: https://lore.kernel.org/r/20250927101931.71575-3-jelonek.jonas@gmail.com --- Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml index 69ac5db8b914..274e2ab8b612 100644 --- a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml @@ -10,7 +10,7 @@ maintainers: - Chris Packham description: - The RTL9300 SoC has two I2C controllers. Each of these has an SCL line (which + RTL9300 SoCs have two I2C controllers. Each of these has an SCL line (which if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be assigned to either I2C controller. @@ -27,7 +27,7 @@ properties: reg: items: - - description: Register offset and size this I2C controller. + - description: Register offset and size of this I2C controller. "#address-cells": const: 1 @@ -42,7 +42,7 @@ patternProperties: properties: reg: - description: The SDA pin associated with the I2C bus. + description: The SDA line number associated with the I2C bus. maxItems: 1 required: -- cgit v1.2.3 From 99fd09e01db2c6fc4c6ffe851b337f64ff93e1b5 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Sat, 27 Sep 2025 10:19:30 +0000 Subject: dt-bindings: i2c: realtek,rtl9301-i2c: extend for RTL9310 support Adjust the regex for child-node address to account for the fact that RTL9310 supports 12 instead of only 8 SDA lines. Also, narrow this per variant. Add a vendor-specific property to explicitly specify the SCL line number of the defined I2C controller/master. This is required, in particular for RTL9310, to operate on the correct SCL for each controller. Require this property to be specified for RTL9310. Add compatibles for known SoC variants RTL9311, RTL9312 and RTL9313. Signed-off-by: Jonas Jelonek Reviewed-by: Rob Herring (Arm) Reviewed-by: Chris Packham Tested-by: Markus Stockhausen Signed-off-by: Andi Shyti Link: https://lore.kernel.org/r/20250927101931.71575-9-jelonek.jonas@gmail.com --- .../bindings/i2c/realtek,rtl9301-i2c.yaml | 39 ++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml index 274e2ab8b612..17ce39c19ab1 100644 --- a/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/realtek,rtl9301-i2c.yaml @@ -13,6 +13,8 @@ description: RTL9300 SoCs have two I2C controllers. Each of these has an SCL line (which if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be assigned to either I2C controller. + RTL9310 SoCs have equal capabilities but support 12 common SDA lines which + can be assigned to either I2C controller. properties: compatible: @@ -23,7 +25,15 @@ properties: - realtek,rtl9302c-i2c - realtek,rtl9303-i2c - const: realtek,rtl9301-i2c - - const: realtek,rtl9301-i2c + - items: + - enum: + - realtek,rtl9311-i2c + - realtek,rtl9312-i2c + - realtek,rtl9313-i2c + - const: realtek,rtl9310-i2c + - enum: + - realtek,rtl9301-i2c + - realtek,rtl9310-i2c reg: items: @@ -35,8 +45,14 @@ properties: "#size-cells": const: 0 + realtek,scl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The SCL line number of this I2C controller. + enum: [ 0, 1 ] + patternProperties: - '^i2c@[0-7]$': + '^i2c@[0-9ab]$': $ref: /schemas/i2c/i2c-controller.yaml unevaluatedProperties: false @@ -48,6 +64,25 @@ patternProperties: required: - reg + +allOf: + - if: + properties: + compatible: + contains: + const: realtek,rtl9310-i2c + then: + required: + - realtek,scl + - if: + properties: + compatible: + contains: + const: realtek,rtl9301-i2c + then: + patternProperties: + '^i2c@[89ab]$': false + required: - compatible - reg -- cgit v1.2.3 From a6b4f791cdc56655b2dee8ac793f5b28dc4e542d Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 24 Sep 2025 17:28:46 -0500 Subject: dt-bindings: rtc: Convert apm,xgene-rtc to DT schema Convert the APM XGene RTC binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250924222848.2949235-1-robh@kernel.org Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/apm,xgene-rtc.yaml | 45 ++++++++++++++++++++++ .../devicetree/bindings/rtc/xgene-rtc.txt | 28 -------------- 2 files changed, 45 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/rtc/apm,xgene-rtc.yaml delete mode 100644 Documentation/devicetree/bindings/rtc/xgene-rtc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/apm,xgene-rtc.yaml b/Documentation/devicetree/bindings/rtc/apm,xgene-rtc.yaml new file mode 100644 index 000000000000..b8f46536fd5a --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/apm,xgene-rtc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/apm,xgene-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene Real Time Clock + +maintainers: + - Khuong Dinh + +properties: + compatible: + const: apm,xgene-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + - clocks + +additionalProperties: false + +examples: + - | + rtc@10510000 { + compatible = "apm,xgene-rtc"; + reg = <0x10510000 0x400>; + interrupts = <0x0 0x46 0x4>; + #clock-cells = <1>; + clocks = <&rtcclk 0>; + }; diff --git a/Documentation/devicetree/bindings/rtc/xgene-rtc.txt b/Documentation/devicetree/bindings/rtc/xgene-rtc.txt deleted file mode 100644 index fd195c358446..000000000000 --- a/Documentation/devicetree/bindings/rtc/xgene-rtc.txt +++ /dev/null @@ -1,28 +0,0 @@ -* APM X-Gene Real Time Clock - -RTC controller for the APM X-Gene Real Time Clock - -Required properties: -- compatible : Should be "apm,xgene-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the RTC. -- #clock-cells: Should be 1. -- clocks: Reference to the clock entry. - -Example: - -rtcclk: rtcclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "rtcclk"; -}; - -rtc: rtc@10510000 { - compatible = "apm,xgene-rtc"; - reg = <0x0 0x10510000 0x0 0x400>; - interrupts = <0x0 0x46 0x4>; - #clock-cells = <1>; - clocks = <&rtcclk 0>; -}; -- cgit v1.2.3 From 526ce9eb455e03a6dcdbf9a6c57c777c06d1ddf2 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Wed, 24 Sep 2025 20:18:31 +0530 Subject: dt-bindings: mailbox: qcom: Document Glymur CPUCP mailbox controller binding Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm Glymur SoCs. It is software compatible with X1E80100 CPUCP mailbox controller hence fallback to it. Signed-off-by: Sibi Sankar Acked-by: Rob Herring (Arm) Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index f7342d04beec..9122c3d2dc30 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -15,8 +15,13 @@ description: properties: compatible: - items: - - const: qcom,x1e80100-cpucp-mbox + oneOf: + - items: + - enum: + - qcom,glymur-cpucp-mbox + - const: qcom,x1e80100-cpucp-mbox + - enum: + - qcom,x1e80100-cpucp-mbox reg: items: -- cgit v1.2.3 From 426f4e9414df5d51e7bc6519edb82bccf07ce52f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:39 +0200 Subject: dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional The GCE Mailbox needs only one clock and the clock-names can be used only by the driver (which, for instance, does not use it), and this is true for all of the currently supported MediaTek SoCs. Stop requiring to specify clock-names on all non-MT8195 GCEs. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Acked-by: Rob Herring (Arm) Reviewed-by: Matthias Brugger Signed-off-by: Jassi Brar --- .../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml index 73d6db34d64a..587126d03fc6 100644 --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml @@ -60,17 +60,6 @@ required: - interrupts - clocks -allOf: - - if: - not: - properties: - compatible: - contains: - const: mediatek,mt8195-gce - then: - required: - - clock-names - additionalProperties: false examples: -- cgit v1.2.3 From d3e35a151a84ee607c817c08692dfd71568b3e0c Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Fri, 3 Oct 2025 22:15:05 +0200 Subject: dt-bindings: mailbox: Add MT8196 GPUEB Mailbox The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB", acting as glue logic to control power and frequency of the Mali GPU. This MCU runs special-purpose firmware for this use, and the main application processor communicates with it through a mailbox. Add a binding that describes this mailbox. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Signed-off-by: Nicolas Frattaroli Signed-off-by: Jassi Brar --- .../mailbox/mediatek,mt8196-gpueb-mbox.yaml | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpueb-mbox.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpueb-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpueb-mbox.yaml new file mode 100644 index 000000000000..ab5b780cb83a --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpueb-mbox.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-gpueb-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics GPUEB Mailbox Controller + +maintainers: + - Nicolas Frattaroli + +properties: + compatible: + enum: + - mediatek,mt8196-gpueb-mbox + + reg: + items: + - description: mailbox data registers + - description: mailbox control registers + + reg-names: + items: + - const: data + - const: ctl + + clocks: + items: + - description: main clock of the GPUEB MCU + + interrupts: + items: + - description: fires when a new message is received + + "#mbox-cells": + const: 1 + description: + The number of the mailbox channel. + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + mailbox@4b09fd80 { + compatible = "mediatek,mt8196-gpueb-mbox"; + reg = <0x4b09fd80 0x280>, + <0x4b170000 0x7c>; + reg-names = "data", "ctl"; + clocks = <&topckgen CLK_TOP_MFG_EB>; + interrupts = ; + #mbox-cells = <1>; + }; -- cgit v1.2.3 From eb4faf6343889fcd7edba3deeae49fc5a06531fd Mon Sep 17 00:00:00 2001 From: Kael D'Alcamo Date: Wed, 8 Oct 2025 22:04:27 +0200 Subject: dt-bindings: i2c: hisilicon,hix5hd2: convert to DT schema Convert the Devicetree binding documentation for hisilicon,hix5hd2-i2c from plain text to DT binding schema. Signed-off-by: Kael D'Alcamo Reviewed-by: Krzysztof Kozlowski Signed-off-by: Wolfram Sang --- .../bindings/i2c/hisilicon,hix5hd2-i2c.yaml | 51 ++++++++++++++++++++++ .../devicetree/bindings/i2c/i2c-hix5hd2.txt | 24 ---------- 2 files changed, 51 insertions(+), 24 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/hisilicon,hix5hd2-i2c.yaml delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/hisilicon,hix5hd2-i2c.yaml b/Documentation/devicetree/bindings/i2c/hisilicon,hix5hd2-i2c.yaml new file mode 100644 index 000000000000..3faa7954e411 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/hisilicon,hix5hd2-i2c.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/hisilicon,hix5hd2-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: I2C for HiSilicon hix5hd2 chipset platform + +maintainers: + - Wei Yan + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - hisilicon,hix5hd2-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: Desired I2C bus frequency in Hz + default: 100000 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + + i2c@f8b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b10000 0x1000>; + interrupts = <0 38 4>; + clocks = <&clock HIX5HD2_I2C0_RST>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt deleted file mode 100644 index f98b37401e6e..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt +++ /dev/null @@ -1,24 +0,0 @@ -I2C for Hisilicon hix5hd2 chipset platform - -Required properties: -- compatible: Must be "hisilicon,hix5hd2-i2c" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: interrupt number to the cpu. -- #address-cells = <1>; -- #size-cells = <0>; -- clocks: phandles to input clocks. - -Optional properties: -- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 -- Child nodes conforming to i2c bus binding - -Examples: -I2C0@f8b10000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0xf8b10000 0x1000>; - interrupts = <0 38 4>; - clocks = <&clock HIX5HD2_I2C0_RST>; - #address-cells = <1>; - #size-cells = <0>; -} -- cgit v1.2.3 From f7045387a6816d51d462447af4522785e1c7251c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 9 Oct 2025 20:37:43 +0200 Subject: dt-bindings: bus: allwinner,sun50i-a64-de2: don't check node names Node names are already and properly checked by the core schema. No need to do it again. Signed-off-by: Wolfram Sang [robh: Also drop [A-F] in unit address] Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml index 9845a187bdf6..232252e8825e 100644 --- a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml +++ b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml @@ -44,7 +44,7 @@ properties: patternProperties: # All other properties should be child nodes with unit-address and 'reg' - "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$": + "@[0-9a-f]+$": type: object additionalProperties: true properties: -- cgit v1.2.3 From ce740955b238761ec1d8cf0590d7e6802d3a813a Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 9 Oct 2025 20:34:53 +0200 Subject: dt-bindings: bus: renesas-bsc: allow additional properties Allow additional properties to enable devices attached to the bus. Fixes warnings like these: arch/arm/boot/dts/renesas/sh73a0-kzm9g.dtb: bus@fec10000 (renesas,bsc-sh73a0): Unevaluated properties are not allowed ('ethernet@10000000' was unexpected) arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dtb: bus@fec10000 (renesas,bsc-r8a73a4): Unevaluated properties are not allowed ('ethernet@8000000', 'flash@0' were unexpected) Reviewed-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/bus/renesas,bsc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/renesas,bsc.yaml b/Documentation/devicetree/bindings/bus/renesas,bsc.yaml index f53a37785413..ff3c78317d28 100644 --- a/Documentation/devicetree/bindings/bus/renesas,bsc.yaml +++ b/Documentation/devicetree/bindings/bus/renesas,bsc.yaml @@ -41,6 +41,18 @@ properties: interrupts: maxItems: 1 +patternProperties: + # All other properties should be child nodes with unit-address and 'reg' + "@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + reg: + maxItems: 1 + + required: + - reg + required: - reg -- cgit v1.2.3