From 2f304c0a0a55072b80957580f1b66256a615d8da Mon Sep 17 00:00:00 2001 From: Jens Axboe Date: Tue, 17 Jun 2008 10:45:23 +0200 Subject: mips: convert to generic helpers for IPI function calls This converts mips to use the new helpers for smp_call_function() and friends, and adds support for smp_call_function_single(). Not tested, but it compiles. mips shares the same IPI for smp_call_function() and smp_call_function_single(), since not all mips platforms have enough available IPIs to support seperate setups. Cc: Ralf Baechle Signed-off-by: Jens Axboe --- include/asm-mips/smp.h | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 84fef1aeec0c..0ff5b523ea77 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -35,16 +35,6 @@ extern int __cpu_logical_map[NR_CPUS]; #define NO_PROC_ID (-1) -struct call_data_struct { - void (*func)(void *); - void *info; - atomic_t started; - atomic_t finished; - int wait; -}; - -extern struct call_data_struct *call_data; - #define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ #define SMP_CALL_FUNCTION 0x2 @@ -67,4 +57,7 @@ static inline void smp_send_reschedule(int cpu) extern asmlinkage void smp_call_function_interrupt(void); +extern void arch_send_call_function_single_ipi(int cpu); +extern void arch_send_call_function_ipi(cpumask_t mask); + #endif /* __ASM_SMP_H */ -- cgit v1.2.3 From 4a161d235b68eb7234f40106560c488a1bdb3851 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 9 Jul 2008 16:27:56 +0200 Subject: ALSA: ASoC: Au12x0/Au1550 PSC Audio support Audio for Au12x0/Au1550 PSCs in AC97 and I2S mode, for ASoC v1 framework. - DBDMA, AC97 and I2S drivers - sample AC97 machine code (Db1200) Signed-off-by: Manuel Lauss Signed-off-by: Liam Girdwood Signed-off-by: Takashi Iwai Signed-off-by: Jaroslav Kysela --- include/asm-mips/mach-au1x00/au1xxx_psc.h | 8 + sound/soc/Kconfig | 1 + sound/soc/Makefile | 2 +- sound/soc/au1x/Kconfig | 32 +++ sound/soc/au1x/Makefile | 13 + sound/soc/au1x/dbdma2.c | 421 ++++++++++++++++++++++++++++++ sound/soc/au1x/psc-ac97.c | 387 +++++++++++++++++++++++++++ sound/soc/au1x/psc-i2s.c | 414 +++++++++++++++++++++++++++++ sound/soc/au1x/psc.h | 53 ++++ sound/soc/au1x/sample-ac97.c | 144 ++++++++++ 10 files changed, 1474 insertions(+), 1 deletion(-) create mode 100644 sound/soc/au1x/Kconfig create mode 100644 sound/soc/au1x/Makefile create mode 100644 sound/soc/au1x/dbdma2.c create mode 100644 sound/soc/au1x/psc-ac97.c create mode 100644 sound/soc/au1x/psc-i2s.c create mode 100644 sound/soc/au1x/psc.h create mode 100644 sound/soc/au1x/sample-ac97.c (limited to 'include/asm-mips') diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h index dae4eca2417e..892b7f168eb4 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_psc.h +++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h @@ -204,6 +204,14 @@ typedef struct psc_i2s { u32 psc_i2sudf; } psc_i2s_t; +#define PSC_I2SCFG_OFFSET 0x08 +#define PSC_I2SMASK_OFFSET 0x0C +#define PSC_I2SPCR_OFFSET 0x10 +#define PSC_I2SSTAT_OFFSET 0x14 +#define PSC_I2SEVENT_OFFSET 0x18 +#define PSC_I2SRXTX_OFFSET 0x1C +#define PSC_I2SUDF_OFFSET 0x20 + /* I2S Config Register. */ #define PSC_I2SCFG_RT_MASK (3 << 30) #define PSC_I2SCFG_RT_FIFO1 (0 << 30) diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index b939e22db7b4..f743530add8f 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -24,6 +24,7 @@ config SND_SOC_AC97_BUS # All the supported Soc's source "sound/soc/at32/Kconfig" source "sound/soc/at91/Kconfig" +source "sound/soc/au1x/Kconfig" source "sound/soc/pxa/Kconfig" source "sound/soc/s3c24xx/Kconfig" source "sound/soc/sh/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 3645f959c264..933a66d30804 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -2,4 +2,4 @@ snd-soc-core-objs := soc-core.o soc-dapm.o obj-$(CONFIG_SND_SOC) += snd-soc-core.o obj-$(CONFIG_SND_SOC) += codecs/ at32/ at91/ pxa/ s3c24xx/ sh/ fsl/ davinci/ -obj-$(CONFIG_SND_SOC) += omap/ +obj-$(CONFIG_SND_SOC) += omap/ au1x/ diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig new file mode 100644 index 000000000000..410a893aa66b --- /dev/null +++ b/sound/soc/au1x/Kconfig @@ -0,0 +1,32 @@ +## +## Au1200/Au1550 PSC + DBDMA +## +config SND_SOC_AU1XPSC + tristate "SoC Audio for Au1200/Au1250/Au1550" + depends on SOC_AU1200 || SOC_AU1550 + help + This option enables support for the Programmable Serial + Controllers in AC97 and I2S mode, and the Descriptor-Based DMA + Controller (DBDMA) as found on the Au1200/Au1250/Au1550 SoC. + +config SND_SOC_AU1XPSC_I2S + tristate + +config SND_SOC_AU1XPSC_AC97 + tristate + select AC97_BUS + select SND_AC97_CODEC + select SND_SOC_AC97_BUS + + +## +## Boards +## +config SND_SOC_SAMPLE_PSC_AC97 + tristate "Sample Au12x0/Au1550 PSC AC97 sound machine" + depends on SND_SOC_AU1XPSC + select SND_SOC_AU1XPSC_AC97 + select SND_SOC_AC97_CODEC + help + This is a sample AC97 sound machine for use in Au12x0/Au1550 + based systems which have audio on PSC1 (e.g. Db1200 demoboard). diff --git a/sound/soc/au1x/Makefile b/sound/soc/au1x/Makefile new file mode 100644 index 000000000000..6c6950b8003a --- /dev/null +++ b/sound/soc/au1x/Makefile @@ -0,0 +1,13 @@ +# Au1200/Au1550 PSC audio +snd-soc-au1xpsc-dbdma-objs := dbdma2.o +snd-soc-au1xpsc-i2s-objs := psc-i2s.o +snd-soc-au1xpsc-ac97-objs := psc-ac97.o + +obj-$(CONFIG_SND_SOC_AU1XPSC) += snd-soc-au1xpsc-dbdma.o +obj-$(CONFIG_SND_SOC_AU1XPSC_I2S) += snd-soc-au1xpsc-i2s.o +obj-$(CONFIG_SND_SOC_AU1XPSC_AC97) += snd-soc-au1xpsc-ac97.o + +# Boards +snd-soc-sample-ac97-objs := sample-ac97.o + +obj-$(CONFIG_SND_SOC_SAMPLE_PSC_AC97) += snd-soc-sample-ac97.o diff --git a/sound/soc/au1x/dbdma2.c b/sound/soc/au1x/dbdma2.c new file mode 100644 index 000000000000..1466d9328800 --- /dev/null +++ b/sound/soc/au1x/dbdma2.c @@ -0,0 +1,421 @@ +/* + * Au12x0/Au1550 PSC ALSA ASoC audio support. + * + * (c) 2007-2008 MSC Vertriebsges.m.b.H., + * Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * DMA glue for Au1x-PSC audio. + * + * NOTE: all of these drivers can only work with a SINGLE instance + * of a PSC. Multiple independent audio devices are impossible + * with ASoC v1. + */ + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "psc.h" + +/*#define PCM_DEBUG*/ + +#define MSG(x...) printk(KERN_INFO "au1xpsc_pcm: " x) +#ifdef PCM_DEBUG +#define DBG MSG +#else +#define DBG(x...) do {} while (0) +#endif + +struct au1xpsc_audio_dmadata { + /* DDMA control data */ + unsigned int ddma_id; /* DDMA direction ID for this PSC */ + u32 ddma_chan; /* DDMA context */ + + /* PCM context (for irq handlers) */ + struct snd_pcm_substream *substream; + unsigned long curr_period; /* current segment DDMA is working on */ + unsigned long q_period; /* queue period(s) */ + unsigned long dma_area; /* address of queued DMA area */ + unsigned long dma_area_s; /* start address of DMA area */ + unsigned long pos; /* current byte position being played */ + unsigned long periods; /* number of SG segments in total */ + unsigned long period_bytes; /* size in bytes of one SG segment */ + + /* runtime data */ + int msbits; +}; + +/* instance data. There can be only one, MacLeod!!!! */ +static struct au1xpsc_audio_dmadata *au1xpsc_audio_pcmdma[2]; + +/* + * These settings are somewhat okay, at least on my machine audio plays + * almost skip-free. Especially the 64kB buffer seems to help a LOT. + */ +#define AU1XPSC_PERIOD_MIN_BYTES 1024 +#define AU1XPSC_BUFFER_MIN_BYTES 65536 + +#define AU1XPSC_PCM_FMTS \ + (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \ + SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \ + SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE | \ + SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE | \ + SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE | \ + 0) + +/* PCM hardware DMA capabilities - platform specific */ +static const struct snd_pcm_hardware au1xpsc_pcm_hardware = { + .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED, + .formats = AU1XPSC_PCM_FMTS, + .period_bytes_min = AU1XPSC_PERIOD_MIN_BYTES, + .period_bytes_max = 4096 * 1024 - 1, + .periods_min = 2, + .periods_max = 4096, /* 2 to as-much-as-you-like */ + .buffer_bytes_max = 4096 * 1024 - 1, + .fifo_size = 16, /* fifo entries of AC97/I2S PSC */ +}; + +static void au1x_pcm_queue_tx(struct au1xpsc_audio_dmadata *cd) +{ + au1xxx_dbdma_put_source_flags(cd->ddma_chan, + (void *)phys_to_virt(cd->dma_area), + cd->period_bytes, DDMA_FLAGS_IE); + + /* update next-to-queue period */ + ++cd->q_period; + cd->dma_area += cd->period_bytes; + if (cd->q_period >= cd->periods) { + cd->q_period = 0; + cd->dma_area = cd->dma_area_s; + } +} + +static void au1x_pcm_queue_rx(struct au1xpsc_audio_dmadata *cd) +{ + au1xxx_dbdma_put_dest_flags(cd->ddma_chan, + (void *)phys_to_virt(cd->dma_area), + cd->period_bytes, DDMA_FLAGS_IE); + + /* update next-to-queue period */ + ++cd->q_period; + cd->dma_area += cd->period_bytes; + if (cd->q_period >= cd->periods) { + cd->q_period = 0; + cd->dma_area = cd->dma_area_s; + } +} + +static void au1x_pcm_dmatx_cb(int irq, void *dev_id) +{ + struct au1xpsc_audio_dmadata *cd = dev_id; + + cd->pos += cd->period_bytes; + if (++cd->curr_period >= cd->periods) { + cd->pos = 0; + cd->curr_period = 0; + } + snd_pcm_period_elapsed(cd->substream); + au1x_pcm_queue_tx(cd); +} + +static void au1x_pcm_dmarx_cb(int irq, void *dev_id) +{ + struct au1xpsc_audio_dmadata *cd = dev_id; + + cd->pos += cd->period_bytes; + if (++cd->curr_period >= cd->periods) { + cd->pos = 0; + cd->curr_period = 0; + } + snd_pcm_period_elapsed(cd->substream); + au1x_pcm_queue_rx(cd); +} + +static void au1x_pcm_dbdma_free(struct au1xpsc_audio_dmadata *pcd) +{ + if (pcd->ddma_chan) { + au1xxx_dbdma_stop(pcd->ddma_chan); + au1xxx_dbdma_reset(pcd->ddma_chan); + au1xxx_dbdma_chan_free(pcd->ddma_chan); + pcd->ddma_chan = 0; + pcd->msbits = 0; + } +} + +/* in case of missing DMA ring or changed TX-source / RX-dest bit widths, + * allocate (or reallocate) a 2-descriptor DMA ring with bit depth according + * to ALSA-supplied sample depth. This is due to limitations in the dbdma api + * (cannot adjust source/dest widths of already allocated descriptor ring). + */ +static int au1x_pcm_dbdma_realloc(struct au1xpsc_audio_dmadata *pcd, + int stype, int msbits) +{ + /* DMA only in 8/16/32 bit widths */ + if (msbits == 24) + msbits = 32; + + /* check current config: correct bits and descriptors allocated? */ + if ((pcd->ddma_chan) && (msbits == pcd->msbits)) + goto out; /* all ok! */ + + au1x_pcm_dbdma_free(pcd); + + if (stype == PCM_RX) + pcd->ddma_chan = au1xxx_dbdma_chan_alloc(pcd->ddma_id, + DSCR_CMD0_ALWAYS, + au1x_pcm_dmarx_cb, (void *)pcd); + else + pcd->ddma_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, + pcd->ddma_id, + au1x_pcm_dmatx_cb, (void *)pcd); + + if (!pcd->ddma_chan) + return -ENOMEM;; + + au1xxx_dbdma_set_devwidth(pcd->ddma_chan, msbits); + au1xxx_dbdma_ring_alloc(pcd->ddma_chan, 2); + + pcd->msbits = msbits; + + au1xxx_dbdma_stop(pcd->ddma_chan); + au1xxx_dbdma_reset(pcd->ddma_chan); + +out: + return 0; +} + +static int au1xpsc_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct au1xpsc_audio_dmadata *pcd; + int stype, ret; + + ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); + if (ret < 0) + goto out; + + stype = SUBSTREAM_TYPE(substream); + pcd = au1xpsc_audio_pcmdma[stype]; + + DBG("runtime->dma_area = 0x%08lx dma_addr_t = 0x%08lx dma_size = %d " + "runtime->min_align %d\n", + (unsigned long)runtime->dma_area, + (unsigned long)runtime->dma_addr, runtime->dma_bytes, + runtime->min_align); + + DBG("bits %d frags %d frag_bytes %d is_rx %d\n", params->msbits, + params_periods(params), params_period_bytes(params), stype); + + ret = au1x_pcm_dbdma_realloc(pcd, stype, params->msbits); + if (ret) { + MSG("DDMA channel (re)alloc failed!\n"); + goto out; + } + + pcd->substream = substream; + pcd->period_bytes = params_period_bytes(params); + pcd->periods = params_periods(params); + pcd->dma_area_s = pcd->dma_area = (unsigned long)runtime->dma_addr; + pcd->q_period = 0; + pcd->curr_period = 0; + pcd->pos = 0; + + ret = 0; +out: + return ret; +} + +static int au1xpsc_pcm_hw_free(struct snd_pcm_substream *substream) +{ + snd_pcm_lib_free_pages(substream); + return 0; +} + +static int au1xpsc_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct au1xpsc_audio_dmadata *pcd = + au1xpsc_audio_pcmdma[SUBSTREAM_TYPE(substream)]; + + au1xxx_dbdma_reset(pcd->ddma_chan); + + if (SUBSTREAM_TYPE(substream) == PCM_RX) { + au1x_pcm_queue_rx(pcd); + au1x_pcm_queue_rx(pcd); + } else { + au1x_pcm_queue_tx(pcd); + au1x_pcm_queue_tx(pcd); + } + + return 0; +} + +static int au1xpsc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + u32 c = au1xpsc_audio_pcmdma[SUBSTREAM_TYPE(substream)]->ddma_chan; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + au1xxx_dbdma_start(c); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + au1xxx_dbdma_stop(c); + break; + default: + return -EINVAL; + } + return 0; +} + +static snd_pcm_uframes_t +au1xpsc_pcm_pointer(struct snd_pcm_substream *substream) +{ + return bytes_to_frames(substream->runtime, + au1xpsc_audio_pcmdma[SUBSTREAM_TYPE(substream)]->pos); +} + +static int au1xpsc_pcm_open(struct snd_pcm_substream *substream) +{ + snd_soc_set_runtime_hwparams(substream, &au1xpsc_pcm_hardware); + return 0; +} + +static int au1xpsc_pcm_close(struct snd_pcm_substream *substream) +{ + au1x_pcm_dbdma_free(au1xpsc_audio_pcmdma[SUBSTREAM_TYPE(substream)]); + return 0; +} + +struct snd_pcm_ops au1xpsc_pcm_ops = { + .open = au1xpsc_pcm_open, + .close = au1xpsc_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = au1xpsc_pcm_hw_params, + .hw_free = au1xpsc_pcm_hw_free, + .prepare = au1xpsc_pcm_prepare, + .trigger = au1xpsc_pcm_trigger, + .pointer = au1xpsc_pcm_pointer, +}; + +static void au1xpsc_pcm_free_dma_buffers(struct snd_pcm *pcm) +{ + snd_pcm_lib_preallocate_free_for_all(pcm); +} + +static int au1xpsc_pcm_new(struct snd_card *card, + struct snd_soc_dai *dai, + struct snd_pcm *pcm) +{ + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, + card->dev, AU1XPSC_BUFFER_MIN_BYTES, (4096 * 1024) - 1); + + return 0; +} + +static int au1xpsc_pcm_probe(struct platform_device *pdev) +{ + struct resource *r; + int ret; + + if (au1xpsc_audio_pcmdma[PCM_TX] || au1xpsc_audio_pcmdma[PCM_RX]) + return -EBUSY; + + /* TX DMA */ + au1xpsc_audio_pcmdma[PCM_TX] + = kzalloc(sizeof(struct au1xpsc_audio_dmadata), GFP_KERNEL); + if (!au1xpsc_audio_pcmdma[PCM_TX]) + return -ENOMEM; + + r = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!r) { + ret = -ENODEV; + goto out1; + } + (au1xpsc_audio_pcmdma[PCM_TX])->ddma_id = r->start; + + /* RX DMA */ + au1xpsc_audio_pcmdma[PCM_RX] + = kzalloc(sizeof(struct au1xpsc_audio_dmadata), GFP_KERNEL); + if (!au1xpsc_audio_pcmdma[PCM_RX]) + return -ENOMEM; + + r = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (!r) { + ret = -ENODEV; + goto out2; + } + (au1xpsc_audio_pcmdma[PCM_RX])->ddma_id = r->start; + + return 0; + +out2: + kfree(au1xpsc_audio_pcmdma[PCM_RX]); + au1xpsc_audio_pcmdma[PCM_RX] = NULL; +out1: + kfree(au1xpsc_audio_pcmdma[PCM_TX]); + au1xpsc_audio_pcmdma[PCM_TX] = NULL; + return ret; +} + +static int au1xpsc_pcm_remove(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < 2; i++) { + if (au1xpsc_audio_pcmdma[i]) { + au1x_pcm_dbdma_free(au1xpsc_audio_pcmdma[i]); + kfree(au1xpsc_audio_pcmdma[i]); + au1xpsc_audio_pcmdma[i] = NULL; + } + } + + return 0; +} + +/* au1xpsc audio platform */ +struct snd_soc_platform au1xpsc_soc_platform = { + .name = "au1xpsc-pcm-dbdma", + .probe = au1xpsc_pcm_probe, + .remove = au1xpsc_pcm_remove, + .pcm_ops = &au1xpsc_pcm_ops, + .pcm_new = au1xpsc_pcm_new, + .pcm_free = au1xpsc_pcm_free_dma_buffers, +}; +EXPORT_SYMBOL_GPL(au1xpsc_soc_platform); + +static int __init au1xpsc_audio_dbdma_init(void) +{ + au1xpsc_audio_pcmdma[PCM_TX] = NULL; + au1xpsc_audio_pcmdma[PCM_RX] = NULL; + return 0; +} + +static void __exit au1xpsc_audio_dbdma_exit(void) +{ +} + +module_init(au1xpsc_audio_dbdma_init); +module_exit(au1xpsc_audio_dbdma_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Au12x0/Au1550 PSC Audio DMA driver"); +MODULE_AUTHOR("Manuel Lauss "); diff --git a/sound/soc/au1x/psc-ac97.c b/sound/soc/au1x/psc-ac97.c new file mode 100644 index 000000000000..57facbad6825 --- /dev/null +++ b/sound/soc/au1x/psc-ac97.c @@ -0,0 +1,387 @@ +/* + * Au12x0/Au1550 PSC ALSA ASoC audio support. + * + * (c) 2007-2008 MSC Vertriebsges.m.b.H., + * Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Au1xxx-PSC AC97 glue. + * + * NOTE: all of these drivers can only work with a SINGLE instance + * of a PSC. Multiple independent audio devices are impossible + * with ASoC v1. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "psc.h" + +#define AC97_DIR \ + (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE) + +#define AC97_RATES \ + SNDRV_PCM_RATE_8000_48000 + +#define AC97_FMTS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3BE) + +#define AC97PCR_START(stype) \ + ((stype) == PCM_TX ? PSC_AC97PCR_TS : PSC_AC97PCR_RS) +#define AC97PCR_STOP(stype) \ + ((stype) == PCM_TX ? PSC_AC97PCR_TP : PSC_AC97PCR_RP) +#define AC97PCR_CLRFIFO(stype) \ + ((stype) == PCM_TX ? PSC_AC97PCR_TC : PSC_AC97PCR_RC) + +/* instance data. There can be only one, MacLeod!!!! */ +static struct au1xpsc_audio_data *au1xpsc_ac97_workdata; + +/* AC97 controller reads codec register */ +static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97, + unsigned short reg) +{ + /* FIXME */ + struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; + unsigned short data, tmo; + + au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), AC97_CDC(pscdata)); + au_sync(); + + tmo = 1000; + while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)) && --tmo) + udelay(2); + + if (!tmo) + data = 0xffff; + else + data = au_readl(AC97_CDC(pscdata)) & 0xffff; + + au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); + au_sync(); + + return data; +} + +/* AC97 controller writes to codec register */ +static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg, + unsigned short val) +{ + /* FIXME */ + struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; + unsigned int tmo; + + au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), AC97_CDC(pscdata)); + au_sync(); + tmo = 1000; + while ((!(au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)) && --tmo) + au_sync(); + + au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); + au_sync(); +} + +/* AC97 controller asserts a warm reset */ +static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97) +{ + /* FIXME */ + struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; + + au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); + au_sync(); + msleep(10); + au_writel(0, AC97_RST(pscdata)); + au_sync(); +} + +static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) +{ + /* FIXME */ + struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; + int i; + + /* disable PSC during cold reset */ + au_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); + au_sync(); + au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata)); + au_sync(); + + /* issue cold reset */ + au_writel(PSC_AC97RST_RST, AC97_RST(pscdata)); + au_sync(); + msleep(500); + au_writel(0, AC97_RST(pscdata)); + au_sync(); + + /* enable PSC */ + au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); + au_sync(); + + /* wait for PSC to indicate it's ready */ + i = 100000; + while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i)) + au_sync(); + + if (i == 0) { + printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n"); + return; + } + + /* enable the ac97 function */ + au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); + au_sync(); + + /* wait for AC97 core to become ready */ + i = 100000; + while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i)) + au_sync(); + if (i == 0) + printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n"); +} + +/* AC97 controller operations */ +struct snd_ac97_bus_ops soc_ac97_ops = { + .read = au1xpsc_ac97_read, + .write = au1xpsc_ac97_write, + .reset = au1xpsc_ac97_cold_reset, + .warm_reset = au1xpsc_ac97_warm_reset, +}; +EXPORT_SYMBOL_GPL(soc_ac97_ops); + +static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + /* FIXME */ + struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; + unsigned long r, stat; + int chans, stype = SUBSTREAM_TYPE(substream); + + chans = params_channels(params); + + r = au_readl(AC97_CFG(pscdata)); + stat = au_readl(AC97_STAT(pscdata)); + + /* already active? */ + if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) { + /* reject parameters not currently set up */ + if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) || + (pscdata->rate != params_rate(params))) + return -EINVAL; + } else { + /* disable AC97 device controller first */ + au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); + au_sync(); + + /* set sample bitdepth: REG[24:21]=(BITS-2)/2 */ + r &= ~PSC_AC97CFG_LEN_MASK; + r |= PSC_AC97CFG_SET_LEN(params->msbits); + + /* channels: enable slots for front L/R channel */ + if (stype == PCM_TX) { + r &= ~PSC_AC97CFG_TXSLOT_MASK; + r |= PSC_AC97CFG_TXSLOT_ENA(3); + r |= PSC_AC97CFG_TXSLOT_ENA(4); + } else { + r &= ~PSC_AC97CFG_RXSLOT_MASK; + r |= PSC_AC97CFG_RXSLOT_ENA(3); + r |= PSC_AC97CFG_RXSLOT_ENA(4); + } + + /* finally enable the AC97 controller again */ + au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); + au_sync(); + + pscdata->cfg = r; + pscdata->rate = params_rate(params); + } + + return 0; +} + +static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream, + int cmd) +{ + /* FIXME */ + struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; + int ret, stype = SUBSTREAM_TYPE(substream); + + ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + au_writel(AC97PCR_START(stype), AC97_PCR(pscdata)); + au_sync(); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata)); + au_sync(); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int au1xpsc_ac97_probe(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + int ret; + struct resource *r; + unsigned long sel; + + if (au1xpsc_ac97_workdata) + return -EBUSY; + + au1xpsc_ac97_workdata = + kzalloc(sizeof(struct au1xpsc_audio_data), GFP_KERNEL); + if (!au1xpsc_ac97_workdata) + return -ENOMEM; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENODEV; + goto out0; + } + + ret = -EBUSY; + au1xpsc_ac97_workdata->ioarea = + request_mem_region(r->start, r->end - r->start + 1, + "au1xpsc_ac97"); + if (!au1xpsc_ac97_workdata->ioarea) + goto out0; + + au1xpsc_ac97_workdata->mmio = ioremap(r->start, 0xffff); + if (!au1xpsc_ac97_workdata->mmio) + goto out1; + + /* configuration: max dma trigger threshold, enable ac97 */ + au1xpsc_ac97_workdata->cfg = PSC_AC97CFG_RT_FIFO8 | + PSC_AC97CFG_TT_FIFO8 | + PSC_AC97CFG_DE_ENABLE; + + /* preserve PSC clock source set up by platform (dev.platform_data + * is already occupied by soc layer) + */ + sel = au_readl(PSC_SEL(au1xpsc_ac97_workdata)) & PSC_SEL_CLK_MASK; + au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata)); + au_sync(); + au_writel(0, PSC_SEL(au1xpsc_ac97_workdata)); + au_sync(); + au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(au1xpsc_ac97_workdata)); + au_sync(); + /* next up: cold reset. Dont check for PSC-ready now since + * there may not be any codec clock yet. + */ + + return 0; + +out1: + release_resource(au1xpsc_ac97_workdata->ioarea); + kfree(au1xpsc_ac97_workdata->ioarea); +out0: + kfree(au1xpsc_ac97_workdata); + au1xpsc_ac97_workdata = NULL; + return ret; +} + +static void au1xpsc_ac97_remove(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + /* disable PSC completely */ + au_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); + au_sync(); + au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata)); + au_sync(); + + iounmap(au1xpsc_ac97_workdata->mmio); + release_resource(au1xpsc_ac97_workdata->ioarea); + kfree(au1xpsc_ac97_workdata->ioarea); + kfree(au1xpsc_ac97_workdata); + au1xpsc_ac97_workdata = NULL; +} + +static int au1xpsc_ac97_suspend(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + /* save interesting registers and disable PSC */ + au1xpsc_ac97_workdata->pm[0] = + au_readl(PSC_SEL(au1xpsc_ac97_workdata)); + + au_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); + au_sync(); + au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_ac97_workdata)); + au_sync(); + + return 0; +} + +static int au1xpsc_ac97_resume(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + /* restore PSC clock config */ + au_writel(au1xpsc_ac97_workdata->pm[0] | PSC_SEL_PS_AC97MODE, + PSC_SEL(au1xpsc_ac97_workdata)); + au_sync(); + + /* after this point the ac97 core will cold-reset the codec. + * During cold-reset the PSC is reinitialized and the last + * configuration set up in hw_params() is restored. + */ + return 0; +} + +struct snd_soc_dai au1xpsc_ac97_dai = { + .name = "au1xpsc_ac97", + .type = SND_SOC_DAI_AC97, + .probe = au1xpsc_ac97_probe, + .remove = au1xpsc_ac97_remove, + .suspend = au1xpsc_ac97_suspend, + .resume = au1xpsc_ac97_resume, + .playback = { + .rates = AC97_RATES, + .formats = AC97_FMTS, + .channels_min = 2, + .channels_max = 2, + }, + .capture = { + .rates = AC97_RATES, + .formats = AC97_FMTS, + .channels_min = 2, + .channels_max = 2, + }, + .ops = { + .trigger = au1xpsc_ac97_trigger, + .hw_params = au1xpsc_ac97_hw_params, + }, +}; +EXPORT_SYMBOL_GPL(au1xpsc_ac97_dai); + +static int __init au1xpsc_ac97_init(void) +{ + au1xpsc_ac97_workdata = NULL; + return 0; +} + +static void __exit au1xpsc_ac97_exit(void) +{ +} + +module_init(au1xpsc_ac97_init); +module_exit(au1xpsc_ac97_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver"); +MODULE_AUTHOR("Manuel Lauss "); diff --git a/sound/soc/au1x/psc-i2s.c b/sound/soc/au1x/psc-i2s.c new file mode 100644 index 000000000000..ba4b5c199f21 --- /dev/null +++ b/sound/soc/au1x/psc-i2s.c @@ -0,0 +1,414 @@ +/* + * Au12x0/Au1550 PSC ALSA ASoC audio support. + * + * (c) 2007-2008 MSC Vertriebsges.m.b.H., + * Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Au1xxx-PSC I2S glue. + * + * NOTE: all of these drivers can only work with a SINGLE instance + * of a PSC. Multiple independent audio devices are impossible + * with ASoC v1. + * NOTE: so far only PSC slave mode (bit- and frameclock) is supported. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "psc.h" + +/* supported I2S DAI hardware formats */ +#define AU1XPSC_I2S_DAIFMT \ + (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | \ + SND_SOC_DAIFMT_NB_NF) + +/* supported I2S direction */ +#define AU1XPSC_I2S_DIR \ + (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE) + +#define AU1XPSC_I2S_RATES \ + SNDRV_PCM_RATE_8000_192000 + +#define AU1XPSC_I2S_FMTS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) + +#define I2SSTAT_BUSY(stype) \ + ((stype) == PCM_TX ? PSC_I2SSTAT_TB : PSC_I2SSTAT_RB) +#define I2SPCR_START(stype) \ + ((stype) == PCM_TX ? PSC_I2SPCR_TS : PSC_I2SPCR_RS) +#define I2SPCR_STOP(stype) \ + ((stype) == PCM_TX ? PSC_I2SPCR_TP : PSC_I2SPCR_RP) +#define I2SPCR_CLRFIFO(stype) \ + ((stype) == PCM_TX ? PSC_I2SPCR_TC : PSC_I2SPCR_RC) + + +/* instance data. There can be only one, MacLeod!!!! */ +static struct au1xpsc_audio_data *au1xpsc_i2s_workdata; + +static int au1xpsc_i2s_set_fmt(struct snd_soc_dai *cpu_dai, + unsigned int fmt) +{ + struct au1xpsc_audio_data *pscdata = au1xpsc_i2s_workdata; + unsigned long ct; + int ret; + + ret = -EINVAL; + + ct = pscdata->cfg; + + ct &= ~(PSC_I2SCFG_XM | PSC_I2SCFG_MLJ); /* left-justified */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + ct |= PSC_I2SCFG_XM; /* enable I2S mode */ + break; + case SND_SOC_DAIFMT_MSB: + break; + case SND_SOC_DAIFMT_LSB: + ct |= PSC_I2SCFG_MLJ; /* LSB (right-) justified */ + break; + default: + goto out; + } + + ct &= ~(PSC_I2SCFG_BI | PSC_I2SCFG_WI); /* IB-IF */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + ct |= PSC_I2SCFG_BI | PSC_I2SCFG_WI; + break; + case SND_SOC_DAIFMT_NB_IF: + ct |= PSC_I2SCFG_BI; + break; + case SND_SOC_DAIFMT_IB_NF: + ct |= PSC_I2SCFG_WI; + break; + case SND_SOC_DAIFMT_IB_IF: + break; + default: + goto out; + } + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: /* CODEC master */ + ct |= PSC_I2SCFG_MS; /* PSC I2S slave mode */ + break; + case SND_SOC_DAIFMT_CBS_CFS: /* CODEC slave */ + ct &= ~PSC_I2SCFG_MS; /* PSC I2S Master mode */ + break; + default: + goto out; + } + + pscdata->cfg = ct; + ret = 0; +out: + return ret; +} + +static int au1xpsc_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct au1xpsc_audio_data *pscdata = au1xpsc_i2s_workdata; + + int cfgbits; + unsigned long stat; + + /* check if the PSC is already streaming data */ + stat = au_readl(I2S_STAT(pscdata)); + if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) { + /* reject parameters not currently set up in hardware */ + cfgbits = au_readl(I2S_CFG(pscdata)); + if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) || + (params_rate(params) != pscdata->rate)) + return -EINVAL; + } else { + /* set sample bitdepth */ + pscdata->cfg &= ~(0x1f << 4); + pscdata->cfg |= PSC_I2SCFG_SET_LEN(params->msbits); + /* remember current rate for other stream */ + pscdata->rate = params_rate(params); + } + return 0; +} + +/* Configure PSC late: on my devel systems the codec is I2S master and + * supplies the i2sbitclock __AND__ i2sMclk (!) to the PSC unit. ASoC + * uses aggressive PM and switches the codec off when it is not in use + * which also means the PSC unit doesn't get any clocks and is therefore + * dead. That's why this chunk here gets called from the trigger callback + * because I can be reasonably certain the codec is driving the clocks. + */ +static int au1xpsc_i2s_configure(struct au1xpsc_audio_data *pscdata) +{ + unsigned long tmo; + + /* bring PSC out of sleep, and configure I2S unit */ + au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); + au_sync(); + + tmo = 1000000; + while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo) + tmo--; + + if (!tmo) + goto psc_err; + + au_writel(0, I2S_CFG(pscdata)); + au_sync(); + au_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata)); + au_sync(); + + /* wait for I2S controller to become ready */ + tmo = 1000000; + while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo) + tmo--; + + if (tmo) + return 0; + +psc_err: + au_writel(0, I2S_CFG(pscdata)); + au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); + au_sync(); + return -ETIMEDOUT; +} + +static int au1xpsc_i2s_start(struct au1xpsc_audio_data *pscdata, int stype) +{ + unsigned long tmo, stat; + int ret; + + ret = 0; + + /* if both TX and RX are idle, configure the PSC */ + stat = au_readl(I2S_STAT(pscdata)); + if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) { + ret = au1xpsc_i2s_configure(pscdata); + if (ret) + goto out; + } + + au_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata)); + au_sync(); + au_writel(I2SPCR_START(stype), I2S_PCR(pscdata)); + au_sync(); + + /* wait for start confirmation */ + tmo = 1000000; + while (!(au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) + tmo--; + + if (!tmo) { + au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); + au_sync(); + ret = -ETIMEDOUT; + } +out: + return ret; +} + +static int au1xpsc_i2s_stop(struct au1xpsc_audio_data *pscdata, int stype) +{ + unsigned long tmo, stat; + + au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); + au_sync(); + + /* wait for stop confirmation */ + tmo = 1000000; + while ((au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) + tmo--; + + /* if both TX and RX are idle, disable PSC */ + stat = au_readl(I2S_STAT(pscdata)); + if (!(stat & (PSC_I2SSTAT_RB | PSC_I2SSTAT_RB))) { + au_writel(0, I2S_CFG(pscdata)); + au_sync(); + au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); + au_sync(); + } + return 0; +} + +static int au1xpsc_i2s_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct au1xpsc_audio_data *pscdata = au1xpsc_i2s_workdata; + int ret, stype = SUBSTREAM_TYPE(substream); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + ret = au1xpsc_i2s_start(pscdata, stype); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + ret = au1xpsc_i2s_stop(pscdata, stype); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int au1xpsc_i2s_probe(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + struct resource *r; + unsigned long sel; + int ret; + + if (au1xpsc_i2s_workdata) + return -EBUSY; + + au1xpsc_i2s_workdata = + kzalloc(sizeof(struct au1xpsc_audio_data), GFP_KERNEL); + if (!au1xpsc_i2s_workdata) + return -ENOMEM; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENODEV; + goto out0; + } + + ret = -EBUSY; + au1xpsc_i2s_workdata->ioarea = + request_mem_region(r->start, r->end - r->start + 1, + "au1xpsc_i2s"); + if (!au1xpsc_i2s_workdata->ioarea) + goto out0; + + au1xpsc_i2s_workdata->mmio = ioremap(r->start, 0xffff); + if (!au1xpsc_i2s_workdata->mmio) + goto out1; + + /* preserve PSC clock source set up by platform (dev.platform_data + * is already occupied by soc layer) + */ + sel = au_readl(PSC_SEL(au1xpsc_i2s_workdata)) & PSC_SEL_CLK_MASK; + au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_i2s_workdata)); + au_sync(); + au_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(au1xpsc_i2s_workdata)); + au_writel(0, I2S_CFG(au1xpsc_i2s_workdata)); + au_sync(); + + /* preconfigure: set max rx/tx fifo depths */ + au1xpsc_i2s_workdata->cfg |= + PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8; + + /* don't wait for I2S core to become ready now; clocks may not + * be running yet; depending on clock input for PSC a wait might + * time out. + */ + + return 0; + +out1: + release_resource(au1xpsc_i2s_workdata->ioarea); + kfree(au1xpsc_i2s_workdata->ioarea); +out0: + kfree(au1xpsc_i2s_workdata); + au1xpsc_i2s_workdata = NULL; + return ret; +} + +static void au1xpsc_i2s_remove(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + au_writel(0, I2S_CFG(au1xpsc_i2s_workdata)); + au_sync(); + au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_i2s_workdata)); + au_sync(); + + iounmap(au1xpsc_i2s_workdata->mmio); + release_resource(au1xpsc_i2s_workdata->ioarea); + kfree(au1xpsc_i2s_workdata->ioarea); + kfree(au1xpsc_i2s_workdata); + au1xpsc_i2s_workdata = NULL; +} + +static int au1xpsc_i2s_suspend(struct platform_device *pdev, + struct snd_soc_dai *cpu_dai) +{ + /* save interesting register and disable PSC */ + au1xpsc_i2s_workdata->pm[0] = + au_readl(PSC_SEL(au1xpsc_i2s_workdata)); + + au_writel(0, I2S_CFG(au1xpsc_i2s_workdata)); + au_sync(); + au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_i2s_workdata)); + au_sync(); + + return 0; +} + +static int au1xpsc_i2s_resume(struct platform_device *pdev, + struct snd_soc_dai *cpu_dai) +{ + /* select I2S mode and PSC clock */ + au_writel(PSC_CTRL_DISABLE, PSC_CTRL(au1xpsc_i2s_workdata)); + au_sync(); + au_writel(0, PSC_SEL(au1xpsc_i2s_workdata)); + au_sync(); + au_writel(au1xpsc_i2s_workdata->pm[0], + PSC_SEL(au1xpsc_i2s_workdata)); + au_sync(); + + return 0; +} + +struct snd_soc_dai au1xpsc_i2s_dai = { + .name = "au1xpsc_i2s", + .type = SND_SOC_DAI_I2S, + .probe = au1xpsc_i2s_probe, + .remove = au1xpsc_i2s_remove, + .suspend = au1xpsc_i2s_suspend, + .resume = au1xpsc_i2s_resume, + .playback = { + .rates = AU1XPSC_I2S_RATES, + .formats = AU1XPSC_I2S_FMTS, + .channels_min = 2, + .channels_max = 8, /* 2 without external help */ + }, + .capture = { + .rates = AU1XPSC_I2S_RATES, + .formats = AU1XPSC_I2S_FMTS, + .channels_min = 2, + .channels_max = 8, /* 2 without external help */ + }, + .ops = { + .trigger = au1xpsc_i2s_trigger, + .hw_params = au1xpsc_i2s_hw_params, + }, + .dai_ops = { + .set_fmt = au1xpsc_i2s_set_fmt, + }, +}; +EXPORT_SYMBOL(au1xpsc_i2s_dai); + +static int __init au1xpsc_i2s_init(void) +{ + au1xpsc_i2s_workdata = NULL; + return 0; +} + +static void __exit au1xpsc_i2s_exit(void) +{ +} + +module_init(au1xpsc_i2s_init); +module_exit(au1xpsc_i2s_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Au12x0/Au1550 PSC I2S ALSA ASoC audio driver"); +MODULE_AUTHOR("Manuel Lauss "); diff --git a/sound/soc/au1x/psc.h b/sound/soc/au1x/psc.h new file mode 100644 index 000000000000..8fdb1a04a07b --- /dev/null +++ b/sound/soc/au1x/psc.h @@ -0,0 +1,53 @@ +/* + * Au12x0/Au1550 PSC ALSA ASoC audio support. + * + * (c) 2007-2008 MSC Vertriebsges.m.b.H., + * Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * NOTE: all of these drivers can only work with a SINGLE instance + * of a PSC. Multiple independent audio devices are impossible + * with ASoC v1. + */ + +#ifndef _AU1X_PCM_H +#define _AU1X_PCM_H + +extern struct snd_soc_dai au1xpsc_ac97_dai; +extern struct snd_soc_dai au1xpsc_i2s_dai; +extern struct snd_soc_platform au1xpsc_soc_platform; +extern struct snd_ac97_bus_ops soc_ac97_ops; + +struct au1xpsc_audio_data { + void __iomem *mmio; + + unsigned long cfg; + unsigned long rate; + + unsigned long pm[2]; + struct resource *ioarea; +}; + +#define PCM_TX 0 +#define PCM_RX 1 + +#define SUBSTREAM_TYPE(substream) \ + ((substream)->stream == SNDRV_PCM_STREAM_PLAYBACK ? PCM_TX : PCM_RX) + +/* easy access macros */ +#define PSC_CTRL(x) ((unsigned long)((x)->mmio) + PSC_CTRL_OFFSET) +#define PSC_SEL(x) ((unsigned long)((x)->mmio) + PSC_SEL_OFFSET) +#define I2S_STAT(x) ((unsigned long)((x)->mmio) + PSC_I2SSTAT_OFFSET) +#define I2S_CFG(x) ((unsigned long)((x)->mmio) + PSC_I2SCFG_OFFSET) +#define I2S_PCR(x) ((unsigned long)((x)->mmio) + PSC_I2SPCR_OFFSET) +#define AC97_CFG(x) ((unsigned long)((x)->mmio) + PSC_AC97CFG_OFFSET) +#define AC97_CDC(x) ((unsigned long)((x)->mmio) + PSC_AC97CDC_OFFSET) +#define AC97_EVNT(x) ((unsigned long)((x)->mmio) + PSC_AC97EVNT_OFFSET) +#define AC97_PCR(x) ((unsigned long)((x)->mmio) + PSC_AC97PCR_OFFSET) +#define AC97_RST(x) ((unsigned long)((x)->mmio) + PSC_AC97RST_OFFSET) +#define AC97_STAT(x) ((unsigned long)((x)->mmio) + PSC_AC97STAT_OFFSET) + +#endif diff --git a/sound/soc/au1x/sample-ac97.c b/sound/soc/au1x/sample-ac97.c new file mode 100644 index 000000000000..f75ae7f62c3d --- /dev/null +++ b/sound/soc/au1x/sample-ac97.c @@ -0,0 +1,144 @@ +/* + * Sample Au12x0/Au1550 PSC AC97 sound machine. + * + * Copyright (c) 2007-2008 Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms outlined in the file COPYING at the root of this + * source archive. + * + * This is a very generic AC97 sound machine driver for boards which + * have (AC97) audio at PSC1 (e.g. DB1200 demoboards). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../codecs/ac97.h" +#include "psc.h" + +static int au1xpsc_sample_ac97_init(struct snd_soc_codec *codec) +{ + snd_soc_dapm_sync(codec); + return 0; +} + +static struct snd_soc_dai_link au1xpsc_sample_ac97_dai = { + .name = "AC97", + .stream_name = "AC97 HiFi", + .cpu_dai = &au1xpsc_ac97_dai, /* see psc-ac97.c */ + .codec_dai = &ac97_dai, /* see codecs/ac97.c */ + .init = au1xpsc_sample_ac97_init, + .ops = NULL, +}; + +static struct snd_soc_machine au1xpsc_sample_ac97_machine = { + .name = "Au1xxx PSC AC97 Audio", + .dai_link = &au1xpsc_sample_ac97_dai, + .num_links = 1, +}; + +static struct snd_soc_device au1xpsc_sample_ac97_devdata = { + .machine = &au1xpsc_sample_ac97_machine, + .platform = &au1xpsc_soc_platform, /* see dbdma2.c */ + .codec_dev = &soc_codec_dev_ac97, +}; + +static struct resource au1xpsc_psc1_res[] = { + [0] = { + .start = CPHYSADDR(PSC1_BASE_ADDR), + .end = CPHYSADDR(PSC1_BASE_ADDR) + 0x000fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { +#ifdef CONFIG_SOC_AU1200 + .start = AU1200_PSC1_INT, + .end = AU1200_PSC1_INT, +#elif defined(CONFIG_SOC_AU1550) + .start = AU1550_PSC1_INT, + .end = AU1550_PSC1_INT, +#endif + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC1_TX, + .end = DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC1_RX, + .end = DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device *au1xpsc_sample_ac97_dev; + +static int __init au1xpsc_sample_ac97_load(void) +{ + int ret; + +#ifdef CONFIG_SOC_AU1200 + unsigned long io; + + /* modify sys_pinfunc for AC97 on PSC1 */ + io = au_readl(SYS_PINFUNC); + io |= SYS_PINFUNC_P1C; + io &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B); + au_writel(io, SYS_PINFUNC); + au_sync(); +#endif + + ret = -ENOMEM; + + /* setup PSC clock source for AC97 part: external clock provided + * by codec. The psc-ac97.c driver depends on this setting! + */ + au_writel(PSC_SEL_CLK_SERCLK, PSC1_BASE_ADDR + PSC_SEL_OFFSET); + au_sync(); + + au1xpsc_sample_ac97_dev = platform_device_alloc("soc-audio", -1); + if (!au1xpsc_sample_ac97_dev) + goto out; + + au1xpsc_sample_ac97_dev->resource = + kmemdup(au1xpsc_psc1_res, sizeof(struct resource) * + ARRAY_SIZE(au1xpsc_psc1_res), GFP_KERNEL); + au1xpsc_sample_ac97_dev->num_resources = ARRAY_SIZE(au1xpsc_psc1_res); + au1xpsc_sample_ac97_dev->id = 1; + + platform_set_drvdata(au1xpsc_sample_ac97_dev, + &au1xpsc_sample_ac97_devdata); + au1xpsc_sample_ac97_devdata.dev = &au1xpsc_sample_ac97_dev->dev; + ret = platform_device_add(au1xpsc_sample_ac97_dev); + + if (ret) { + platform_device_put(au1xpsc_sample_ac97_dev); + au1xpsc_sample_ac97_dev = NULL; + } + +out: + return ret; +} + +static void __exit au1xpsc_sample_ac97_exit(void) +{ + platform_device_unregister(au1xpsc_sample_ac97_dev); +} + +module_init(au1xpsc_sample_ac97_load); +module_exit(au1xpsc_sample_ac97_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Au1xxx PSC sample AC97 machine"); +MODULE_AUTHOR("Manuel Lauss "); -- cgit v1.2.3 From c4223c2c91fa9e5addd6eadd804e57a925ac5e5e Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 9 Jun 2008 08:36:13 +0200 Subject: au1xmmc: remove db1200 board code, rewrite probe. Remove the DB1200 board-specific functions (card present, read-only, activity LED methods) and instead add platform data which is passed to the driver. This also allows for platforms to implement other carddetect schemes (e.g. dedicated irq) without having to pollute the driver code. The poll timer (used for pb1200) is kept for compatibility. With the board-specific stuff gone, the driver's ->probe() code can be cleaned up considerably. Signed-off-by: Manuel Lauss Signed-off-by: Pierre Ossman --- drivers/mmc/host/au1xmmc.c | 573 ++++++++++++++++++------------ drivers/mmc/host/au1xmmc.h | 9 +- include/asm-mips/mach-au1x00/au1100_mmc.h | 18 +- 3 files changed, 354 insertions(+), 246 deletions(-) (limited to 'include/asm-mips') diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index cc5f7bc546af..d8776d61b3cc 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -41,8 +41,9 @@ #include #include #include - +#include #include + #include #include #include @@ -54,6 +55,7 @@ #define DRIVER_NAME "au1xxx-mmc" /* Set this to enable special debugging macros */ +/* #define DEBUG */ #ifdef DEBUG #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args) @@ -61,32 +63,6 @@ #define DBG(fmt, idx, args...) #endif -const struct { - u32 iobase; - u32 tx_devid, rx_devid; - u16 bcsrpwr; - u16 bcsrstatus; - u16 wpstatus; -} au1xmmc_card_table[] = { - { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0, - BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP }, -#ifndef CONFIG_MIPS_DB1200 - { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1, - BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP } -#endif -}; - -#define AU1XMMC_CONTROLLER_COUNT (ARRAY_SIZE(au1xmmc_card_table)) - -/* This array stores pointers for the hosts (used by the IRQ handler) */ -struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT]; -static int dma = 1; - -#ifdef MODULE -module_param(dma, bool, 0); -MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)"); -#endif - static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) { u32 val = au_readl(HOST_CONFIG(host)); @@ -135,26 +111,33 @@ static inline void SEND_STOP(struct au1xmmc_host *host) static void au1xmmc_set_power(struct au1xmmc_host *host, int state) { - - u32 val = au1xmmc_card_table[host->id].bcsrpwr; - - bcsr->board &= ~val; - if (state) bcsr->board |= val; - - au_sync_delay(1); + if (host->platdata && host->platdata->set_power) + host->platdata->set_power(host->mmc, state); } -static inline int au1xmmc_card_inserted(struct au1xmmc_host *host) +static int au1xmmc_card_inserted(struct au1xmmc_host *host) { - return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus) - ? 1 : 0; + int ret; + + if (host->platdata && host->platdata->card_inserted) + ret = host->platdata->card_inserted(host->mmc); + else + ret = 1; /* assume there is a card */ + + return ret; } static int au1xmmc_card_readonly(struct mmc_host *mmc) { struct au1xmmc_host *host = mmc_priv(mmc); - return (bcsr->status & au1xmmc_card_table[host->id].wpstatus) - ? 1 : 0; + int ret; + + if (host->platdata && host->platdata->card_readonly) + ret = host->platdata->card_readonly(mmc); + else + ret = 0; /* assume card is read-write */ + + return ret; } static void au1xmmc_finish_request(struct au1xmmc_host *host) @@ -163,7 +146,7 @@ static void au1xmmc_finish_request(struct au1xmmc_host *host) struct mmc_request *mrq = host->mrq; host->mrq = NULL; - host->flags &= HOST_F_ACTIVE; + host->flags &= HOST_F_ACTIVE | HOST_F_DMA; host->dma.len = 0; host->dma.dir = 0; @@ -174,8 +157,6 @@ static void au1xmmc_finish_request(struct au1xmmc_host *host) host->status = HOST_S_IDLE; - bcsr->disk_leds |= (1 << 8); - mmc_request_done(host->mmc, mrq); } @@ -299,11 +280,13 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) if (!data->error) { if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ u32 chan = DMA_CHANNEL(host); chan_tab_t *c = *((chan_tab_t **) chan); au1x_dma_chan_t *cp = c->chan_ptr; data->bytes_xfered = cp->ddma_bytecnt; +#endif } else data->bytes_xfered = @@ -420,18 +403,18 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) break; if (status & SD_STATUS_RC) { - DBG("RX CRC Error [%d + %d].\n", host->id, + DBG("RX CRC Error [%d + %d].\n", host->pdev->id, host->pio.len, count); break; } if (status & SD_STATUS_RO) { - DBG("RX Overrun [%d + %d]\n", host->id, + DBG("RX Overrun [%d + %d]\n", host->pdev->id, host->pio.len, count); break; } else if (status & SD_STATUS_RU) { - DBG("RX Underrun [%d + %d]\n", host->id, + DBG("RX Underrun [%d + %d]\n", host->pdev->id, host->pio.len, count); break; } @@ -528,6 +511,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) host->status = HOST_S_DATA; if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ u32 channel = DMA_CHANNEL(host); /* Start the DMA as soon as the buffer gets something in it */ @@ -540,6 +524,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) } au1xxx_dbdma_start(channel); +#endif } } @@ -571,12 +556,8 @@ static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) static int au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) { - int datalen = data->blocks * data->blksz; - if (dma != 0) - host->flags |= HOST_F_DMA; - if (data->flags & MMC_DATA_READ) host->flags |= HOST_F_RECV; else @@ -596,6 +577,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) au_writel(data->blksz - 1, HOST_BLKSIZE(host)); if (host->flags & HOST_F_DMA) { +#ifdef CONFIG_SOC_AU1200 /* DBDMA */ int i; u32 channel = DMA_CHANNEL(host); @@ -621,11 +603,12 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) len, flags); } - if (!ret) + if (!ret) goto dataerr; datalen -= len; } +#endif } else { host->pio.index = 0; @@ -641,8 +624,9 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) return 0; - dataerr: - dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir); +dataerr: + dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, + host->dma.dir); return -ETIMEDOUT; } @@ -663,8 +647,6 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) host->mrq = mrq; host->status = HOST_S_CMD; - bcsr->disk_leds &= ~(1 << 8); - if (mrq->data) { FLUSH_FIFO(host); flags = mrq->data->flags; @@ -728,149 +710,145 @@ static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) } } -static void au1xmmc_dma_callback(int irq, void *dev_id) -{ - struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id; - - /* Avoid spurious interrupts */ - - if (!host->mrq) - return; - - if (host->flags & HOST_F_STOP) - SEND_STOP(host); - - tasklet_schedule(&host->data_task); -} - #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) #define STATUS_DATA_IN (SD_STATUS_NE) #define STATUS_DATA_OUT (SD_STATUS_TH) static irqreturn_t au1xmmc_irq(int irq, void *dev_id) { - + struct au1xmmc_host *host = dev_id; u32 status; - int i, ret = 0; - - disable_irq(AU1100_SD_IRQ); - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct au1xmmc_host * host = au1xmmc_hosts[i]; - u32 handled = 1; - - status = au_readl(HOST_STATUS(host)); + status = au_readl(HOST_STATUS(host)); - if (host->mrq && (status & STATUS_TIMEOUT)) { - if (status & SD_STATUS_RAT) - host->mrq->cmd->error = -ETIMEDOUT; + if (!(status & SD_STATUS_I)) + return IRQ_NONE; /* not ours */ - else if (status & SD_STATUS_DT) - host->mrq->data->error = -ETIMEDOUT; + if (host->mrq && (status & STATUS_TIMEOUT)) { + if (status & SD_STATUS_RAT) + host->mrq->cmd->error = -ETIMEDOUT; + else if (status & SD_STATUS_DT) + host->mrq->data->error = -ETIMEDOUT; - /* In PIO mode, interrupts might still be enabled */ - IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); + /* In PIO mode, interrupts might still be enabled */ + IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); - //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF); - tasklet_schedule(&host->finish_task); - } + /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ + tasklet_schedule(&host->finish_task); + } #if 0 - else if (status & SD_STATUS_DD) { - - /* Sometimes we get a DD before a NE in PIO mode */ - - if (!(host->flags & HOST_F_DMA) && - (status & SD_STATUS_NE)) - au1xmmc_receive_pio(host); - else { - au1xmmc_data_complete(host, status); - //tasklet_schedule(&host->data_task); - } - } -#endif - else if (status & (SD_STATUS_CR)) { - if (host->status == HOST_S_CMD) - au1xmmc_cmd_complete(host,status); - } - else if (!(host->flags & HOST_F_DMA)) { - if ((host->flags & HOST_F_XMIT) && - (status & STATUS_DATA_OUT)) - au1xmmc_send_pio(host); - else if ((host->flags & HOST_F_RECV) && - (status & STATUS_DATA_IN)) - au1xmmc_receive_pio(host); - } - else if (status & 0x203FBC70) { - DBG("Unhandled status %8.8x\n", host->id, status); - handled = 0; + else if (status & SD_STATUS_DD) { + /* Sometimes we get a DD before a NE in PIO mode */ + if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) + au1xmmc_receive_pio(host); + else { + au1xmmc_data_complete(host, status); + /* tasklet_schedule(&host->data_task); */ } - - au_writel(status, HOST_STATUS(host)); - au_sync(); - - ret |= handled; } - - enable_irq(AU1100_SD_IRQ); - return ret; -} - -static void au1xmmc_poll_event(unsigned long arg) -{ - struct au1xmmc_host *host = (struct au1xmmc_host *) arg; - - int card = au1xmmc_card_inserted(host); - int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0; - - if (card != controller) { - host->flags &= ~HOST_F_ACTIVE; - if (card) host->flags |= HOST_F_ACTIVE; - mmc_detect_change(host->mmc, 0); +#endif + else if (status & SD_STATUS_CR) { + if (host->status == HOST_S_CMD) + au1xmmc_cmd_complete(host, status); + + } else if (!(host->flags & HOST_F_DMA)) { + if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) + au1xmmc_send_pio(host); + else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) + au1xmmc_receive_pio(host); + + } else if (status & 0x203F3C70) { + DBG("Unhandled status %8.8x\n", host->pdev->id, + status); } - if (host->mrq != NULL) { - u32 status = au_readl(HOST_STATUS(host)); - DBG("PENDING - %8.8x\n", host->id, status); - } + au_writel(status, HOST_STATUS(host)); + au_sync(); - mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT); + return IRQ_HANDLED; } -static dbdev_tab_t au1xmmc_mem_dbdev = -{ - DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0 +#ifdef CONFIG_SOC_AU1200 +/* 8bit memory DMA device */ +static dbdev_tab_t au1xmmc_mem_dbdev = { + .dev_id = DSCR_CMD0_ALWAYS, + .dev_flags = DEV_FLAGS_ANYUSE, + .dev_tsize = 0, + .dev_devwidth = 8, + .dev_physaddr = 0x00000000, + .dev_intlevel = 0, + .dev_intpolarity = 0, }; +static int memid; -static void au1xmmc_init_dma(struct au1xmmc_host *host) +static void au1xmmc_dbdma_callback(int irq, void *dev_id) { + struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; - u32 rxchan, txchan; + /* Avoid spurious interrupts */ + if (!host->mrq) + return; - int txid = au1xmmc_card_table[host->id].tx_devid; - int rxid = au1xmmc_card_table[host->id].rx_devid; + if (host->flags & HOST_F_STOP) + SEND_STOP(host); - /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride - of 8 bits. And since devices are shared, we need to create - our own to avoid freaking out other devices - */ + tasklet_schedule(&host->data_task); +} - int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); +static int au1xmmc_dbdma_init(struct au1xmmc_host *host) +{ + struct resource *res; + int txid, rxid; + + res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); + if (!res) + return -ENODEV; + txid = res->start; + + res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); + if (!res) + return -ENODEV; + rxid = res->start; + + if (!memid) + return -ENODEV; + + host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, + au1xmmc_dbdma_callback, (void *)host); + if (!host->tx_chan) { + dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); + return -ENODEV; + } + + host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, + au1xmmc_dbdma_callback, (void *)host); + if (!host->rx_chan) { + dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); + au1xxx_dbdma_chan_free(host->tx_chan); + return -ENODEV; + } - txchan = au1xxx_dbdma_chan_alloc(memid, txid, - au1xmmc_dma_callback, (void *) host); + au1xxx_dbdma_set_devwidth(host->tx_chan, 8); + au1xxx_dbdma_set_devwidth(host->rx_chan, 8); - rxchan = au1xxx_dbdma_chan_alloc(rxid, memid, - au1xmmc_dma_callback, (void *) host); + au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); + au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); - au1xxx_dbdma_set_devwidth(txchan, 8); - au1xxx_dbdma_set_devwidth(rxchan, 8); + /* DBDMA is good to go */ + host->flags |= HOST_F_DMA; - au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT); - au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT); + return 0; +} - host->tx_chan = txchan; - host->rx_chan = rxchan; +static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) +{ + if (host->flags & HOST_F_DMA) { + host->flags &= ~HOST_F_DMA; + au1xxx_dbdma_chan_free(host->tx_chan); + au1xxx_dbdma_chan_free(host->rx_chan); + } } +#endif static const struct mmc_host_ops au1xmmc_ops = { .request = au1xmmc_request, @@ -878,116 +856,235 @@ static const struct mmc_host_ops au1xmmc_ops = { .get_ro = au1xmmc_card_readonly, }; -static int __devinit au1xmmc_probe(struct platform_device *pdev) +static void au1xmmc_poll_event(unsigned long arg) { + struct au1xmmc_host *host = (struct au1xmmc_host *)arg; + int card = au1xmmc_card_inserted(host); + int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0; + + if (card != controller) { + host->flags &= ~HOST_F_ACTIVE; + if (card) + host->flags |= HOST_F_ACTIVE; + mmc_detect_change(host->mmc, 0); + } - int i, ret = 0; +#ifdef DEBUG + if (host->mrq != NULL) { + u32 status = au_readl(HOST_STATUS(host)); + DBG("PENDING - %8.8x\n", host->pdev->id, status); + } +#endif + mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT); +} - /* THe interrupt is shared among all controllers */ - ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0); +static void au1xmmc_init_cd_poll_timer(struct au1xmmc_host *host) +{ + init_timer(&host->timer); + host->timer.function = au1xmmc_poll_event; + host->timer.data = (unsigned long)host; + host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT; +} - if (ret) { - printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n", - AU1100_SD_IRQ, ret); - return -ENXIO; +static int __devinit au1xmmc_probe(struct platform_device *pdev) +{ + struct mmc_host *mmc; + struct au1xmmc_host *host; + struct resource *r; + int ret; + + mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); + if (!mmc) { + dev_err(&pdev->dev, "no memory for mmc_host\n"); + ret = -ENOMEM; + goto out0; } - disable_irq(AU1100_SD_IRQ); + host = mmc_priv(mmc); + host->mmc = mmc; + host->platdata = pdev->dev.platform_data; + host->pdev = pdev; - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); - struct au1xmmc_host *host = 0; + ret = -ENODEV; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no mmio defined\n"); + goto out1; + } - if (!mmc) { - printk(DRIVER_NAME "ERROR: no mem for host %d\n", i); - au1xmmc_hosts[i] = 0; - continue; - } + host->ioarea = request_mem_region(r->start, r->end - r->start + 1, + pdev->name); + if (!host->ioarea) { + dev_err(&pdev->dev, "mmio already in use\n"); + goto out1; + } - mmc->ops = &au1xmmc_ops; + host->iobase = (unsigned long)ioremap(r->start, 0x3c); + if (!host->iobase) { + dev_err(&pdev->dev, "cannot remap mmio\n"); + goto out2; + } + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!r) { + dev_err(&pdev->dev, "no IRQ defined\n"); + goto out3; + } - mmc->f_min = 450000; - mmc->f_max = 24000000; + host->irq = r->start; + /* IRQ is shared among both SD controllers */ + ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED, + DRIVER_NAME, host); + if (ret) { + dev_err(&pdev->dev, "cannot grab IRQ\n"); + goto out3; + } - mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; - mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; + mmc->ops = &au1xmmc_ops; - mmc->max_blk_size = 2048; - mmc->max_blk_count = 512; + mmc->f_min = 450000; + mmc->f_max = 24000000; - mmc->ocr_avail = AU1XMMC_OCR; + mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; + mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; - host = mmc_priv(mmc); - host->mmc = mmc; + mmc->max_blk_size = 2048; + mmc->max_blk_count = 512; - host->id = i; - host->iobase = au1xmmc_card_table[host->id].iobase; - host->clock = 0; - host->power_mode = MMC_POWER_OFF; + mmc->ocr_avail = AU1XMMC_OCR; + mmc->caps = 0; - host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0; - host->status = HOST_S_IDLE; + host->status = HOST_S_IDLE; - init_timer(&host->timer); + /* board-specific carddetect setup, if any */ + if (host->platdata && host->platdata->cd_setup) { + ret = host->platdata->cd_setup(mmc, 1); + if (ret) { + dev_err(&pdev->dev, "board CD setup failed\n"); + goto out4; + } + } else { + /* poll the board-specific is-card-in-socket-? method */ + au1xmmc_init_cd_poll_timer(host); + } - host->timer.function = au1xmmc_poll_event; - host->timer.data = (unsigned long) host; - host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT; + tasklet_init(&host->data_task, au1xmmc_tasklet_data, + (unsigned long)host); - tasklet_init(&host->data_task, au1xmmc_tasklet_data, - (unsigned long) host); + tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, + (unsigned long)host); - tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, - (unsigned long) host); +#ifdef CONFIG_SOC_AU1200 + ret = au1xmmc_dbdma_init(host); + if (ret) + printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n"); +#endif - spin_lock_init(&host->lock); +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) { + struct led_classdev *led = host->platdata->led; + led->name = mmc_hostname(mmc); + led->brightness = LED_OFF; + led->default_trigger = mmc_hostname(mmc); + ret = led_classdev_register(mmc_dev(mmc), led); + if (ret) + goto out5; + } +#endif - if (dma != 0) - au1xmmc_init_dma(host); + au1xmmc_reset_controller(host); - au1xmmc_reset_controller(host); + ret = mmc_add_host(mmc); + if (ret) { + dev_err(&pdev->dev, "cannot add mmc host\n"); + goto out6; + } - mmc_add_host(mmc); - au1xmmc_hosts[i] = host; + platform_set_drvdata(pdev, mmc); + /* start the carddetect poll timer if necessary */ + if (!(host->platdata && host->platdata->cd_setup)) add_timer(&host->timer); - printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n", - host->id, host->iobase, dma ? "dma" : "pio"); - } + printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X" + " (mode=%s)\n", pdev->id, host->iobase, + host->flags & HOST_F_DMA ? "dma" : "pio"); - enable_irq(AU1100_SD_IRQ); + return 0; /* all ok */ - return 0; +out6: +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) + led_classdev_unregister(host->platdata->led); +out5: +#endif + au_writel(0, HOST_ENABLE(host)); + au_writel(0, HOST_CONFIG(host)); + au_writel(0, HOST_CONFIG2(host)); + au_sync(); + +#ifdef CONFIG_SOC_AU1200 + au1xmmc_dbdma_shutdown(host); +#endif + + tasklet_kill(&host->data_task); + tasklet_kill(&host->finish_task); + + if (host->platdata && host->platdata->cd_setup) + host->platdata->cd_setup(mmc, 0); +out4: + free_irq(host->irq, host); +out3: + iounmap((void *)host->iobase); +out2: + release_resource(host->ioarea); + kfree(host->ioarea); +out1: + mmc_free_host(mmc); +out0: + return ret; } static int __devexit au1xmmc_remove(struct platform_device *pdev) { + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct au1xmmc_host *host; + + if (mmc) { + host = mmc_priv(mmc); + + mmc_remove_host(mmc); - int i; +#ifdef CONFIG_LEDS_CLASS + if (host->platdata && host->platdata->led) + led_classdev_unregister(host->platdata->led); +#endif - disable_irq(AU1100_SD_IRQ); + if (host->platdata && host->platdata->cd_setup) + host->platdata->cd_setup(mmc, 0); + else + del_timer_sync(&host->timer); - for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { - struct au1xmmc_host *host = au1xmmc_hosts[i]; - if (!host) continue; + au_writel(0, HOST_ENABLE(host)); + au_writel(0, HOST_CONFIG(host)); + au_writel(0, HOST_CONFIG2(host)); + au_sync(); tasklet_kill(&host->data_task); tasklet_kill(&host->finish_task); - del_timer_sync(&host->timer); +#ifdef CONFIG_SOC_AU1200 + au1xmmc_dbdma_shutdown(host); +#endif au1xmmc_set_power(host, 0); - mmc_remove_host(host->mmc); + free_irq(host->irq, host); + iounmap((void *)host->iobase); + release_resource(host->ioarea); + kfree(host->ioarea); - au1xxx_dbdma_chan_free(host->tx_chan); - au1xxx_dbdma_chan_free(host->rx_chan); - - au_writel(0x0, HOST_ENABLE(host)); - au_sync(); + mmc_free_host(mmc); } - - free_irq(AU1100_SD_IRQ, 0); return 0; } @@ -1004,21 +1101,31 @@ static struct platform_driver au1xmmc_driver = { static int __init au1xmmc_init(void) { +#ifdef CONFIG_SOC_AU1200 + /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride + * of 8 bits. And since devices are shared, we need to create + * our own to avoid freaking out other devices. + */ + memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); + if (!memid) + printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n"); +#endif return platform_driver_register(&au1xmmc_driver); } static void __exit au1xmmc_exit(void) { +#ifdef CONFIG_SOC_AU1200 + if (memid) + au1xxx_ddma_del_device(memid); +#endif platform_driver_unregister(&au1xmmc_driver); } module_init(au1xmmc_init); module_exit(au1xmmc_exit); -#ifdef MODULE MODULE_AUTHOR("Advanced Micro Devices, Inc"); MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:au1xxx-mmc"); -#endif - diff --git a/drivers/mmc/host/au1xmmc.h b/drivers/mmc/host/au1xmmc.h index 341cbdf0baca..3b400654e59c 100644 --- a/drivers/mmc/host/au1xmmc.h +++ b/drivers/mmc/host/au1xmmc.h @@ -49,8 +49,6 @@ struct au1xmmc_host { struct mmc_host *mmc; struct mmc_request *mrq; - u32 id; - u32 flags; u32 iobase; u32 clock; @@ -73,11 +71,14 @@ struct au1xmmc_host { u32 tx_chan; u32 rx_chan; + int irq; + struct timer_list timer; struct tasklet_struct finish_task; struct tasklet_struct data_task; - - spinlock_t lock; + struct au1xmmc_platform_data *platdata; + struct platform_device *pdev; + struct resource *ioarea; }; /* Status flags used by the host structure */ diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h index 9e0028f60a43..c35e20918490 100644 --- a/include/asm-mips/mach-au1x00/au1100_mmc.h +++ b/include/asm-mips/mach-au1x00/au1100_mmc.h @@ -38,15 +38,15 @@ #ifndef __ASM_AU1100_MMC_H #define __ASM_AU1100_MMC_H - -#define NUM_AU1100_MMC_CONTROLLERS 2 - -#if defined(CONFIG_SOC_AU1100) -#define AU1100_SD_IRQ AU1100_SD_INT -#elif defined(CONFIG_SOC_AU1200) -#define AU1100_SD_IRQ AU1200_SD_INT -#endif - +#include + +struct au1xmmc_platform_data { + int(*cd_setup)(void *mmc_host, int on); + int(*card_inserted)(void *mmc_host); + int(*card_readonly)(void *mmc_host); + void(*set_power)(void *mmc_host, int state); + struct led_classdev *led; +}; #define SD0_BASE 0xB0600000 #define SD1_BASE 0xB0680000 -- cgit v1.2.3 From 2954c02a884dc0ba9e91882c0aba13bcb9d22e6c Mon Sep 17 00:00:00 2001 From: "Chen, Huacai" Date: Tue, 10 Jun 2008 09:05:08 +0800 Subject: [MIPS] modify the MIPS CPU classfication Signed-off-by: Huacai Chen Signed-off-by: Ralf Baechle --- include/asm-mips/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 1c35cac6f35b..229a786101d9 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -66,8 +66,10 @@ #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ #define PRID_IMP_RM9000 0x3400 +#define PRID_IMP_LOONGSON1 0x4200 #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 +#define PRID_IMP_LOONGSON2 0x6300 #define PRID_IMP_UNKNOWN 0xff00 @@ -90,8 +92,6 @@ #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 #define PRID_IMP_1004K 0x9900 -#define PRID_IMP_LOONGSON1 0x4200 -#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE -- cgit v1.2.3 From cb11dfa0247df479e384c4a7ab6846f3a6bf1570 Mon Sep 17 00:00:00 2001 From: David Daney Date: Mon, 9 Jun 2008 16:30:03 -0700 Subject: [MIPS] Remove board_watchpoint_handler It is not used anywhere in tree. Signed-off-by: David Daney Signed-off-by: Andrew Morton Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 6 ------ include/asm-mips/traps.h | 1 - 2 files changed, 7 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f9165d1a17bf..6e7e4a2775f6 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -71,7 +71,6 @@ extern asmlinkage void handle_reserved(void); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu); -void (*board_watchpoint_handler)(struct pt_regs *regs); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); void (*board_nmi_handler_setup)(void); @@ -892,11 +891,6 @@ asmlinkage void do_mdmx(struct pt_regs *regs) asmlinkage void do_watch(struct pt_regs *regs) { - if (board_watchpoint_handler) { - (*board_watchpoint_handler)(regs); - return; - } - /* * We use the watch exception where available to detect stack * overflows. diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h index e5dbde625ec2..90ff2f497c50 100644 --- a/include/asm-mips/traps.h +++ b/include/asm-mips/traps.h @@ -24,6 +24,5 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup); extern void (*board_nmi_handler_setup)(void); extern void (*board_ejtag_handler_setup)(void); extern void (*board_bind_eic_interrupt)(int irq, int regset); -extern void (*board_watchpoint_handler)(struct pt_regs *regs); #endif /* _ASM_TRAPS_H */ -- cgit v1.2.3 From c88a8b4ab0e1a1f06938939d9ba42e9da6144ccb Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 9 Jun 2008 17:19:53 +0100 Subject: [MIPS] Remove obsolete isa_slot_offset The isa_slot_offset variable and its __ISA_IO_base macro is not used anywhere anymore. It does not look like a decent interface per today's standards either. Remove both including all places of initialization. Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle --- arch/mips/jazz/setup.c | 1 - arch/mips/kernel/setup.c | 7 ------- arch/mips/pci/pci-bcm1480.c | 2 -- arch/mips/pci/pci-sb1250.c | 3 --- arch/mips/sni/setup.c | 1 - include/asm-mips/io.h | 17 ----------------- 6 files changed, 31 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index a7947199c99b..f136c8a8591c 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -79,7 +79,6 @@ void __init plat_mem_setup(void) if (mips_machtype == MACH_MIPS_MAGNUM_4000) EISA_bus = 1; #endif - isa_slot_offset = 0xe3000000; /* request I/O space for devices used on all i[345]86 PCs */ for (i = 0; i < ARRAY_SIZE(jazz_io_resources); i++) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index c6a063b2a0d9..c04e4e3afede 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -68,13 +68,6 @@ static char command_line[CL_SIZE]; const unsigned long mips_io_port_base __read_mostly = -1; EXPORT_SYMBOL(mips_io_port_base); -/* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. - */ -unsigned long isa_slot_offset; -EXPORT_SYMBOL(isa_slot_offset); - static struct resource code_resource = { .name = "Kernel code", }; static struct resource data_resource = { .name = "Kernel data", }; diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index 87e2c8f54e2d..d19d262157f2 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -254,8 +254,6 @@ static int __init bcm1480_pcibios_init(void) ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536); bcm1480_controller.io_map_base -= bcm1480_controller.io_offset; set_io_port_base(bcm1480_controller.io_map_base); - isa_slot_offset = (unsigned long) - ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024); register_pci_controller(&bcm1480_controller); diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 2a09ad91ec8c..9bc102a1380e 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -254,9 +254,6 @@ static int __init sb1250_pcibios_init(void) * works correctly with most of Linux's drivers. * XXX ehs: Should this happen in PCI Device mode? */ - isa_slot_offset = (unsigned long) - ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024); - io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024); sb1250_controller.io_map_base = io_map_base; set_io_port_base((unsigned long)io_map_base); diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 5484e1c62054..a49272ce7ef5 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -116,7 +116,6 @@ void __init plat_mem_setup(void) /* * Setup (E)ISA I/O memory access stuff */ - isa_slot_offset = CKSEG1ADDR(0xb0000000); #ifdef CONFIG_EISA EISA_bus = 1; #endif diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index f18d2816cbec..501a40b9f18d 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -160,13 +160,6 @@ static inline void * isa_bus_to_virt(unsigned long address) #define virt_to_bus virt_to_phys #define bus_to_virt phys_to_virt -/* - * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped - * for the processor. This implies the assumption that there is only - * one of these busses. - */ -extern unsigned long isa_slot_offset; - /* * Change "struct page" to physical address. */ @@ -527,16 +520,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int memcpy((void __force *) dst, src, count); } -/* - * ISA space is 'always mapped' on currently supported MIPS systems, no need - * to explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): - */ -#define __ISA_IO_base ((char *)(isa_slot_offset)) - /* * The caches on some architectures aren't dma-coherent and have need to * handle this in software. There are three types of operations that -- cgit v1.2.3 From 07cdb78436d52416a582e645b9afb6e26f986bc9 Mon Sep 17 00:00:00 2001 From: Dmitri Vorobiev Date: Thu, 29 May 2008 17:57:08 +0300 Subject: [MIPS] fix sparse warning about setup_early_printk() This patch fixes the following sparse warning: <<<<<<<< arch/mips/kernel/early_printk.c:35:13: warning: symbol 'setup_early_printk' was not declared. Should it be static? <<<<<<<< The fix is to define a prototype of the setup_early_printk() function and to include the appropriate header into arch/mips/kernel/early_printk.c. [Ralf: Sorted includes again] Signed-off-by: Dmitri Vorobiev Signed-off-by: Ralf Baechle --- arch/mips/kernel/early_printk.c | 2 ++ arch/mips/kernel/setup.c | 6 +----- include/asm-mips/setup.h | 2 ++ 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c index 9dccfa4752b2..9ae813eb782e 100644 --- a/arch/mips/kernel/early_printk.c +++ b/arch/mips/kernel/early_printk.c @@ -10,6 +10,8 @@ #include #include +#include + extern void prom_putchar(char); static void __init diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index c04e4e3afede..8af84867e74d 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -550,11 +550,7 @@ void __init setup_arch(char **cmdline_p) prom_init(); #ifdef CONFIG_EARLY_PRINTK - { - extern void setup_early_printk(void); - - setup_early_printk(); - } + setup_early_printk(); #endif cpu_report(); check_bugs_early(); diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h index 70009a902639..883f59bfa097 100644 --- a/include/asm-mips/setup.h +++ b/include/asm-mips/setup.h @@ -3,4 +3,6 @@ #define COMMAND_LINE_SIZE 256 +extern void setup_early_printk(void); + #endif /* __SETUP_H */ -- cgit v1.2.3 From 997288517ec839b7639fcba77111256b13a66000 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Mon, 9 Jun 2008 08:39:58 +0200 Subject: [MIPS] Alchemy: remove unused MMC macros from db1x00 header. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- include/asm-mips/mach-db1x00/db1x00.h | 45 ----------------------------------- 1 file changed, 45 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index 612ae90dbcb8..1a515b8c870f 100644 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -145,51 +145,6 @@ typedef volatile struct #define SET_VCC_VPP(VCC, VPP, SLOT)\ ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) -/* - * SD controller macros - */ - -/* Detect card. */ -#define mmc_card_inserted(_n_, _res_) \ - do { \ - BCSR * const bcsr = (BCSR *)0xAE000000; \ - unsigned long mmc_wp, board_specific; \ - if ((_n_)) { \ - mmc_wp = BCSR_BOARD_SD1_WP; \ - } else { \ - mmc_wp = BCSR_BOARD_SD0_WP; \ - } \ - board_specific = au_readl((unsigned long)(&bcsr->specific)); \ - if (!(board_specific & mmc_wp)) {/* low means card present */ \ - *(int *)(_res_) = 1; \ - } else { \ - *(int *)(_res_) = 0; \ - } \ - } while (0) - -/* - * Apply power to card slot(s). - */ -#define mmc_power_on(_n_) \ - do { \ - BCSR * const bcsr = (BCSR *)0xAE000000; \ - unsigned long mmc_pwr, mmc_wp, board_specific; \ - if ((_n_)) { \ - mmc_pwr = BCSR_BOARD_SD1_PWR; \ - mmc_wp = BCSR_BOARD_SD1_WP; \ - } else { \ - mmc_pwr = BCSR_BOARD_SD0_PWR; \ - mmc_wp = BCSR_BOARD_SD0_WP; \ - } \ - board_specific = au_readl((unsigned long)(&bcsr->specific)); \ - if (!(board_specific & mmc_wp)) {/* low means card present */ \ - board_specific |= mmc_pwr; \ - au_writel(board_specific, (int)(&bcsr->specific)); \ - au_sync(); \ - } \ - } while (0) - - /* * NAND defines * -- cgit v1.2.3 From 2957c9e61ee9c37e7ebf2c8acab03e073fe942fd Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 15 Jul 2008 18:44:30 +0100 Subject: [MIPS] IRIX: Goodbye and thanks for all the fish Never terribly functional or popular, plagued by hard to fix bugs the time to say goodbye has more than arrived. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 4 - arch/mips/kernel/Makefile | 4 - arch/mips/kernel/irix5sys.S | 1041 ------------------- arch/mips/kernel/irixelf.c | 1361 ------------------------- arch/mips/kernel/irixinv.c | 78 -- arch/mips/kernel/irixioctl.c | 213 ---- arch/mips/kernel/irixsig.c | 888 ----------------- arch/mips/kernel/process.c | 7 - arch/mips/kernel/scall32-o32.S | 19 - arch/mips/kernel/sysirix.c | 2140 ---------------------------------------- include/asm-mips/inventory.h | 24 - include/asm-mips/namei.h | 25 +- include/asm-mips/prctl.h | 41 - include/asm-mips/signal.h | 3 - 14 files changed, 5 insertions(+), 5843 deletions(-) delete mode 100644 arch/mips/kernel/irix5sys.S delete mode 100644 arch/mips/kernel/irixelf.c delete mode 100644 arch/mips/kernel/irixinv.c delete mode 100644 arch/mips/kernel/irixioctl.c delete mode 100644 arch/mips/kernel/irixsig.c delete mode 100644 arch/mips/kernel/sysirix.c delete mode 100644 include/asm-mips/inventory.h delete mode 100644 include/asm-mips/prctl.h (limited to 'include/asm-mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 24c5dee91768..21d6ec1e5368 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2064,10 +2064,6 @@ source "fs/Kconfig.binfmt" config TRAD_SIGNALS bool -config BINFMT_IRIX - bool "Include IRIX binary compatibility" - depends on CPU_BIG_ENDIAN && 32BIT && BROKEN - config MIPS32_COMPAT bool "Kernel support for Linux/MIPS 32-bit binary compatibility" depends on 64BIT diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 65e46a6d4178..48ae915b38e0 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -20,9 +20,6 @@ obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o -binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ - irix5sys.o sysirix.o - obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += mips_ksyms.o module.o @@ -70,7 +67,6 @@ obj-$(CONFIG_IRQ_GIC) += irq-gic.o obj-$(CONFIG_32BIT) += scall32-o32.o obj-$(CONFIG_64BIT) += scall64-64.o -obj-$(CONFIG_BINFMT_IRIX) += binfmt_irix.o obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o diff --git a/arch/mips/kernel/irix5sys.S b/arch/mips/kernel/irix5sys.S deleted file mode 100644 index eeef891093ed..000000000000 --- a/arch/mips/kernel/irix5sys.S +++ /dev/null @@ -1,1041 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * 32-bit IRIX5 ABI system call table derived from original file 'irix5sys.h' - * created by David S. Miller. - * - * Copyright (C) 1996 - 2004 David S. Miller - * Copyright (C) 2004 Steven J. Hill - */ -#include - - /* - * Key: - * V == Valid and should work as expected for most cases. - * HV == Half Valid, some things will work, some likely will not - * IV == InValid, certainly will not work at all yet - * ?V == ?'ably Valid, I have not done enough looking into it - * DC == Don't Care, a rats ass we couldn't give - */ - - .macro irix5syscalltable - - sys sys_syscall 0 /* 1000 sysindir() V*/ - sys sys_exit 1 /* 1001 exit() V*/ - sys sys_fork 0 /* 1002 fork() V*/ - sys sys_read 3 /* 1003 read() V*/ - sys sys_write 3 /* 1004 write() V*/ - sys sys_open 3 /* 1005 open() V*/ - sys sys_close 1 /* 1006 close() V*/ - sys irix_unimp 0 /* 1007 (XXX IRIX 4 wait) V*/ - sys sys_creat 2 /* 1008 creat() V*/ - sys sys_link 2 /* 1009 link() V*/ - sys sys_unlink 1 /* 1010 unlink() V*/ - sys irix_exec 0 /* 1011 exec() V*/ - sys sys_chdir 1 /* 1012 chdir() V*/ - sys irix_gtime 0 /* 1013 time() V*/ - sys irix_unimp 0 /* 1014 (XXX IRIX 4 mknod) V*/ - sys sys_chmod 2 /* 1015 chmod() V*/ - sys sys_chown 3 /* 1016 chown() V*/ - sys irix_brk 1 /* 1017 break() V*/ - sys irix_unimp 0 /* 1018 (XXX IRIX 4 stat) V*/ - sys sys_lseek 3 /* 1019 lseek() XXX64bit HV*/ - sys irix_getpid 0 /* 1020 getpid() V*/ - sys irix_mount 6 /* 1021 mount() IV*/ - sys sys_umount 1 /* 1022 umount() V*/ - sys sys_setuid 1 /* 1023 setuid() V*/ - sys irix_getuid 0 /* 1024 getuid() V*/ - sys irix_stime 1 /* 1025 stime() V*/ - sys irix_unimp 4 /* 1026 XXX ptrace() IV*/ - sys irix_alarm 1 /* 1027 alarm() V*/ - sys irix_unimp 0 /* 1028 (XXX IRIX 4 fstat) V*/ - sys irix_pause 0 /* 1029 pause() V*/ - sys sys_utime 2 /* 1030 utime() V*/ - sys irix_unimp 0 /* 1031 nuthin' V*/ - sys irix_unimp 0 /* 1032 nobody home man... V*/ - sys sys_access 2 /* 1033 access() V*/ - sys sys_nice 1 /* 1034 nice() V*/ - sys irix_statfs 2 /* 1035 statfs() V*/ - sys sys_sync 0 /* 1036 sync() V*/ - sys sys_kill 2 /* 1037 kill() V*/ - sys irix_fstatfs 2 /* 1038 fstatfs() V*/ - sys irix_setpgrp 1 /* 1039 setpgrp() V*/ - sys irix_syssgi 0 /* 1040 syssgi() HV*/ - sys sys_dup 1 /* 1041 dup() V*/ - sys sys_pipe 0 /* 1042 pipe() V*/ - sys irix_times 1 /* 1043 times() V*/ - sys irix_unimp 0 /* 1044 XXX profil() IV*/ - sys irix_unimp 0 /* 1045 XXX lock() IV*/ - sys sys_setgid 1 /* 1046 setgid() V*/ - sys irix_getgid 0 /* 1047 getgid() V*/ - sys irix_unimp 0 /* 1048 (XXX IRIX 4 ssig) V*/ - sys irix_msgsys 6 /* 1049 sys_msgsys V*/ - sys sys_sysmips 4 /* 1050 sysmips() HV*/ - sys irix_unimp 0 /* 1051 XXX sysacct() IV*/ - sys irix_shmsys 5 /* 1052 sys_shmsys V*/ - sys irix_semsys 0 /* 1053 sys_semsys V*/ - sys irix_ioctl 3 /* 1054 ioctl() HV*/ - sys irix_uadmin 0 /* 1055 XXX sys_uadmin() HC*/ - sys irix_sysmp 0 /* 1056 sysmp() HV*/ - sys irix_utssys 4 /* 1057 sys_utssys() HV*/ - sys irix_unimp 0 /* 1058 nada enchilada V*/ - sys irix_exece 0 /* 1059 exece() V*/ - sys sys_umask 1 /* 1060 umask() V*/ - sys sys_chroot 1 /* 1061 chroot() V*/ - sys irix_fcntl 3 /* 1062 fcntl() ?V*/ - sys irix_ulimit 2 /* 1063 ulimit() HV*/ - sys irix_unimp 0 /* 1064 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1065 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1066 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1067 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1068 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1069 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1070 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1071 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1072 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1073 XXX AFS shit DC*/ - sys irix_unimp 0 /* 1074 nuttin' V*/ - sys irix_unimp 0 /* 1075 XXX sys_getrlimit64()IV*/ - sys irix_unimp 0 /* 1076 XXX sys_setrlimit64()IV*/ - sys sys_nanosleep 2 /* 1077 nanosleep() V*/ - sys irix_lseek64 5 /* 1078 lseek64() ?V*/ - sys sys_rmdir 1 /* 1079 rmdir() V*/ - sys sys_mkdir 2 /* 1080 mkdir() V*/ - sys sys_getdents 3 /* 1081 getdents() V*/ - sys irix_sginap 1 /* 1082 sys_sginap() V*/ - sys irix_sgikopt 3 /* 1083 sys_sgikopt() DC*/ - sys sys_sysfs 3 /* 1084 sysfs() ?V*/ - sys irix_unimp 0 /* 1085 XXX sys_getmsg() DC*/ - sys irix_unimp 0 /* 1086 XXX sys_putmsg() DC*/ - sys sys_poll 3 /* 1087 poll() V*/ - sys irix_sigreturn 0 /* 1088 sigreturn() ?V*/ - sys sys_accept 3 /* 1089 accept() V*/ - sys sys_bind 3 /* 1090 bind() V*/ - sys sys_connect 3 /* 1091 connect() V*/ - sys irix_gethostid 0 /* 1092 sys_gethostid() ?V*/ - sys sys_getpeername 3 /* 1093 getpeername() V*/ - sys sys_getsockname 3 /* 1094 getsockname() V*/ - sys sys_getsockopt 5 /* 1095 getsockopt() V*/ - sys sys_listen 2 /* 1096 listen() V*/ - sys sys_recv 4 /* 1097 recv() V*/ - sys sys_recvfrom 6 /* 1098 recvfrom() V*/ - sys sys_recvmsg 3 /* 1099 recvmsg() V*/ - sys sys_select 5 /* 1100 select() V*/ - sys sys_send 4 /* 1101 send() V*/ - sys sys_sendmsg 3 /* 1102 sendmsg() V*/ - sys sys_sendto 6 /* 1103 sendto() V*/ - sys irix_sethostid 1 /* 1104 sys_sethostid() ?V*/ - sys sys_setsockopt 5 /* 1105 setsockopt() V*/ - sys sys_shutdown 2 /* 1106 shutdown() ?V*/ - sys irix_socket 3 /* 1107 socket() V*/ - sys sys_gethostname 2 /* 1108 sys_gethostname() ?V*/ - sys sys_sethostname 2 /* 1109 sethostname() ?V*/ - sys irix_getdomainname 2 /* 1110 sys_getdomainname() ?V*/ - sys sys_setdomainname 2 /* 1111 setdomainname() ?V*/ - sys sys_truncate 2 /* 1112 truncate() V*/ - sys sys_ftruncate 2 /* 1113 ftruncate() V*/ - sys sys_rename 2 /* 1114 rename() V*/ - sys sys_symlink 2 /* 1115 symlink() V*/ - sys sys_readlink 3 /* 1116 readlink() V*/ - sys irix_unimp 0 /* 1117 XXX IRIX 4 lstat() DC*/ - sys irix_unimp 0 /* 1118 nothin' V*/ - sys irix_unimp 0 /* 1119 XXX nfs_svc() DC*/ - sys irix_unimp 0 /* 1120 XXX nfs_getfh() DC*/ - sys irix_unimp 0 /* 1121 XXX async_daemon() DC*/ - sys irix_unimp 0 /* 1122 XXX exportfs() DC*/ - sys sys_setregid 2 /* 1123 setregid() V*/ - sys sys_setreuid 2 /* 1124 setreuid() V*/ - sys sys_getitimer 2 /* 1125 getitimer() V*/ - sys sys_setitimer 3 /* 1126 setitimer() V*/ - sys irix_unimp 1 /* 1127 XXX adjtime() IV*/ - sys irix_gettimeofday 1 /* 1128 gettimeofday() V*/ - sys irix_unimp 0 /* 1129 XXX sproc() IV*/ - sys irix_prctl 0 /* 1130 prctl() HV*/ - sys irix_unimp 0 /* 1131 XXX procblk() IV*/ - sys irix_unimp 0 /* 1132 XXX sprocsp() IV*/ - sys irix_unimp 0 /* 1133 XXX sgigsc() IV*/ - sys irix_mmap32 6 /* 1134 mmap() XXXflags? ?V*/ - sys sys_munmap 2 /* 1135 munmap() V*/ - sys sys_mprotect 3 /* 1136 mprotect() V*/ - sys sys_msync 4 /* 1137 msync() V*/ - sys irix_madvise 3 /* 1138 madvise() DC*/ - sys irix_pagelock 3 /* 1139 pagelock() IV*/ - sys irix_getpagesize 0 /* 1140 getpagesize() V*/ - sys irix_quotactl 0 /* 1141 quotactl() V*/ - sys irix_unimp 0 /* 1142 nobody home man V*/ - sys sys_getpgid 1 /* 1143 BSD getpgrp() V*/ - sys irix_BSDsetpgrp 2 /* 1143 BSD setpgrp() V*/ - sys sys_vhangup 0 /* 1144 vhangup() V*/ - sys sys_fsync 1 /* 1145 fsync() V*/ - sys sys_fchdir 1 /* 1146 fchdir() V*/ - sys sys_getrlimit 2 /* 1147 getrlimit() ?V*/ - sys sys_setrlimit 2 /* 1148 setrlimit() ?V*/ - sys sys_cacheflush 3 /* 1150 cacheflush() HV*/ - sys sys_cachectl 3 /* 1151 cachectl() HV*/ - sys sys_fchown 3 /* 1152 fchown() ?V*/ - sys sys_fchmod 2 /* 1153 fchmod() ?V*/ - sys irix_unimp 0 /* 1154 XXX IRIX 4 wait3() V*/ - sys sys_socketpair 4 /* 1155 socketpair() V*/ - sys irix_systeminfo 3 /* 1156 systeminfo() IV*/ - sys irix_uname 1 /* 1157 uname() IV*/ - sys irix_xstat 3 /* 1158 xstat() V*/ - sys irix_lxstat 3 /* 1159 lxstat() V*/ - sys irix_fxstat 3 /* 1160 fxstat() V*/ - sys irix_xmknod 0 /* 1161 xmknod() ?V*/ - sys irix_sigaction 4 /* 1162 sigaction() ?V*/ - sys irix_sigpending 1 /* 1163 sigpending() ?V*/ - sys irix_sigprocmask 3 /* 1164 sigprocmask() ?V*/ - sys irix_sigsuspend 0 /* 1165 sigsuspend() ?V*/ - sys irix_sigpoll_sys 3 /* 1166 sigpoll_sys() IV*/ - sys irix_swapctl 2 /* 1167 swapctl() IV*/ - sys irix_getcontext 0 /* 1168 getcontext() HV*/ - sys irix_setcontext 0 /* 1169 setcontext() HV*/ - sys irix_waitsys 5 /* 1170 waitsys() IV*/ - sys irix_sigstack 2 /* 1171 sigstack() HV*/ - sys irix_sigaltstack 2 /* 1172 sigaltstack() HV*/ - sys irix_sigsendset 2 /* 1173 sigsendset() IV*/ - sys irix_statvfs 2 /* 1174 statvfs() V*/ - sys irix_fstatvfs 2 /* 1175 fstatvfs() V*/ - sys irix_unimp 0 /* 1176 XXX getpmsg() DC*/ - sys irix_unimp 0 /* 1177 XXX putpmsg() DC*/ - sys sys_lchown 3 /* 1178 lchown() V*/ - sys irix_priocntl 0 /* 1179 priocntl() DC*/ - sys irix_sigqueue 4 /* 1180 sigqueue() IV*/ - sys sys_readv 3 /* 1181 readv() V*/ - sys sys_writev 3 /* 1182 writev() V*/ - sys irix_truncate64 4 /* 1183 truncate64() XX32bit HV*/ - sys irix_ftruncate64 4 /* 1184 ftruncate64()XX32bit HV*/ - sys irix_mmap64 0 /* 1185 mmap64() XX32bit HV*/ - sys irix_dmi 0 /* 1186 dmi() DC*/ - sys irix_pread 6 /* 1187 pread() IV*/ - sys irix_pwrite 6 /* 1188 pwrite() IV*/ - sys sys_fsync 1 /* 1189 fdatasync() XXPOSIX HV*/ - sys irix_sgifastpath 7 /* 1190 sgifastpath() WHEEE IV*/ - sys irix_unimp 0 /* 1191 XXX attr_get() DC*/ - sys irix_unimp 0 /* 1192 XXX attr_getf() DC*/ - sys irix_unimp 0 /* 1193 XXX attr_set() DC*/ - sys irix_unimp 0 /* 1194 XXX attr_setf() DC*/ - sys irix_unimp 0 /* 1195 XXX attr_remove() DC*/ - sys irix_unimp 0 /* 1196 XXX attr_removef() DC*/ - sys irix_unimp 0 /* 1197 XXX attr_list() DC*/ - sys irix_unimp 0 /* 1198 XXX attr_listf() DC*/ - sys irix_unimp 0 /* 1199 XXX attr_multi() DC*/ - sys irix_unimp 0 /* 1200 XXX attr_multif() DC*/ - sys irix_statvfs64 2 /* 1201 statvfs64() V*/ - sys irix_fstatvfs64 2 /* 1202 fstatvfs64() V*/ - sys irix_getmountid 2 /* 1203 getmountid()XXXfsids HV*/ - sys irix_nsproc 5 /* 1204 nsproc() IV*/ - sys irix_getdents64 3 /* 1205 getdents64() HV*/ - sys irix_unimp 0 /* 1206 XXX DFS garbage DC*/ - sys irix_ngetdents 4 /* 1207 ngetdents() XXXeop HV*/ - sys irix_ngetdents64 4 /* 1208 ngetdents64() XXXeop HV*/ - sys irix_unimp 0 /* 1209 nothin' V*/ - sys irix_unimp 0 /* 1210 XXX pidsprocsp() */ - sys irix_unimp 0 /* 1211 XXX rexec() */ - sys irix_unimp 0 /* 1212 XXX timer_create() */ - sys irix_unimp 0 /* 1213 XXX timer_delete() */ - sys irix_unimp 0 /* 1214 XXX timer_settime() */ - sys irix_unimp 0 /* 1215 XXX timer_gettime() */ - sys irix_unimp 0 /* 1216 XXX timer_setoverrun() */ - sys sys_sched_rr_get_interval 2 /* 1217 sched_rr_get_interval()V*/ - sys sys_sched_yield 0 /* 1218 sched_yield() V*/ - sys sys_sched_getscheduler 1 /* 1219 sched_getscheduler() V*/ - sys sys_sched_setscheduler 3 /* 1220 sched_setscheduler() V*/ - sys sys_sched_getparam 2 /* 1221 sched_getparam() V*/ - sys sys_sched_setparam 2 /* 1222 sched_setparam() V*/ - sys irix_unimp 0 /* 1223 XXX usync_cntl() */ - sys irix_unimp 0 /* 1224 XXX psema_cntl() */ - sys irix_unimp 0 /* 1225 XXX restartreturn() */ - - /* Just to pad things out nicely. */ - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - sys irix_unimp 0 - - .endm - - /* - * Pre-compute the number of _instruction_ bytes needed to load - * or store the arguments 6-8. Negative values are ignored. - */ - .macro sys function, nargs - PTR \function - LONG (\nargs << 2) - (5 << 2) - .endm - - .align 4 -EXPORT(sys_call_table_irix5) - irix5syscalltable diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c deleted file mode 100644 index 469c7237e5ba..000000000000 --- a/arch/mips/kernel/irixelf.c +++ /dev/null @@ -1,1361 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * irixelf.c: Code to load IRIX ELF executables conforming to the MIPS ABI. - * Based off of work by Eric Youngdale. - * - * Copyright (C) 1993 - 1994 Eric Youngdale - * Copyright (C) 1996 - 2004 David S. Miller - * Copyright (C) 2004 - 2005 Steven J. Hill - */ -#undef DEBUG - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define DLINFO_ITEMS 12 - -#include - -static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs); -static int load_irix_library(struct file *); -static int irix_core_dump(long signr, struct pt_regs * regs, - struct file *file, unsigned long limit); - -static struct linux_binfmt irix_format = { - .module = THIS_MODULE, - .load_binary = load_irix_binary, - .load_shlib = load_irix_library, - .core_dump = irix_core_dump, - .min_coredump = PAGE_SIZE, -}; - -/* Debugging routines. */ -static char *get_elf_p_type(Elf32_Word p_type) -{ -#ifdef DEBUG - switch (p_type) { - case PT_NULL: - return "PT_NULL"; - break; - - case PT_LOAD: - return "PT_LOAD"; - break; - - case PT_DYNAMIC: - return "PT_DYNAMIC"; - break; - - case PT_INTERP: - return "PT_INTERP"; - break; - - case PT_NOTE: - return "PT_NOTE"; - break; - - case PT_SHLIB: - return "PT_SHLIB"; - break; - - case PT_PHDR: - return "PT_PHDR"; - break; - - case PT_LOPROC: - return "PT_LOPROC/REGINFO"; - break; - - case PT_HIPROC: - return "PT_HIPROC"; - break; - - default: - return "PT_BOGUS"; - break; - } -#endif -} - -static void print_elfhdr(struct elfhdr *ehp) -{ - int i; - - pr_debug("ELFHDR: e_ident<"); - for (i = 0; i < (EI_NIDENT - 1); i++) - pr_debug("%x ", ehp->e_ident[i]); - pr_debug("%x>\n", ehp->e_ident[i]); - pr_debug(" e_type[%04x] e_machine[%04x] e_version[%08lx]\n", - (unsigned short) ehp->e_type, (unsigned short) ehp->e_machine, - (unsigned long) ehp->e_version); - pr_debug(" e_entry[%08lx] e_phoff[%08lx] e_shoff[%08lx] " - "e_flags[%08lx]\n", - (unsigned long) ehp->e_entry, (unsigned long) ehp->e_phoff, - (unsigned long) ehp->e_shoff, (unsigned long) ehp->e_flags); - pr_debug(" e_ehsize[%04x] e_phentsize[%04x] e_phnum[%04x]\n", - (unsigned short) ehp->e_ehsize, - (unsigned short) ehp->e_phentsize, - (unsigned short) ehp->e_phnum); - pr_debug(" e_shentsize[%04x] e_shnum[%04x] e_shstrndx[%04x]\n", - (unsigned short) ehp->e_shentsize, - (unsigned short) ehp->e_shnum, - (unsigned short) ehp->e_shstrndx); -} - -static void print_phdr(int i, struct elf_phdr *ep) -{ - pr_debug("PHDR[%d]: p_type[%s] p_offset[%08lx] p_vaddr[%08lx] " - "p_paddr[%08lx]\n", i, get_elf_p_type(ep->p_type), - (unsigned long) ep->p_offset, (unsigned long) ep->p_vaddr, - (unsigned long) ep->p_paddr); - pr_debug(" p_filesz[%08lx] p_memsz[%08lx] p_flags[%08lx] " - "p_align[%08lx]\n", (unsigned long) ep->p_filesz, - (unsigned long) ep->p_memsz, (unsigned long) ep->p_flags, - (unsigned long) ep->p_align); -} - -static void dump_phdrs(struct elf_phdr *ep, int pnum) -{ - int i; - - for (i = 0; i < pnum; i++, ep++) { - if ((ep->p_type == PT_LOAD) || - (ep->p_type == PT_INTERP) || - (ep->p_type == PT_PHDR)) - print_phdr(i, ep); - } -} - -static void set_brk(unsigned long start, unsigned long end) -{ - start = PAGE_ALIGN(start); - end = PAGE_ALIGN(end); - if (end <= start) - return; - down_write(¤t->mm->mmap_sem); - do_brk(start, end - start); - up_write(¤t->mm->mmap_sem); -} - - -/* We need to explicitly zero any fractional pages - * after the data section (i.e. bss). This would - * contain the junk from the file that should not - * be in memory. - */ -static void padzero(unsigned long elf_bss) -{ - unsigned long nbyte; - - nbyte = elf_bss & (PAGE_SIZE-1); - if (nbyte) { - nbyte = PAGE_SIZE - nbyte; - clear_user((void __user *) elf_bss, nbyte); - } -} - -static unsigned long * create_irix_tables(char * p, int argc, int envc, - struct elfhdr * exec, unsigned int load_addr, - unsigned int interp_load_addr, struct pt_regs *regs, - struct elf_phdr *ephdr) -{ - elf_addr_t *argv; - elf_addr_t *envp; - elf_addr_t *sp, *csp; - - pr_debug("create_irix_tables: p[%p] argc[%d] envc[%d] " - "load_addr[%08x] interp_load_addr[%08x]\n", - p, argc, envc, load_addr, interp_load_addr); - - sp = (elf_addr_t *) (~15UL & (unsigned long) p); - csp = sp; - csp -= exec ? DLINFO_ITEMS*2 : 2; - csp -= envc+1; - csp -= argc+1; - csp -= 1; /* argc itself */ - if ((unsigned long)csp & 15UL) { - sp -= (16UL - ((unsigned long)csp & 15UL)) / sizeof(*sp); - } - - /* - * Put the ELF interpreter info on the stack - */ -#define NEW_AUX_ENT(nr, id, val) \ - __put_user((id), sp+(nr*2)); \ - __put_user((val), sp+(nr*2+1)); \ - - sp -= 2; - NEW_AUX_ENT(0, AT_NULL, 0); - - if (exec) { - sp -= 11*2; - - NEW_AUX_ENT(0, AT_PHDR, load_addr + exec->e_phoff); - NEW_AUX_ENT(1, AT_PHENT, sizeof(struct elf_phdr)); - NEW_AUX_ENT(2, AT_PHNUM, exec->e_phnum); - NEW_AUX_ENT(3, AT_PAGESZ, ELF_EXEC_PAGESIZE); - NEW_AUX_ENT(4, AT_BASE, interp_load_addr); - NEW_AUX_ENT(5, AT_FLAGS, 0); - NEW_AUX_ENT(6, AT_ENTRY, (elf_addr_t) exec->e_entry); - NEW_AUX_ENT(7, AT_UID, (elf_addr_t) current->uid); - NEW_AUX_ENT(8, AT_EUID, (elf_addr_t) current->euid); - NEW_AUX_ENT(9, AT_GID, (elf_addr_t) current->gid); - NEW_AUX_ENT(10, AT_EGID, (elf_addr_t) current->egid); - } -#undef NEW_AUX_ENT - - sp -= envc+1; - envp = sp; - sp -= argc+1; - argv = sp; - - __put_user((elf_addr_t)argc, --sp); - current->mm->arg_start = (unsigned long) p; - while (argc-->0) { - __put_user((unsigned long)p, argv++); - p += strlen_user(p); - } - __put_user((unsigned long) NULL, argv); - current->mm->arg_end = current->mm->env_start = (unsigned long) p; - while (envc-->0) { - __put_user((unsigned long)p, envp++); - p += strlen_user(p); - } - __put_user((unsigned long) NULL, envp); - current->mm->env_end = (unsigned long) p; - return sp; -} - - -/* This is much more generalized than the library routine read function, - * so we keep this separate. Technically the library read function - * is only provided so that we can read a.out libraries that have - * an ELF header. - */ -static unsigned int load_irix_interp(struct elfhdr * interp_elf_ex, - struct file * interpreter, - unsigned int *interp_load_addr) -{ - struct elf_phdr *elf_phdata = NULL; - struct elf_phdr *eppnt; - unsigned int len; - unsigned int load_addr; - int elf_bss; - int retval; - unsigned int last_bss; - int error; - int i; - unsigned int k; - - elf_bss = 0; - last_bss = 0; - error = load_addr = 0; - - print_elfhdr(interp_elf_ex); - - /* First of all, some simple consistency checks */ - if ((interp_elf_ex->e_type != ET_EXEC && - interp_elf_ex->e_type != ET_DYN) || - !interpreter->f_op->mmap) { - printk("IRIX interp has bad e_type %d\n", interp_elf_ex->e_type); - return 0xffffffff; - } - - /* Now read in all of the header information */ - if (sizeof(struct elf_phdr) * interp_elf_ex->e_phnum > PAGE_SIZE) { - printk("IRIX interp header bigger than a page (%d)\n", - (sizeof(struct elf_phdr) * interp_elf_ex->e_phnum)); - return 0xffffffff; - } - - elf_phdata = kmalloc(sizeof(struct elf_phdr) * interp_elf_ex->e_phnum, - GFP_KERNEL); - - if (!elf_phdata) { - printk("Cannot kmalloc phdata for IRIX interp.\n"); - return 0xffffffff; - } - - /* If the size of this structure has changed, then punt, since - * we will be doing the wrong thing. - */ - if (interp_elf_ex->e_phentsize != 32) { - printk("IRIX interp e_phentsize == %d != 32 ", - interp_elf_ex->e_phentsize); - kfree(elf_phdata); - return 0xffffffff; - } - - retval = kernel_read(interpreter, interp_elf_ex->e_phoff, - (char *) elf_phdata, - sizeof(struct elf_phdr) * interp_elf_ex->e_phnum); - - dump_phdrs(elf_phdata, interp_elf_ex->e_phnum); - - eppnt = elf_phdata; - for (i = 0; i < interp_elf_ex->e_phnum; i++, eppnt++) { - if (eppnt->p_type == PT_LOAD) { - int elf_type = MAP_PRIVATE | MAP_DENYWRITE; - int elf_prot = 0; - unsigned long vaddr = 0; - if (eppnt->p_flags & PF_R) - elf_prot = PROT_READ; - if (eppnt->p_flags & PF_W) - elf_prot |= PROT_WRITE; - if (eppnt->p_flags & PF_X) - elf_prot |= PROT_EXEC; - elf_type |= MAP_FIXED; - vaddr = eppnt->p_vaddr; - - pr_debug("INTERP do_mmap" - "(%p, %08lx, %08lx, %08lx, %08lx, %08lx) ", - interpreter, vaddr, - (unsigned long) - (eppnt->p_filesz + (eppnt->p_vaddr & 0xfff)), - (unsigned long) - elf_prot, (unsigned long) elf_type, - (unsigned long) - (eppnt->p_offset & 0xfffff000)); - - down_write(¤t->mm->mmap_sem); - error = do_mmap(interpreter, vaddr, - eppnt->p_filesz + (eppnt->p_vaddr & 0xfff), - elf_prot, elf_type, - eppnt->p_offset & 0xfffff000); - up_write(¤t->mm->mmap_sem); - - if (error < 0 && error > -1024) { - printk("Aieee IRIX interp mmap error=%d\n", - error); - break; /* Real error */ - } - pr_debug("error=%08lx ", (unsigned long) error); - if (!load_addr && interp_elf_ex->e_type == ET_DYN) { - load_addr = error; - pr_debug("load_addr = error "); - } - - /* - * Find the end of the file mapping for this phdr, and - * keep track of the largest address we see for this. - */ - k = eppnt->p_vaddr + eppnt->p_filesz; - if (k > elf_bss) - elf_bss = k; - - /* Do the same thing for the memory mapping - between - * elf_bss and last_bss is the bss section. - */ - k = eppnt->p_memsz + eppnt->p_vaddr; - if (k > last_bss) - last_bss = k; - pr_debug("\n"); - } - } - - /* Now use mmap to map the library into memory. */ - if (error < 0 && error > -1024) { - pr_debug("got error %d\n", error); - kfree(elf_phdata); - return 0xffffffff; - } - - /* Now fill out the bss section. First pad the last page up - * to the page boundary, and then perform a mmap to make sure - * that there are zero-mapped pages up to and including the - * last bss page. - */ - pr_debug("padzero(%08lx) ", (unsigned long) (elf_bss)); - padzero(elf_bss); - len = (elf_bss + 0xfff) & 0xfffff000; /* What we have mapped so far */ - - pr_debug("last_bss[%08lx] len[%08lx]\n", (unsigned long) last_bss, - (unsigned long) len); - - /* Map the last of the bss segment */ - if (last_bss > len) { - down_write(¤t->mm->mmap_sem); - do_brk(len, (last_bss - len)); - up_write(¤t->mm->mmap_sem); - } - kfree(elf_phdata); - - *interp_load_addr = load_addr; - return ((unsigned int) interp_elf_ex->e_entry); -} - -/* Check sanity of IRIX elf executable header. */ -static int verify_binary(struct elfhdr *ehp, struct linux_binprm *bprm) -{ - if (memcmp(ehp->e_ident, ELFMAG, SELFMAG) != 0) - return -ENOEXEC; - - /* First of all, some simple consistency checks */ - if ((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) || - !bprm->file->f_op->mmap) { - return -ENOEXEC; - } - - /* XXX Don't support N32 or 64bit binaries yet because they can - * XXX and do execute 64 bit instructions and expect all registers - * XXX to be 64 bit as well. We need to make the kernel save - * XXX all registers as 64bits on cpu's capable of this at - * XXX exception time plus frob the XTLB exception vector. - */ - if ((ehp->e_flags & EF_MIPS_ABI2)) - return -ENOEXEC; - - return 0; -} - -/* - * This is where the detailed check is performed. Irix binaries - * use interpreters with 'libc.so' in the name, so this function - * can differentiate between Linux and Irix binaries. - */ -static inline int look_for_irix_interpreter(char **name, - struct file **interpreter, - struct elfhdr *interp_elf_ex, - struct elf_phdr *epp, - struct linux_binprm *bprm, int pnum) -{ - int i; - int retval = -EINVAL; - struct file *file = NULL; - - *name = NULL; - for (i = 0; i < pnum; i++, epp++) { - if (epp->p_type != PT_INTERP) - continue; - - /* It is illegal to have two interpreters for one executable. */ - if (*name != NULL) - goto out; - - *name = kmalloc(epp->p_filesz + strlen(IRIX_EMUL), GFP_KERNEL); - if (!*name) - return -ENOMEM; - - strcpy(*name, IRIX_EMUL); - retval = kernel_read(bprm->file, epp->p_offset, (*name + 16), - epp->p_filesz); - if (retval < 0) - goto out; - - file = open_exec(*name); - if (IS_ERR(file)) { - retval = PTR_ERR(file); - goto out; - } - retval = kernel_read(file, 0, bprm->buf, 128); - if (retval < 0) - goto dput_and_out; - - *interp_elf_ex = *(struct elfhdr *) bprm->buf; - } - *interpreter = file; - return 0; - -dput_and_out: - fput(file); -out: - kfree(*name); - return retval; -} - -static inline int verify_irix_interpreter(struct elfhdr *ihp) -{ - if (memcmp(ihp->e_ident, ELFMAG, SELFMAG) != 0) - return -ELIBBAD; - return 0; -} - -#define EXEC_MAP_FLAGS (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE) - -static inline void map_executable(struct file *fp, struct elf_phdr *epp, int pnum, - unsigned int *estack, unsigned int *laddr, - unsigned int *scode, unsigned int *ebss, - unsigned int *ecode, unsigned int *edata, - unsigned int *ebrk) -{ - unsigned int tmp; - int i, prot; - - for (i = 0; i < pnum; i++, epp++) { - if (epp->p_type != PT_LOAD) - continue; - - /* Map it. */ - prot = (epp->p_flags & PF_R) ? PROT_READ : 0; - prot |= (epp->p_flags & PF_W) ? PROT_WRITE : 0; - prot |= (epp->p_flags & PF_X) ? PROT_EXEC : 0; - down_write(¤t->mm->mmap_sem); - (void) do_mmap(fp, (epp->p_vaddr & 0xfffff000), - (epp->p_filesz + (epp->p_vaddr & 0xfff)), - prot, EXEC_MAP_FLAGS, - (epp->p_offset & 0xfffff000)); - up_write(¤t->mm->mmap_sem); - - /* Fixup location tracking vars. */ - if ((epp->p_vaddr & 0xfffff000) < *estack) - *estack = (epp->p_vaddr & 0xfffff000); - if (!*laddr) - *laddr = epp->p_vaddr - epp->p_offset; - if (epp->p_vaddr < *scode) - *scode = epp->p_vaddr; - - tmp = epp->p_vaddr + epp->p_filesz; - if (tmp > *ebss) - *ebss = tmp; - if ((epp->p_flags & PF_X) && *ecode < tmp) - *ecode = tmp; - if (*edata < tmp) - *edata = tmp; - - tmp = epp->p_vaddr + epp->p_memsz; - if (tmp > *ebrk) - *ebrk = tmp; - } - -} - -static inline int map_interpreter(struct elf_phdr *epp, struct elfhdr *ihp, - struct file *interp, unsigned int *iladdr, - int pnum, mm_segment_t old_fs, - unsigned int *eentry) -{ - int i; - - *eentry = 0xffffffff; - for (i = 0; i < pnum; i++, epp++) { - if (epp->p_type != PT_INTERP) - continue; - - /* We should have fielded this error elsewhere... */ - if (*eentry != 0xffffffff) - return -1; - - set_fs(old_fs); - *eentry = load_irix_interp(ihp, interp, iladdr); - old_fs = get_fs(); - set_fs(get_ds()); - - fput(interp); - - if (*eentry == 0xffffffff) - return -1; - } - return 0; -} - -/* - * IRIX maps a page at 0x200000 that holds information about the - * process and the system, here we map the page and fill the - * structure - */ -static int irix_map_prda_page(void) -{ - unsigned long v; - struct prda *pp; - - down_write(¤t->mm->mmap_sem); - v = do_brk(PRDA_ADDRESS, PAGE_SIZE); - up_write(¤t->mm->mmap_sem); - - if (v != PRDA_ADDRESS) - return v; /* v must be an error code */ - - pp = (struct prda *) v; - pp->prda_sys.t_pid = task_pid_vnr(current); - pp->prda_sys.t_prid = read_c0_prid(); - pp->prda_sys.t_rpid = task_pid_vnr(current); - - /* We leave the rest set to zero */ - - return 0; -} - - - -/* These are the functions used to load ELF style executables and shared - * libraries. There is no binary dependent code anywhere else. - */ -static int load_irix_binary(struct linux_binprm * bprm, struct pt_regs * regs) -{ - struct elfhdr elf_ex, interp_elf_ex; - struct file *interpreter; - struct elf_phdr *elf_phdata, *elf_ihdr, *elf_ephdr; - unsigned int load_addr, elf_bss, elf_brk; - unsigned int elf_entry, interp_load_addr = 0; - unsigned int start_code, end_code, end_data, elf_stack; - int retval, has_interp, has_ephdr, size, i; - char *elf_interpreter; - mm_segment_t old_fs; - - load_addr = 0; - has_interp = has_ephdr = 0; - elf_ihdr = elf_ephdr = NULL; - elf_ex = *((struct elfhdr *) bprm->buf); - retval = -ENOEXEC; - - if (verify_binary(&elf_ex, bprm)) - goto out; - - /* - * Telling -o32 static binaries from Linux and Irix apart from each - * other is difficult. There are 2 differences to be noted for static - * binaries from the 2 operating systems: - * - * 1) Irix binaries have their .text section before their .init - * section. Linux binaries are just the opposite. - * - * 2) Irix binaries usually have <= 12 sections and Linux - * binaries have > 20. - * - * We will use Method #2 since Method #1 would require us to read in - * the section headers which is way too much overhead. This appears - * to work for everything we have ran into so far. If anyone has a - * better method to tell the binaries apart, I'm listening. - */ - if (elf_ex.e_shnum > 20) - goto out; - - print_elfhdr(&elf_ex); - - /* Now read in all of the header information */ - size = elf_ex.e_phentsize * elf_ex.e_phnum; - if (size > 65536) - goto out; - elf_phdata = kmalloc(size, GFP_KERNEL); - if (elf_phdata == NULL) { - retval = -ENOMEM; - goto out; - } - - retval = kernel_read(bprm->file, elf_ex.e_phoff, (char *)elf_phdata, size); - if (retval < 0) - goto out_free_ph; - - dump_phdrs(elf_phdata, elf_ex.e_phnum); - - /* Set some things for later. */ - for (i = 0; i < elf_ex.e_phnum; i++) { - switch (elf_phdata[i].p_type) { - case PT_INTERP: - has_interp = 1; - elf_ihdr = &elf_phdata[i]; - break; - case PT_PHDR: - has_ephdr = 1; - elf_ephdr = &elf_phdata[i]; - break; - }; - } - - pr_debug("\n"); - - elf_bss = 0; - elf_brk = 0; - - elf_stack = 0xffffffff; - elf_interpreter = NULL; - start_code = 0xffffffff; - end_code = 0; - end_data = 0; - - /* - * If we get a return value, we change the value to be ENOEXEC - * so that we can exit gracefully and the main binary format - * search loop in 'fs/exec.c' will move onto the next handler - * which should be the normal ELF binary handler. - */ - retval = look_for_irix_interpreter(&elf_interpreter, &interpreter, - &interp_elf_ex, elf_phdata, bprm, - elf_ex.e_phnum); - if (retval) { - retval = -ENOEXEC; - goto out_free_file; - } - - if (elf_interpreter) { - retval = verify_irix_interpreter(&interp_elf_ex); - if (retval) - goto out_free_interp; - } - - /* OK, we are done with that, now set up the arg stuff, - * and then start this sucker up. - */ - retval = -E2BIG; - if (!bprm->sh_bang && !bprm->p) - goto out_free_interp; - - /* Flush all traces of the currently running executable */ - retval = flush_old_exec(bprm); - if (retval) - goto out_free_dentry; - - /* OK, This is the point of no return */ - current->mm->end_data = 0; - current->mm->end_code = 0; - current->mm->mmap = NULL; - current->flags &= ~PF_FORKNOEXEC; - elf_entry = (unsigned int) elf_ex.e_entry; - - /* Do this so that we can load the interpreter, if need be. We will - * change some of these later. - */ - setup_arg_pages(bprm, STACK_TOP, EXSTACK_DEFAULT); - current->mm->start_stack = bprm->p; - - /* At this point, we assume that the image should be loaded at - * fixed address, not at a variable address. - */ - old_fs = get_fs(); - set_fs(get_ds()); - - map_executable(bprm->file, elf_phdata, elf_ex.e_phnum, &elf_stack, - &load_addr, &start_code, &elf_bss, &end_code, - &end_data, &elf_brk); - - if (elf_interpreter) { - retval = map_interpreter(elf_phdata, &interp_elf_ex, - interpreter, &interp_load_addr, - elf_ex.e_phnum, old_fs, &elf_entry); - kfree(elf_interpreter); - if (retval) { - set_fs(old_fs); - printk("Unable to load IRIX ELF interpreter\n"); - send_sig(SIGSEGV, current, 0); - retval = 0; - goto out_free_file; - } - } - - set_fs(old_fs); - - kfree(elf_phdata); - set_personality(PER_IRIX32); - set_binfmt(&irix_format); - compute_creds(bprm); - current->flags &= ~PF_FORKNOEXEC; - bprm->p = (unsigned long) - create_irix_tables((char *)bprm->p, bprm->argc, bprm->envc, - (elf_interpreter ? &elf_ex : NULL), - load_addr, interp_load_addr, regs, elf_ephdr); - current->mm->start_brk = current->mm->brk = elf_brk; - current->mm->end_code = end_code; - current->mm->start_code = start_code; - current->mm->end_data = end_data; - current->mm->start_stack = bprm->p; - - /* Calling set_brk effectively mmaps the pages that we need for the - * bss and break sections. - */ - set_brk(elf_bss, elf_brk); - - /* - * IRIX maps a page at 0x200000 which holds some system - * information. Programs depend on this. - */ - if (irix_map_prda_page()) - goto out_free_dentry; - - padzero(elf_bss); - - pr_debug("(start_brk) %lx\n" , (long) current->mm->start_brk); - pr_debug("(end_code) %lx\n" , (long) current->mm->end_code); - pr_debug("(start_code) %lx\n" , (long) current->mm->start_code); - pr_debug("(end_data) %lx\n" , (long) current->mm->end_data); - pr_debug("(start_stack) %lx\n" , (long) current->mm->start_stack); - pr_debug("(brk) %lx\n" , (long) current->mm->brk); - -#if 0 /* XXX No fucking way dude... */ - /* Why this, you ask??? Well SVr4 maps page 0 as read-only, - * and some applications "depend" upon this behavior. - * Since we do not have the power to recompile these, we - * emulate the SVr4 behavior. Sigh. - */ - down_write(¤t->mm->mmap_sem); - (void) do_mmap(NULL, 0, 4096, PROT_READ | PROT_EXEC, - MAP_FIXED | MAP_PRIVATE, 0); - up_write(¤t->mm->mmap_sem); -#endif - - start_thread(regs, elf_entry, bprm->p); - if (current->ptrace & PT_PTRACED) - send_sig(SIGTRAP, current, 0); - return 0; -out: - return retval; - -out_free_dentry: - allow_write_access(interpreter); - fput(interpreter); -out_free_interp: - kfree(elf_interpreter); -out_free_file: -out_free_ph: - kfree(elf_phdata); - goto out; -} - -/* This is really simpleminded and specialized - we are loading an - * a.out library that is given an ELF header. - */ -static int load_irix_library(struct file *file) -{ - struct elfhdr elf_ex; - struct elf_phdr *elf_phdata = NULL; - unsigned int len = 0; - int elf_bss = 0; - int retval; - unsigned int bss; - int error; - int i, j, k; - - error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex)); - if (error != sizeof(elf_ex)) - return -ENOEXEC; - - if (memcmp(elf_ex.e_ident, ELFMAG, SELFMAG) != 0) - return -ENOEXEC; - - /* First of all, some simple consistency checks. */ - if (elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 || - !file->f_op->mmap) - return -ENOEXEC; - - /* Now read in all of the header information. */ - if (sizeof(struct elf_phdr) * elf_ex.e_phnum > PAGE_SIZE) - return -ENOEXEC; - - elf_phdata = kmalloc(sizeof(struct elf_phdr) * elf_ex.e_phnum, GFP_KERNEL); - if (elf_phdata == NULL) - return -ENOMEM; - - retval = kernel_read(file, elf_ex.e_phoff, (char *) elf_phdata, - sizeof(struct elf_phdr) * elf_ex.e_phnum); - - j = 0; - for (i=0; ip_type == PT_LOAD) j++; - - if (j != 1) { - kfree(elf_phdata); - return -ENOEXEC; - } - - while (elf_phdata->p_type != PT_LOAD) elf_phdata++; - - /* Now use mmap to map the library into memory. */ - down_write(¤t->mm->mmap_sem); - error = do_mmap(file, - elf_phdata->p_vaddr & 0xfffff000, - elf_phdata->p_filesz + (elf_phdata->p_vaddr & 0xfff), - PROT_READ | PROT_WRITE | PROT_EXEC, - MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE, - elf_phdata->p_offset & 0xfffff000); - up_write(¤t->mm->mmap_sem); - - k = elf_phdata->p_vaddr + elf_phdata->p_filesz; - if (k > elf_bss) elf_bss = k; - - if (error != (elf_phdata->p_vaddr & 0xfffff000)) { - kfree(elf_phdata); - return error; - } - - padzero(elf_bss); - - len = (elf_phdata->p_filesz + elf_phdata->p_vaddr+ 0xfff) & 0xfffff000; - bss = elf_phdata->p_memsz + elf_phdata->p_vaddr; - if (bss > len) { - down_write(¤t->mm->mmap_sem); - do_brk(len, bss-len); - up_write(¤t->mm->mmap_sem); - } - kfree(elf_phdata); - return 0; -} - -/* Called through irix_syssgi() to map an elf image given an FD, - * a phdr ptr USER_PHDRP in userspace, and a count CNT telling how many - * phdrs there are in the USER_PHDRP array. We return the vaddr the - * first phdr was successfully mapped to. - */ -unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt) -{ - unsigned long type, vaddr, filesz, offset, flags; - struct elf_phdr __user *hp; - struct file *filp; - int i, retval; - - pr_debug("irix_mapelf: fd[%d] user_phdrp[%p] cnt[%d]\n", - fd, user_phdrp, cnt); - - /* First get the verification out of the way. */ - hp = user_phdrp; - if (!access_ok(VERIFY_READ, hp, (sizeof(struct elf_phdr) * cnt))) { - pr_debug("irix_mapelf: bad pointer to ELF PHDR!\n"); - - return -EFAULT; - } - - dump_phdrs(user_phdrp, cnt); - - for (i = 0; i < cnt; i++, hp++) { - if (__get_user(type, &hp->p_type)) - return -EFAULT; - if (type != PT_LOAD) { - printk("irix_mapelf: One section is not PT_LOAD!\n"); - return -ENOEXEC; - } - } - - filp = fget(fd); - if (!filp) - return -EACCES; - if (!filp->f_op) { - printk("irix_mapelf: Bogon filp!\n"); - fput(filp); - return -EACCES; - } - - hp = user_phdrp; - for (i = 0; i < cnt; i++, hp++) { - int prot; - - retval = __get_user(vaddr, &hp->p_vaddr); - retval |= __get_user(filesz, &hp->p_filesz); - retval |= __get_user(offset, &hp->p_offset); - retval |= __get_user(flags, &hp->p_flags); - if (retval) - return retval; - - prot = (flags & PF_R) ? PROT_READ : 0; - prot |= (flags & PF_W) ? PROT_WRITE : 0; - prot |= (flags & PF_X) ? PROT_EXEC : 0; - - down_write(¤t->mm->mmap_sem); - retval = do_mmap(filp, (vaddr & 0xfffff000), - (filesz + (vaddr & 0xfff)), - prot, (MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE), - (offset & 0xfffff000)); - up_write(¤t->mm->mmap_sem); - - if (retval != (vaddr & 0xfffff000)) { - printk("irix_mapelf: do_mmap fails with %d!\n", retval); - fput(filp); - return retval; - } - } - - pr_debug("irix_mapelf: Success, returning %08lx\n", - (unsigned long) user_phdrp->p_vaddr); - - fput(filp); - - if (__get_user(vaddr, &user_phdrp->p_vaddr)) - return -EFAULT; - - return vaddr; -} - -/* - * ELF core dumper - * - * Modelled on fs/exec.c:aout_core_dump() - * Jeremy Fitzhardinge - */ - -/* These are the only things you should do on a core-file: use only these - * functions to write out all the necessary info. - */ -static int dump_write(struct file *file, const void __user *addr, int nr) -{ - return file->f_op->write(file, (const char __user *) addr, nr, &file->f_pos) == nr; -} - -static int dump_seek(struct file *file, off_t off) -{ - if (file->f_op->llseek) { - if (file->f_op->llseek(file, off, 0) != off) - return 0; - } else - file->f_pos = off; - return 1; -} - -/* Decide whether a segment is worth dumping; default is yes to be - * sure (missing info is worse than too much; etc). - * Personally I'd include everything, and use the coredump limit... - * - * I think we should skip something. But I am not sure how. H.J. - */ -static inline int maydump(struct vm_area_struct *vma) -{ - if (!(vma->vm_flags & (VM_READ|VM_WRITE|VM_EXEC))) - return 0; -#if 1 - if (vma->vm_flags & (VM_WRITE|VM_GROWSUP|VM_GROWSDOWN)) - return 1; - if (vma->vm_flags & (VM_READ|VM_EXEC|VM_EXECUTABLE|VM_SHARED)) - return 0; -#endif - return 1; -} - -/* An ELF note in memory. */ -struct memelfnote -{ - const char *name; - int type; - unsigned int datasz; - void *data; -}; - -static int notesize(struct memelfnote *en) -{ - int sz; - - sz = sizeof(struct elf_note); - sz += roundup(strlen(en->name) + 1, 4); - sz += roundup(en->datasz, 4); - - return sz; -} - -#define DUMP_WRITE(addr, nr) \ - if (!dump_write(file, (addr), (nr))) \ - goto end_coredump; -#define DUMP_SEEK(off) \ - if (!dump_seek(file, (off))) \ - goto end_coredump; - -static int writenote(struct memelfnote *men, struct file *file) -{ - struct elf_note en; - - en.n_namesz = strlen(men->name) + 1; - en.n_descsz = men->datasz; - en.n_type = men->type; - - DUMP_WRITE(&en, sizeof(en)); - DUMP_WRITE(men->name, en.n_namesz); - /* XXX - cast from long long to long to avoid need for libgcc.a */ - DUMP_SEEK(roundup((unsigned long)file->f_pos, 4)); /* XXX */ - DUMP_WRITE(men->data, men->datasz); - DUMP_SEEK(roundup((unsigned long)file->f_pos, 4)); /* XXX */ - - return 1; - -end_coredump: - return 0; -} -#undef DUMP_WRITE -#undef DUMP_SEEK - -#define DUMP_WRITE(addr, nr) \ - if (!dump_write(file, (addr), (nr))) \ - goto end_coredump; -#define DUMP_SEEK(off) \ - if (!dump_seek(file, (off))) \ - goto end_coredump; - -/* Actual dumper. - * - * This is a two-pass process; first we find the offsets of the bits, - * and then they are actually written out. If we run out of core limit - * we just truncate. - */ -static int irix_core_dump(long signr, struct pt_regs *regs, struct file *file, unsigned long limit) -{ - int has_dumped = 0; - mm_segment_t fs; - int segs; - int i; - size_t size; - struct vm_area_struct *vma; - struct elfhdr elf; - off_t offset = 0, dataoff; - int numnote = 3; - struct memelfnote notes[3]; - struct elf_prstatus prstatus; /* NT_PRSTATUS */ - elf_fpregset_t fpu; /* NT_PRFPREG */ - struct elf_prpsinfo psinfo; /* NT_PRPSINFO */ - - /* Count what's needed to dump, up to the limit of coredump size. */ - segs = 0; - size = 0; - for (vma = current->mm->mmap; vma != NULL; vma = vma->vm_next) { - if (maydump(vma)) - { - int sz = vma->vm_end-vma->vm_start; - - if (size+sz >= limit) - break; - else - size += sz; - } - - segs++; - } - pr_debug("irix_core_dump: %d segs taking %d bytes\n", segs, size); - - /* Set up header. */ - memcpy(elf.e_ident, ELFMAG, SELFMAG); - elf.e_ident[EI_CLASS] = ELFCLASS32; - elf.e_ident[EI_DATA] = ELFDATA2LSB; - elf.e_ident[EI_VERSION] = EV_CURRENT; - elf.e_ident[EI_OSABI] = ELF_OSABI; - memset(elf.e_ident+EI_PAD, 0, EI_NIDENT-EI_PAD); - - elf.e_type = ET_CORE; - elf.e_machine = ELF_ARCH; - elf.e_version = EV_CURRENT; - elf.e_entry = 0; - elf.e_phoff = sizeof(elf); - elf.e_shoff = 0; - elf.e_flags = 0; - elf.e_ehsize = sizeof(elf); - elf.e_phentsize = sizeof(struct elf_phdr); - elf.e_phnum = segs+1; /* Include notes. */ - elf.e_shentsize = 0; - elf.e_shnum = 0; - elf.e_shstrndx = 0; - - fs = get_fs(); - set_fs(KERNEL_DS); - - has_dumped = 1; - current->flags |= PF_DUMPCORE; - - DUMP_WRITE(&elf, sizeof(elf)); - offset += sizeof(elf); /* Elf header. */ - offset += (segs+1) * sizeof(struct elf_phdr); /* Program headers. */ - - /* Set up the notes in similar form to SVR4 core dumps made - * with info from their /proc. - */ - memset(&psinfo, 0, sizeof(psinfo)); - memset(&prstatus, 0, sizeof(prstatus)); - - notes[0].name = "CORE"; - notes[0].type = NT_PRSTATUS; - notes[0].datasz = sizeof(prstatus); - notes[0].data = &prstatus; - prstatus.pr_info.si_signo = prstatus.pr_cursig = signr; - prstatus.pr_sigpend = current->pending.signal.sig[0]; - prstatus.pr_sighold = current->blocked.sig[0]; - psinfo.pr_pid = prstatus.pr_pid = task_pid_vnr(current); - psinfo.pr_ppid = prstatus.pr_ppid = task_pid_vnr(current->parent); - psinfo.pr_pgrp = prstatus.pr_pgrp = task_pgrp_vnr(current); - psinfo.pr_sid = prstatus.pr_sid = task_session_vnr(current); - if (thread_group_leader(current)) { - /* - * This is the record for the group leader. Add in the - * cumulative times of previous dead threads. This total - * won't include the time of each live thread whose state - * is included in the core dump. The final total reported - * to our parent process when it calls wait4 will include - * those sums as well as the little bit more time it takes - * this and each other thread to finish dying after the - * core dump synchronization phase. - */ - jiffies_to_timeval(current->utime + current->signal->utime, - &prstatus.pr_utime); - jiffies_to_timeval(current->stime + current->signal->stime, - &prstatus.pr_stime); - } else { - jiffies_to_timeval(current->utime, &prstatus.pr_utime); - jiffies_to_timeval(current->stime, &prstatus.pr_stime); - } - jiffies_to_timeval(current->signal->cutime, &prstatus.pr_cutime); - jiffies_to_timeval(current->signal->cstime, &prstatus.pr_cstime); - - if (sizeof(elf_gregset_t) != sizeof(struct pt_regs)) { - printk("sizeof(elf_gregset_t) (%d) != sizeof(struct pt_regs) " - "(%d)\n", sizeof(elf_gregset_t), sizeof(struct pt_regs)); - } else { - *(struct pt_regs *)&prstatus.pr_reg = *regs; - } - - notes[1].name = "CORE"; - notes[1].type = NT_PRPSINFO; - notes[1].datasz = sizeof(psinfo); - notes[1].data = &psinfo; - i = current->state ? ffz(~current->state) + 1 : 0; - psinfo.pr_state = i; - psinfo.pr_sname = (i < 0 || i > 5) ? '.' : "RSDZTD"[i]; - psinfo.pr_zomb = psinfo.pr_sname == 'Z'; - psinfo.pr_nice = task_nice(current); - psinfo.pr_flag = current->flags; - psinfo.pr_uid = current->uid; - psinfo.pr_gid = current->gid; - { - int i, len; - - set_fs(fs); - - len = current->mm->arg_end - current->mm->arg_start; - len = len >= ELF_PRARGSZ ? ELF_PRARGSZ : len; - (void *) copy_from_user(&psinfo.pr_psargs, - (const char __user *)current->mm->arg_start, len); - for (i = 0; i < len; i++) - if (psinfo.pr_psargs[i] == 0) - psinfo.pr_psargs[i] = ' '; - psinfo.pr_psargs[len] = 0; - - set_fs(KERNEL_DS); - } - strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname)); - - /* Try to dump the FPU. */ - prstatus.pr_fpvalid = dump_fpu(regs, &fpu); - if (!prstatus.pr_fpvalid) { - numnote--; - } else { - notes[2].name = "CORE"; - notes[2].type = NT_PRFPREG; - notes[2].datasz = sizeof(fpu); - notes[2].data = &fpu; - } - - /* Write notes phdr entry. */ - { - struct elf_phdr phdr; - int sz = 0; - - for (i = 0; i < numnote; i++) - sz += notesize(¬es[i]); - - phdr.p_type = PT_NOTE; - phdr.p_offset = offset; - phdr.p_vaddr = 0; - phdr.p_paddr = 0; - phdr.p_filesz = sz; - phdr.p_memsz = 0; - phdr.p_flags = 0; - phdr.p_align = 0; - - offset += phdr.p_filesz; - DUMP_WRITE(&phdr, sizeof(phdr)); - } - - /* Page-align dumped data. */ - dataoff = offset = roundup(offset, PAGE_SIZE); - - /* Write program headers for segments dump. */ - for (vma = current->mm->mmap, i = 0; - i < segs && vma != NULL; vma = vma->vm_next) { - struct elf_phdr phdr; - size_t sz; - - i++; - - sz = vma->vm_end - vma->vm_start; - - phdr.p_type = PT_LOAD; - phdr.p_offset = offset; - phdr.p_vaddr = vma->vm_start; - phdr.p_paddr = 0; - phdr.p_filesz = maydump(vma) ? sz : 0; - phdr.p_memsz = sz; - offset += phdr.p_filesz; - phdr.p_flags = vma->vm_flags & VM_READ ? PF_R : 0; - if (vma->vm_flags & VM_WRITE) - phdr.p_flags |= PF_W; - if (vma->vm_flags & VM_EXEC) - phdr.p_flags |= PF_X; - phdr.p_align = PAGE_SIZE; - - DUMP_WRITE(&phdr, sizeof(phdr)); - } - - for (i = 0; i < numnote; i++) - if (!writenote(¬es[i], file)) - goto end_coredump; - - set_fs(fs); - - DUMP_SEEK(dataoff); - - for (i = 0, vma = current->mm->mmap; - i < segs && vma != NULL; - vma = vma->vm_next) { - unsigned long addr = vma->vm_start; - unsigned long len = vma->vm_end - vma->vm_start; - - if (!maydump(vma)) - continue; - i++; - pr_debug("elf_core_dump: writing %08lx %lx\n", addr, len); - DUMP_WRITE((void __user *)addr, len); - } - - if ((off_t) file->f_pos != offset) { - /* Sanity check. */ - printk("elf_core_dump: file->f_pos (%ld) != offset (%ld)\n", - (off_t) file->f_pos, offset); - } - -end_coredump: - set_fs(fs); - return has_dumped; -} - -static int __init init_irix_binfmt(void) -{ - extern int init_inventory(void); - extern asmlinkage unsigned long sys_call_table; - extern asmlinkage unsigned long sys_call_table_irix5; - - init_inventory(); - - /* - * Copy the IRIX5 syscall table (8000 bytes) into the main syscall - * table. The IRIX5 calls are located by an offset of 8000 bytes - * from the beginning of the main table. - */ - memcpy((void *) ((unsigned long) &sys_call_table + 8000), - &sys_call_table_irix5, 8000); - - return register_binfmt(&irix_format); -} - -static void __exit exit_irix_binfmt(void) -{ - /* - * Remove the Irix ELF loader. - */ - unregister_binfmt(&irix_format); -} - -module_init(init_irix_binfmt) -module_exit(exit_irix_binfmt) diff --git a/arch/mips/kernel/irixinv.c b/arch/mips/kernel/irixinv.c deleted file mode 100644 index cf2dcd3d6a93..000000000000 --- a/arch/mips/kernel/irixinv.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Support the inventory interface for IRIX binaries - * This is invoked before the mm layer is working, so we do not - * use the linked lists for the inventory yet. - * - * Miguel de Icaza, 1997. - */ -#include -#include -#include - -#define MAX_INVENTORY 50 -int inventory_items = 0; - -static inventory_t inventory [MAX_INVENTORY]; - -void add_to_inventory(int class, int type, int controller, int unit, int state) -{ - inventory_t *ni = &inventory [inventory_items]; - - if (inventory_items == MAX_INVENTORY) - return; - - ni->inv_class = class; - ni->inv_type = type; - ni->inv_controller = controller; - ni->inv_unit = unit; - ni->inv_state = state; - ni->inv_next = ni; - inventory_items++; -} - -int dump_inventory_to_user(void __user *userbuf, int size) -{ - inventory_t *inv = &inventory [0]; - inventory_t __user *user = userbuf; - int v; - - if (!access_ok(VERIFY_WRITE, userbuf, size)) - return -EFAULT; - - for (v = 0; v < inventory_items; v++){ - inv = &inventory [v]; - if (copy_to_user (user, inv, sizeof (inventory_t))) - return -EFAULT; - user++; - } - return inventory_items * sizeof(inventory_t); -} - -int __init init_inventory(void) -{ - /* - * gross hack while we put the right bits all over the kernel - * most likely this will not let just anyone run the X server - * until we put the right values all over the place - */ - add_to_inventory(10, 3, 0, 0, 16400); - add_to_inventory(1, 1, 150, -1, 12); - add_to_inventory(1, 3, 0, 0, 8976); - add_to_inventory(1, 2, 0, 0, 8976); - add_to_inventory(4, 8, 0, 0, 2); - add_to_inventory(5, 5, 0, 0, 1); - add_to_inventory(3, 3, 0, 0, 32768); - add_to_inventory(3, 4, 0, 0, 32768); - add_to_inventory(3, 8, 0, 0, 524288); - add_to_inventory(3, 9, 0, 0, 64); - add_to_inventory(3, 1, 0, 0, 67108864); - add_to_inventory(12, 3, 0, 0, 16); - add_to_inventory(8, 7, 17, 0, 16777472); - add_to_inventory(8, 0, 0, 0, 1); - add_to_inventory(2, 1, 0, 13, 2); - add_to_inventory(2, 2, 0, 2, 0); - add_to_inventory(2, 2, 0, 1, 0); - add_to_inventory(7, 14, 0, 0, 6); - - return 0; -} diff --git a/arch/mips/kernel/irixioctl.c b/arch/mips/kernel/irixioctl.c deleted file mode 100644 index b39bdba82e02..000000000000 --- a/arch/mips/kernel/irixioctl.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * irixioctl.c: A fucking mess... - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#undef DEBUG_IOCTLS -#undef DEBUG_MISSING_IOCTL - -struct irix_termios { - tcflag_t c_iflag, c_oflag, c_cflag, c_lflag; - cc_t c_cc[NCCS]; -}; - -asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg) -{ - struct tty_struct *tp, *rtp; - mm_segment_t old_fs; - int i, error = 0; - -#ifdef DEBUG_IOCTLS - printk("[%s:%d] irix_ioctl(%d, ", current->comm, current->pid, fd); -#endif - switch(cmd) { - case 0x00005401: -#ifdef DEBUG_IOCTLS - printk("TCGETA, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TCGETA, arg); - break; - - case 0x0000540d: { - struct termios kt; - struct irix_termios __user *it = - (struct irix_termios __user *) arg; - -#ifdef DEBUG_IOCTLS - printk("TCGETS, %08lx) ", arg); -#endif - if (!access_ok(VERIFY_WRITE, it, sizeof(*it))) { - error = -EFAULT; - break; - } - old_fs = get_fs(); set_fs(get_ds()); - error = sys_ioctl(fd, TCGETS, (unsigned long) &kt); - set_fs(old_fs); - if (error) - break; - - error = __put_user(kt.c_iflag, &it->c_iflag); - error |= __put_user(kt.c_oflag, &it->c_oflag); - error |= __put_user(kt.c_cflag, &it->c_cflag); - error |= __put_user(kt.c_lflag, &it->c_lflag); - - for (i = 0; i < NCCS; i++) - error |= __put_user(kt.c_cc[i], &it->c_cc[i]); - break; - } - - case 0x0000540e: { - struct termios kt; - struct irix_termios *it = (struct irix_termios *) arg; - -#ifdef DEBUG_IOCTLS - printk("TCSETS, %08lx) ", arg); -#endif - if (!access_ok(VERIFY_READ, it, sizeof(*it))) { - error = -EFAULT; - break; - } - old_fs = get_fs(); set_fs(get_ds()); - error = sys_ioctl(fd, TCGETS, (unsigned long) &kt); - set_fs(old_fs); - if (error) - break; - - error = __get_user(kt.c_iflag, &it->c_iflag); - error |= __get_user(kt.c_oflag, &it->c_oflag); - error |= __get_user(kt.c_cflag, &it->c_cflag); - error |= __get_user(kt.c_lflag, &it->c_lflag); - - for (i = 0; i < NCCS; i++) - error |= __get_user(kt.c_cc[i], &it->c_cc[i]); - - if (error) - break; - old_fs = get_fs(); set_fs(get_ds()); - error = sys_ioctl(fd, TCSETS, (unsigned long) &kt); - set_fs(old_fs); - break; - } - - case 0x0000540f: -#ifdef DEBUG_IOCTLS - printk("TCSETSW, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TCSETSW, arg); - break; - - case 0x00005471: -#ifdef DEBUG_IOCTLS - printk("TIOCNOTTY, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TIOCNOTTY, arg); - break; - - case 0x00007416: { - pid_t pid; -#ifdef DEBUG_IOCTLS - printk("TIOCGSID, %08lx) ", arg); -#endif - old_fs = get_fs(); set_fs(get_ds()); - error = sys_ioctl(fd, TIOCGSID, (unsigned long)&pid); - set_fs(old_fs); - if (!error) - error = put_user(pid, (unsigned long __user *) arg); - break; - } - case 0x746e: - /* TIOCSTART, same effect as hitting ^Q */ -#ifdef DEBUG_IOCTLS - printk("TIOCSTART, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TCXONC, TCOON); - break; - - case 0x20006968: -#ifdef DEBUG_IOCTLS - printk("SIOCGETLABEL, %08lx) ", arg); -#endif - error = -ENOPKG; - break; - - case 0x40047477: -#ifdef DEBUG_IOCTLS - printk("TIOCGPGRP, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TIOCGPGRP, arg); -#ifdef DEBUG_IOCTLS - printk("arg=%d ", *(int *)arg); -#endif - break; - - case 0x40087468: -#ifdef DEBUG_IOCTLS - printk("TIOCGWINSZ, %08lx) ", arg); -#endif - error = sys_ioctl(fd, TIOCGWINSZ, arg); - break; - - case 0x8004667e: - error = sys_ioctl(fd, FIONBIO, arg); - break; - - case 0x80047476: - error = sys_ioctl(fd, TIOCSPGRP, arg); - break; - - case 0x8020690c: - error = sys_ioctl(fd, SIOCSIFADDR, arg); - break; - - case 0x80206910: - error = sys_ioctl(fd, SIOCSIFFLAGS, arg); - break; - - case 0xc0206911: - error = sys_ioctl(fd, SIOCGIFFLAGS, arg); - break; - - case 0xc020691b: - error = sys_ioctl(fd, SIOCGIFMETRIC, arg); - break; - - default: { -#ifdef DEBUG_MISSING_IOCTL - char *msg = "Unimplemented IOCTL cmd tell linux-mips@linux-mips.org\n"; - -#ifdef DEBUG_IOCTLS - printk("UNIMP_IOCTL, %08lx)\n", arg); -#endif - old_fs = get_fs(); set_fs(get_ds()); - sys_write(2, msg, strlen(msg)); - set_fs(old_fs); - printk("[%s:%d] Does unimplemented IRIX ioctl cmd %08lx\n", - current->comm, current->pid, cmd); - do_exit(255); -#else - error = sys_ioctl(fd, cmd, arg); -#endif - } - - }; -#ifdef DEBUG_IOCTLS - printk("error=%d\n", error); -#endif - return error; -} diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c deleted file mode 100644 index 0215c805a592..000000000000 --- a/arch/mips/kernel/irixsig.c +++ /dev/null @@ -1,888 +0,0 @@ -/* - * irixsig.c: WHEEE, IRIX signals! YOW, am I compatible or what?!?! - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997 - 2000 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2000 Silicon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#undef DEBUG_SIG - -#define _S(nr) (1<<((nr)-1)) - -#define _BLOCKABLE (~(_S(SIGKILL) | _S(SIGSTOP))) - -#define _IRIX_NSIG 128 -#define _IRIX_NSIG_BPW BITS_PER_LONG -#define _IRIX_NSIG_WORDS (_IRIX_NSIG / _IRIX_NSIG_BPW) - -typedef struct { - unsigned long sig[_IRIX_NSIG_WORDS]; -} irix_sigset_t; - -struct sigctx_irix5 { - u32 rmask, cp0_status; - u64 pc; - u64 regs[32]; - u64 fpregs[32]; - u32 usedfp, fpcsr, fpeir, sstk_flags; - u64 hi, lo; - u64 cp0_cause, cp0_badvaddr, _unused0; - irix_sigset_t sigset; - u64 weird_fpu_thing; - u64 _unused1[31]; -}; - -#ifdef DEBUG_SIG -/* Debugging */ -static inline void dump_irix5_sigctx(struct sigctx_irix5 *c) -{ - int i; - - printk("misc: rmask[%08lx] status[%08lx] pc[%08lx]\n", - (unsigned long) c->rmask, - (unsigned long) c->cp0_status, - (unsigned long) c->pc); - printk("regs: "); - for(i = 0; i < 16; i++) - printk("[%d]<%08lx> ", i, (unsigned long) c->regs[i]); - printk("\nregs: "); - for(i = 16; i < 32; i++) - printk("[%d]<%08lx> ", i, (unsigned long) c->regs[i]); - printk("\nfpregs: "); - for(i = 0; i < 16; i++) - printk("[%d]<%08lx> ", i, (unsigned long) c->fpregs[i]); - printk("\nfpregs: "); - for(i = 16; i < 32; i++) - printk("[%d]<%08lx> ", i, (unsigned long) c->fpregs[i]); - printk("misc: usedfp[%d] fpcsr[%08lx] fpeir[%08lx] stk_flgs[%08lx]\n", - (int) c->usedfp, (unsigned long) c->fpcsr, - (unsigned long) c->fpeir, (unsigned long) c->sstk_flags); - printk("misc: hi[%08lx] lo[%08lx] cause[%08lx] badvaddr[%08lx]\n", - (unsigned long) c->hi, (unsigned long) c->lo, - (unsigned long) c->cp0_cause, (unsigned long) c->cp0_badvaddr); - printk("misc: sigset<0>[%08lx] sigset<1>[%08lx] sigset<2>[%08lx] " - "sigset<3>[%08lx]\n", (unsigned long) c->sigset.sig[0], - (unsigned long) c->sigset.sig[1], - (unsigned long) c->sigset.sig[2], - (unsigned long) c->sigset.sig[3]); -} -#endif - -static int setup_irix_frame(struct k_sigaction *ka, struct pt_regs *regs, - int signr, sigset_t *oldmask) -{ - struct sigctx_irix5 __user *ctx; - unsigned long sp; - int error, i; - - sp = regs->regs[29]; - sp -= sizeof(struct sigctx_irix5); - sp &= ~(0xf); - ctx = (struct sigctx_irix5 __user *) sp; - if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) - goto segv_and_exit; - - error = __put_user(0, &ctx->weird_fpu_thing); - error |= __put_user(~(0x00000001), &ctx->rmask); - error |= __put_user(0, &ctx->regs[0]); - for(i = 1; i < 32; i++) - error |= __put_user((u64) regs->regs[i], &ctx->regs[i]); - - error |= __put_user((u64) regs->hi, &ctx->hi); - error |= __put_user((u64) regs->lo, &ctx->lo); - error |= __put_user((u64) regs->cp0_epc, &ctx->pc); - error |= __put_user(!!used_math(), &ctx->usedfp); - error |= __put_user((u64) regs->cp0_cause, &ctx->cp0_cause); - error |= __put_user((u64) regs->cp0_badvaddr, &ctx->cp0_badvaddr); - - error |= __put_user(0, &ctx->sstk_flags); /* XXX sigstack unimp... todo... */ - - error |= __copy_to_user(&ctx->sigset, oldmask, sizeof(irix_sigset_t)) ? -EFAULT : 0; - - if (error) - goto segv_and_exit; - -#ifdef DEBUG_SIG - dump_irix5_sigctx(ctx); -#endif - - regs->regs[4] = (unsigned long) signr; - regs->regs[5] = 0; /* XXX sigcode XXX */ - regs->regs[6] = regs->regs[29] = sp; - regs->regs[7] = (unsigned long) ka->sa.sa_handler; - regs->regs[25] = regs->cp0_epc = (unsigned long) ka->sa_restorer; - - return 1; - -segv_and_exit: - force_sigsegv(signr, current); - return 0; -} - -static int inline -setup_irix_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *oldmask, siginfo_t *info) -{ - printk("Aiee: setup_tr_frame wants to be written"); - do_exit(SIGSEGV); -} - -static inline int handle_signal(unsigned long sig, siginfo_t *info, - struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs) -{ - int ret; - - switch(regs->regs[0]) { - case ERESTARTNOHAND: - regs->regs[2] = EINTR; - break; - case ERESTARTSYS: - if(!(ka->sa.sa_flags & SA_RESTART)) { - regs->regs[2] = EINTR; - break; - } - /* fallthrough */ - case ERESTARTNOINTR: /* Userland will reload $v0. */ - regs->cp0_epc -= 8; - } - - regs->regs[0] = 0; /* Don't deal with this again. */ - - if (ka->sa.sa_flags & SA_SIGINFO) - ret = setup_irix_rt_frame(ka, regs, sig, oldset, info); - else - ret = setup_irix_frame(ka, regs, sig, oldset); - - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked, sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - return ret; -} - -void do_irix_signal(struct pt_regs *regs) -{ - struct k_sigaction ka; - siginfo_t info; - int signr; - sigset_t *oldset; - - /* - * We want the common case to go fast, which is why we may in certain - * cases get here from kernel mode. Just return without doing anything - * if so. - */ - if (!user_mode(regs)) - return; - - if (test_thread_flag(TIF_RESTORE_SIGMASK)) - oldset = ¤t->saved_sigmask; - else - oldset = ¤t->blocked; - - signr = get_signal_to_deliver(&info, &ka, regs, NULL); - if (signr > 0) { - /* Whee! Actually deliver the signal. */ - if (handle_signal(signr, &info, &ka, oldset, regs) == 0) { - /* a signal was successfully delivered; the saved - * sigmask will have been stored in the signal frame, - * and will be restored by sigreturn, so we can simply - * clear the TIF_RESTORE_SIGMASK flag */ - if (test_thread_flag(TIF_RESTORE_SIGMASK)) - clear_thread_flag(TIF_RESTORE_SIGMASK); - } - - return; - } - - /* - * Who's code doesn't conform to the restartable syscall convention - * dies here!!! The li instruction, a single machine instruction, - * must directly be followed by the syscall instruction. - */ - if (regs->regs[0]) { - if (regs->regs[2] == ERESTARTNOHAND || - regs->regs[2] == ERESTARTSYS || - regs->regs[2] == ERESTARTNOINTR) { - regs->cp0_epc -= 8; - } - if (regs->regs[2] == ERESTART_RESTARTBLOCK) { - regs->regs[2] = __NR_restart_syscall; - regs->regs[7] = regs->regs[26]; - regs->cp0_epc -= 4; - } - regs->regs[0] = 0; /* Don't deal with this again. */ - } - - /* - * If there's no signal to deliver, we just put the saved sigmask - * back - */ - if (test_thread_flag(TIF_RESTORE_SIGMASK)) { - clear_thread_flag(TIF_RESTORE_SIGMASK); - sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); - } -} - -asmlinkage void -irix_sigreturn(struct pt_regs *regs) -{ - struct sigctx_irix5 __user *context, *magic; - unsigned long umask, mask; - u64 *fregs; - u32 usedfp; - int error, sig, i, base = 0; - sigset_t blocked; - - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - if (regs->regs[2] == 1000) - base = 1; - - context = (struct sigctx_irix5 __user *) regs->regs[base + 4]; - magic = (struct sigctx_irix5 __user *) regs->regs[base + 5]; - sig = (int) regs->regs[base + 6]; -#ifdef DEBUG_SIG - printk("[%s:%d] IRIX sigreturn(scp[%p],ucp[%p],sig[%d])\n", - current->comm, current->pid, context, magic, sig); -#endif - if (!context) - context = magic; - if (!access_ok(VERIFY_READ, context, sizeof(struct sigctx_irix5))) - goto badframe; - -#ifdef DEBUG_SIG - dump_irix5_sigctx(context); -#endif - - error = __get_user(regs->cp0_epc, &context->pc); - error |= __get_user(umask, &context->rmask); - - mask = 2; - for (i = 1; i < 32; i++, mask <<= 1) { - if (umask & mask) - error |= __get_user(regs->regs[i], &context->regs[i]); - } - error |= __get_user(regs->hi, &context->hi); - error |= __get_user(regs->lo, &context->lo); - - error |= __get_user(usedfp, &context->usedfp); - if ((umask & 1) && usedfp) { - fregs = (u64 *) ¤t->thread.fpu; - - for(i = 0; i < 32; i++) - error |= __get_user(fregs[i], &context->fpregs[i]); - error |= __get_user(current->thread.fpu.fcr31, &context->fpcsr); - } - - /* XXX do sigstack crapola here... XXX */ - - error |= __copy_from_user(&blocked, &context->sigset, sizeof(blocked)) ? -EFAULT : 0; - - if (error) - goto badframe; - - sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - /* - * Don't let your children do this ... - */ - __asm__ __volatile__( - "move\t$29,%0\n\t" - "j\tsyscall_exit" - :/* no outputs */ - :"r" (®s)); - /* Unreached */ - -badframe: - force_sig(SIGSEGV, current); -} - -struct sigact_irix5 { - int flags; - void (*handler)(int); - u32 sigset[4]; - int _unused0[2]; -}; - -#define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: - set only the low 32 bit of the sigset. */ - -#ifdef DEBUG_SIG -static inline void dump_sigact_irix5(struct sigact_irix5 *p) -{ - printk("", p->flags, - (unsigned long) p->handler, - (unsigned long) p->sigset[0]); -} -#endif - -asmlinkage int -irix_sigaction(int sig, const struct sigaction __user *act, - struct sigaction __user *oact, void __user *trampoline) -{ - struct k_sigaction new_ka, old_ka; - int ret; - -#ifdef DEBUG_SIG - printk(" (%d,%s,%s,%08lx) ", sig, (!new ? "0" : "NEW"), - (!old ? "0" : "OLD"), trampoline); - if(new) { - dump_sigact_irix5(new); printk(" "); - } -#endif - if (act) { - sigset_t mask; - int err; - - if (!access_ok(VERIFY_READ, act, sizeof(*act))) - return -EFAULT; - err = __get_user(new_ka.sa.sa_handler, &act->sa_handler); - err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); - - err |= __copy_from_user(&mask, &act->sa_mask, sizeof(sigset_t)) ? -EFAULT : 0; - if (err) - return err; - - /* - * Hmmm... methinks IRIX libc always passes a valid trampoline - * value for all invocations of sigaction. Will have to - * investigate. POSIX POSIX, die die die... - */ - new_ka.sa_restorer = trampoline; - } - -/* XXX Implement SIG_SETMASK32 for IRIX compatibility */ - ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); - - if (!ret && oact) { - int err; - - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact))) - return -EFAULT; - - err = __put_user(old_ka.sa.sa_handler, &oact->sa_handler); - err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); - err |= __copy_to_user(&oact->sa_mask, &old_ka.sa.sa_mask, - sizeof(sigset_t)) ? -EFAULT : 0; - if (err) - return -EFAULT; - } - - return ret; -} - -asmlinkage int irix_sigpending(irix_sigset_t __user *set) -{ - return do_sigpending(set, sizeof(*set)); -} - -asmlinkage int irix_sigprocmask(int how, irix_sigset_t __user *new, - irix_sigset_t __user *old) -{ - sigset_t oldbits, newbits; - - if (new) { - if (!access_ok(VERIFY_READ, new, sizeof(*new))) - return -EFAULT; - if (__copy_from_user(&newbits, new, sizeof(unsigned long)*4)) - return -EFAULT; - sigdelsetmask(&newbits, ~_BLOCKABLE); - - spin_lock_irq(¤t->sighand->siglock); - oldbits = current->blocked; - - switch(how) { - case 1: - sigorsets(&newbits, &oldbits, &newbits); - break; - - case 2: - sigandsets(&newbits, &oldbits, &newbits); - break; - - case 3: - break; - - case 256: - siginitset(&newbits, newbits.sig[0]); - break; - - default: - spin_unlock_irq(¤t->sighand->siglock); - return -EINVAL; - } - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - } - if (old) - return copy_to_user(old, ¤t->blocked, - sizeof(unsigned long)*4) ? -EFAULT : 0; - - return 0; -} - -asmlinkage int irix_sigsuspend(struct pt_regs *regs) -{ - sigset_t newset; - sigset_t __user *uset; - - uset = (sigset_t __user *) regs->regs[4]; - if (copy_from_user(&newset, uset, sizeof(sigset_t))) - return -EFAULT; - sigdelsetmask(&newset, ~_BLOCKABLE); - - spin_lock_irq(¤t->sighand->siglock); - current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); - - current->state = TASK_INTERRUPTIBLE; - schedule(); - set_thread_flag(TIF_RESTORE_SIGMASK); - return -ERESTARTNOHAND; -} - -/* hate hate hate... */ -struct irix5_siginfo { - int sig, code, error; - union { - char unused[128 - (3 * 4)]; /* Safety net. */ - struct { - int pid; - union { - int uid; - struct { - int utime, status, stime; - } child; - } procdata; - } procinfo; - - unsigned long fault_addr; - - struct { - int fd; - long band; - } fileinfo; - - unsigned long sigval; - } stuff; -}; - -asmlinkage int irix_sigpoll_sys(unsigned long __user *set, - struct irix5_siginfo __user *info, struct timespec __user *tp) -{ - long expire = MAX_SCHEDULE_TIMEOUT; - sigset_t kset; - int i, sig, error, timeo = 0; - struct timespec ktp; - -#ifdef DEBUG_SIG - printk("[%s:%d] irix_sigpoll_sys(%p,%p,%p)\n", - current->comm, current->pid, set, info, tp); -#endif - - /* Must always specify the signal set. */ - if (!set) - return -EINVAL; - - if (copy_from_user(&kset, set, sizeof(set))) - return -EFAULT; - - if (info && clear_user(info, sizeof(*info))) { - error = -EFAULT; - goto out; - } - - if (tp) { - if (copy_from_user(&ktp, tp, sizeof(*tp))) - return -EFAULT; - - if (!ktp.tv_sec && !ktp.tv_nsec) - return -EINVAL; - - expire = timespec_to_jiffies(&ktp) + - (ktp.tv_sec || ktp.tv_nsec); - } - - while(1) { - long tmp = 0; - - expire = schedule_timeout_interruptible(expire); - - for (i=0; i < _IRIX_NSIG_WORDS; i++) - tmp |= (current->pending.signal.sig[i] & kset.sig[i]); - - if (tmp) - break; - if (!expire) { - timeo = 1; - break; - } - if (signal_pending(current)) - return -EINTR; - } - if (timeo) - return -EAGAIN; - - for (sig = 1; i <= 65 /* IRIX_NSIG */; sig++) { - if (sigismember (&kset, sig)) - continue; - if (sigismember (¤t->pending.signal, sig)) { - /* XXX need more than this... */ - if (info) - return copy_to_user(&info->sig, &sig, sizeof(sig)); - return 0; - } - } - - /* Should not get here, but do something sane if we do. */ - error = -EINTR; - -out: - return error; -} - -/* This is here because of irix5_siginfo definition. */ -#define IRIX_P_PID 0 -#define IRIX_P_PGID 2 -#define IRIX_P_ALL 7 - -#define W_EXITED 1 -#define W_TRAPPED 2 -#define W_STOPPED 4 -#define W_CONT 8 -#define W_NOHANG 64 - -#define W_MASK (W_EXITED | W_TRAPPED | W_STOPPED | W_CONT | W_NOHANG) - -asmlinkage int irix_waitsys(int type, int upid, - struct irix5_siginfo __user *info, int options, - struct rusage __user *ru) -{ - struct pid *pid = NULL; - int flag, retval; - DECLARE_WAITQUEUE(wait, current); - struct task_struct *tsk; - struct task_struct *p; - struct list_head *_p; - - if (!info) - return -EINVAL; - - if (!access_ok(VERIFY_WRITE, info, sizeof(*info))) - return -EFAULT; - - if (ru) - if (!access_ok(VERIFY_WRITE, ru, sizeof(*ru))) - return -EFAULT; - - if (options & ~W_MASK) - return -EINVAL; - - if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL) - return -EINVAL; - - if (type != IRIX_P_ALL) - pid = find_get_pid(upid); - add_wait_queue(¤t->signal->wait_chldexit, &wait); -repeat: - flag = 0; - current->state = TASK_INTERRUPTIBLE; - read_lock(&tasklist_lock); - tsk = current; - list_for_each(_p, &tsk->children) { - p = list_entry(_p, struct task_struct, sibling); - if ((type == IRIX_P_PID) && task_pid(p) != pid) - continue; - if ((type == IRIX_P_PGID) && task_pgrp(p) != pid) - continue; - if ((p->exit_signal != SIGCHLD)) - continue; - flag = 1; - switch (p->state) { - case TASK_STOPPED: - if (!p->exit_code) - continue; - if (!(options & (W_TRAPPED|W_STOPPED)) && - !(p->ptrace & PT_PTRACED)) - continue; - read_unlock(&tasklist_lock); - - /* move to end of parent's list to avoid starvation */ - write_lock_irq(&tasklist_lock); - remove_parent(p); - add_parent(p); - write_unlock_irq(&tasklist_lock); - retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0; - if (retval) - goto end_waitsys; - - retval = __put_user(SIGCHLD, &info->sig); - retval |= __put_user(0, &info->code); - retval |= __put_user(task_pid_vnr(p), &info->stuff.procinfo.pid); - retval |= __put_user((p->exit_code >> 8) & 0xff, - &info->stuff.procinfo.procdata.child.status); - retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); - retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); - if (retval) - goto end_waitsys; - - p->exit_code = 0; - goto end_waitsys; - - case EXIT_ZOMBIE: - current->signal->cutime += p->utime + p->signal->cutime; - current->signal->cstime += p->stime + p->signal->cstime; - if (ru != NULL) - getrusage(p, RUSAGE_BOTH, ru); - retval = __put_user(SIGCHLD, &info->sig); - retval |= __put_user(1, &info->code); /* CLD_EXITED */ - retval |= __put_user(task_pid_vnr(p), &info->stuff.procinfo.pid); - retval |= __put_user((p->exit_code >> 8) & 0xff, - &info->stuff.procinfo.procdata.child.status); - retval |= __put_user(p->utime, - &info->stuff.procinfo.procdata.child.utime); - retval |= __put_user(p->stime, - &info->stuff.procinfo.procdata.child.stime); - if (retval) - goto end_waitsys; - - if (p->real_parent != p->parent) { - write_lock_irq(&tasklist_lock); - remove_parent(p); - p->parent = p->real_parent; - add_parent(p); - do_notify_parent(p, SIGCHLD); - write_unlock_irq(&tasklist_lock); - } else - release_task(p); - goto end_waitsys; - default: - continue; - } - tsk = next_thread(tsk); - } - read_unlock(&tasklist_lock); - if (flag) { - retval = 0; - if (options & W_NOHANG) - goto end_waitsys; - retval = -ERESTARTSYS; - if (signal_pending(current)) - goto end_waitsys; - current->state = TASK_INTERRUPTIBLE; - schedule(); - goto repeat; - } - retval = -ECHILD; -end_waitsys: - current->state = TASK_RUNNING; - remove_wait_queue(¤t->signal->wait_chldexit, &wait); - put_pid(pid); - - return retval; -} - -struct irix5_context { - u32 flags; - u32 link; - u32 sigmask[4]; - struct { u32 sp, size, flags; } stack; - int regs[36]; - u32 fpregs[32]; - u32 fpcsr; - u32 _unused0; - u32 _unused1[47]; - u32 weird_graphics_thing; -}; - -asmlinkage int irix_getcontext(struct pt_regs *regs) -{ - int error, i, base = 0; - struct irix5_context __user *ctx; - unsigned long flags; - - if (regs->regs[2] == 1000) - base = 1; - ctx = (struct irix5_context __user *) regs->regs[base + 4]; - -#ifdef DEBUG_SIG - printk("[%s:%d] irix_getcontext(%p)\n", - current->comm, current->pid, ctx); -#endif - - if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx))) - return -EFAULT; - - error = __put_user(current->thread.irix_oldctx, &ctx->link); - - error |= __copy_to_user(&ctx->sigmask, ¤t->blocked, sizeof(irix_sigset_t)) ? -EFAULT : 0; - - /* XXX Do sigstack stuff someday... */ - error |= __put_user(0, &ctx->stack.sp); - error |= __put_user(0, &ctx->stack.size); - error |= __put_user(0, &ctx->stack.flags); - - error |= __put_user(0, &ctx->weird_graphics_thing); - error |= __put_user(0, &ctx->regs[0]); - for (i = 1; i < 32; i++) - error |= __put_user(regs->regs[i], &ctx->regs[i]); - error |= __put_user(regs->lo, &ctx->regs[32]); - error |= __put_user(regs->hi, &ctx->regs[33]); - error |= __put_user(regs->cp0_cause, &ctx->regs[34]); - error |= __put_user(regs->cp0_epc, &ctx->regs[35]); - - flags = 0x0f; - if (!used_math()) { - flags &= ~(0x08); - } else { - /* XXX wheee... */ - printk("Wheee, no code for saving IRIX FPU context yet.\n"); - } - error |= __put_user(flags, &ctx->flags); - - return error; -} - -asmlinkage void irix_setcontext(struct pt_regs *regs) -{ - struct irix5_context __user *ctx; - int err, base = 0; - u32 flags; - - if (regs->regs[2] == 1000) - base = 1; - ctx = (struct irix5_context __user *) regs->regs[base + 4]; - -#ifdef DEBUG_SIG - printk("[%s:%d] irix_setcontext(%p)\n", - current->comm, current->pid, ctx); -#endif - - if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))) - goto segv_and_exit; - - err = __get_user(flags, &ctx->flags); - if (flags & 0x02) { - /* XXX sigstack garbage, todo... */ - printk("Wheee, cannot do sigstack stuff in setcontext\n"); - } - - if (flags & 0x04) { - int i; - - /* XXX extra control block stuff... todo... */ - for (i = 1; i < 32; i++) - err |= __get_user(regs->regs[i], &ctx->regs[i]); - err |= __get_user(regs->lo, &ctx->regs[32]); - err |= __get_user(regs->hi, &ctx->regs[33]); - err |= __get_user(regs->cp0_epc, &ctx->regs[35]); - } - - if (flags & 0x08) - /* XXX fpu context, blah... */ - printk(KERN_ERR "Wheee, cannot restore FPU context yet...\n"); - - err |= __get_user(current->thread.irix_oldctx, &ctx->link); - if (err) - goto segv_and_exit; - - /* - * Don't let your children do this ... - */ - __asm__ __volatile__( - "move\t$29,%0\n\t" - "j\tsyscall_exit" - :/* no outputs */ - :"r" (®s)); - /* Unreached */ - -segv_and_exit: - force_sigsegv(SIGSEGV, current); -} - -struct irix_sigstack { - unsigned long sp; - int status; -}; - -asmlinkage int irix_sigstack(struct irix_sigstack __user *new, - struct irix_sigstack __user *old) -{ -#ifdef DEBUG_SIG - printk("[%s:%d] irix_sigstack(%p,%p)\n", - current->comm, current->pid, new, old); -#endif - if (new) { - if (!access_ok(VERIFY_READ, new, sizeof(*new))) - return -EFAULT; - } - - if (old) { - if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - return -EFAULT; - } - - return 0; -} - -struct irix_sigaltstack { unsigned long sp; int size; int status; }; - -asmlinkage int irix_sigaltstack(struct irix_sigaltstack __user *new, - struct irix_sigaltstack __user *old) -{ -#ifdef DEBUG_SIG - printk("[%s:%d] irix_sigaltstack(%p,%p)\n", - current->comm, current->pid, new, old); -#endif - if (new) - if (!access_ok(VERIFY_READ, new, sizeof(*new))) - return -EFAULT; - - if (old) { - if (!access_ok(VERIFY_WRITE, old, sizeof(*old))) - return -EFAULT; - } - - return 0; -} - -struct irix_procset { - int cmd, ltype, lid, rtype, rid; -}; - -asmlinkage int irix_sigsendset(struct irix_procset __user *pset, int sig) -{ - if (!access_ok(VERIFY_READ, pset, sizeof(*pset))) - return -EFAULT; -#ifdef DEBUG_SIG - printk("[%s:%d] irix_sigsendset([%d,%d,%d,%d,%d],%d)\n", - current->comm, current->pid, - pset->cmd, pset->ltype, pset->lid, pset->rtype, pset->rid, - sig); -#endif - return -EINVAL; -} diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 2c09a442e5e5..c06f5b5d764c 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -125,13 +125,6 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, *childregs = *regs; childregs->regs[7] = 0; /* Clear error flag */ -#if defined(CONFIG_BINFMT_IRIX) - if (current->personality != PER_LINUX) { - /* Under IRIX things are a little different. */ - childregs->regs[3] = 1; - regs->regs[3] = 0; - } -#endif childregs->regs[2] = 0; /* Child gets zero as return value */ regs->regs[2] = p->pid; diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 08a9c5070ea8..c058c0b61a2a 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -34,12 +34,8 @@ NESTED(handle_sys, PT_SIZE, sp) lw t1, PT_EPC(sp) # skip syscall on return -#if defined(CONFIG_BINFMT_IRIX) - sltiu t0, v0, MAX_SYSCALL_NO + 1 # check syscall number -#else subu v0, v0, __NR_O32_Linux # check syscall number sltiu t0, v0, __NR_O32_Linux_syscalls + 1 -#endif addiu t1, 4 # skip to next instruction sw t1, PT_EPC(sp) beqz t0, illegal_syscall @@ -264,22 +260,14 @@ bad_alignment: END(sys_sysmips) LEAF(sys_syscall) -#if defined(CONFIG_BINFMT_IRIX) - sltiu v0, a0, MAX_SYSCALL_NO + 1 # check syscall number -#else subu t0, a0, __NR_O32_Linux # check syscall number sltiu v0, t0, __NR_O32_Linux_syscalls + 1 -#endif sll t1, t0, 3 beqz v0, einval lw t2, sys_call_table(t1) # syscall routine -#if defined(CONFIG_BINFMT_IRIX) - li v1, 4000 # nr of sys_syscall -#else li v1, 4000 - __NR_O32_Linux # index of sys_syscall -#endif beq t0, v1, einval # do not recurse /* Some syscalls like execve get their arguments from struct pt_regs @@ -324,13 +312,6 @@ einval: li v0, -EINVAL .endm .macro syscalltable -#if defined(CONFIG_BINFMT_IRIX) - mille sys_ni_syscall 0 /* 0 - 999 SVR4 flavour */ - mille sys_ni_syscall 0 /* 1000 - 1999 32-bit IRIX */ - mille sys_ni_syscall 0 /* 2000 - 2999 BSD43 flavour */ - mille sys_ni_syscall 0 /* 3000 - 3999 POSIX flavour */ -#endif - sys sys_syscall 8 /* 4000 */ sys sys_exit 1 sys sys_fork 0 diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c deleted file mode 100644 index c357762b8012..000000000000 --- a/arch/mips/kernel/sysirix.c +++ /dev/null @@ -1,2140 +0,0 @@ -/* - * sysirix.c: IRIX system call emulation. - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1997 Miguel de Icaza - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* 2,191 lines of complete and utter shit coming up... */ - -extern int max_threads; - -/* The sysmp commands supported thus far. */ -#define MP_NPROCS 1 /* # processor in complex */ -#define MP_NAPROCS 2 /* # active processors in complex */ -#define MP_PGSIZE 14 /* Return system page size in v1. */ - -asmlinkage int irix_sysmp(struct pt_regs *regs) -{ - unsigned long cmd; - int base = 0; - int error = 0; - - if(regs->regs[2] == 1000) - base = 1; - cmd = regs->regs[base + 4]; - switch(cmd) { - case MP_PGSIZE: - error = PAGE_SIZE; - break; - case MP_NPROCS: - case MP_NAPROCS: - error = num_online_cpus(); - break; - default: - printk("SYSMP[%s:%d]: Unsupported opcode %d\n", - current->comm, current->pid, (int)cmd); - error = -EINVAL; - break; - } - - return error; -} - -/* The prctl commands. */ -#define PR_MAXPROCS 1 /* Tasks/user. */ -#define PR_ISBLOCKED 2 /* If blocked, return 1. */ -#define PR_SETSTACKSIZE 3 /* Set largest task stack size. */ -#define PR_GETSTACKSIZE 4 /* Get largest task stack size. */ -#define PR_MAXPPROCS 5 /* Num parallel tasks. */ -#define PR_UNBLKONEXEC 6 /* When task exec/exit's, unblock. */ -#define PR_SETEXITSIG 8 /* When task exit's, set signal. */ -#define PR_RESIDENT 9 /* Make task unswappable. */ -#define PR_ATTACHADDR 10 /* (Re-)Connect a vma to a task. */ -#define PR_DETACHADDR 11 /* Disconnect a vma from a task. */ -#define PR_TERMCHILD 12 /* Kill child if the parent dies. */ -#define PR_GETSHMASK 13 /* Get the sproc() share mask. */ -#define PR_GETNSHARE 14 /* Number of share group members. */ -#define PR_COREPID 15 /* Add task pid to name when it core. */ -#define PR_ATTACHADDRPERM 16 /* (Re-)Connect vma, with specified prot. */ -#define PR_PTHREADEXIT 17 /* Kill a pthread, only for IRIX 6.[234] */ - -asmlinkage int irix_prctl(unsigned option, ...) -{ - va_list args; - int error = 0; - - va_start(args, option); - switch (option) { - case PR_MAXPROCS: - printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n", - current->comm, current->pid); - error = max_threads; - break; - - case PR_ISBLOCKED: { - struct task_struct *task; - - printk("irix_prctl[%s:%d]: Wants PR_ISBLOCKED\n", - current->comm, current->pid); - read_lock(&tasklist_lock); - task = find_task_by_vpid(va_arg(args, pid_t)); - error = -ESRCH; - if (error) - error = (task->run_list.next != NULL); - read_unlock(&tasklist_lock); - /* Can _your_ OS find this out that fast? */ - break; - } - - case PR_SETSTACKSIZE: { - long value = va_arg(args, long); - - printk("irix_prctl[%s:%d]: Wants PR_SETSTACKSIZE<%08lx>\n", - current->comm, current->pid, (unsigned long) value); - if (value > RLIM_INFINITY) - value = RLIM_INFINITY; - if (capable(CAP_SYS_ADMIN)) { - task_lock(current->group_leader); - current->signal->rlim[RLIMIT_STACK].rlim_max = - current->signal->rlim[RLIMIT_STACK].rlim_cur = value; - task_unlock(current->group_leader); - error = value; - break; - } - task_lock(current->group_leader); - if (value > current->signal->rlim[RLIMIT_STACK].rlim_max) { - error = -EINVAL; - task_unlock(current->group_leader); - break; - } - current->signal->rlim[RLIMIT_STACK].rlim_cur = value; - task_unlock(current->group_leader); - error = value; - break; - } - - case PR_GETSTACKSIZE: - printk("irix_prctl[%s:%d]: Wants PR_GETSTACKSIZE\n", - current->comm, current->pid); - error = current->signal->rlim[RLIMIT_STACK].rlim_cur; - break; - - case PR_MAXPPROCS: - printk("irix_prctl[%s:%d]: Wants PR_MAXPROCS\n", - current->comm, current->pid); - error = 1; - break; - - case PR_UNBLKONEXEC: - printk("irix_prctl[%s:%d]: Wants PR_UNBLKONEXEC\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_SETEXITSIG: - printk("irix_prctl[%s:%d]: Wants PR_SETEXITSIG\n", - current->comm, current->pid); - - /* We can probably play some game where we set the task - * exit_code to some non-zero value when this is requested, - * and check whether exit_code is already set in do_exit(). - */ - error = -EINVAL; - break; - - case PR_RESIDENT: - printk("irix_prctl[%s:%d]: Wants PR_RESIDENT\n", - current->comm, current->pid); - error = 0; /* Compatibility indeed. */ - break; - - case PR_ATTACHADDR: - printk("irix_prctl[%s:%d]: Wants PR_ATTACHADDR\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_DETACHADDR: - printk("irix_prctl[%s:%d]: Wants PR_DETACHADDR\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_TERMCHILD: - printk("irix_prctl[%s:%d]: Wants PR_TERMCHILD\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_GETSHMASK: - printk("irix_prctl[%s:%d]: Wants PR_GETSHMASK\n", - current->comm, current->pid); - error = -EINVAL; /* Until I have the sproc() stuff in. */ - break; - - case PR_GETNSHARE: - error = 0; /* Until I have the sproc() stuff in. */ - break; - - case PR_COREPID: - printk("irix_prctl[%s:%d]: Wants PR_COREPID\n", - current->comm, current->pid); - error = -EINVAL; - break; - - case PR_ATTACHADDRPERM: - printk("irix_prctl[%s:%d]: Wants PR_ATTACHADDRPERM\n", - current->comm, current->pid); - error = -EINVAL; - break; - - default: - printk("irix_prctl[%s:%d]: Non-existant opcode %d\n", - current->comm, current->pid, option); - error = -EINVAL; - break; - } - va_end(args); - - return error; -} - -#undef DEBUG_PROCGRPS - -extern unsigned long irix_mapelf(int fd, struct elf_phdr __user *user_phdrp, int cnt); -extern char *prom_getenv(char *name); -extern long prom_setenv(char *name, char *value); - -/* The syssgi commands supported thus far. */ -#define SGI_SYSID 1 /* Return unique per-machine identifier. */ -#define SGI_INVENT 5 /* Fetch inventory */ -# define SGI_INV_SIZEOF 1 -# define SGI_INV_READ 2 -#define SGI_RDNAME 6 /* Return string name of a process. */ -#define SGI_SETNVRAM 8 /* Set PROM variable. */ -#define SGI_GETNVRAM 9 /* Get PROM variable. */ -#define SGI_SETPGID 21 /* Set process group id. */ -#define SGI_SYSCONF 22 /* POSIX sysconf garbage. */ -#define SGI_PATHCONF 24 /* POSIX sysconf garbage. */ -#define SGI_SETGROUPS 40 /* POSIX sysconf garbage. */ -#define SGI_GETGROUPS 41 /* POSIX sysconf garbage. */ -#define SGI_RUSAGE 56 /* BSD style rusage(). */ -#define SGI_SSYNC 62 /* Synchronous fs sync. */ -#define SGI_GETSID 65 /* SysVr4 get session id. */ -#define SGI_ELFMAP 68 /* Map an elf image. */ -#define SGI_TOSSTSAVE 108 /* Toss saved vma's. */ -#define SGI_FP_BCOPY 129 /* Should FPU bcopy be used on this machine? */ -#define SGI_PHYSP 1011 /* Translate virtual into physical page. */ - -asmlinkage int irix_syssgi(struct pt_regs *regs) -{ - unsigned long cmd; - int retval, base = 0; - - if (regs->regs[2] == 1000) - base = 1; - - cmd = regs->regs[base + 4]; - switch(cmd) { - case SGI_SYSID: { - char __user *buf = (char __user *) regs->regs[base + 5]; - - /* XXX Use ethernet addr.... */ - retval = clear_user(buf, 64) ? -EFAULT : 0; - break; - } -#if 0 - case SGI_RDNAME: { - int pid = (int) regs->regs[base + 5]; - char __user *buf = (char __user *) regs->regs[base + 6]; - struct task_struct *p; - char tcomm[sizeof(current->comm)]; - - read_lock(&tasklist_lock); - p = find_task_by_pid(pid); - if (!p) { - read_unlock(&tasklist_lock); - retval = -ESRCH; - break; - } - get_task_comm(tcomm, p); - read_unlock(&tasklist_lock); - - /* XXX Need to check sizes. */ - retval = copy_to_user(buf, tcomm, sizeof(tcomm)) ? -EFAULT : 0; - break; - } - - case SGI_GETNVRAM: { - char __user *name = (char __user *) regs->regs[base+5]; - char __user *buf = (char __user *) regs->regs[base+6]; - char *value; - return -EINVAL; /* til I fix it */ - value = prom_getenv(name); /* PROM lock? */ - if (!value) { - retval = -EINVAL; - break; - } - /* Do I strlen() for the length? */ - retval = copy_to_user(buf, value, 128) ? -EFAULT : 0; - break; - } - - case SGI_SETNVRAM: { - char __user *name = (char __user *) regs->regs[base+5]; - char __user *value = (char __user *) regs->regs[base+6]; - return -EINVAL; /* til I fix it */ - retval = prom_setenv(name, value); - /* XXX make sure retval conforms to syssgi(2) */ - printk("[%s:%d] setnvram(\"%s\", \"%s\"): retval %d", - current->comm, current->pid, name, value, retval); -/* if (retval == PROM_ENOENT) - retval = -ENOENT; */ - break; - } -#endif - - case SGI_SETPGID: { -#ifdef DEBUG_PROCGRPS - printk("[%s:%d] setpgid(%d, %d) ", - current->comm, current->pid, - (int) regs->regs[base + 5], (int)regs->regs[base + 6]); -#endif - retval = sys_setpgid(regs->regs[base + 5], regs->regs[base + 6]); - -#ifdef DEBUG_PROCGRPS - printk("retval=%d\n", retval); -#endif - } - - case SGI_SYSCONF: { - switch(regs->regs[base + 5]) { - case 1: - retval = (MAX_ARG_PAGES >> 4); /* XXX estimate... */ - goto out; - case 2: - retval = max_threads; - goto out; - case 3: - retval = HZ; - goto out; - case 4: - retval = NGROUPS_MAX; - goto out; - case 5: - retval = sysctl_nr_open; - goto out; - case 6: - retval = 1; - goto out; - case 7: - retval = 1; - goto out; - case 8: - retval = 199009; - goto out; - case 11: - retval = PAGE_SIZE; - goto out; - case 12: - retval = 4; - goto out; - case 25: - case 26: - case 27: - case 28: - case 29: - case 30: - retval = 0; - goto out; - case 31: - retval = 32; - goto out; - default: - retval = -EINVAL; - goto out; - }; - } - - case SGI_SETGROUPS: - retval = sys_setgroups((int) regs->regs[base + 5], - (gid_t __user *) regs->regs[base + 6]); - break; - - case SGI_GETGROUPS: - retval = sys_getgroups((int) regs->regs[base + 5], - (gid_t __user *) regs->regs[base + 6]); - break; - - case SGI_RUSAGE: { - struct rusage __user *ru = (struct rusage __user *) regs->regs[base + 6]; - - switch((int) regs->regs[base + 5]) { - case 0: - /* rusage self */ - retval = getrusage(current, RUSAGE_SELF, ru); - goto out; - - case -1: - /* rusage children */ - retval = getrusage(current, RUSAGE_CHILDREN, ru); - goto out; - - default: - retval = -EINVAL; - goto out; - }; - } - - case SGI_SSYNC: - sys_sync(); - retval = 0; - break; - - case SGI_GETSID: -#ifdef DEBUG_PROCGRPS - printk("[%s:%d] getsid(%d) ", current->comm, current->pid, - (int) regs->regs[base + 5]); -#endif - retval = sys_getsid(regs->regs[base + 5]); -#ifdef DEBUG_PROCGRPS - printk("retval=%d\n", retval); -#endif - break; - - case SGI_ELFMAP: - retval = irix_mapelf((int) regs->regs[base + 5], - (struct elf_phdr __user *) regs->regs[base + 6], - (int) regs->regs[base + 7]); - break; - - case SGI_TOSSTSAVE: - /* XXX We don't need to do anything? */ - retval = 0; - break; - - case SGI_FP_BCOPY: - retval = 0; - break; - - case SGI_PHYSP: { - unsigned long addr = regs->regs[base + 5]; - int __user *pageno = (int __user *) (regs->regs[base + 6]); - struct mm_struct *mm = current->mm; - pgd_t *pgdp; - pud_t *pudp; - pmd_t *pmdp; - pte_t *ptep; - - down_read(&mm->mmap_sem); - pgdp = pgd_offset(mm, addr); - pudp = pud_offset(pgdp, addr); - pmdp = pmd_offset(pudp, addr); - ptep = pte_offset(pmdp, addr); - retval = -EINVAL; - if (ptep) { - pte_t pte = *ptep; - - if (pte_val(pte) & (_PAGE_VALID | _PAGE_PRESENT)) { - /* b0rked on 64-bit */ - retval = put_user((pte_val(pte) & PAGE_MASK) >> - PAGE_SHIFT, pageno); - } - } - up_read(&mm->mmap_sem); - break; - } - - case SGI_INVENT: { - int arg1 = (int) regs->regs [base + 5]; - void __user *buffer = (void __user *) regs->regs [base + 6]; - int count = (int) regs->regs [base + 7]; - - switch (arg1) { - case SGI_INV_SIZEOF: - retval = sizeof(inventory_t); - break; - case SGI_INV_READ: - retval = dump_inventory_to_user(buffer, count); - break; - default: - retval = -EINVAL; - } - break; - } - - default: - printk("irix_syssgi: Unsupported command %d\n", (int)cmd); - retval = -EINVAL; - break; - }; - -out: - return retval; -} - -asmlinkage int irix_gtime(struct pt_regs *regs) -{ - return get_seconds(); -} - -/* - * IRIX is completely broken... it returns 0 on success, otherwise - * ENOMEM. - */ -asmlinkage int irix_brk(unsigned long brk) -{ - unsigned long rlim; - unsigned long newbrk, oldbrk; - struct mm_struct *mm = current->mm; - int ret; - - down_write(&mm->mmap_sem); - if (brk < mm->end_code) { - ret = -ENOMEM; - goto out; - } - - newbrk = PAGE_ALIGN(brk); - oldbrk = PAGE_ALIGN(mm->brk); - if (oldbrk == newbrk) { - mm->brk = brk; - ret = 0; - goto out; - } - - /* - * Always allow shrinking brk - */ - if (brk <= mm->brk) { - mm->brk = brk; - do_munmap(mm, newbrk, oldbrk-newbrk); - ret = 0; - goto out; - } - /* - * Check against rlimit and stack.. - */ - rlim = current->signal->rlim[RLIMIT_DATA].rlim_cur; - if (rlim >= RLIM_INFINITY) - rlim = ~0; - if (brk - mm->end_code > rlim) { - ret = -ENOMEM; - goto out; - } - - /* - * Check against existing mmap mappings. - */ - if (find_vma_intersection(mm, oldbrk, newbrk+PAGE_SIZE)) { - ret = -ENOMEM; - goto out; - } - - /* - * Ok, looks good - let it rip. - */ - if (do_brk(oldbrk, newbrk-oldbrk) != oldbrk) { - ret = -ENOMEM; - goto out; - } - mm->brk = brk; - ret = 0; - -out: - up_write(&mm->mmap_sem); - return ret; -} - -asmlinkage int irix_getpid(struct pt_regs *regs) -{ - regs->regs[3] = task_pid_vnr(current->real_parent); - return task_pid_vnr(current); -} - -asmlinkage int irix_getuid(struct pt_regs *regs) -{ - regs->regs[3] = current->euid; - return current->uid; -} - -asmlinkage int irix_getgid(struct pt_regs *regs) -{ - regs->regs[3] = current->egid; - return current->gid; -} - -asmlinkage int irix_stime(int value) -{ - int err; - struct timespec tv; - - tv.tv_sec = value; - tv.tv_nsec = 0; - err = security_settime(&tv, NULL); - if (err) - return err; - - write_seqlock_irq(&xtime_lock); - xtime.tv_sec = value; - xtime.tv_nsec = 0; - ntp_clear(); - write_sequnlock_irq(&xtime_lock); - - return 0; -} - -static inline void jiffiestotv(unsigned long jiffies, struct timeval *value) -{ - value->tv_usec = (jiffies % HZ) * (1000000 / HZ); - value->tv_sec = jiffies / HZ; -} - -static inline void getitimer_real(struct itimerval *value) -{ - register unsigned long val, interval; - - interval = current->it_real_incr; - val = 0; - if (del_timer(¤t->real_timer)) { - unsigned long now = jiffies; - val = current->real_timer.expires; - add_timer(¤t->real_timer); - /* look out for negative/zero itimer.. */ - if (val <= now) - val = now+1; - val -= now; - } - jiffiestotv(val, &value->it_value); - jiffiestotv(interval, &value->it_interval); -} - -asmlinkage unsigned int irix_alarm(unsigned int seconds) -{ - return alarm_setitimer(seconds); -} - -asmlinkage int irix_pause(void) -{ - current->state = TASK_INTERRUPTIBLE; - schedule(); - - return -EINTR; -} - -/* XXX need more than this... */ -asmlinkage int irix_mount(char __user *dev_name, char __user *dir_name, - unsigned long flags, char __user *type, void __user *data, int datalen) -{ - printk("[%s:%d] irix_mount(%p,%p,%08lx,%p,%p,%d)\n", - current->comm, current->pid, - dev_name, dir_name, flags, type, data, datalen); - - return sys_mount(dev_name, dir_name, type, flags, data); -} - -struct irix_statfs { - short f_type; - long f_bsize, f_frsize, f_blocks, f_bfree, f_files, f_ffree; - char f_fname[6], f_fpack[6]; -}; - -asmlinkage int irix_statfs(const char __user *path, - struct irix_statfs __user *buf, int len, int fs_type) -{ - struct nameidata nd; - struct kstatfs kbuf; - int error, i; - - /* We don't support this feature yet. */ - if (fs_type) { - error = -EINVAL; - goto out; - } - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statfs))) { - error = -EFAULT; - goto out; - } - - error = user_path_walk(path, &nd); - if (error) - goto out; - - error = vfs_statfs(nd.path.dentry, &kbuf); - if (error) - goto dput_and_out; - - error = __put_user(kbuf.f_type, &buf->f_type); - error |= __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - for (i = 0; i < 6; i++) { - error |= __put_user(0, &buf->f_fname[i]); - error |= __put_user(0, &buf->f_fpack[i]); - } - -dput_and_out: - path_put(&nd.path); -out: - return error; -} - -asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs __user *buf) -{ - struct kstatfs kbuf; - struct file *file; - int error, i; - - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statfs))) { - error = -EFAULT; - goto out; - } - - if (!(file = fget(fd))) { - error = -EBADF; - goto out; - } - - error = vfs_statfs(file->f_path.dentry, &kbuf); - if (error) - goto out_f; - - error = __put_user(kbuf.f_type, &buf->f_type); - error |= __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - - for (i = 0; i < 6; i++) { - error |= __put_user(0, &buf->f_fname[i]); - error |= __put_user(0, &buf->f_fpack[i]); - } - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_setpgrp(int flags) -{ - int error; - -#ifdef DEBUG_PROCGRPS - printk("[%s:%d] setpgrp(%d) ", current->comm, current->pid, flags); -#endif - if(!flags) - error = task_pgrp_vnr(current); - else - error = sys_setsid(); -#ifdef DEBUG_PROCGRPS - printk("returning %d\n", error); -#endif - - return error; -} - -asmlinkage int irix_times(struct tms __user *tbuf) -{ - int err = 0; - - if (tbuf) { - if (!access_ok(VERIFY_WRITE, tbuf, sizeof *tbuf)) - return -EFAULT; - - err = __put_user(current->utime, &tbuf->tms_utime); - err |= __put_user(current->stime, &tbuf->tms_stime); - err |= __put_user(current->signal->cutime, &tbuf->tms_cutime); - err |= __put_user(current->signal->cstime, &tbuf->tms_cstime); - } - - return err; -} - -asmlinkage int irix_exec(struct pt_regs *regs) -{ - int error, base = 0; - char *filename; - - if(regs->regs[2] == 1000) - base = 1; - filename = getname((char __user *) (long)regs->regs[base + 4]); - error = PTR_ERR(filename); - if (IS_ERR(filename)) - return error; - - error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5], - NULL, regs); - putname(filename); - - return error; -} - -asmlinkage int irix_exece(struct pt_regs *regs) -{ - int error, base = 0; - char *filename; - - if (regs->regs[2] == 1000) - base = 1; - filename = getname((char __user *) (long)regs->regs[base + 4]); - error = PTR_ERR(filename); - if (IS_ERR(filename)) - return error; - error = do_execve(filename, (char __user * __user *) (long)regs->regs[base + 5], - (char __user * __user *) (long)regs->regs[base + 6], regs); - putname(filename); - - return error; -} - -asmlinkage unsigned long irix_gethostid(void) -{ - printk("[%s:%d]: irix_gethostid() called...\n", - current->comm, current->pid); - - return -EINVAL; -} - -asmlinkage unsigned long irix_sethostid(unsigned long val) -{ - printk("[%s:%d]: irix_sethostid(%08lx) called...\n", - current->comm, current->pid, val); - - return -EINVAL; -} - -asmlinkage int irix_socket(int family, int type, int protocol) -{ - switch(type) { - case 1: - type = SOCK_DGRAM; - break; - - case 2: - type = SOCK_STREAM; - break; - - case 3: - type = 9; /* Invalid... */ - break; - - case 4: - type = SOCK_RAW; - break; - - case 5: - type = SOCK_RDM; - break; - - case 6: - type = SOCK_SEQPACKET; - break; - - default: - break; - } - - return sys_socket(family, type, protocol); -} - -asmlinkage int irix_getdomainname(char __user *name, int len) -{ - int err; - - down_read(&uts_sem); - if (len > __NEW_UTS_LEN) - len = __NEW_UTS_LEN; - err = copy_to_user(name, utsname()->domainname, len) ? -EFAULT : 0; - up_read(&uts_sem); - - return err; -} - -asmlinkage unsigned long irix_getpagesize(void) -{ - return PAGE_SIZE; -} - -asmlinkage int irix_msgsys(int opcode, unsigned long arg0, unsigned long arg1, - unsigned long arg2, unsigned long arg3, - unsigned long arg4) -{ - switch (opcode) { - case 0: - return sys_msgget((key_t) arg0, (int) arg1); - case 1: - return sys_msgctl((int) arg0, (int) arg1, - (struct msqid_ds __user *)arg2); - case 2: - return sys_msgrcv((int) arg0, (struct msgbuf __user *) arg1, - (size_t) arg2, (long) arg3, (int) arg4); - case 3: - return sys_msgsnd((int) arg0, (struct msgbuf __user *) arg1, - (size_t) arg2, (int) arg3); - default: - return -EINVAL; - } -} - -asmlinkage int irix_shmsys(int opcode, unsigned long arg0, unsigned long arg1, - unsigned long arg2, unsigned long arg3) -{ - switch (opcode) { - case 0: - return do_shmat((int) arg0, (char __user *) arg1, (int) arg2, - (unsigned long *) arg3); - case 1: - return sys_shmctl((int)arg0, (int)arg1, - (struct shmid_ds __user *)arg2); - case 2: - return sys_shmdt((char __user *)arg0); - case 3: - return sys_shmget((key_t) arg0, (int) arg1, (int) arg2); - default: - return -EINVAL; - } -} - -asmlinkage int irix_semsys(int opcode, unsigned long arg0, unsigned long arg1, - unsigned long arg2, int arg3) -{ - switch (opcode) { - case 0: - return sys_semctl((int) arg0, (int) arg1, (int) arg2, - (union semun) arg3); - case 1: - return sys_semget((key_t) arg0, (int) arg1, (int) arg2); - case 2: - return sys_semop((int) arg0, (struct sembuf __user *)arg1, - (unsigned int) arg2); - default: - return -EINVAL; - } -} - -static inline loff_t llseek(struct file *file, loff_t offset, int origin) -{ - loff_t (*fn)(struct file *, loff_t, int); - loff_t retval; - - fn = default_llseek; - if (file->f_op && file->f_op->llseek) - fn = file->f_op->llseek; - lock_kernel(); - retval = fn(file, offset, origin); - unlock_kernel(); - - return retval; -} - -asmlinkage int irix_lseek64(int fd, int _unused, int offhi, int offlow, - int origin) -{ - struct file * file; - loff_t offset; - int retval; - - retval = -EBADF; - file = fget(fd); - if (!file) - goto bad; - retval = -EINVAL; - if (origin > 2) - goto out_putf; - - offset = llseek(file, ((loff_t) offhi << 32) | offlow, origin); - retval = (int) offset; - -out_putf: - fput(file); -bad: - return retval; -} - -asmlinkage int irix_sginap(int ticks) -{ - schedule_timeout_interruptible(ticks); - return 0; -} - -asmlinkage int irix_sgikopt(char __user *istring, char __user *ostring, int len) -{ - return -EINVAL; -} - -asmlinkage int irix_gettimeofday(struct timeval __user *tv) -{ - time_t sec; - long nsec, seq; - int err; - - if (!access_ok(VERIFY_WRITE, tv, sizeof(struct timeval))) - return -EFAULT; - - do { - seq = read_seqbegin(&xtime_lock); - sec = xtime.tv_sec; - nsec = xtime.tv_nsec; - } while (read_seqretry(&xtime_lock, seq)); - - err = __put_user(sec, &tv->tv_sec); - err |= __put_user((nsec / 1000), &tv->tv_usec); - - return err; -} - -#define IRIX_MAP_AUTOGROW 0x40 - -asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot, - int flags, int fd, off_t offset) -{ - struct file *file = NULL; - unsigned long retval; - - if (!(flags & MAP_ANONYMOUS)) { - if (!(file = fget(fd))) - return -EBADF; - - /* Ok, bad taste hack follows, try to think in something else - * when reading this. */ - if (flags & IRIX_MAP_AUTOGROW) { - unsigned long old_pos; - long max_size = offset + len; - - if (max_size > file->f_path.dentry->d_inode->i_size) { - old_pos = sys_lseek(fd, max_size - 1, 0); - sys_write(fd, (void __user *) "", 1); - sys_lseek(fd, old_pos, 0); - } - } - } - - flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); - - down_write(¤t->mm->mmap_sem); - retval = do_mmap(file, addr, len, prot, flags, offset); - up_write(¤t->mm->mmap_sem); - if (file) - fput(file); - - return retval; -} - -asmlinkage int irix_madvise(unsigned long addr, int len, int behavior) -{ - printk("[%s:%d] Wheee.. irix_madvise(%08lx,%d,%d)\n", - current->comm, current->pid, addr, len, behavior); - - return -EINVAL; -} - -asmlinkage int irix_pagelock(char __user *addr, int len, int op) -{ - printk("[%s:%d] Wheee.. irix_pagelock(%p,%d,%d)\n", - current->comm, current->pid, addr, len, op); - - return -EINVAL; -} - -asmlinkage int irix_quotactl(struct pt_regs *regs) -{ - printk("[%s:%d] Wheee.. irix_quotactl()\n", - current->comm, current->pid); - - return -EINVAL; -} - -asmlinkage int irix_BSDsetpgrp(int pid, int pgrp) -{ - int error; - -#ifdef DEBUG_PROCGRPS - printk("[%s:%d] BSDsetpgrp(%d, %d) ", current->comm, current->pid, - pid, pgrp); -#endif - if(!pid) - pid = task_pid_vnr(current); - - /* Wheee, weird sysv thing... */ - if ((pgrp == 0) && (pid == task_pid_vnr(current))) - error = sys_setsid(); - else - error = sys_setpgid(pid, pgrp); - -#ifdef DEBUG_PROCGRPS - printk("error = %d\n", error); -#endif - - return error; -} - -asmlinkage int irix_systeminfo(int cmd, char __user *buf, int cnt) -{ - printk("[%s:%d] Wheee.. irix_systeminfo(%d,%p,%d)\n", - current->comm, current->pid, cmd, buf, cnt); - - return -EINVAL; -} - -struct iuname { - char sysname[257], nodename[257], release[257]; - char version[257], machine[257]; - char m_type[257], base_rel[257]; - char _unused0[257], _unused1[257], _unused2[257]; - char _unused3[257], _unused4[257], _unused5[257]; -}; - -asmlinkage int irix_uname(struct iuname __user *buf) -{ - down_read(&uts_sem); - if (copy_from_user(utsname()->sysname, buf->sysname, 65) - || copy_from_user(utsname()->nodename, buf->nodename, 65) - || copy_from_user(utsname()->release, buf->release, 65) - || copy_from_user(utsname()->version, buf->version, 65) - || copy_from_user(utsname()->machine, buf->machine, 65)) { - return -EFAULT; - } - up_read(&uts_sem); - - return 1; -} - -#undef DEBUG_XSTAT - -static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf) -{ - struct xstat32 { - u32 st_dev, st_pad1[3], st_ino, st_mode, st_nlink, st_uid, st_gid; - u32 st_rdev, st_pad2[2], st_size, st_pad3; - u32 st_atime0, st_atime1; - u32 st_mtime0, st_mtime1; - u32 st_ctime0, st_ctime1; - u32 st_blksize, st_blocks; - char st_fstype[16]; - u32 st_pad4[8]; - } ub; - - if (!sysv_valid_dev(stat->dev) || !sysv_valid_dev(stat->rdev)) - return -EOVERFLOW; - ub.st_dev = sysv_encode_dev(stat->dev); - ub.st_ino = stat->ino; - ub.st_mode = stat->mode; - ub.st_nlink = stat->nlink; - SET_UID(ub.st_uid, stat->uid); - SET_GID(ub.st_gid, stat->gid); - ub.st_rdev = sysv_encode_dev(stat->rdev); -#if BITS_PER_LONG == 32 - if (stat->size > MAX_NON_LFS) - return -EOVERFLOW; -#endif - ub.st_size = stat->size; - ub.st_atime0 = stat->atime.tv_sec; - ub.st_atime1 = stat->atime.tv_nsec; - ub.st_mtime0 = stat->mtime.tv_sec; - ub.st_mtime1 = stat->atime.tv_nsec; - ub.st_ctime0 = stat->ctime.tv_sec; - ub.st_ctime1 = stat->atime.tv_nsec; - ub.st_blksize = stat->blksize; - ub.st_blocks = stat->blocks; - strcpy(ub.st_fstype, "efs"); - - return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; -} - -static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf) -{ - struct xstat64 { - u32 st_dev; s32 st_pad1[3]; - unsigned long long st_ino; - u32 st_mode; - u32 st_nlink; s32 st_uid; s32 st_gid; u32 st_rdev; - s32 st_pad2[2]; - long long st_size; - s32 st_pad3; - struct { s32 tv_sec, tv_nsec; } st_atime, st_mtime, st_ctime; - s32 st_blksize; - long long st_blocks; - char st_fstype[16]; - s32 st_pad4[8]; - } ks; - - if (!sysv_valid_dev(stat->dev) || !sysv_valid_dev(stat->rdev)) - return -EOVERFLOW; - - ks.st_dev = sysv_encode_dev(stat->dev); - ks.st_pad1[0] = ks.st_pad1[1] = ks.st_pad1[2] = 0; - ks.st_ino = (unsigned long long) stat->ino; - ks.st_mode = (u32) stat->mode; - ks.st_nlink = (u32) stat->nlink; - ks.st_uid = (s32) stat->uid; - ks.st_gid = (s32) stat->gid; - ks.st_rdev = sysv_encode_dev(stat->rdev); - ks.st_pad2[0] = ks.st_pad2[1] = 0; - ks.st_size = (long long) stat->size; - ks.st_pad3 = 0; - - /* XXX hackety hack... */ - ks.st_atime.tv_sec = (s32) stat->atime.tv_sec; - ks.st_atime.tv_nsec = stat->atime.tv_nsec; - ks.st_mtime.tv_sec = (s32) stat->mtime.tv_sec; - ks.st_mtime.tv_nsec = stat->mtime.tv_nsec; - ks.st_ctime.tv_sec = (s32) stat->ctime.tv_sec; - ks.st_ctime.tv_nsec = stat->ctime.tv_nsec; - - ks.st_blksize = (s32) stat->blksize; - ks.st_blocks = (long long) stat->blocks; - memset(ks.st_fstype, 0, 16); - ks.st_pad4[0] = ks.st_pad4[1] = ks.st_pad4[2] = ks.st_pad4[3] = 0; - ks.st_pad4[4] = ks.st_pad4[5] = ks.st_pad4[6] = ks.st_pad4[7] = 0; - - /* Now write it all back. */ - return copy_to_user(ubuf, &ks, sizeof(ks)) ? -EFAULT : 0; -} - -asmlinkage int irix_xstat(int version, char __user *filename, struct stat __user *statbuf) -{ - int retval; - struct kstat stat; - -#ifdef DEBUG_XSTAT - printk("[%s:%d] Wheee.. irix_xstat(%d,%s,%p) ", - current->comm, current->pid, version, filename, statbuf); -#endif - - retval = vfs_stat(filename, &stat); - if (!retval) { - switch(version) { - case 2: - retval = irix_xstat32_xlate(&stat, statbuf); - break; - case 3: - retval = irix_xstat64_xlate(&stat, statbuf); - break; - default: - retval = -EINVAL; - } - } - return retval; -} - -asmlinkage int irix_lxstat(int version, char __user *filename, struct stat __user *statbuf) -{ - int error; - struct kstat stat; - -#ifdef DEBUG_XSTAT - printk("[%s:%d] Wheee.. irix_lxstat(%d,%s,%p) ", - current->comm, current->pid, version, filename, statbuf); -#endif - - error = vfs_lstat(filename, &stat); - - if (!error) { - switch (version) { - case 2: - error = irix_xstat32_xlate(&stat, statbuf); - break; - case 3: - error = irix_xstat64_xlate(&stat, statbuf); - break; - default: - error = -EINVAL; - } - } - return error; -} - -asmlinkage int irix_fxstat(int version, int fd, struct stat __user *statbuf) -{ - int error; - struct kstat stat; - -#ifdef DEBUG_XSTAT - printk("[%s:%d] Wheee.. irix_fxstat(%d,%d,%p) ", - current->comm, current->pid, version, fd, statbuf); -#endif - - error = vfs_fstat(fd, &stat); - if (!error) { - switch (version) { - case 2: - error = irix_xstat32_xlate(&stat, statbuf); - break; - case 3: - error = irix_xstat64_xlate(&stat, statbuf); - break; - default: - error = -EINVAL; - } - } - return error; -} - -asmlinkage int irix_xmknod(int ver, char __user *filename, int mode, unsigned dev) -{ - int retval; - printk("[%s:%d] Wheee.. irix_xmknod(%d,%s,%x,%x)\n", - current->comm, current->pid, ver, filename, mode, dev); - - switch(ver) { - case 2: - /* shouldn't we convert here as well as on stat()? */ - retval = sys_mknod(filename, mode, dev); - break; - - default: - retval = -EINVAL; - break; - }; - - return retval; -} - -asmlinkage int irix_swapctl(int cmd, char __user *arg) -{ - printk("[%s:%d] Wheee.. irix_swapctl(%d,%p)\n", - current->comm, current->pid, cmd, arg); - - return -EINVAL; -} - -struct irix_statvfs { - u32 f_bsize; u32 f_frsize; u32 f_blocks; - u32 f_bfree; u32 f_bavail; u32 f_files; u32 f_ffree; u32 f_favail; - u32 f_fsid; char f_basetype[16]; - u32 f_flag; u32 f_namemax; - char f_fstr[32]; u32 f_filler[16]; -}; - -asmlinkage int irix_statvfs(char __user *fname, struct irix_statvfs __user *buf) -{ - struct nameidata nd; - struct kstatfs kbuf; - int error, i; - - printk("[%s:%d] Wheee.. irix_statvfs(%s,%p)\n", - current->comm, current->pid, fname, buf); - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) - return -EFAULT; - - error = user_path_walk(fname, &nd); - if (error) - goto out; - error = vfs_statfs(nd.path.dentry, &kbuf); - if (error) - goto dput_and_out; - - error |= __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ -#ifdef __MIPSEB__ - error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); -#else - error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); -#endif - for (i = 0; i < 16; i++) - error |= __put_user(0, &buf->f_basetype[i]); - error |= __put_user(0, &buf->f_flag); - error |= __put_user(kbuf.f_namelen, &buf->f_namemax); - for (i = 0; i < 32; i++) - error |= __put_user(0, &buf->f_fstr[i]); - -dput_and_out: - path_put(&nd.path); -out: - return error; -} - -asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs __user *buf) -{ - struct kstatfs kbuf; - struct file *file; - int error, i; - - printk("[%s:%d] Wheee.. irix_fstatvfs(%d,%p)\n", - current->comm, current->pid, fd, buf); - - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) - return -EFAULT; - - if (!(file = fget(fd))) { - error = -EBADF; - goto out; - } - error = vfs_statfs(file->f_path.dentry, &kbuf); - if (error) - goto out_f; - - error = __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ -#ifdef __MIPSEB__ - error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); -#else - error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); -#endif - for(i = 0; i < 16; i++) - error |= __put_user(0, &buf->f_basetype[i]); - error |= __put_user(0, &buf->f_flag); - error |= __put_user(kbuf.f_namelen, &buf->f_namemax); - error |= __clear_user(&buf->f_fstr, sizeof(buf->f_fstr)) ? -EFAULT : 0; - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_priocntl(struct pt_regs *regs) -{ - printk("[%s:%d] Wheee.. irix_priocntl()\n", - current->comm, current->pid); - - return -EINVAL; -} - -asmlinkage int irix_sigqueue(int pid, int sig, int code, int val) -{ - printk("[%s:%d] Wheee.. irix_sigqueue(%d,%d,%d,%d)\n", - current->comm, current->pid, pid, sig, code, val); - - return -EINVAL; -} - -asmlinkage int irix_truncate64(char __user *name, int pad, int size1, int size2) -{ - int retval; - - if (size1) { - retval = -EINVAL; - goto out; - } - retval = sys_truncate(name, size2); - -out: - return retval; -} - -asmlinkage int irix_ftruncate64(int fd, int pad, int size1, int size2) -{ - int retval; - - if (size1) { - retval = -EINVAL; - goto out; - } - retval = sys_ftruncate(fd, size2); - -out: - return retval; -} - -asmlinkage int irix_mmap64(struct pt_regs *regs) -{ - int len, prot, flags, fd, off1, off2, error, base = 0; - unsigned long addr, pgoff, *sp; - struct file *file = NULL; - int err; - - if (regs->regs[2] == 1000) - base = 1; - sp = (unsigned long *) (regs->regs[29] + 16); - addr = regs->regs[base + 4]; - len = regs->regs[base + 5]; - prot = regs->regs[base + 6]; - if (!base) { - flags = regs->regs[base + 7]; - if (!access_ok(VERIFY_READ, sp, (4 * sizeof(unsigned long)))) - return -EFAULT; - fd = sp[0]; - err = __get_user(off1, &sp[1]); - err |= __get_user(off2, &sp[2]); - } else { - if (!access_ok(VERIFY_READ, sp, (5 * sizeof(unsigned long)))) - return -EFAULT; - err = __get_user(flags, &sp[0]); - err |= __get_user(fd, &sp[1]); - err |= __get_user(off1, &sp[2]); - err |= __get_user(off2, &sp[3]); - } - - if (err) - return err; - - if (off1 & PAGE_MASK) - return -EOVERFLOW; - - pgoff = (off1 << (32 - PAGE_SHIFT)) | (off2 >> PAGE_SHIFT); - - if (!(flags & MAP_ANONYMOUS)) { - if (!(file = fget(fd))) - return -EBADF; - - /* Ok, bad taste hack follows, try to think in something else - when reading this */ - if (flags & IRIX_MAP_AUTOGROW) { - unsigned long old_pos; - long max_size = off2 + len; - - if (max_size > file->f_path.dentry->d_inode->i_size) { - old_pos = sys_lseek(fd, max_size - 1, 0); - sys_write(fd, (void __user *) "", 1); - sys_lseek(fd, old_pos, 0); - } - } - } - - flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); - - down_write(¤t->mm->mmap_sem); - error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff); - up_write(¤t->mm->mmap_sem); - - if (file) - fput(file); - - return error; -} - -asmlinkage int irix_dmi(struct pt_regs *regs) -{ - printk("[%s:%d] Wheee.. irix_dmi()\n", - current->comm, current->pid); - - return -EINVAL; -} - -asmlinkage int irix_pread(int fd, char __user *buf, int cnt, int off64, - int off1, int off2) -{ - printk("[%s:%d] Wheee.. irix_pread(%d,%p,%d,%d,%d,%d)\n", - current->comm, current->pid, fd, buf, cnt, off64, off1, off2); - - return -EINVAL; -} - -asmlinkage int irix_pwrite(int fd, char __user *buf, int cnt, int off64, - int off1, int off2) -{ - printk("[%s:%d] Wheee.. irix_pwrite(%d,%p,%d,%d,%d,%d)\n", - current->comm, current->pid, fd, buf, cnt, off64, off1, off2); - - return -EINVAL; -} - -asmlinkage int irix_sgifastpath(int cmd, unsigned long arg0, unsigned long arg1, - unsigned long arg2, unsigned long arg3, - unsigned long arg4, unsigned long arg5) -{ - printk("[%s:%d] Wheee.. irix_fastpath(%d,%08lx,%08lx,%08lx,%08lx," - "%08lx,%08lx)\n", - current->comm, current->pid, cmd, arg0, arg1, arg2, - arg3, arg4, arg5); - - return -EINVAL; -} - -struct irix_statvfs64 { - u32 f_bsize; u32 f_frsize; - u64 f_blocks; u64 f_bfree; u64 f_bavail; - u64 f_files; u64 f_ffree; u64 f_favail; - u32 f_fsid; - char f_basetype[16]; - u32 f_flag; u32 f_namemax; - char f_fstr[32]; - u32 f_filler[16]; -}; - -asmlinkage int irix_statvfs64(char __user *fname, struct irix_statvfs64 __user *buf) -{ - struct nameidata nd; - struct kstatfs kbuf; - int error, i; - - printk("[%s:%d] Wheee.. irix_statvfs64(%s,%p)\n", - current->comm, current->pid, fname, buf); - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs64))) { - error = -EFAULT; - goto out; - } - - error = user_path_walk(fname, &nd); - if (error) - goto out; - error = vfs_statfs(nd.path.dentry, &kbuf); - if (error) - goto dput_and_out; - - error = __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ -#ifdef __MIPSEB__ - error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); -#else - error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); -#endif - for(i = 0; i < 16; i++) - error |= __put_user(0, &buf->f_basetype[i]); - error |= __put_user(0, &buf->f_flag); - error |= __put_user(kbuf.f_namelen, &buf->f_namemax); - for(i = 0; i < 32; i++) - error |= __put_user(0, &buf->f_fstr[i]); - -dput_and_out: - path_put(&nd.path); -out: - return error; -} - -asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs __user *buf) -{ - struct kstatfs kbuf; - struct file *file; - int error, i; - - printk("[%s:%d] Wheee.. irix_fstatvfs64(%d,%p)\n", - current->comm, current->pid, fd, buf); - - if (!access_ok(VERIFY_WRITE, buf, sizeof(struct irix_statvfs))) { - error = -EFAULT; - goto out; - } - if (!(file = fget(fd))) { - error = -EBADF; - goto out; - } - error = vfs_statfs(file->f_path.dentry, &kbuf); - if (error) - goto out_f; - - error = __put_user(kbuf.f_bsize, &buf->f_bsize); - error |= __put_user(kbuf.f_frsize, &buf->f_frsize); - error |= __put_user(kbuf.f_blocks, &buf->f_blocks); - error |= __put_user(kbuf.f_bfree, &buf->f_bfree); - error |= __put_user(kbuf.f_bfree, &buf->f_bavail); /* XXX hackety hack... */ - error |= __put_user(kbuf.f_files, &buf->f_files); - error |= __put_user(kbuf.f_ffree, &buf->f_ffree); - error |= __put_user(kbuf.f_ffree, &buf->f_favail); /* XXX hackety hack... */ -#ifdef __MIPSEB__ - error |= __put_user(kbuf.f_fsid.val[1], &buf->f_fsid); -#else - error |= __put_user(kbuf.f_fsid.val[0], &buf->f_fsid); -#endif - for(i = 0; i < 16; i++) - error |= __put_user(0, &buf->f_basetype[i]); - error |= __put_user(0, &buf->f_flag); - error |= __put_user(kbuf.f_namelen, &buf->f_namemax); - error |= __clear_user(buf->f_fstr, sizeof(buf->f_fstr[i])) ? -EFAULT : 0; - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_getmountid(char __user *fname, unsigned long __user *midbuf) -{ - int err; - - printk("[%s:%d] irix_getmountid(%s, %p)\n", - current->comm, current->pid, fname, midbuf); - if (!access_ok(VERIFY_WRITE, midbuf, (sizeof(unsigned long) * 4))) - return -EFAULT; - - /* - * The idea with this system call is that when trying to determine - * 'pwd' and it's a toss-up for some reason, userland can use the - * fsid of the filesystem to try and make the right decision, but - * we don't have this so for now. XXX - */ - err = __put_user(0, &midbuf[0]); - err |= __put_user(0, &midbuf[1]); - err |= __put_user(0, &midbuf[2]); - err |= __put_user(0, &midbuf[3]); - - return err; -} - -asmlinkage int irix_nsproc(unsigned long entry, unsigned long mask, - unsigned long arg, unsigned long sp, int slen) -{ - printk("[%s:%d] Wheee.. irix_nsproc(%08lx,%08lx,%08lx,%08lx,%d)\n", - current->comm, current->pid, entry, mask, arg, sp, slen); - - return -EINVAL; -} - -#undef DEBUG_GETDENTS - -struct irix_dirent32 { - u32 d_ino; - u32 d_off; - unsigned short d_reclen; - char d_name[1]; -}; - -struct irix_dirent32_callback { - struct irix_dirent32 __user *current_dir; - struct irix_dirent32 __user *previous; - int count; - int error; -}; - -#define NAME_OFFSET32(de) ((int) ((de)->d_name - (char *) (de))) -#define ROUND_UP32(x) (((x)+sizeof(u32)-1) & ~(sizeof(u32)-1)) - -static int irix_filldir32(void *__buf, const char *name, - int namlen, loff_t offset, u64 ino, unsigned int d_type) -{ - struct irix_dirent32 __user *dirent; - struct irix_dirent32_callback *buf = __buf; - unsigned short reclen = ROUND_UP32(NAME_OFFSET32(dirent) + namlen + 1); - int err = 0; - u32 d_ino; - -#ifdef DEBUG_GETDENTS - printk("\nirix_filldir32[reclen<%d>namlen<%d>count<%d>]", - reclen, namlen, buf->count); -#endif - buf->error = -EINVAL; /* only used if we fail.. */ - if (reclen > buf->count) - return -EINVAL; - d_ino = ino; - if (sizeof(d_ino) < sizeof(ino) && d_ino != ino) - return -EOVERFLOW; - dirent = buf->previous; - if (dirent) - err = __put_user(offset, &dirent->d_off); - dirent = buf->current_dir; - err |= __put_user(dirent, &buf->previous); - err |= __put_user(d_ino, &dirent->d_ino); - err |= __put_user(reclen, &dirent->d_reclen); - err |= copy_to_user((char __user *)dirent->d_name, name, namlen) ? -EFAULT : 0; - err |= __put_user(0, &dirent->d_name[namlen]); - dirent = (struct irix_dirent32 __user *) ((char __user *) dirent + reclen); - - buf->current_dir = dirent; - buf->count -= reclen; - - return err; -} - -asmlinkage int irix_ngetdents(unsigned int fd, void __user * dirent, - unsigned int count, int __user *eob) -{ - struct file *file; - struct irix_dirent32 __user *lastdirent; - struct irix_dirent32_callback buf; - int error; - -#ifdef DEBUG_GETDENTS - printk("[%s:%d] ngetdents(%d, %p, %d, %p) ", current->comm, - current->pid, fd, dirent, count, eob); -#endif - error = -EBADF; - file = fget(fd); - if (!file) - goto out; - - buf.current_dir = (struct irix_dirent32 __user *) dirent; - buf.previous = NULL; - buf.count = count; - buf.error = 0; - - error = vfs_readdir(file, irix_filldir32, &buf); - if (error < 0) - goto out_putf; - - error = buf.error; - lastdirent = buf.previous; - if (lastdirent) { - put_user(file->f_pos, &lastdirent->d_off); - error = count - buf.count; - } - - if (put_user(0, eob) < 0) { - error = -EFAULT; - goto out_putf; - } - -#ifdef DEBUG_GETDENTS - printk("eob=%d returning %d\n", *eob, count - buf.count); -#endif - error = count - buf.count; - -out_putf: - fput(file); -out: - return error; -} - -struct irix_dirent64 { - u64 d_ino; - u64 d_off; - unsigned short d_reclen; - char d_name[1]; -}; - -struct irix_dirent64_callback { - struct irix_dirent64 __user *curr; - struct irix_dirent64 __user *previous; - int count; - int error; -}; - -#define NAME_OFFSET64(de) ((int) ((de)->d_name - (char *) (de))) -#define ROUND_UP64(x) (((x)+sizeof(u64)-1) & ~(sizeof(u64)-1)) - -static int irix_filldir64(void *__buf, const char *name, - int namlen, loff_t offset, u64 ino, unsigned int d_type) -{ - struct irix_dirent64 __user *dirent; - struct irix_dirent64_callback * buf = __buf; - unsigned short reclen = ROUND_UP64(NAME_OFFSET64(dirent) + namlen + 1); - int err = 0; - - if (!access_ok(VERIFY_WRITE, buf, sizeof(*buf))) - return -EFAULT; - - if (__put_user(-EINVAL, &buf->error)) /* only used if we fail.. */ - return -EFAULT; - if (reclen > buf->count) - return -EINVAL; - dirent = buf->previous; - if (dirent) - err = __put_user(offset, &dirent->d_off); - dirent = buf->curr; - buf->previous = dirent; - err |= __put_user(ino, &dirent->d_ino); - err |= __put_user(reclen, &dirent->d_reclen); - err |= __copy_to_user((char __user *)dirent->d_name, name, namlen) - ? -EFAULT : 0; - err |= __put_user(0, &dirent->d_name[namlen]); - - dirent = (struct irix_dirent64 __user *) ((char __user *) dirent + reclen); - - buf->curr = dirent; - buf->count -= reclen; - - return err; -} - -asmlinkage int irix_getdents64(int fd, void __user *dirent, int cnt) -{ - struct file *file; - struct irix_dirent64 __user *lastdirent; - struct irix_dirent64_callback buf; - int error; - -#ifdef DEBUG_GETDENTS - printk("[%s:%d] getdents64(%d, %p, %d) ", current->comm, - current->pid, fd, dirent, cnt); -#endif - error = -EBADF; - if (!(file = fget(fd))) - goto out; - - error = -EFAULT; - if (!access_ok(VERIFY_WRITE, dirent, cnt)) - goto out_f; - - error = -EINVAL; - if (cnt < (sizeof(struct irix_dirent64) + 255)) - goto out_f; - - buf.curr = (struct irix_dirent64 __user *) dirent; - buf.previous = NULL; - buf.count = cnt; - buf.error = 0; - error = vfs_readdir(file, irix_filldir64, &buf); - if (error < 0) - goto out_f; - lastdirent = buf.previous; - if (!lastdirent) { - error = buf.error; - goto out_f; - } - if (put_user(file->f_pos, &lastdirent->d_off)) - return -EFAULT; -#ifdef DEBUG_GETDENTS - printk("returning %d\n", cnt - buf.count); -#endif - error = cnt - buf.count; - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_ngetdents64(int fd, void __user *dirent, int cnt, int *eob) -{ - struct file *file; - struct irix_dirent64 __user *lastdirent; - struct irix_dirent64_callback buf; - int error; - -#ifdef DEBUG_GETDENTS - printk("[%s:%d] ngetdents64(%d, %p, %d) ", current->comm, - current->pid, fd, dirent, cnt); -#endif - error = -EBADF; - if (!(file = fget(fd))) - goto out; - - error = -EFAULT; - if (!access_ok(VERIFY_WRITE, dirent, cnt) || - !access_ok(VERIFY_WRITE, eob, sizeof(*eob))) - goto out_f; - - error = -EINVAL; - if (cnt < (sizeof(struct irix_dirent64) + 255)) - goto out_f; - - *eob = 0; - buf.curr = (struct irix_dirent64 __user *) dirent; - buf.previous = NULL; - buf.count = cnt; - buf.error = 0; - error = vfs_readdir(file, irix_filldir64, &buf); - if (error < 0) - goto out_f; - lastdirent = buf.previous; - if (!lastdirent) { - error = buf.error; - goto out_f; - } - if (put_user(file->f_pos, &lastdirent->d_off)) - return -EFAULT; -#ifdef DEBUG_GETDENTS - printk("eob=%d returning %d\n", *eob, cnt - buf.count); -#endif - error = cnt - buf.count; - -out_f: - fput(file); -out: - return error; -} - -asmlinkage int irix_uadmin(unsigned long op, unsigned long func, unsigned long arg) -{ - int retval; - - switch (op) { - case 1: - /* Reboot */ - printk("[%s:%d] irix_uadmin: Wants to reboot...\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 2: - /* Shutdown */ - printk("[%s:%d] irix_uadmin: Wants to shutdown...\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 4: - /* Remount-root */ - printk("[%s:%d] irix_uadmin: Wants to remount root...\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 8: - /* Kill all tasks. */ - printk("[%s:%d] irix_uadmin: Wants to kill all tasks...\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 256: - /* Set magic mushrooms... */ - printk("[%s:%d] irix_uadmin: Wants to set magic mushroom[%d]...\n", - current->comm, current->pid, (int) func); - retval = -EINVAL; - goto out; - - default: - printk("[%s:%d] irix_uadmin: Unknown operation [%d]...\n", - current->comm, current->pid, (int) op); - retval = -EINVAL; - goto out; - }; - -out: - return retval; -} - -asmlinkage int irix_utssys(char __user *inbuf, int arg, int type, char __user *outbuf) -{ - int retval; - - switch(type) { - case 0: - /* uname() */ - retval = irix_uname((struct iuname __user *)inbuf); - goto out; - - case 2: - /* ustat() */ - printk("[%s:%d] irix_utssys: Wants to do ustat()\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 3: - /* fusers() */ - printk("[%s:%d] irix_utssys: Wants to do fusers()\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - default: - printk("[%s:%d] irix_utssys: Wants to do unknown type[%d]\n", - current->comm, current->pid, (int) type); - retval = -EINVAL; - goto out; - } - -out: - return retval; -} - -#undef DEBUG_FCNTL - -#define IRIX_F_ALLOCSP 10 - -asmlinkage int irix_fcntl(int fd, int cmd, int arg) -{ - int retval; - -#ifdef DEBUG_FCNTL - printk("[%s:%d] irix_fcntl(%d, %d, %d) ", current->comm, - current->pid, fd, cmd, arg); -#endif - if (cmd == IRIX_F_ALLOCSP){ - return 0; - } - retval = sys_fcntl(fd, cmd, arg); -#ifdef DEBUG_FCNTL - printk("%d\n", retval); -#endif - return retval; -} - -asmlinkage int irix_ulimit(int cmd, int arg) -{ - int retval; - - switch(cmd) { - case 1: - printk("[%s:%d] irix_ulimit: Wants to get file size limit.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 2: - printk("[%s:%d] irix_ulimit: Wants to set file size limit.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 3: - printk("[%s:%d] irix_ulimit: Wants to get brk limit.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - case 4: -#if 0 - printk("[%s:%d] irix_ulimit: Wants to get fd limit.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; -#endif - retval = current->signal->rlim[RLIMIT_NOFILE].rlim_cur; - goto out; - - case 5: - printk("[%s:%d] irix_ulimit: Wants to get txt offset.\n", - current->comm, current->pid); - retval = -EINVAL; - goto out; - - default: - printk("[%s:%d] irix_ulimit: Unknown command [%d].\n", - current->comm, current->pid, cmd); - retval = -EINVAL; - goto out; - } -out: - return retval; -} - -asmlinkage int irix_unimp(struct pt_regs *regs) -{ - printk("irix_unimp [%s:%d] v0=%d v1=%d a0=%08lx a1=%08lx a2=%08lx " - "a3=%08lx\n", current->comm, current->pid, - (int) regs->regs[2], (int) regs->regs[3], - regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); - - return -ENOSYS; -} diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h deleted file mode 100644 index cc88aed23f0f..000000000000 --- a/include/asm-mips/inventory.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Miguel de Icaza - */ -#ifndef __ASM_INVENTORY_H -#define __ASM_INVENTORY_H - -#include - -typedef struct inventory_s { - struct inventory_s *inv_next; - int inv_class; - int inv_type; - int inv_controller; - int inv_unit; - int inv_state; -} inventory_t; - -extern int inventory_items; - -extern void add_to_inventory(int class, int type, int controller, int unit, int state); -extern int dump_inventory_to_user(void __user *userbuf, int size); -extern int __init init_inventory(void); - -#endif /* __ASM_INVENTORY_H */ diff --git a/include/asm-mips/namei.h b/include/asm-mips/namei.h index c94d12d1f868..a6605a752469 100644 --- a/include/asm-mips/namei.h +++ b/include/asm-mips/namei.h @@ -1,26 +1,11 @@ #ifndef _ASM_NAMEI_H #define _ASM_NAMEI_H -#include -#include +/* + * This dummy routine maybe changed to something useful + * for /usr/gnemul/ emulation stuff. + */ -#define IRIX_EMUL "/usr/gnemul/irix/" -#define RISCOS_EMUL "/usr/gnemul/riscos/" - -static inline char *__emul_prefix(void) -{ - switch (current->personality) { - case PER_IRIX32: - case PER_IRIXN32: - case PER_IRIX64: - return IRIX_EMUL; - - case PER_RISCOS: - return RISCOS_EMUL; - - default: - return NULL; - } -} +#define __emul_prefix() NULL #endif /* _ASM_NAMEI_H */ diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h deleted file mode 100644 index 8121a9a75bfd..000000000000 --- a/include/asm-mips/prctl.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * IRIX prctl interface - * - * The IRIX kernel maps a page at PRDA_ADDRESS with the - * contents of prda and fills it the bits on prda_sys. - */ - -#ifndef __PRCTL_H__ -#define __PRCTL_H__ - -#define PRDA_ADDRESS 0x200000L -#define PRDA ((struct prda *) PRDA_ADDRESS) - -struct prda_sys { - pid_t t_pid; - u32 t_hint; - u32 t_dlactseq; - u32 t_fpflags; - u32 t_prid; /* processor type, $prid CP0 register */ - u32 t_dlendseq; - u64 t_unused1[5]; - pid_t t_rpid; - s32 t_resched; - u32 t_unused[8]; - u32 t_cpu; /* current/last cpu */ - - /* FIXME: The signal information, not supported by Linux now */ - u32 t_flags; /* if true, then the sigprocmask is in userspace */ - u32 t_sigprocmask [1]; /* the sigprocmask */ -}; - -struct prda { - char fill [0xe00]; - struct prda_sys prda_sys; -}; - -#define t_sys prda_sys - -ptrdiff_t prctl(int op, int v1, int v2); - -#endif diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index 7a28989f7ee3..bee5153aca48 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h @@ -119,9 +119,6 @@ struct sigaction { struct k_sigaction { struct sigaction sa; -#ifdef CONFIG_BINFMT_IRIX - void (*sa_restorer)(void); -#endif }; /* IRIX compatible stack_t */ -- cgit v1.2.3 From 043ebd6c9de7500a399017643bbc5cafd4e37060 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Fri, 13 Jun 2008 00:25:36 +0100 Subject: [MIPS] DECstation: Document more MB ASIC register bits Document a few more register bits provided by the MB ASIC used on R4000SC (KN04) and R4400SC (KN05) CPU daughtercards with the DECstation. Reverse-engineered and not documented anywhere else to the best of my knowledge. Bit names appended to the last underscore the same as reported by the firmware in register dumps. Signed-off-by: Maciej W. Rozycki Signed-off-by: Ralf Baechle --- include/asm-mips/dec/kn05.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h index 15fe8f881e60..56d22dc8803a 100644 --- a/include/asm-mips/dec/kn05.h +++ b/include/asm-mips/dec/kn05.h @@ -6,7 +6,7 @@ * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC * definitions. * - * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki + * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -54,11 +54,11 @@ */ #define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ #define KN4K_MB_INT_RTC (1<<1) /* RTC? */ -#define KN4K_MB_INT_MT (1<<3) /* ??? */ +#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */ /* * Bits for the MB control & status register. - * Set to 0x00bf8001 on my system by the ROM. + * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware. */ #define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ #define KN4K_MB_CSR_F (1<<1) /* ??? */ @@ -69,7 +69,8 @@ #define KN4K_MB_CSR_IM (1<<13) /* ??? */ #define KN4K_MB_CSR_NC (1<<14) /* ??? */ #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ -#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */ +#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ #define KN4K_MB_CSR_FW (1<<21) /* ??? */ +#define KN4K_MB_CSR_W (1<<31) /* ??? */ #endif /* __ASM_MIPS_DEC_KN05_H */ -- cgit v1.2.3 From 94daeb90698c56a85ed219eeb18d4a8cddde7b03 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 11 Jun 2008 10:04:25 -0700 Subject: [MIPS] Fix asm constraints for 'ins' instructions. The third operand to 'ins' must be a constant int, not a register. [Ralf: The bug was actually intensional. Some versions used to throw an error under certain circumstances for code like: static inline void f(unsigned nr, unsigned *p) { unsigned short bit = nr & 5; if (__builtin_constant_p(bit)) { __asm__ __volatile__ (" foo %0, %1" : "=m" (*p) : "i" (bit)); } else { /* Do something else. */ } } because gcc was not able to figure out that the "i" constraint was possibly at the early stage when the constraint are getting verified. The solution was using "ri" instead of "i". The "ri" would keep gcc happy but in the end for code generation always the "i" constraint would be satisfied. The problem afair originally appeared in the i386 io.h and also hit it's mips equivalent. From there the workaround spread to many of the inline assembler functions.] Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 642724734eba..9a7274ba6a0b 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m), "r" (~0)); + : "i" (bit), "m" (*m), "r" (~0)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( @@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) - : "ir" (bit), "m" (*m)); + : "i" (bit), "m" (*m)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( @@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr, "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m), "=&r" (res) - : "ri" (bit), "m" (*m) + : "i" (bit), "m" (*m) : "memory"); #endif } else if (cpu_has_llsc) { -- cgit v1.2.3 From 7a2852e49fe2d19296812c0f0f833b0ee3043bbb Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Tue, 18 Mar 2008 22:47:56 +0100 Subject: [MIPS] IP28: switch to "normal" mode after PROM no longer needed SGI-IP28 is running in so called slow mode, when kernel is started from the PROM. PROM calls must be done in slow mode otherwise the PROM will issue an error. To get better memory performance we now switch to normal mode, when the PROM is no longer needed. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/sgi-ip22/ip22-mc.c | 26 ++++++++++++++++++++++++++ include/asm-mips/barrier.h | 14 ++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'include/asm-mips') diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c index 3f35d6367bec..5268ac187bbd 100644 --- a/arch/mips/sgi-ip22/ip22-mc.c +++ b/arch/mips/sgi-ip22/ip22-mc.c @@ -208,4 +208,30 @@ void __init sgimc_init(void) void __init prom_meminit(void) {} void __init prom_free_prom_memory(void) { +#ifdef CONFIG_SGI_IP28 + u32 mconfig1; + unsigned long flags; + spinlock_t lock; + + /* + * because ARCS accesses memory uncached we wait until ARCS + * isn't needed any longer, before we switch from slow to + * normal mode + */ + spin_lock_irqsave(&lock, flags); + mconfig1 = sgimc->mconfig1; + /* map ECC register */ + sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060; + iob(); + /* switch to normal mode */ + *(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0; + iob(); + /* reduce WR_COL */ + sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4; + iob(); + /* restore old config */ + sgimc->mconfig1 = mconfig1; + iob(); + spin_unlock_irqrestore(&lock, flags); +#endif } diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h index 9d8cfbb5e796..8e9ac313ca3b 100644 --- a/include/asm-mips/barrier.h +++ b/include/asm-mips/barrier.h @@ -92,11 +92,25 @@ #define fast_wmb() __sync() #define fast_rmb() __sync() #define fast_mb() __sync() +#ifdef CONFIG_SGI_IP28 +#define fast_iob() \ + __asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + "lw $0,%0\n\t" \ + "sync\n\t" \ + "lw $0,%0\n\t" \ + ".set pop" \ + : /* no output */ \ + : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \ + : "memory") +#else #define fast_iob() \ do { \ __sync(); \ __fast_iob(); \ } while (0) +#endif #ifdef CONFIG_CPU_HAS_WB -- cgit v1.2.3 From af3e69cfc9644c742a22647a5091779b9dfb9653 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 4 Jul 2008 00:59:40 +0900 Subject: [MIPS] Declare some pci variables in header file Declare pci_probe_only, etc. in asm-mips/pci.h file. This will fix some sparse warnings. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/pci/fixup-vr4133.c | 1 - arch/mips/pci/pci-bcm1480.c | 1 - arch/mips/pci/pci-ip27.c | 1 - arch/mips/pci/pci-sb1250.c | 1 - include/asm-mips/pci.h | 3 +++ 5 files changed, 3 insertions(+), 4 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c index de5e5f6bbf4c..34e651bd2b5e 100644 --- a/arch/mips/pci/fixup-vr4133.c +++ b/arch/mips/pci/fixup-vr4133.c @@ -171,7 +171,6 @@ void i8259_init(void) int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - extern int pci_probe_only; pci_probe_only = 1; #ifdef CONFIG_ROCKHOPPER diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index d19d262157f2..a9060c771840 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -202,7 +202,6 @@ static int __init bcm1480_pcibios_init(void) { uint32_t cmdreg; uint64_t reg; - extern int pci_probe_only; /* CFE will assign PCI resources */ pci_probe_only = 1; diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index a18516925cdd..ce92f82b16d2 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -47,7 +47,6 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) static int num_bridges = 0; bridge_t *bridge; int slot; - extern int pci_probe_only; pci_probe_only = 1; diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 9bc102a1380e..bf639590b8b2 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -210,7 +210,6 @@ static int __init sb1250_pcibios_init(void) void __iomem *io_map_base; uint32_t cmdreg; uint64_t reg; - extern int pci_probe_only; /* CFE will assign PCI resources */ pci_probe_only = 1; diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 301ff2f28012..d3be83436070 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -172,4 +172,7 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } +extern int pci_probe_only; +extern unsigned int pcibios_max_latency; + #endif /* _ASM_PCI_H */ -- cgit v1.2.3 From b29eee4935d9e5952a7ea8543ea499f06fb86808 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Wed, 16 Apr 2008 02:00:45 +0900 Subject: [MIPS] rbtx4927: misc cleanups * Merge tx4927_pci.h into tx4927.h * Kill (broken) external PCI clock frequency reporting * Kill unnecessary wbflush() * Kill unnecessary includes * Kill debug garbages Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/pci/fixup-rbtx4927.c | 1 - arch/mips/pci/ops-tx4927.c | 5 +- arch/mips/tx4927/common/tx4927_dbgio.c | 5 +- arch/mips/tx4927/common/tx4927_prom.c | 8 +- .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 234 +-------------- .../toshiba_rbtx4927/toshiba_rbtx4927_prom.c | 7 +- .../toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 322 +-------------------- include/asm-mips/tx4927/toshiba_rbtx4927.h | 4 - include/asm-mips/tx4927/tx4927.h | 240 ++++++++++++++- include/asm-mips/tx4927/tx4927_pci.h | 268 ----------------- 10 files changed, 266 insertions(+), 828 deletions(-) delete mode 100644 include/asm-mips/tx4927/tx4927_pci.h (limited to 'include/asm-mips') diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 7450c335b387..2d234ca017db 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -38,7 +38,6 @@ #include #include -#include #undef DEBUG #ifdef DEBUG diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 150419c8b414..1bbafeb4a774 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -40,10 +40,7 @@ #include #include #include - -#include -#include -#include +#include /* initialize in setup */ struct resource pci_io_resource = { diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c index d8423e001b2d..ea1ff23f4b72 100644 --- a/arch/mips/tx4927/common/tx4927_dbgio.c +++ b/arch/mips/tx4927/common/tx4927_dbgio.c @@ -28,9 +28,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include -#include +#include u8 getDebugChar(void) { @@ -38,7 +36,6 @@ u8 getDebugChar(void) return (txx9_sio_kdbg_rd()); } - int putDebugChar(u8 byte) { extern int txx9_sio_kdbg_wr( u8 ch ); diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c index 6eed53d8f386..cc2aa9d63e82 100644 --- a/arch/mips/tx4927/common/tx4927_prom.c +++ b/arch/mips/tx4927/common/tx4927_prom.c @@ -30,12 +30,8 @@ */ #include -#include -#include -#include - -#include -#include +#include +#include #include static unsigned int __init tx4927_process_sdccr(unsigned long addr) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 6d31f2a98abf..c18901a75cc4 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -28,8 +28,6 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ - - /* IRQ Device 00 RBTX4927-ISA/00 @@ -112,76 +110,14 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB */ #include -#include #include -#include -#include -#include -#include #include -#include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include #ifdef CONFIG_TOSHIBA_FPCIB0 #include -#include #endif #include - -#undef TOSHIBA_RBTX4927_IRQ_DEBUG - -#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG -#define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000 - -#define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 ) -#define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 ) -#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) - -#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) -#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) -#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) - -#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff -#endif - - -#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG -static const u32 toshiba_rbtx4927_irq_debug_flag = - (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | - TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR -// | TOSHIBA_RBTX4927_IRQ_IOC_INIT -// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE - ); -#endif - - -#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG -#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \ - if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \ - { \ - char tmp[100]; \ - sprintf( tmp, str ); \ - printk( "%s(%s:%u)::%s", __func__, __FILE__, __LINE__, tmp ); \ - } -#else -#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag, str...) -#endif - - - - #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 @@ -207,39 +143,22 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { #define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL #define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL - -u32 bit2num(u32 num) -{ - u32 i; - - for (i = 0; i < (sizeof(num) * 8); i++) { - if (num & (1 << i)) { - return (i); - } - } - return (0); -} - int toshiba_rbtx4927_irq_nested(int sw_irq) { - u32 level3; + u8 level3; level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; if (level3) { - sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); - if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { - goto RETURN; - } - } + sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; #ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) { - int irq = i8259_irq(); - if (irq >= 0) - sw_irq = irq; - } + if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && + tx4927_using_backplane) { + int irq = i8259_irq(); + if (irq >= 0) + sw_irq = irq; + } #endif - - RETURN: + } return (sw_irq); } @@ -250,21 +169,10 @@ static struct irqaction toshiba_rbtx4927_irq_ioc_action = { .name = TOSHIBA_RBTX4927_IOC_NAME }; - -/**********************************************************************************/ -/* Functions for ioc */ -/**********************************************************************************/ - - static void __init toshiba_rbtx4927_irq_ioc_init(void) { int i; - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT, - "beg=%d end=%d\n", - TOSHIBA_RBTX4927_IRQ_IOC_BEG, - TOSHIBA_RBTX4927_IRQ_IOC_END); - for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, @@ -276,37 +184,16 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void) static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) { - volatile unsigned char v; - - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG - || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } + unsigned char v; v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); } - static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) { - volatile unsigned char v; - - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, - "irq=%d\n", irq); - - if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG - || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, - "bad irq=%d\n", irq); - panic("\n"); - } + unsigned char v; v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); @@ -314,7 +201,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) mmiowb(); } - void __init arch_init_irq(void) { extern void tx4927_irq_init(void); @@ -327,102 +213,4 @@ void __init arch_init_irq(void) #endif /* Onboard 10M Ether: High Active */ set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); - - wbflush(); -} - -void toshiba_rbtx4927_irq_dump(char *key) -{ -#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG - { - u32 i, j = 0; - for (i = 0; i < NR_IRQS; i++) { - if (strcmp(irq_desc[i].chip->name, "none") - == 0) - continue; - - if ((i >= 1) - && (irq_desc[i - 1].chip->name == - irq_desc[i].chip->name)) { - j++; - } else { - j = 0; - } - TOSHIBA_RBTX4927_IRQ_DPRINTK - (TOSHIBA_RBTX4927_IRQ_INFO, - "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n", - key, i, i, irq_desc[i].status, - (u32) irq_desc[i].chip, - (u32) irq_desc[i].action, - (u32) (irq_desc[i].action ? irq_desc[i]. - action->handler : 0), - irq_desc[i].depth, - irq_desc[i].chip->name, j); - } - } -#endif -} - -void toshiba_rbtx4927_irq_dump_pics(char *s) -{ - u32 level0_m; - u32 level0_s; - u32 level1_m; - u32 level1_s; - u32 level2; - u32 level2_p; - u32 level2_s; - u32 level3_m; - u32 level3_s; - u32 level4_m; - u32 level4_s; - u32 level5_m; - u32 level5_s; - - if (s == NULL) - s = "null"; - - level0_m = (read_c0_status() & 0x0000ff00) >> 8; - level0_s = (read_c0_cause() & 0x0000ff00) >> 8; - - level1_m = level0_m; - level1_s = level0_s & 0x87; - - level2 = __raw_readl((void __iomem *)0xff1ff6a0UL); - level2_p = (((level2 & 0x10000)) ? 0 : 1); - level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); - - level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; - level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; - - level4_m = inb(0x21); - outb(0x0A, 0x20); - level4_s = inb(0x20); - - level5_m = inb(0xa1); - outb(0x0A, 0xa0); - level5_s = inb(0xa0); - - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "dump_raw_pic() "); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "cp0:m=0x%02x/s=0x%02x ", level0_m, - level0_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "cp0:m=0x%02x/s=0x%02x ", level1_m, - level1_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "pic:e=0x%02x/s=0x%02x ", level2_p, - level2_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "ioc:m=0x%02x/s=0x%02x ", level3_m, - level3_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "sbm:m=0x%02x/s=0x%02x ", level4_m, - level4_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, - "sbs:m=0x%02x/s=0x%02x ", level5_m, - level5_s); - TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", - s); } diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c index f3f86857beae..fdbad4bc6021 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c @@ -30,13 +30,10 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include -#include -#include - -#include +#include #include #include +#include #include void __init prom_init_cmdline(void) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 2203c77b2ce2..185f303c0e2a 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -62,43 +62,10 @@ #include #endif #include -#ifdef CONFIG_PCI -#include -#endif #ifdef CONFIG_SERIAL_TXX9 #include #endif -#undef TOSHIBA_RBTX4927_SETUP_DEBUG - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG -#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 ) -#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 ) -#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 ) -#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 ) - -#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff -#endif - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG -static const u32 toshiba_rbtx4927_setup_debug_flag = - (TOSHIBA_RBTX4927_SETUP_SETUP | - | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 | - TOSHIBA_RBTX4927_SETUP_PCI2); -#endif - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG -#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \ - if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \ - { \ - char tmp[100]; \ - sprintf( tmp, str ); \ - printk( "%s(%s:%u)::%s", __func__, __FILE__, __LINE__, tmp ); \ - } -#else -#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...) -#endif - /* These functions are used for rebooting or halting the machine*/ extern void toshiba_rbtx4927_restart(char *command); extern void toshiba_rbtx4927_halt(void); @@ -124,7 +91,6 @@ unsigned long mips_memory_upper; static int tx4927_ccfg_toeon = 1; static int tx4927_pcic_trdyto = 0; /* default: disabled */ unsigned long tx4927_ce_base[8]; -void tx4927_reset_pci_pcic(void); int tx4927_pci66 = 0; /* 0:auto */ #endif @@ -172,9 +138,6 @@ static int __init tx4927_pcibios_init(void) int busno = 0; /* One bus on the Toshiba */ struct pci_controller *hose = &tx4927_controller; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, - "-\n"); - for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { early_read_config_dword(hose, busno, busno, pci_devfn, PCI_VENDOR_ID, &id); @@ -187,13 +150,6 @@ static int __init tx4927_pcibios_init(void) u8 v08_64; u32 v32_b0; u8 v08_e1; -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG - char *s = " sb/isa --"; -#endif - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", - s); early_read_config_byte(hose, busno, busno, pci_devfn, 0x64, &v08_64); @@ -202,16 +158,6 @@ static int __init tx4927_pcibios_init(void) early_read_config_byte(hose, busno, busno, pci_devfn, 0xe1, &v08_e1); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x64 = 0x%02x\n", s, v08_64); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0xb0 = 0x%02x\n", s, v32_b0); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0xe1 = 0x%02x\n", s, v08_e1); - /* serial irq control */ v08_64 = 0xd0; @@ -222,50 +168,12 @@ static int __init tx4927_pcibios_init(void) v08_e1 &= 0xf0; v08_e1 |= 0x0d; - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x64 = 0x%02x\n", s, v08_64); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0xb0 = 0x%02x\n", s, v32_b0); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0xe1 = 0x%02x\n", s, v08_e1); - early_write_config_byte(hose, busno, busno, pci_devfn, 0x64, v08_64); early_write_config_dword(hose, busno, busno, pci_devfn, 0xb0, v32_b0); early_write_config_byte(hose, busno, busno, pci_devfn, 0xe1, v08_e1); - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG - { - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x64, - &v08_64); - early_read_config_dword(hose, busno, busno, - pci_devfn, 0xb0, - &v32_b0); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0xe1, - &v08_e1); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x64 = 0x%02x\n", s, v08_64); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0xb0 = 0x%02x\n", s, v32_b0); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0xe1 = 0x%02x\n", s, v08_e1); - } -#endif - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", - s); } if (id == 0x91301055) { @@ -274,13 +182,6 @@ static int __init tx4927_pcibios_init(void) u8 v08_41; u8 v08_43; u8 v08_5c; -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG - char *s = " sb/ide --"; -#endif - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", - s); early_read_config_byte(hose, busno, busno, pci_devfn, 0x04, &v08_04); @@ -293,22 +194,6 @@ static int __init tx4927_pcibios_init(void) early_read_config_byte(hose, busno, busno, pci_devfn, 0x5c, &v08_5c); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x04 = 0x%02x\n", s, v08_04); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x09 = 0x%02x\n", s, v08_09); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x41 = 0x%02x\n", s, v08_41); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x43 = 0x%02x\n", s, v08_43); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s beg 0x5c = 0x%02x\n", s, v08_5c); - /* enable ide master/io */ v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); @@ -332,22 +217,6 @@ static int __init tx4927_pcibios_init(void) */ v08_5c |= 0x01; - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x04 = 0x%02x\n", s, v08_04); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x09 = 0x%02x\n", s, v08_09); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x41 = 0x%02x\n", s, v08_41); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x43 = 0x%02x\n", s, v08_43); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s mid 0x5c = 0x%02x\n", s, v08_5c); - early_write_config_byte(hose, busno, busno, pci_devfn, 0x5c, v08_5c); early_write_config_byte(hose, busno, busno, @@ -358,54 +227,11 @@ static int __init tx4927_pcibios_init(void) pci_devfn, 0x41, v08_41); early_write_config_byte(hose, busno, busno, pci_devfn, 0x43, v08_43); - -#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG - { - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x04, - &v08_04); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x09, - &v08_09); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x41, - &v08_41); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x43, - &v08_43); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x5c, - &v08_5c); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x04 = 0x%02x\n", s, v08_04); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x09 = 0x%02x\n", s, v08_09); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x41 = 0x%02x\n", s, v08_41); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x43 = 0x%02x\n", s, v08_43); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, - ":%s end 0x5c = 0x%02x\n", s, v08_5c); - } -#endif - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", - s); } } register_pci_controller(&tx4927_controller); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, - "+\n"); - return 0; } @@ -419,45 +245,13 @@ void __init tx4927_pci_setup(void) static int called = 0; extern unsigned int tx4927_get_mem_size(void); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n"); - mips_memory_upper = tx4927_get_mem_size() << 20; mips_memory_upper += KSEG0; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_memory_upper\n", - mips_memory_upper); mips_pci_io_base = TX4927_PCIIO; mips_pci_io_size = TX4927_PCIIO_SIZE; mips_pci_mem_base = TX4927_PCIMEM; mips_pci_mem_size = TX4927_PCIMEM_SIZE; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_pci_io_base\n", - mips_pci_io_base); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_pci_io_size\n", - mips_pci_io_size); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_pci_mem_base\n", - mips_pci_mem_base); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_pci_mem_size\n", - mips_pci_mem_size); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=pci_io_resource.start\n", - pci_io_resource.start); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=pci_io_resource.end\n", - pci_io_resource.end); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=pci_mem_resource.start\n", - pci_mem_resource.start); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=pci_mem_resource.end\n", - pci_mem_resource.end); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "0x%08lx=mips_io_port_base", - mips_io_port_base); if (!called) { printk ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", @@ -521,29 +315,10 @@ void __init tx4927_pci_setup(void) } printk("Internal(%dMHz)", pciclk / 1000000); - } else { - int pciclk = 0; - int pciclk_setting = *tx4927_pci_clk_ptr; - switch (pciclk_setting & TX4927_PCI_CLK_MASK) { - case TX4927_PCI_CLK_33: - pciclk = 33333333; - break; - case TX4927_PCI_CLK_25: - pciclk = 25000000; - break; - case TX4927_PCI_CLK_66: - pciclk = 66666666; - break; - case TX4927_PCI_CLK_50: - pciclk = 50000000; - break; - } - printk("External(%dMHz)", pciclk / 1000000); - } + } else + printk("External"); printk("\n"); - - /* GB->PCI mappings */ tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; tx4927_pcicptr->g2piogbase = mips_pci_io_base | @@ -644,12 +419,7 @@ void __init tx4927_pci_setup(void) tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - ":pci setup complete:\n"); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n"); } - #endif /* CONFIG_PCI */ static void __noreturn wait_forever(void) @@ -679,7 +449,6 @@ void toshiba_rbtx4927_restart(char *command) /* no return */ } - void toshiba_rbtx4927_halt(void) { printk(KERN_NOTICE "System Halted\n"); @@ -702,33 +471,19 @@ void __init plat_mem_setup(void) printk("CPU is %s\n", toshiba_name); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - "-\n"); - /* f/w leaves this on at startup */ - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":Clearing STO_ERL.\n"); clear_c0_status(ST0_ERL); /* enable caches -- HCP5 does this, pmon does not */ - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n"); cp0_config = read_c0_config(); cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); write_c0_config(cp0_config); set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":mips_io_port_base=0x%08lx\n", - mips_io_port_base); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":Resource\n"); ioport_resource.end = 0xffffffff; iomem_resource.end = 0xffffffff; - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - ":ResetRoutines\n"); _machine_restart = toshiba_rbtx4927_restart; _machine_halt = toshiba_rbtx4927_halt; pm_power_off = toshiba_rbtx4927_power_off; @@ -761,23 +516,6 @@ void __init plat_mem_setup(void) * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) * */ - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, - "ccfg is %lx, PCIDIVMODE is %x\n", - (unsigned long) tx4927_ccfgptr->ccfg, - (unsigned long) tx4927_ccfgptr->ccfg & - (mips_machtype == MACH_TOSHIBA_RBTX4937 ? - TX4937_CCFG_PCIDIVMODE_MASK : - TX4927_CCFG_PCIDIVMODE_MASK)); - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, - "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n", - (unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCI66, - (unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIMIDE, - (unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIXARB); - if (mips_machtype == MACH_TOSHIBA_RBTX4937) switch ((unsigned long)tx4927_ccfgptr-> ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { @@ -818,49 +556,18 @@ void __init plat_mem_setup(void) /* this is on ISA bus behind PCI bus, so need PCI up first */ #ifdef CONFIG_TOSHIBA_FPCIB0 - { - if (tx4927_using_backplane) { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":fpcibo=yes\n"); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_init()\n"); - smsc_fdc37m81x_init(0x3f0); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_beg()\n"); - smsc_fdc37m81x_config_beg(); - - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_set(KBD)\n"); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, - SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, - 1); - - smsc_fdc37m81x_config_end(); - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":smsc_fdc37m81x_config_end()\n"); - } else { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, - ":fpcibo=not_found\n"); - } - } -#else - { - TOSHIBA_RBTX4927_SETUP_DPRINTK - (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n"); + if (tx4927_using_backplane) { + smsc_fdc37m81x_init(0x3f0); + smsc_fdc37m81x_config_beg(); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + smsc_fdc37m81x_config_end(); } #endif - #endif /* CONFIG_PCI */ #ifdef CONFIG_SERIAL_TXX9 @@ -894,17 +601,12 @@ void __init plat_mem_setup(void) } #endif - #ifdef CONFIG_IP_PNP argptr = prom_getcmdline(); if (strstr(argptr, "ip=") == NULL) { strcat(argptr, " ip=any"); } #endif - - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, - "+\n"); } void __init plat_time_init(void) diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index b188a659ce02..d6b32acd6b7b 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -28,9 +28,6 @@ #define __ASM_TX4927_TOSHIBA_RBTX4927_H #include -#ifdef CONFIG_PCI -#include -#endif #ifdef CONFIG_PCI #define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO @@ -44,7 +41,6 @@ #define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL #define RBTX4927_SW_RESET_ENABLE_SET 0x01 - #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) #define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 193e80a17c12..1d4816f3266f 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -36,11 +36,245 @@ #define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) -#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) -#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) +#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) +#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) #define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) -#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) +#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) #define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) +#define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_WR 0x00008000 +#define TX4927_CCFG_TINTDIS 0x01000000 + +#define TX4927_PCIMEM 0x08000000 +#define TX4927_PCIMEM_SIZE 0x08000000 +#define TX4927_PCIIO 0x16000000 +#define TX4927_PCIIO_SIZE 0x01000000 + +#define TX4927_SDRAMC_REG 0xff1f8000 +#define TX4927_EBUSC_REG 0xff1f9000 +#define TX4927_PCIC_REG 0xff1fd000 +#define TX4927_CCFG_REG 0xff1fe000 +#define TX4927_IRC_REG 0xff1ff600 +#define TX4927_NR_TMR 3 +#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) + +/* bits for ISTAT3/IMASK3/IMSTAT3 */ +#define TX4927_INT3B_PCID 0 +#define TX4927_INT3B_PCIC 1 +#define TX4927_INT3B_PCIB 2 +#define TX4927_INT3B_PCIA 3 +#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) +#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) +#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) +#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) + +#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG +#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ + +#define TX4927_IR_PCIC 16 +#define TX4927_IR_PCIERR 22 +#define TX4927_IR_PCIPMA 23 +#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) +#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) +#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) +#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) +#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) +#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) +#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) + +#ifdef _LANGUAGE_ASSEMBLY +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +struct tx4927_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; +}; + +struct tx4927_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4927_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; +}; + +struct tx4927_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmcut; + volatile unsigned long long pdmcnt; /* +220 */ + volatile unsigned long long pdmsts; + volatile unsigned long long unused8[2]; + volatile unsigned long long pdmdb[4]; /* +240 */ + volatile unsigned long long pdmtdh; /* +260 */ + volatile unsigned long long pdmdms; +}; + +#endif /* _LANGUAGE_ASSEMBLY */ + +/* + * PCIC + */ + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4927_PCIC_PBACFG_RPBA 0x00000004 +#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc + +/* bits for PCICCFG */ +#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 +#define TX4927_PCIC_PCICCFG_HRST 0x00000800 +#define TX4927_PCIC_PCICCFG_SRST 0x00000400 +#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 +#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 +#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 +#define TX4927_PCIC_PCICCFG_IISE 0x00000020 +#define TX4927_PCIC_PCICCFG_ATR 0x00000010 +#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4927_CCFG_PCI66 0x00800000 +#define TX4927_CCFG_PCIMIDE 0x00400000 +#define TX4927_CCFG_PCIXARB 0x00002000 +#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 +#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 +#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 +#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 +#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 + +#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 +#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 +#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 +#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 +#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 +#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 +#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 + +/* PCFG : Pin Configuration */ +#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) + +/* CLKCTR : Clock Control */ +#define TX4927_CLKCTR_PCICKD 0x00400000 +#define TX4927_CLKCTR_PCIRST 0x00000040 + +#ifndef _LANGUAGE_ASSEMBLY + +#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) +#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) +#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) +#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) + +#endif /* _LANGUAGE_ASSEMBLY */ + #endif /* __ASM_TX4927_TX4927_H */ diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h deleted file mode 100644 index 0be77df70f2b..000000000000 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - */ -#ifndef __ASM_TX4927_TX4927_PCI_H -#define __ASM_TX4927_TX4927_PCI_H - -#define TX4927_CCFG_TOE 0x00004000 -#define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TINTDIS 0x01000000 - -#define TX4927_PCIMEM 0x08000000 -#define TX4927_PCIMEM_SIZE 0x08000000 -#define TX4927_PCIIO 0x16000000 -#define TX4927_PCIIO_SIZE 0x01000000 - -#define TX4927_SDRAMC_REG 0xff1f8000 -#define TX4927_EBUSC_REG 0xff1f9000 -#define TX4927_PCIC_REG 0xff1fd000 -#define TX4927_CCFG_REG 0xff1fe000 -#define TX4927_IRC_REG 0xff1ff600 -#define TX4927_NR_TMR 3 -#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) -#define TX4927_CE3 0x17f00000 /* 1M */ -#define TX4927_PCIRESET_ADDR 0xbc00f006 -#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) - -#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n)) -#define tx4927_imstat_ptr(n) \ - ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n)) - -/* bits for ISTAT3/IMASK3/IMSTAT3 */ -#define TX4927_INT3B_PCID 0 -#define TX4927_INT3B_PCIC 1 -#define TX4927_INT3B_PCIB 2 -#define TX4927_INT3B_PCIA 3 -#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) -#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) -#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) -#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) - -/* bits for PCI_CLK (S6) */ -#define TX4927_PCI_CLK_HOST 0x80 -#define TX4927_PCI_CLK_MASK (0x0f << 3) -#define TX4927_PCI_CLK_33 (0x01 << 3) -#define TX4927_PCI_CLK_25 (0x04 << 3) -#define TX4927_PCI_CLK_66 (0x09 << 3) -#define TX4927_PCI_CLK_50 (0x0c << 3) -#define TX4927_PCI_CLK_ACK 0x04 -#define TX4927_PCI_CLK_ACE 0x02 -#define TX4927_PCI_CLK_ENDIAN 0x01 -#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG -#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ - -#define TX4927_IR_PCIC 16 -#define TX4927_IR_PCIERR 22 -#define TX4927_IR_PCIPMA 23 -#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) -#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) -#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) -#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) -#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) -#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) -#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) - -#ifdef _LANGUAGE_ASSEMBLY -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include - -#define tx4927_pcireset_ptr \ - ((volatile unsigned char *)TX4927_PCIRESET_ADDR) -#define tx4927_pci_clk_ptr \ - ((volatile unsigned char *)TX4927_PCI_CLK_ADDR) - -struct tx4927_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; -}; - -struct tx4927_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4927_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; -}; - -struct tx4927_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmcut; - volatile unsigned long long pdmcnt; /* +220 */ - volatile unsigned long long pdmsts; - volatile unsigned long long unused8[2]; - volatile unsigned long long pdmdb[4]; /* +240 */ - volatile unsigned long long pdmtdh; /* +260 */ - volatile unsigned long long pdmdms; -}; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * PCIC - */ - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 -#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc - -/* bits for PCICCFG */ -#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 -#define TX4927_PCIC_PCICCFG_HRST 0x00000800 -#define TX4927_PCIC_PCICCFG_SRST 0x00000400 -#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 -#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 -#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 -#define TX4927_PCIC_PCICCFG_IISE 0x00000020 -#define TX4927_PCIC_PCICCFG_ATR 0x00000010 -#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4927_CCFG_PCI66 0x00800000 -#define TX4927_CCFG_PCIMIDE 0x00400000 -#define TX4927_CCFG_PCIXARB 0x00002000 -#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 -#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 -#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 -#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 -#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 - -#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 -#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 -#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 -#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 -#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 -#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 -#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 -#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 - -/* PCFG : Pin Configuration */ -#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) - -/* CLKCTR : Clock Control */ -#define TX4927_CLKCTR_PCICKD 0x00400000 -#define TX4927_CLKCTR_PCIRST 0x00000040 - - -#ifndef _LANGUAGE_ASSEMBLY - -#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) -#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) -#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) -#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) - -#endif /* _LANGUAGE_ASSEMBLY */ - -#endif /* __ASM_TX4927_TX4927_PCI_H */ -- cgit v1.2.3 From 2157bc68711bf0e69f9aca4d310bd863298fbb3f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 15 Jul 2008 18:44:33 +0100 Subject: [MIPS] Atlas: Remove support code. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 32 - arch/mips/Makefile | 9 - arch/mips/configs/atlas_defconfig | 1472 ---------------------------- arch/mips/configs/bcm47xx_defconfig | 1 - arch/mips/configs/bigsur_defconfig | 1 - arch/mips/configs/capcella_defconfig | 1 - arch/mips/configs/cobalt_defconfig | 1 - arch/mips/configs/db1000_defconfig | 1 - arch/mips/configs/db1100_defconfig | 1 - arch/mips/configs/db1200_defconfig | 1 - arch/mips/configs/db1500_defconfig | 1 - arch/mips/configs/db1550_defconfig | 1 - arch/mips/configs/decstation_defconfig | 1 - arch/mips/configs/e55_defconfig | 1 - arch/mips/configs/emma2rh_defconfig | 1 - arch/mips/configs/excite_defconfig | 1 - arch/mips/configs/fulong_defconfig | 1 - arch/mips/configs/ip22_defconfig | 1 - arch/mips/configs/ip27_defconfig | 1 - arch/mips/configs/ip28_defconfig | 1 - arch/mips/configs/ip32_defconfig | 1 - arch/mips/configs/jazz_defconfig | 1 - arch/mips/configs/jmr3927_defconfig | 1 - arch/mips/configs/lasat_defconfig | 1 - arch/mips/configs/malta_defconfig | 1 - arch/mips/configs/mipssim_defconfig | 1 - arch/mips/configs/mpc30x_defconfig | 1 - arch/mips/configs/msp71xx_defconfig | 1 - arch/mips/configs/mtx1_defconfig | 1 - arch/mips/configs/pb1100_defconfig | 1 - arch/mips/configs/pb1500_defconfig | 1 - arch/mips/configs/pb1550_defconfig | 1 - arch/mips/configs/pnx8550-jbs_defconfig | 1 - arch/mips/configs/pnx8550-stb810_defconfig | 1 - arch/mips/configs/rbhma4200_defconfig | 1 - arch/mips/configs/rbhma4500_defconfig | 1 - arch/mips/configs/rm200_defconfig | 1 - arch/mips/configs/sb1250-swarm_defconfig | 1 - arch/mips/configs/sead_defconfig | 1 - arch/mips/configs/tb0219_defconfig | 1 - arch/mips/configs/tb0226_defconfig | 1 - arch/mips/configs/tb0287_defconfig | 1 - arch/mips/configs/workpad_defconfig | 1 - arch/mips/configs/wrppmc_defconfig | 1 - arch/mips/configs/yosemite_defconfig | 1 - arch/mips/mips-boards/atlas/Makefile | 22 - arch/mips/mips-boards/atlas/atlas_gdb.c | 97 -- arch/mips/mips-boards/atlas/atlas_int.c | 272 ----- arch/mips/mips-boards/atlas/atlas_setup.c | 82 -- arch/mips/mips-boards/generic/console.c | 11 +- arch/mips/mips-boards/generic/init.c | 8 - arch/mips/mips-boards/generic/reset.c | 17 - arch/mips/mips-boards/generic/time.c | 5 +- arch/mips/pci/Makefile | 1 - arch/mips/pci/fixup-atlas.c | 91 -- include/asm-mips/mach-atlas/mc146818rtc.h | 60 -- 56 files changed, 2 insertions(+), 2219 deletions(-) delete mode 100644 arch/mips/configs/atlas_defconfig delete mode 100644 arch/mips/mips-boards/atlas/Makefile delete mode 100644 arch/mips/mips-boards/atlas/atlas_gdb.c delete mode 100644 arch/mips/mips-boards/atlas/atlas_int.c delete mode 100644 arch/mips/mips-boards/atlas/atlas_setup.c delete mode 100644 arch/mips/pci/fixup-atlas.c delete mode 100644 include/asm-mips/mach-atlas/mc146818rtc.h (limited to 'include/asm-mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 21d6ec1e5368..6383c700686c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -181,38 +181,6 @@ config LEMOTE_FULONG Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and an FPGA northbridge -config MIPS_ATLAS - bool "MIPS Atlas board" - select BOOT_ELF32 - select BOOT_RAW - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select SYS_HAS_EARLY_PRINTK - select IRQ_CPU - select HW_HAS_PCI - select MIPS_BOARDS_GEN - select MIPS_BONITO64 - select PCI_GT64XXX_PCI0 - select MIPS_MSC - select RM7000_CPU_SCACHE - select SWAP_IO_SPACE - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_CPU_MIPS64_R1 - select SYS_HAS_CPU_NEVADA - select SYS_HAS_CPU_RM7000 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL - select SYS_SUPPORTS_SMARTMIPS - select GENERIC_HARDIRQS_NO__DO_IRQ - help - This enables support for the MIPS Technologies Atlas evaluation - board. - config MIPS_MALTA bool "MIPS Malta board" select ARCH_MAY_HAVE_PC_FDC diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0b8d82d55c66..9bc2c763909f 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -309,15 +309,6 @@ cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote # core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ -# -# MIPS Atlas board -# -core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/ -cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas -cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips -load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 -all-$(CONFIG_MIPS_ATLAS) := vmlinux.bin - # # MIPS Malta board # diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig deleted file mode 100644 index 3443f6cd57bb..000000000000 --- a/arch/mips/configs/atlas_defconfig +++ /dev/null @@ -1,1472 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Sun Feb 18 21:27:35 2007 -# -CONFIG_MIPS=y - -# -# Machine selection -# -CONFIG_ZONE_DMA=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -CONFIG_MIPS_ATLAS=y -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_MIPS_BONITO64=y -CONFIG_MIPS_MSC=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_BOARDS_GEN=y -CONFIG_MIPS_GT64120=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_CPU_MIPS64_R1=y -CONFIG_SYS_HAS_CPU_NEVADA=y -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPSR1=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_RM7000_CPU_SCACHE=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -# CONFIG_CPU_HAS_SMARTMIPS is not set -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_SMARTMIPS=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -# CONFIG_HZ_48 is not set -CONFIG_HZ_100=y -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -# CONFIG_HZ_1000 is not set -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=100 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set -# CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_RELAY=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# PCI Hotplug Support -# -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# -CONFIG_NET=y - -# -# Networking options -# -# CONFIG_NETDEBUG is not set -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# -CONFIG_IP_VS=m -# CONFIG_IP_VS_DEBUG is not set -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m -CONFIG_IPV6=m -CONFIG_IPV6_PRIVACY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=y -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_IPRANGE=m -CONFIG_IP_NF_MATCH_TOS=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_OWNER=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_SAME=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_TOS=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration (EXPERIMENTAL) -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_OWNER=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_RAW=m - -# -# Bridge: Netfilter Configuration -# -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_ULOG=m - -# -# DCCP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y - -# -# TIPC Configuration (EXPERIMENTAL) -# -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -# CONFIG_DECNET is not set -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_IPDDP_ENCAP=y -CONFIG_IPDDP_DECAP=y -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_FIFO=y -CONFIG_NET_SCH_CLK_JIFFIES=y -# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set -# CONFIG_NET_SCH_CLK_CPU is not set - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_INGRESS=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -# CONFIG_CLS_U32_PERF is not set -# CONFIG_CLS_U32_MARK is not set -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_POLICE=y -CONFIG_NET_CLS_IND=y -CONFIG_NET_ESTIMATOR=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y -CONFIG_FIB_RULES=y - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# -CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_UMEM=m -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=m - -# -# Misc devices -# -CONFIG_SGI_IOC4=m -# CONFIG_TIFM_CORE is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_IDE_ARM is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_TGT=m -CONFIG_SCSI_NETLINK=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=m -CONFIG_CHR_DEV_SCH=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=y -CONFIG_SCSI_FC_ATTRS=y -CONFIG_SCSI_ISCSI_ATTRS=m -CONFIG_SCSI_SAS_ATTRS=m -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SAS_LIBSAS_DEBUG=y - -# -# SCSI low-level drivers -# -CONFIG_ISCSI_TCP=m -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_AIC79XX is not set -CONFIG_SCSI_AIC94XX=m -# CONFIG_AIC94XX_DEBUG is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_STEX is not set -CONFIG_SCSI_SYM53C8XX_2=y -CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 -CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -CONFIG_SCSI_SYM53C8XX_MMIO=y -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_SRP is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# -# CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID5_RESHAPE=y -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_EMC=m - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_IEEE1394 is not set - -# -# I2O device support -# -# CONFIG_I2O is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# PHY device support -# -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -CONFIG_VITESSE_PHY=m -CONFIG_SMSC_PHY=m -# CONFIG_BROADCOM_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_DM9000 is not set - -# -# Tulip family network device support -# -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -# CONFIG_PCNET32_NAPI is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set -# CONFIG_EEPRO100 is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -CONFIG_LAN_SAA9730=y -# CONFIG_SC92031 is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -CONFIG_QLA3XXX=m -# CONFIG_ATL1 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -CONFIG_CHELSIO_T3=m -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -CONFIG_NETXEN_NIC=m - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -CONFIG_INPUT_MOUSE=y -# CONFIG_MOUSE_PS2 is not set -CONFIG_MOUSE_SERIAL=m -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=y -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=m -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# HID Devices -# -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# -# CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=m -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -CONFIG_XFS_QUOTA=y -CONFIG_XFS_SECURITY=y -CONFIG_XFS_POSIX_ACL=y -# CONFIG_XFS_RT is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -CONFIG_MINIX_FS=m -CONFIG_ROMFS_FS=m -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=y -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m -CONFIG_GENERIC_ACL=y - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -CONFIG_AFFS_FS=m -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_CRAMFS=m -CONFIG_VXFS_FS=m -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -# CONFIG_NFSD_V3_ACL is not set -# CONFIG_NFSD_V4 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=m -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# -CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=m -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=m -CONFIG_CRC32=y -CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index c0e42e74dfbd..10d83e4aca58 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -16,7 +16,6 @@ CONFIG_BCM47XX=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 2b4ad5f3e959..a9926861f14c 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index a94f14b5c8fa..ee8a7fc99f54 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index b7295e988381..ce31a47f1a15 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS_COBALT=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 36578968d386..f99b6f8c9788 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1000=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 5a90740c363a..0d6ba9e65ff5 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1100=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 76f37a1159fe..0c6f2a469f09 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1200=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 508c91944f30..02db28f5dc03 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1500=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 0c2c70d21db9..a0f19f2e7d59 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_DB1550=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 58c2cd68c3a7..c1ab8a21bb07 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set CONFIG_MACH_DECSTATION=y # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 90d81f5dcebc..88c2420bc627 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig index f9a003c2b3a1..03f0baad1b67 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/emma2rh_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig index 15efacc75d73..873597a4aaf1 100644 --- a/arch/mips/configs/excite_defconfig +++ b/arch/mips/configs/excite_defconfig @@ -27,7 +27,6 @@ CONFIG_BASLER_EXCITE=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig index 5887a1735fba..13e1ef2240ea 100644 --- a/arch/mips/configs/fulong_defconfig +++ b/arch/mips/configs/fulong_defconfig @@ -14,7 +14,6 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 4f5e56c9335e..7daf203c1481 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -15,7 +15,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index f40e437bd9e5..83d769f941d6 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index ec188be9a67a..3c5090a248b7 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 2c5c624c5d42..f8d1cf3e8749 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 56148745e8f2..72ff710c878f 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set CONFIG_MACH_JAZZ=y -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index a7cd67753aac..8dc8bef471b4 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig index e6aef999854c..a8fa2055c071 100644 --- a/arch/mips/configs/lasat_defconfig +++ b/arch/mips/configs/lasat_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set CONFIG_LASAT=y # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 3d0da952811c..9a8ed74cc1a9 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -15,7 +15,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set CONFIG_MIPS_MALTA=y # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 4f6bce99d5cf..1d205446ee70 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set CONFIG_MIPS_SIM=y diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 27e23fc9363a..0c7f35acb702 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index b12b73f6d74f..2dd2a4f38fbe 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index fa3aa3919448..17d66526fa48 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -14,7 +14,6 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 1d0157d3a5bb..eaf608ca65a6 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_PB1100=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index d0491a05ee58..62c5a7098ab1 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_PB1500=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 16d78d3cd2aa..29c8548b68f7 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -27,7 +27,6 @@ CONFIG_MIPS_PB1550=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 780c7fc24b82..c714f43e7dc8 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index 267f21ed1d0f..c1adcfac6c54 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig index 470f6f4d3ea2..9e1083626292 100644 --- a/arch/mips/configs/rbhma4200_defconfig +++ b/arch/mips/configs/rbhma4200_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 5a39f56b175e..462a652ee022 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 56371b860eb0..2562f355dbf1 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 4b8799802788..ff89765f87f7 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 3ee75b15c0b0..d3db59bf399b 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set CONFIG_MIPS_SEAD=y # CONFIG_WR_PPMC is not set diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index 8dd3ae39bcad..34ce11de5367 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index 2ba240e897c6..e5ae6b1839b2 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index a5d0f3c55ed1..2fdfd6659ef1 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index edf90b321fe6..ee411216d373 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -14,7 +14,6 @@ CONFIG_MIPS=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index 2e3c683b2052..66d3c11a0382 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set CONFIG_WR_PPMC=y diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index b6178ffbc523..daa4e48a7232 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -26,7 +26,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set diff --git a/arch/mips/mips-boards/atlas/Makefile b/arch/mips/mips-boards/atlas/Makefile deleted file mode 100644 index f71c2dd1041a..000000000000 --- a/arch/mips/mips-boards/atlas/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# - -obj-y := atlas_int.o atlas_setup.o -obj-$(CONFIG_KGDB) += atlas_gdb.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/atlas/atlas_gdb.c b/arch/mips/mips-boards/atlas/atlas_gdb.c deleted file mode 100644 index 00c98cff62dc..000000000000 --- a/arch/mips/mips-boards/atlas/atlas_gdb.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * This is the interface to the remote debugger stub. - */ -#include -#include -#include - -#define INB(a) inb((unsigned long)a) -#define OUTB(x, a) outb(x, (unsigned long)a) - -/* - * This is the interface to the remote debugger stub - * if the Philips part is used for the debug port, - * called from the platform setup code. - */ -void *saa9730_base = (void *)ATLAS_SAA9730_REG; - -static int saa9730_kgdb_active = 0; - -#define SAA9730_BAUDCLOCK(baud) (((ATLAS_SAA9730_BAUDCLOCK/(baud))/16)-1) - -int saa9730_kgdb_hook(int speed) -{ - int baudclock; - t_uart_saa9730_regmap *kgdb_uart = (t_uart_saa9730_regmap *)(saa9730_base + SAA9730_UART_REGS_ADDR); - - /* - * Clear all interrupts - */ - (void) INB(&kgdb_uart->Lsr); - (void) INB(&kgdb_uart->Msr); - (void) INB(&kgdb_uart->Thr_Rbr); - (void) INB(&kgdb_uart->Iir_Fcr); - - /* - * Now, initialize the UART - */ - /* 8 data bits, one stop bit, no parity */ - OUTB(SAA9730_LCR_DATA8, &kgdb_uart->Lcr); - - baudclock = SAA9730_BAUDCLOCK(speed); - - OUTB((baudclock >> 16) & 0xff, &kgdb_uart->BaudDivMsb); - OUTB( baudclock & 0xff, &kgdb_uart->BaudDivLsb); - - /* Set RTS/DTR active */ - OUTB(SAA9730_MCR_DTR | SAA9730_MCR_RTS, &kgdb_uart->Mcr); - saa9730_kgdb_active = 1; - - return speed; -} - -int saa9730_putDebugChar(char c) -{ - t_uart_saa9730_regmap *kgdb_uart = (t_uart_saa9730_regmap *)(saa9730_base + SAA9730_UART_REGS_ADDR); - - if (!saa9730_kgdb_active) { /* need to init device first */ - return 0; - } - - while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_THRE)) - ; - OUTB(c, &kgdb_uart->Thr_Rbr); - - return 1; -} - -char saa9730_getDebugChar(void) -{ - t_uart_saa9730_regmap *kgdb_uart = (t_uart_saa9730_regmap *)(saa9730_base + SAA9730_UART_REGS_ADDR); - char c; - - if (!saa9730_kgdb_active) { /* need to init device first */ - return 0; - } - while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_DR)) - ; - - c = INB(&kgdb_uart->Thr_Rbr); - return(c); -} diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c deleted file mode 100644 index 6fb29c3ff62d..000000000000 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2006 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Routines for generic manipulation of the interrupts found on the MIPS - * Atlas board. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -static struct atlas_ictrl_regs *atlas_hw0_icregs; - -#if 0 -#define DEBUG_INT(x...) printk(x) -#else -#define DEBUG_INT(x...) -#endif - -void disable_atlas_irq(unsigned int irq_nr) -{ - atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE); - iob(); -} - -void enable_atlas_irq(unsigned int irq_nr) -{ - atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE); - iob(); -} - -static void end_atlas_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_atlas_irq(irq); -} - -static struct irq_chip atlas_irq_type = { - .name = "Atlas", - .ack = disable_atlas_irq, - .mask = disable_atlas_irq, - .mask_ack = disable_atlas_irq, - .unmask = enable_atlas_irq, - .eoi = enable_atlas_irq, - .end = end_atlas_irq, -}; - -static inline int ls1bit32(unsigned int x) -{ - int b = 31, s; - - s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; - s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; - s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; - s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; - s = 1; if (x << 1 == 0) s = 0; b -= s; - - return b; -} - -static inline void atlas_hw0_irqdispatch(void) -{ - unsigned long int_status; - int irq; - - int_status = atlas_hw0_icregs->intstatus; - - /* if int_status == 0, then the interrupt has already been cleared */ - if (unlikely(int_status == 0)) - return; - - irq = ATLAS_INT_BASE + ls1bit32(int_status); - - DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq); - - do_IRQ(irq); -} - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = s0 & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0x8000; - t0 = t0 < 1; - //t0 = t0 << 2; - a0 = a0 - t0; - //s0 = s0 << t0; - - return a0; -#endif -} - -/* - * IRQs on the Atlas board look basically like (all external interrupt - * sources are combined together on hardware interrupt 0 (MIPS IRQ 2)): - * - * MIPS IRQ Source - * -------- ------ - * 0 Software 0 (reschedule IPI on MT) - * 1 Software 1 (remote call IPI on MT) - * 2 Combined Atlas hardware interrupt (hw0) - * 3 Hardware (ignored) - * 4 Hardware (ignored) - * 5 Hardware (ignored) - * 6 Hardware (ignored) - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Lowest ---- Software 0 - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq == MIPSCPU_INT_ATLAS) - atlas_hw0_irqdispatch(); - else if (irq >= 0) - do_IRQ(MIPS_CPU_IRQ_BASE + irq); - else - spurious_interrupt(); -} - -static inline void init_atlas_irqs(int base) -{ - int i; - - atlas_hw0_icregs = (struct atlas_ictrl_regs *) - ioremap(ATLAS_ICTRL_REGS_BASE, - sizeof(struct atlas_ictrl_regs *)); - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - atlas_hw0_icregs->intrsten = 0xffffffff; - - for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) - set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq); -} - -static struct irqaction atlasirq = { - .handler = no_action, - .name = "Atlas cascade" -}; - -msc_irqmap_t __initdata msc_irqmap[] = { - {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, - {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, -}; -int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); - -msc_irqmap_t __initdata msc_eicirqmap[] = { - {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_ATLAS, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, - {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} -}; -int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); - -void __init arch_init_irq(void) -{ - init_atlas_irqs(ATLAS_INT_BASE); - - if (!cpu_has_veic) - mips_cpu_irq_init(); - - switch(mips_revision_corid) { - case MIPS_REVISION_CORID_CORE_MSC: - case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_FPGA3: - case MIPS_REVISION_CORID_CORE_FPGA4: - case MIPS_REVISION_CORID_CORE_24K: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: - if (cpu_has_veic) - init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE, - msc_eicirqmap, msc_nr_eicirqs); - else - init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE, - msc_irqmap, msc_nr_irqs); - } - - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch); - setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq); - } else if (cpu_has_vint) { - set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch); -#ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, - &atlasirq, (0x100 << MIPSCPU_INT_ATLAS)); -#else /* Not SMTC */ - setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); -#endif /* CONFIG_MIPS_MT_SMTC */ - } else - setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); -} diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c deleted file mode 100644 index 5c500802271e..000000000000 --- a/arch/mips/mips-boards/atlas/atlas_setup.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void __init serial_init(void); - -const char *get_system_type(void) -{ - return "MIPS Atlas"; -} - -const char display_string[] = " LINUX ON ATLAS "; - -void __init plat_mem_setup(void) -{ - mips_pcibios_init(); - - ioport_resource.end = 0x7fffffff; - - serial_init(); - -#ifdef CONFIG_KGDB - kgdb_config(); -#endif - mips_reboot_setup(); -} - -static void __init serial_init(void) -{ -#ifdef CONFIG_SERIAL_8250 - struct uart_port s; - - memset(&s, 0, sizeof(s)); - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - s.iobase = ATLAS_UART_REGS_BASE; -#else - s.iobase = ATLAS_UART_REGS_BASE+3; -#endif - s.irq = ATLAS_INT_UART; - s.uartclk = ATLAS_BASE_BAUD * 16; - s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ; - s.iotype = UPIO_PORT; - s.regshift = 3; - - if (early_serial_setup(&s) != 0) { - printk(KERN_ERR "Serial setup failed!\n"); - } -#endif -} diff --git a/arch/mips/mips-boards/generic/console.c b/arch/mips/mips-boards/generic/console.c index 4d8ab99e4155..4a2aecc6da1b 100644 --- a/arch/mips/mips-boards/generic/console.c +++ b/arch/mips/mips-boards/generic/console.c @@ -22,16 +22,7 @@ #include #include -#ifdef CONFIG_MIPS_ATLAS -#include - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define PORT(offset) (ATLAS_UART_REGS_BASE + ((offset)<<3)) -#else -#define PORT(offset) (ATLAS_UART_REGS_BASE + 3 + ((offset)<<3)) -#endif - -#elif defined(CONFIG_MIPS_SEAD) +#if defined(CONFIG_MIPS_SEAD) #include diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 83b9dc739203..bac23b5fbf3f 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -197,14 +197,6 @@ void __init kgdb_config(void) while ((c = *++argptr) && ('0' <= c && c <= '9')) speed = speed * 10 + c - '0'; } -#ifdef CONFIG_MIPS_ATLAS - if (line == 1) { - speed = saa9730_kgdb_hook(speed); - generic_putDebugChar = saa9730_putDebugChar; - generic_getDebugChar = saa9730_getDebugChar; - } - else -#endif { speed = rs_kgdb_hook(line, speed); generic_putDebugChar = rs_putDebugChar; diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c index 583d468d98a9..5f73ff6180eb 100644 --- a/arch/mips/mips-boards/generic/reset.c +++ b/arch/mips/mips-boards/generic/reset.c @@ -27,15 +27,9 @@ #include #include #include -#if defined(CONFIG_MIPS_ATLAS) -#include -#endif static void mips_machine_restart(char *command); static void mips_machine_halt(void); -#if defined(CONFIG_MIPS_ATLAS) -static void atlas_machine_power_off(void); -#endif static void mips_machine_restart(char *command) { @@ -53,22 +47,11 @@ static void mips_machine_halt(void) __raw_writel(GORESET, softres_reg); } -#if defined(CONFIG_MIPS_ATLAS) -static void atlas_machine_power_off(void) -{ - unsigned int __iomem *psustby_reg = ioremap(ATLAS_PSUSTBY_REG, sizeof(unsigned int)); - - writew(ATLAS_GOSTBY, psustby_reg); -} -#endif void mips_reboot_setup(void) { _machine_restart = mips_machine_restart; _machine_halt = mips_machine_halt; -#if defined(CONFIG_MIPS_ATLAS) - pm_power_off = atlas_machine_power_off; -#endif #if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_SEAD) pm_power_off = mips_machine_halt; #endif diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index fe2cac1b4514..d224267846b0 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -42,9 +42,6 @@ #include #include -#ifdef CONFIG_MIPS_ATLAS -#include -#endif #ifdef CONFIG_MIPS_MALTA #include #endif @@ -89,7 +86,7 @@ static unsigned int __init estimate_cpu_frequency(void) else count = 6000000; #endif -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) +#ifdef CONFIG_MIPS_MALTA unsigned long flags; unsigned int start; diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index ed0c07622baa..80fa5abb25d4 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -21,7 +21,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o # obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o obj-$(CONFIG_LASAT) += pci-lasat.o -obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c deleted file mode 100644 index 506e883a8c71..000000000000 --- a/arch/mips/pci/fixup-atlas.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * Author: Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include - -#include - -#define PCIA ATLAS_INT_PCIA -#define PCIB ATLAS_INT_PCIB -#define PCIC ATLAS_INT_PCIC -#define PCID ATLAS_INT_PCID -#define INTA ATLAS_INT_INTA -#define INTB ATLAS_INT_INTB -#define ETH ATLAS_INT_ETH -#define INTC ATLAS_INT_INTC -#define SCSI ATLAS_INT_SCSI -#define INTD ATLAS_INT_INTD - -static char irq_tab[][5] __initdata = { - /* INTA INTB INTC INTD */ - {0, 0, 0, 0, 0 }, /* 0: Unused */ - {0, 0, 0, 0, 0 }, /* 1: Unused */ - {0, 0, 0, 0, 0 }, /* 2: Unused */ - {0, 0, 0, 0, 0 }, /* 3: Unused */ - {0, 0, 0, 0, 0 }, /* 4: Unused */ - {0, 0, 0, 0, 0 }, /* 5: Unused */ - {0, 0, 0, 0, 0 }, /* 6: Unused */ - {0, 0, 0, 0, 0 }, /* 7: Unused */ - {0, 0, 0, 0, 0 }, /* 8: Unused */ - {0, 0, 0, 0, 0 }, /* 9: Unused */ - {0, 0, 0, 0, 0 }, /* 10: Unused */ - {0, 0, 0, 0, 0 }, /* 11: Unused */ - {0, 0, 0, 0, 0 }, /* 12: Unused */ - {0, 0, 0, 0, 0 }, /* 13: Unused */ - {0, 0, 0, 0, 0 }, /* 14: Unused */ - {0, PCIA, PCIB, PCIC, PCID }, /* 15: cPCI (behind 21150) */ - {0, SCSI, 0, 0, 0 }, /* 16: SYM53C810A SCSI */ - {0, 0, 0, 0, 0 }, /* 17: Core */ - {0, INTA, INTB, INTC, INTD }, /* 18: PCI Slot */ - {0, ETH, 0, 0, 0 }, /* 19: SAA9730 Eth. et al. */ - {0, 0, 0, 0, 0 }, /* 20: Unused */ - {0, 0, 0, 0, 0 } /* 21: Unused */ -}; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_tab[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -#ifdef CONFIG_KGDB -/* - * The PCI scan may have moved the saa9730 I/O address, so reread - * the address here. - * This does mean that it's not possible to debug the PCI bus configuration - * code, but it is better than nothing... - */ - -static void atlas_saa9730_base_fixup(struct pci_dev *pdev) -{ - extern void *saa9730_base; - if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19) - (void) pci_read_config_dword(pdev, 0x14, (u32 *)&saa9730_base); - printk("saa9730_base = %x\n", saa9730_base); -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730, - atlas_saa9730_base_fixup); - -#endif diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h deleted file mode 100644 index 51d337e1bbd1..000000000000 --- a/include/asm-mips/mach-atlas/mc146818rtc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * Copyright (C) 2003, 05 Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef __ASM_MACH_ATLAS_MC146818RTC_H -#define __ASM_MACH_ATLAS_MC146818RTC_H - -#include - -#include - -#include -#include - -#define ARCH_RTC_LOCATION - -#define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8) -#define RTC_IO_EXTENT 0x100 -#define RTC_IOMAPPED 0 -#define RTC_IRQ ATLAS_INT_RTC - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0)); - volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1)); - - *ireg = addr; - return *dreg; -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0)); - volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1)); - - *ireg = addr; - *dreg = data; -} - -#define RTC_ALWAYS_BCD 0 - -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) - -#endif /* __ASM_MACH_ATLAS_MC146818RTC_H */ -- cgit v1.2.3 From 1398ddb2ebdb41e8efe6ba42505fd452704c8405 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 15 Jul 2008 18:44:33 +0100 Subject: [MIPS] SEAD: Remove support code. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 20 - arch/mips/Makefile | 8 - arch/mips/configs/bcm47xx_defconfig | 1 - arch/mips/configs/bigsur_defconfig | 1 - arch/mips/configs/capcella_defconfig | 1 - arch/mips/configs/cobalt_defconfig | 1 - arch/mips/configs/db1000_defconfig | 1 - arch/mips/configs/db1100_defconfig | 1 - arch/mips/configs/db1200_defconfig | 1 - arch/mips/configs/db1500_defconfig | 1 - arch/mips/configs/db1550_defconfig | 1 - arch/mips/configs/decstation_defconfig | 1 - arch/mips/configs/e55_defconfig | 1 - arch/mips/configs/emma2rh_defconfig | 1 - arch/mips/configs/excite_defconfig | 1 - arch/mips/configs/fulong_defconfig | 1 - arch/mips/configs/ip22_defconfig | 1 - arch/mips/configs/ip27_defconfig | 1 - arch/mips/configs/ip28_defconfig | 1 - arch/mips/configs/ip32_defconfig | 1 - arch/mips/configs/jazz_defconfig | 1 - arch/mips/configs/jmr3927_defconfig | 1 - arch/mips/configs/lasat_defconfig | 1 - arch/mips/configs/malta_defconfig | 1 - arch/mips/configs/mipssim_defconfig | 1 - arch/mips/configs/mpc30x_defconfig | 1 - arch/mips/configs/msp71xx_defconfig | 1 - arch/mips/configs/mtx1_defconfig | 1 - arch/mips/configs/pb1100_defconfig | 1 - arch/mips/configs/pb1500_defconfig | 1 - arch/mips/configs/pb1550_defconfig | 1 - arch/mips/configs/pnx8550-jbs_defconfig | 1 - arch/mips/configs/pnx8550-stb810_defconfig | 1 - arch/mips/configs/rbhma4200_defconfig | 1 - arch/mips/configs/rbhma4500_defconfig | 1 - arch/mips/configs/rm200_defconfig | 1 - arch/mips/configs/sb1250-swarm_defconfig | 1 - arch/mips/configs/sead_defconfig | 641 ----------------------------- arch/mips/configs/tb0219_defconfig | 1 - arch/mips/configs/tb0226_defconfig | 1 - arch/mips/configs/tb0287_defconfig | 1 - arch/mips/configs/workpad_defconfig | 1 - arch/mips/configs/wrppmc_defconfig | 1 - arch/mips/configs/yosemite_defconfig | 1 - arch/mips/mips-boards/generic/console.c | 12 - arch/mips/mips-boards/generic/init.c | 4 - arch/mips/mips-boards/generic/reset.c | 2 +- arch/mips/mips-boards/generic/time.c | 5 +- arch/mips/mips-boards/sead/Makefile | 28 -- arch/mips/mips-boards/sead/sead_int.c | 117 ------ arch/mips/mips-boards/sead/sead_setup.c | 77 ---- include/asm-mips/mips-boards/generic.h | 9 - 52 files changed, 2 insertions(+), 962 deletions(-) delete mode 100644 arch/mips/configs/sead_defconfig delete mode 100644 arch/mips/mips-boards/sead/Makefile delete mode 100644 arch/mips/mips-boards/sead/sead_int.c delete mode 100644 arch/mips/mips-boards/sead/sead_setup.c (limited to 'include/asm-mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6383c700686c..a0381427ec5c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -217,26 +217,6 @@ config MIPS_MALTA This enables support for the MIPS Technologies Malta evaluation board. -config MIPS_SEAD - bool "MIPS SEAD board" - select CEVT_R4K - select CSRC_R4K - select IRQ_CPU - select DMA_NONCOHERENT - select SYS_HAS_EARLY_PRINTK - select MIPS_BOARDS_GEN - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_CPU_MIPS32_R2 - select SYS_HAS_CPU_MIPS64_R1 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_SMARTMIPS - help - This enables support for the MIPS Technologies SEAD evaluation - board. - config MIPS_SIM bool 'MIPS simulator (MIPSsim)' select CEVT_R4K diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 9bc2c763909f..800a73db822a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -317,14 +317,6 @@ cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 all-$(CONFIG_MIPS_MALTA) := vmlinux.bin -# -# MIPS SEAD board -# -core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ -cflags-$(CONFIG_MIPS_SEAD) += -Iinclude/asm-mips/mach-mips -load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 -all-$(CONFIG_MIPS_SEAD) := vmlinux.srec - # # MIPS SIM # diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index 10d83e4aca58..d8694332b344 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -17,7 +17,6 @@ CONFIG_BCM47XX=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index a9926861f14c..a3bbbf067a3b 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index ee8a7fc99f54..185df23fd460 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index ce31a47f1a15..2678b7ec3351 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS_COBALT=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index f99b6f8c9788..ebb8ad62b3a3 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1000=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 0d6ba9e65ff5..ad4e5ef65592 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1100=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 0c6f2a469f09..d0dc2e83ad35 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1200=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 02db28f5dc03..9155082313c8 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1500=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index a0f19f2e7d59..e4e324422cd9 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_DB1550=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index c1ab8a21bb07..9e65e6a2dcb3 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y CONFIG_MACH_DECSTATION=y # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 88c2420bc627..1bd84d42b14f 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig index 03f0baad1b67..634bb4eaf132 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/emma2rh_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig index 873597a4aaf1..3572e80356d2 100644 --- a/arch/mips/configs/excite_defconfig +++ b/arch/mips/configs/excite_defconfig @@ -28,7 +28,6 @@ CONFIG_BASLER_EXCITE=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig index 13e1ef2240ea..620980081a30 100644 --- a/arch/mips/configs/fulong_defconfig +++ b/arch/mips/configs/fulong_defconfig @@ -15,7 +15,6 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_PNX8550_JBS is not set diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 7daf203c1481..cc8e6bf2b245 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -16,7 +16,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 83d769f941d6..138c575a0151 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 3c5090a248b7..822b01f643e3 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index f8d1cf3e8749..fe4699df9626 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 72ff710c878f..bbacc35d804f 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set CONFIG_MACH_JAZZ=y # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 8dc8bef471b4..92000a3a871d 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig index a8fa2055c071..bc9159fda728 100644 --- a/arch/mips/configs/lasat_defconfig +++ b/arch/mips/configs/lasat_defconfig @@ -16,7 +16,6 @@ CONFIG_MIPS=y CONFIG_LASAT=y # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 9a8ed74cc1a9..55288cf50b72 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -16,7 +16,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set CONFIG_MIPS_MALTA=y -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 1d205446ee70..2c0a6314e901 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set CONFIG_MIPS_SIM=y # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 0c7f35acb702..8c720e51795b 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index 2dd2a4f38fbe..59d19472b161 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 17d66526fa48..bacf0dd0e345 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -15,7 +15,6 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index eaf608ca65a6..6dfe6f793cef 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_PB1100=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 62c5a7098ab1..c965a87e6a96 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_PB1500=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 29c8548b68f7..0778996c682f 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -28,7 +28,6 @@ CONFIG_MIPS_PB1550=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index c714f43e7dc8..37c7b5ffd474 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index c1adcfac6c54..893e5c4ab66d 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig index 9e1083626292..f89482a2aa6b 100644 --- a/arch/mips/configs/rbhma4200_defconfig +++ b/arch/mips/configs/rbhma4200_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 462a652ee022..70cf69761673 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 2562f355dbf1..0f4da0325ea4 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index ff89765f87f7..1ea97865f2ce 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set # CONFIG_MACH_VR41XX is not set diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig deleted file mode 100644 index d3db59bf399b..000000000000 --- a/arch/mips/configs/sead_defconfig +++ /dev/null @@ -1,641 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Sun Feb 18 21:28:10 2007 -# -CONFIG_MIPS=y - -# -# Machine selection -# -CONFIG_ZONE_DMA=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_SEAD=y -# CONFIG_WR_PPMC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_MIPS_BOARDS_GEN=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_CPU_MIPS64_R1=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPSR1=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set -# CONFIG_64BIT_PHYS_ADDR is not set -CONFIG_CPU_HAS_LLSC=y -# CONFIG_CPU_HAS_SMARTMIPS is not set -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_SMARTMIPS=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_UTS_NS is not set -# CONFIG_IKCONFIG is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_RELAY=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_HOTPLUG is not set -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# Block layer -# -CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# - -# -# PCI Hotplug Support -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Power management options -# -CONFIG_PM=y -# CONFIG_PM_LEGACY is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_SYSFS_DEPRECATED is not set - -# -# Networking -# -# CONFIG_NET is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=18432 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CDROM_PKTCDVD is not set - -# -# Misc devices -# - -# -# ATA/ATAPI/MFM/RLL support -# -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=y -# CONFIG_SCSI is not set -# CONFIG_SCSI_NETLINK is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# -# CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# ISDN subsystem -# - -# -# Telephony Support -# -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# SPI support -# -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# -# CONFIG_W1 is not set - -# -# Hardware Monitoring support -# -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# - -# -# Graphics support -# -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# -# CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MSDOS_PARTITION is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# -# CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="" - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Library routines -# -# CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y -# CONFIG_CRC32 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index 34ce11de5367..b5059881bc7e 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index e5ae6b1839b2..b06a716bf23f 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 2fdfd6659ef1..46512cf7ce04 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -17,7 +17,6 @@ CONFIG_MIPS=y # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index ee411216d373..b437eb7f8672 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -15,7 +15,6 @@ CONFIG_MIPS=y # CONFIG_MACH_JAZZ is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_MIPS_SIM is not set # CONFIG_MARKEINS is not set CONFIG_MACH_VR41XX=y diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index 66d3c11a0382..fc2c56731b98 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set CONFIG_WR_PPMC=y # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index daa4e48a7232..7f86c43d1bda 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -27,7 +27,6 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SEAD is not set # CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set # CONFIG_MOMENCO_JAGUAR_ATX is not set diff --git a/arch/mips/mips-boards/generic/console.c b/arch/mips/mips-boards/generic/console.c index 4a2aecc6da1b..43bcfb4f8167 100644 --- a/arch/mips/mips-boards/generic/console.c +++ b/arch/mips/mips-boards/generic/console.c @@ -22,21 +22,9 @@ #include #include -#if defined(CONFIG_MIPS_SEAD) - -#include - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define PORT(offset) (SEAD_UART0_REGS_BASE + ((offset)<<3)) -#else -#define PORT(offset) (SEAD_UART0_REGS_BASE + 3 + ((offset)<<3)) -#endif - -#else #define PORT(offset) (0x3f8 + (offset)) -#endif static inline unsigned int serial_in(int offset) { diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index bac23b5fbf3f..c0653021a171 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -252,9 +252,6 @@ void __init prom_init(void) mips_display_message("LINUX"); -#ifdef CONFIG_MIPS_SEAD - set_io_port_base(KSEG1); -#else /* * early setup of _pcictrl_bonito so that we can determine * the system controller on a CORE_EMUL board @@ -406,7 +403,6 @@ void __init prom_init(void) mips_display_message("SC Error"); while (1); /* We die here... */ } -#endif board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c index 5f73ff6180eb..ea932b843962 100644 --- a/arch/mips/mips-boards/generic/reset.c +++ b/arch/mips/mips-boards/generic/reset.c @@ -52,7 +52,7 @@ void mips_reboot_setup(void) { _machine_restart = mips_machine_restart; _machine_halt = mips_machine_halt; -#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_SEAD) +#ifdef CONFIG_MIPS_MALTA pm_power_off = mips_machine_halt; #endif } diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index d224267846b0..637897e8e4fb 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -45,9 +45,6 @@ #ifdef CONFIG_MIPS_MALTA #include #endif -#ifdef CONFIG_MIPS_SEAD -#include -#endif unsigned long cpu_khz; @@ -73,7 +70,7 @@ static unsigned int __init estimate_cpu_frequency(void) unsigned int prid = read_c0_prid() & 0xffff00; unsigned int count; -#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) +#ifdef CONFIG_MIPS_SIM /* * The SEAD board doesn't have a real time clock, so we can't * really calculate the timer frequency diff --git a/arch/mips/mips-boards/sead/Makefile b/arch/mips/mips-boards/sead/Makefile deleted file mode 100644 index 3682fe217bd5..000000000000 --- a/arch/mips/mips-boards/sead/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. -# -# ######################################################################## -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# ####################################################################### -# -# Makefile for the MIPS SEAD specific kernel interface routines -# under Linux. -# - -obj-y := sead_int.o sead_setup.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c deleted file mode 100644 index ec6dd194c14a..000000000000 --- a/arch/mips/mips-boards/sead/sead_int.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2004 Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Routines for generic manipulation of the interrupts found on the MIPS - * Sead board. - */ -#include -#include - -#include -#include -#include - -#include - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = s0 & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - s0 = s0 << t0; - - t0 = s0 & 0x8000; - t0 = t0 < 1; - //t0 = t0 << 2; - a0 = a0 - t0; - //s0 = s0 << t0; - - return a0; -#endif -} - -/* - * IRQs on the SEAD board look basically are combined together on hardware - * interrupt 0 (MIPS IRQ 2)) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 UART0 (hw0) - * 3 UART1 (hw1) - * 4 Hardware (ignored) - * 5 Hardware (ignored) - * 6 Hardware (ignored) - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Lowest ---- Combined hardware interrupt - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq >= 0) - do_IRQ(MIPS_CPU_IRQ_BASE + irq); - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(); -} diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c deleted file mode 100644 index 8aa8e5b7b074..000000000000 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * SEAD specific setup. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -static void __init serial_init(void); - -const char *get_system_type(void) -{ - return "MIPS SEAD"; -} - -const char display_string[] = " LINUX ON SEAD "; - -void __init plat_mem_setup(void) -{ - ioport_resource.end = 0x7fffffff; - - serial_init(); - - mips_reboot_setup(); -} - -static void __init serial_init(void) -{ -#ifdef CONFIG_SERIAL_8250 - struct uart_port s; - - memset(&s, 0, sizeof(s)); - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - s.iobase = SEAD_UART0_REGS_BASE; -#else - s.iobase = SEAD_UART0_REGS_BASE+3; -#endif - s.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_UART0; - s.uartclk = SEAD_BASE_BAUD * 16; - s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ; - s.iotype = UPIO_PORT; - s.regshift = 3; - - if (early_serial_setup(&s) != 0) { - printk(KERN_ERR "Serial setup failed!\n"); - } -#endif -} diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index 33407bee4e73..7f0b034dd9a5 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -27,12 +27,8 @@ /* * Display register base. */ -#ifdef CONFIG_MIPS_SEAD -#define ASCII_DISPLAY_POS_BASE 0x1f0005c0 -#else #define ASCII_DISPLAY_WORD_BASE 0x1f000410 #define ASCII_DISPLAY_POS_BASE 0x1f000418 -#endif /* @@ -44,13 +40,8 @@ /* * Reset register. */ -#ifdef CONFIG_MIPS_SEAD -#define SOFTRES_REG 0x1e800050 -#define GORESET 0x4d -#else #define SOFTRES_REG 0x1f000500 #define GORESET 0x42 -#endif /* * Revision register. -- cgit v1.2.3 From 315806cb19f9d375dccbc2d60fa14e16afdcd5ac Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 15 Jul 2008 18:44:34 +0100 Subject: [MIPS] Malta: Cleanup organization of code into directories. Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 5 +- arch/mips/mips-boards/generic/Makefile | 29 - arch/mips/mips-boards/generic/amon.c | 80 --- arch/mips/mips-boards/generic/cmdline.c | 59 -- arch/mips/mips-boards/generic/console.c | 47 -- arch/mips/mips-boards/generic/display.c | 64 -- arch/mips/mips-boards/generic/gdb_hook.c | 133 ---- arch/mips/mips-boards/generic/init.c | 424 ------------ arch/mips/mips-boards/generic/memory.c | 177 ----- arch/mips/mips-boards/generic/pci.c | 243 ------- arch/mips/mips-boards/generic/reset.c | 56 -- arch/mips/mips-boards/generic/time.c | 163 ----- arch/mips/mips-boards/malta/Makefile | 27 - arch/mips/mips-boards/malta/malta_int.c | 712 --------------------- arch/mips/mips-boards/malta/malta_mtd.c | 63 -- arch/mips/mips-boards/malta/malta_platform.c | 65 -- arch/mips/mips-boards/malta/malta_setup.c | 229 ------- arch/mips/mips-boards/malta/malta_smtc.c | 154 ----- arch/mips/mti-malta/Makefile | 21 + arch/mips/mti-malta/malta-amon.c | 80 +++ arch/mips/mti-malta/malta-cmdline.c | 59 ++ arch/mips/mti-malta/malta-console.c | 47 ++ arch/mips/mti-malta/malta-display.c | 64 ++ arch/mips/mti-malta/malta-init.c | 424 ++++++++++++ arch/mips/mti-malta/malta-int.c | 712 +++++++++++++++++++++ arch/mips/mti-malta/malta-kgdb.c | 133 ++++ arch/mips/mti-malta/malta-memory.c | 177 +++++ arch/mips/mti-malta/malta-mtd.c | 63 ++ arch/mips/mti-malta/malta-pci.c | 243 +++++++ arch/mips/mti-malta/malta-platform.c | 65 ++ arch/mips/mti-malta/malta-reset.c | 56 ++ arch/mips/mti-malta/malta-setup.c | 229 +++++++ arch/mips/mti-malta/malta-smtc.c | 154 +++++ arch/mips/mti-malta/malta-time.c | 163 +++++ .../asm-mips/mach-malta/cpu-feature-overrides.h | 72 +++ include/asm-mips/mach-malta/irq.h | 9 + include/asm-mips/mach-malta/kernel-entry-init.h | 52 ++ include/asm-mips/mach-malta/mach-gt64120.h | 19 + include/asm-mips/mach-malta/mc146818rtc.h | 48 ++ include/asm-mips/mach-malta/war.h | 25 + include/asm-mips/mach-mips/cpu-feature-overrides.h | 72 --- include/asm-mips/mach-mips/irq.h | 9 - include/asm-mips/mach-mips/kernel-entry-init.h | 52 -- include/asm-mips/mach-mips/mach-gt64120.h | 19 - include/asm-mips/mach-mips/mc146818rtc.h | 48 -- include/asm-mips/mach-mips/war.h | 25 - 46 files changed, 2917 insertions(+), 2953 deletions(-) delete mode 100644 arch/mips/mips-boards/generic/Makefile delete mode 100644 arch/mips/mips-boards/generic/amon.c delete mode 100644 arch/mips/mips-boards/generic/cmdline.c delete mode 100644 arch/mips/mips-boards/generic/console.c delete mode 100644 arch/mips/mips-boards/generic/display.c delete mode 100644 arch/mips/mips-boards/generic/gdb_hook.c delete mode 100644 arch/mips/mips-boards/generic/init.c delete mode 100644 arch/mips/mips-boards/generic/memory.c delete mode 100644 arch/mips/mips-boards/generic/pci.c delete mode 100644 arch/mips/mips-boards/generic/reset.c delete mode 100644 arch/mips/mips-boards/generic/time.c delete mode 100644 arch/mips/mips-boards/malta/Makefile delete mode 100644 arch/mips/mips-boards/malta/malta_int.c delete mode 100644 arch/mips/mips-boards/malta/malta_mtd.c delete mode 100644 arch/mips/mips-boards/malta/malta_platform.c delete mode 100644 arch/mips/mips-boards/malta/malta_setup.c delete mode 100644 arch/mips/mips-boards/malta/malta_smtc.c create mode 100644 arch/mips/mti-malta/Makefile create mode 100644 arch/mips/mti-malta/malta-amon.c create mode 100644 arch/mips/mti-malta/malta-cmdline.c create mode 100644 arch/mips/mti-malta/malta-console.c create mode 100644 arch/mips/mti-malta/malta-display.c create mode 100644 arch/mips/mti-malta/malta-init.c create mode 100644 arch/mips/mti-malta/malta-int.c create mode 100644 arch/mips/mti-malta/malta-kgdb.c create mode 100644 arch/mips/mti-malta/malta-memory.c create mode 100644 arch/mips/mti-malta/malta-mtd.c create mode 100644 arch/mips/mti-malta/malta-pci.c create mode 100644 arch/mips/mti-malta/malta-platform.c create mode 100644 arch/mips/mti-malta/malta-reset.c create mode 100644 arch/mips/mti-malta/malta-setup.c create mode 100644 arch/mips/mti-malta/malta-smtc.c create mode 100644 arch/mips/mti-malta/malta-time.c create mode 100644 include/asm-mips/mach-malta/cpu-feature-overrides.h create mode 100644 include/asm-mips/mach-malta/irq.h create mode 100644 include/asm-mips/mach-malta/kernel-entry-init.h create mode 100644 include/asm-mips/mach-malta/mach-gt64120.h create mode 100644 include/asm-mips/mach-malta/mc146818rtc.h create mode 100644 include/asm-mips/mach-malta/war.h delete mode 100644 include/asm-mips/mach-mips/cpu-feature-overrides.h delete mode 100644 include/asm-mips/mach-mips/irq.h delete mode 100644 include/asm-mips/mach-mips/kernel-entry-init.h delete mode 100644 include/asm-mips/mach-mips/mach-gt64120.h delete mode 100644 include/asm-mips/mach-mips/mc146818rtc.h delete mode 100644 include/asm-mips/mach-mips/war.h (limited to 'include/asm-mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ed8821ac8a8e..36aa690484c8 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -307,9 +307,8 @@ cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote # # MIPS Malta board # -core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/generic/ \ - arch/mips/mips-boards/malta/ -cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips +core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/ +cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-malta load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 all-$(CONFIG_MIPS_MALTA) := vmlinux.bin diff --git a/arch/mips/mips-boards/generic/Makefile b/arch/mips/mips-boards/generic/Makefile deleted file mode 100644 index f7f87fc09d1e..000000000000 --- a/arch/mips/mips-boards/generic/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# Makefile for the MIPS boards generic routines under Linux. -# - -obj-y := reset.o display.o init.o memory.o \ - cmdline.o time.o -obj-y += amon.o - -obj-$(CONFIG_EARLY_PRINTK) += console.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_KGDB) += gdb_hook.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/generic/amon.c b/arch/mips/mips-boards/generic/amon.c deleted file mode 100644 index 96236bf33838..000000000000 --- a/arch/mips/mips-boards/generic/amon.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2007 MIPS Technologies, Inc. - * All rights reserved. - - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Arbitrary Monitor interface - */ - -#include -#include -#include - -#include -#include -#include - -int amon_cpu_avail(int cpu) -{ - struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - - if (cpu < 0 || cpu >= NCPULAUNCH) { - pr_debug("avail: cpu%d is out of range\n", cpu); - return 0; - } - - launch += cpu; - if (!(launch->flags & LAUNCH_FREADY)) { - pr_debug("avail: cpu%d is not ready\n", cpu); - return 0; - } - if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) { - pr_debug("avail: too late.. cpu%d is already gone\n", cpu); - return 0; - } - - return 1; -} - -void amon_cpu_start(int cpu, - unsigned long pc, unsigned long sp, - unsigned long gp, unsigned long a0) -{ - volatile struct cpulaunch *launch = - (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - - if (!amon_cpu_avail(cpu)) - return; - if (cpu == smp_processor_id()) { - pr_debug("launch: I am cpu%d!\n", cpu); - return; - } - launch += cpu; - - pr_debug("launch: starting cpu%d\n", cpu); - - launch->pc = pc; - launch->gp = gp; - launch->sp = sp; - launch->a0 = a0; - - /* Make sure target sees parameters before the go bit */ - smp_mb(); - - launch->flags |= LAUNCH_FGO; - while ((launch->flags & LAUNCH_FGONE) == 0) - ; - pr_debug("launch: cpu%d gone!\n", cpu); -} diff --git a/arch/mips/mips-boards/generic/cmdline.c b/arch/mips/mips-boards/generic/cmdline.c deleted file mode 100644 index 1871c30ed2eb..000000000000 --- a/arch/mips/mips-boards/generic/cmdline.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Kernel command line creation using the prom monitor (YAMON) argc/argv. - */ -#include -#include - -#include - -extern int prom_argc; -extern int *_prom_argv; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension. - */ -#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv(actr)); - cp += strlen(prom_argv(actr)); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) { - /* get rid of trailing space */ - --cp; - *cp = '\0'; - } -} diff --git a/arch/mips/mips-boards/generic/console.c b/arch/mips/mips-boards/generic/console.c deleted file mode 100644 index 43bcfb4f8167..000000000000 --- a/arch/mips/mips-boards/generic/console.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Putting things on the screen/serial line using YAMONs facilities. - */ -#include -#include -#include -#include - - -#define PORT(offset) (0x3f8 + (offset)) - - -static inline unsigned int serial_in(int offset) -{ - return inb(PORT(offset)); -} - -static inline void serial_out(int offset, int value) -{ - outb(value, PORT(offset)); -} - -int prom_putchar(char c) -{ - while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(UART_TX, c); - - return 1; -} diff --git a/arch/mips/mips-boards/generic/display.c b/arch/mips/mips-boards/generic/display.c deleted file mode 100644 index 7c8828fcb0ad..000000000000 --- a/arch/mips/mips-boards/generic/display.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Display routines for display messages in MIPS boards ascii display. - */ - -#include -#include -#include -#include -#include - -extern const char display_string[]; -static unsigned int display_count; -static unsigned int max_display_count; - -void mips_display_message(const char *str) -{ - static unsigned int __iomem *display = NULL; - int i; - - if (unlikely(display == NULL)) - display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int)); - - for (i = 0; i <= 14; i=i+2) { - if (*str) - __raw_writel(*str++, display + i); - else - __raw_writel(' ', display + i); - } -} - -static void scroll_display_message(unsigned long data); -static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0); - -static void scroll_display_message(unsigned long data) -{ - mips_display_message(&display_string[display_count++]); - if (display_count == max_display_count) - display_count = 0; - - mod_timer(&mips_scroll_timer, jiffies + HZ); -} - -void mips_scroll_message(void) -{ - del_timer_sync(&mips_scroll_timer); - max_display_count = strlen(display_string) + 1 - 8; - mod_timer(&mips_scroll_timer, jiffies + 1); -} diff --git a/arch/mips/mips-boards/generic/gdb_hook.c b/arch/mips/mips-boards/generic/gdb_hook.c deleted file mode 100644 index 6a1854de4579..000000000000 --- a/arch/mips/mips-boards/generic/gdb_hook.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * This is the interface to the remote debugger stub. - */ -#include -#include -#include -#include - -#include -#include - -static struct serial_state rs_table[] = { - SERIAL_PORT_DFNS /* Defined in serial.h */ -}; - -static struct async_struct kdb_port_info = {0}; - -int (*generic_putDebugChar)(char); -char (*generic_getDebugChar)(void); - -static __inline__ unsigned int serial_in(struct async_struct *info, int offset) -{ - return inb(info->port + offset); -} - -static __inline__ void serial_out(struct async_struct *info, int offset, - int value) -{ - outb(value, info->port+offset); -} - -int rs_kgdb_hook(int tty_no, int speed) { - int t; - struct serial_state *ser = &rs_table[tty_no]; - - kdb_port_info.state = ser; - kdb_port_info.magic = SERIAL_MAGIC; - kdb_port_info.port = ser->port; - kdb_port_info.flags = ser->flags; - - /* - * Clear all interrupts - */ - serial_in(&kdb_port_info, UART_LSR); - serial_in(&kdb_port_info, UART_RX); - serial_in(&kdb_port_info, UART_IIR); - serial_in(&kdb_port_info, UART_MSR); - - /* - * Now, initialize the UART - */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ - if (kdb_port_info.flags & ASYNC_FOURPORT) { - kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS; - t = UART_MCR_DTR | UART_MCR_OUT1; - } else { - kdb_port_info.MCR - = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; - t = UART_MCR_DTR | UART_MCR_RTS; - } - - kdb_port_info.MCR = t; /* no interrupts, please */ - serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR); - - /* - * and set the speed of the serial port - */ - if (speed == 0) - speed = 9600; - - t = kdb_port_info.state->baud_base / speed; - /* set DLAB */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB); - serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */ - serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */ - /* reset DLAB */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); - - return speed; -} - -int putDebugChar(char c) -{ - return generic_putDebugChar(c); -} - -char getDebugChar(void) -{ - return generic_getDebugChar(); -} - -int rs_putDebugChar(char c) -{ - - if (!kdb_port_info.state) { /* need to init device first */ - return 0; - } - - while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(&kdb_port_info, UART_TX, c); - - return 1; -} - -char rs_getDebugChar(void) -{ - if (!kdb_port_info.state) { /* need to init device first */ - return 0; - } - - while (!(serial_in(&kdb_port_info, UART_LSR) & 1)) - ; - - return serial_in(&kdb_port_info, UART_RX); -} diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c deleted file mode 100644 index c0653021a171..000000000000 --- a/arch/mips/mips-boards/generic/init.c +++ /dev/null @@ -1,424 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * PROM library initialisation code. - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_KGDB -extern int rs_kgdb_hook(int, int); -extern int rs_putDebugChar(char); -extern char rs_getDebugChar(void); -extern int saa9730_kgdb_hook(int); -extern int saa9730_putDebugChar(char); -extern char saa9730_getDebugChar(void); -#endif - -int prom_argc; -int *_prom_argv, *_prom_envp; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension, if running in 64-bit mode. - */ -#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) - -int init_debug = 0; - -int mips_revision_corid; -int mips_revision_sconid; - -/* Bonito64 system controller register base. */ -unsigned long _pcictrl_bonito; -unsigned long _pcictrl_bonito_pcicfg; - -/* GT64120 system controller register base */ -unsigned long _pcictrl_gt64120; - -/* MIPS System controller register base */ -unsigned long _pcictrl_msc; - -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * In 64-bit mode: we're using 64-bit pointers, but all pointers - * in the PROM structures are only 32-bit, so we need some - * workarounds, if we are running in 64-bit mode. - */ - int i, index=0; - - i = strlen(envname); - - while (prom_envp(index)) { - if(strncmp(envname, prom_envp(index), i) == 0) { - return(prom_envp(index+1)); - } - index += 2; - } - - return NULL; -} - -static inline unsigned char str2hexnum(unsigned char c) -{ - if (c >= '0' && c <= '9') - return c - '0'; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return 0; /* foo */ -} - -static inline void str2eaddr(unsigned char *ea, unsigned char *str) -{ - int i; - - for (i = 0; i < 6; i++) { - unsigned char num; - - if((*str == '.') || (*str == ':')) - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; - } -} - -int get_ethernet_addr(char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = prom_getenv("ethaddr"); - if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); - return -1; - } - str2eaddr(ethernet_addr, ethaddr_str); - - if (init_debug > 1) { - int i; - printk("get_ethernet_addr: "); - for (i=0; i<5; i++) - printk("%02x:", (unsigned char)*(ethernet_addr+i)); - printk("%02x\n", *(ethernet_addr+i)); - } - - return 0; -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static void __init console_config(void) -{ - char console_string[40]; - int baud = 0; - char parity = '\0', bits = '\0', flow = '\0'; - char *s; - - if ((strstr(prom_getcmdline(), "console=")) == NULL) { - s = prom_getenv("modetty0"); - if (s) { - while (*s >= '0' && *s <= '9') - baud = baud*10 + *s++ - '0'; - if (*s == ',') s++; - if (*s) parity = *s++; - if (*s == ',') s++; - if (*s) bits = *s++; - if (*s == ',') s++; - if (*s == 'h') flow = 'r'; - } - if (baud == 0) - baud = 38400; - if (parity != 'n' && parity != 'o' && parity != 'e') - parity = 'n'; - if (bits != '7' && bits != '8') - bits = '8'; - if (flow == '\0') - flow = 'r'; - sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); - strcat(prom_getcmdline(), console_string); - pr_info("Config serial console:%s\n", console_string); - } -} -#endif - -#ifdef CONFIG_KGDB -void __init kgdb_config(void) -{ - extern int (*generic_putDebugChar)(char); - extern char (*generic_getDebugChar)(void); - char *argptr; - int line, speed; - - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { - argptr += strlen("kgdb=ttyS"); - if (*argptr != '0' && *argptr != '1') - printk("KGDB: Unknown serial line /dev/ttyS%c, " - "falling back to /dev/ttyS1\n", *argptr); - line = *argptr == '0' ? 0 : 1; - printk("KGDB: Using serial line /dev/ttyS%d for session\n", line); - - speed = 0; - if (*++argptr == ',') - { - int c; - while ((c = *++argptr) && ('0' <= c && c <= '9')) - speed = speed * 10 + c - '0'; - } - { - speed = rs_kgdb_hook(line, speed); - generic_putDebugChar = rs_putDebugChar; - generic_getDebugChar = rs_getDebugChar; - } - - pr_info("KGDB: Using serial line /dev/ttyS%d at %d for " - "session, please connect your debugger\n", - line ? 1 : 0, speed); - - { - char *s; - for (s = "Please connect GDB to this port\r\n"; *s; ) - generic_putDebugChar(*s++); - } - - /* Breakpoint is invoked after interrupts are initialised */ - } -} -#endif - -static void __init mips_nmi_setup(void) -{ - void *base; - extern char except_vec_nmi; - - base = cpu_has_veic ? - (void *)(CAC_BASE + 0xa80) : - (void *)(CAC_BASE + 0x380); - memcpy(base, &except_vec_nmi, 0x80); - flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); -} - -static void __init mips_ejtag_setup(void) -{ - void *base; - extern char except_vec_ejtag_debug; - - base = cpu_has_veic ? - (void *)(CAC_BASE + 0xa00) : - (void *)(CAC_BASE + 0x300); - memcpy(base, &except_vec_ejtag_debug, 0x80); - flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); -} - -extern struct plat_smp_ops msmtc_smp_ops; - -void __init prom_init(void) -{ - prom_argc = fw_arg0; - _prom_argv = (int *) fw_arg1; - _prom_envp = (int *) fw_arg2; - - mips_display_message("LINUX"); - - /* - * early setup of _pcictrl_bonito so that we can determine - * the system controller on a CORE_EMUL board - */ - _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); - - mips_revision_corid = MIPS_REVISION_CORID; - - if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { - if (BONITO_PCIDID == 0x0001df53 || - BONITO_PCIDID == 0x0003df53) - mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; - else - mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; - } - - mips_revision_sconid = MIPS_REVISION_SCONID; - if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { - switch (mips_revision_corid) { - case MIPS_REVISION_CORID_QED_RM5261: - case MIPS_REVISION_CORID_CORE_LV: - case MIPS_REVISION_CORID_CORE_FPGA: - case MIPS_REVISION_CORID_CORE_FPGAR2: - mips_revision_sconid = MIPS_REVISION_SCON_GT64120; - break; - case MIPS_REVISION_CORID_CORE_EMUL_BON: - case MIPS_REVISION_CORID_BONITO64: - case MIPS_REVISION_CORID_CORE_20K: - mips_revision_sconid = MIPS_REVISION_SCON_BONITO; - break; - case MIPS_REVISION_CORID_CORE_MSC: - case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_24K: - /* - * SOCit/ROCit support is essentially identical - * but make an attempt to distinguish them - */ - mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; - break; - case MIPS_REVISION_CORID_CORE_FPGA3: - case MIPS_REVISION_CORID_CORE_FPGA4: - case MIPS_REVISION_CORID_CORE_FPGA5: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: - default: - /* See above */ - mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; - break; - } - } - - switch (mips_revision_sconid) { - u32 start, map, mask, data; - - case MIPS_REVISION_SCON_GT64120: - /* - * Setup the North bridge to do Master byte-lane swapping - * when running in bigendian. - */ - _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); - -#ifdef CONFIG_CPU_LITTLE_ENDIAN - GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | - GT_PCI0_CMD_SBYTESWAP_BIT); -#else - GT_WRITE(GT_PCI0_CMD_OFS, 0); -#endif - /* Fix up PCI I/O mapping if necessary (for Atlas). */ - start = GT_READ(GT_PCI0IOLD_OFS); - map = GT_READ(GT_PCI0IOREMAP_OFS); - if ((start & map) != 0) { - map &= ~start; - GT_WRITE(GT_PCI0IOREMAP_OFS, map); - } - - set_io_port_base(MALTA_GT_PORT_BASE); - break; - - case MIPS_REVISION_SCON_BONITO: - _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); - - /* - * Disable Bonito IOBC. - */ - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & - ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - - /* - * Setup the North bridge to do Master byte-lane swapping - * when running in bigendian. - */ -#ifdef CONFIG_CPU_LITTLE_ENDIAN - BONITO_BONGENCFG = BONITO_BONGENCFG & - ~(BONITO_BONGENCFG_MSTRBYTESWAP | - BONITO_BONGENCFG_BYTESWAP); -#else - BONITO_BONGENCFG = BONITO_BONGENCFG | - BONITO_BONGENCFG_MSTRBYTESWAP | - BONITO_BONGENCFG_BYTESWAP; -#endif - - set_io_port_base(MALTA_BONITO_PORT_BASE); - break; - - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); - mips_pci_controller: - mb(); - MSC_READ(MSC01_PCI_CFG, data); - MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); - wmb(); - - /* Fix up lane swapping. */ -#ifdef CONFIG_CPU_LITTLE_ENDIAN - MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); -#else - MSC_WRITE(MSC01_PCI_SWAP, - MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | - MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | - MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); -#endif - /* Fix up target memory mapping. */ - MSC_READ(MSC01_PCI_BAR0, mask); - MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); - - /* Don't handle target retries indefinitely. */ - if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == - MSC01_PCI_CFG_MAXRTRY_MSK) - data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << - MSC01_PCI_CFG_MAXRTRY_SHF)) | - ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << - MSC01_PCI_CFG_MAXRTRY_SHF); - - wmb(); - MSC_WRITE(MSC01_PCI_CFG, data); - mb(); - - set_io_port_base(MALTA_MSC_PORT_BASE); - break; - - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); - goto mips_pci_controller; - - default: - /* Unknown system controller */ - mips_display_message("SC Error"); - while (1); /* We die here... */ - } - board_nmi_handler_setup = mips_nmi_setup; - board_ejtag_handler_setup = mips_ejtag_setup; - - pr_info("\nLINUX started...\n"); - prom_init_cmdline(); - prom_meminit(); -#ifdef CONFIG_SERIAL_8250_CONSOLE - console_config(); -#endif -#ifdef CONFIG_MIPS_CMP - register_smp_ops(&cmp_smp_ops); -#endif -#ifdef CONFIG_MIPS_MT_SMP - register_smp_ops(&vsmp_smp_ops); -#endif -#ifdef CONFIG_MIPS_MT_SMTC - register_smp_ops(&msmtc_smp_ops); -#endif -} diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c deleted file mode 100644 index 61888ff72c87..000000000000 --- a/arch/mips/mips-boards/generic/memory.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * PROM library functions for acquiring/using memory descriptors given to - * us from the YAMON. - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -/*#define DEBUG*/ - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; -static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -#ifdef DEBUG -static char *mtypes[3] = { - "Dont use memory", - "YAMON PROM memory", - "Free memmory", -}; -#endif - -/* determined physical memory size, not overridden by command line args */ -unsigned long physical_memsize = 0L; - -static struct prom_pmemblock * __init prom_getmdesc(void) -{ - char *memsize_str; - unsigned int memsize; - char cmdline[CL_SIZE], *ptr; - - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - printk(KERN_WARNING - "memsize not set in boot prom, set to default (32Mb)\n"); - physical_memsize = 0x02000000; - } else { -#ifdef DEBUG - pr_debug("prom_memsize = %s\n", memsize_str); -#endif - physical_memsize = simple_strtol(memsize_str, NULL, 0); - } - -#ifdef CONFIG_CPU_BIG_ENDIAN - /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last - word of physical memory */ - physical_memsize -= PAGE_SIZE; -#endif - - /* Check the command line for a memsize directive that overrides - the physical/default amount */ - strcpy(cmdline, arcs_cmdline); - ptr = strstr(cmdline, "memsize="); - if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) - ptr = strstr(ptr, " memsize="); - - if (ptr) - memsize = memparse(ptr + 8, &ptr); - else - memsize = physical_memsize; - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = yamon_dontuse; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = yamon_prom; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ef000; - - /* - * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the - * south bridge and PCI access always forwarded to the ISA Bus and - * BIOSCS# is always generated. - * This mean that this area can't be used as DMA memory for PCI - * devices. - */ - mdesc[2].type = yamon_dontuse; - mdesc[2].base = 0x000f0000; - mdesc[2].size = 0x00010000; - - mdesc[3].type = yamon_dontuse; - mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; - - mdesc[4].type = yamon_free; - mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[4].size = memsize - mdesc[4].base; - - return &mdesc[0]; -} - -static int __init prom_memtype_classify(unsigned int type) -{ - switch (type) { - case yamon_free: - return BOOT_MEM_RAM; - case yamon_prom: - return BOOT_MEM_ROM_DATA; - default: - return BOOT_MEM_RESERVED; - } -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *p; - -#ifdef DEBUG - pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); - p = prom_getmdesc(); - while (p->size) { - int i = 0; - pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", - i, p, p->base, p->size, mtypes[p->type]); - p++; - i++; - } -#endif - p = prom_getmdesc(); - - while (p->size) { - long type; - unsigned long base, size; - - type = prom_memtype_classify(p->type); - base = p->base; - size = p->size; - - add_memory_region(base, size, type); - p++; - } -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c deleted file mode 100644 index b9743190609a..000000000000 --- a/arch/mips/mips-boards/generic/pci.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * MIPS boards specific PCI support. - */ -#include -#include -#include -#include - -#include - -#include -#include -#include - -static struct resource bonito64_mem_resource = { - .name = "Bonito PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource bonito64_io_resource = { - .name = "Bonito PCI I/O", - .start = 0x00000000UL, - .end = 0x000fffffUL, - .flags = IORESOURCE_IO, -}; - -static struct resource gt64120_mem_resource = { - .name = "GT-64120 PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource gt64120_io_resource = { - .name = "GT-64120 PCI I/O", - .flags = IORESOURCE_IO, -}; - -static struct resource msc_mem_resource = { - .name = "MSC PCI MEM", - .flags = IORESOURCE_MEM, -}; - -static struct resource msc_io_resource = { - .name = "MSC PCI I/O", - .flags = IORESOURCE_IO, -}; - -extern struct pci_ops bonito64_pci_ops; -extern struct pci_ops gt64xxx_pci0_ops; -extern struct pci_ops msc_pci_ops; - -static struct pci_controller bonito64_controller = { - .pci_ops = &bonito64_pci_ops, - .io_resource = &bonito64_io_resource, - .mem_resource = &bonito64_mem_resource, - .io_offset = 0x00000000UL, -}; - -static struct pci_controller gt64120_controller = { - .pci_ops = >64xxx_pci0_ops, - .io_resource = >64120_io_resource, - .mem_resource = >64120_mem_resource, -}; - -static struct pci_controller msc_controller = { - .pci_ops = &msc_pci_ops, - .io_resource = &msc_io_resource, - .mem_resource = &msc_mem_resource, -}; - -void __init mips_pcibios_init(void) -{ - struct pci_controller *controller; - resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; - - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_GT64120: - /* - * Due to a bug in the Galileo system controller, we need - * to setup the PCI BAR for the Galileo internal registers. - * This should be done in the bios/bootprom and will be - * fixed in a later revision of YAMON (the MIPS boards - * boot prom). - */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ - (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ - ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ - GT_PCI0_CFGADDR_CONFIGEN_BIT); - - /* Perform the write */ - GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); - - /* Set up resource ranges from the controller's registers. */ - start = GT_READ(GT_PCI0M0LD_OFS); - end = GT_READ(GT_PCI0M0HD_OFS); - map = GT_READ(GT_PCI0M0REMAP_OFS); - end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); - start1 = GT_READ(GT_PCI0M1LD_OFS); - end1 = GT_READ(GT_PCI0M1HD_OFS); - map1 = GT_READ(GT_PCI0M1REMAP_OFS); - end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); - /* Cannot support multiple windows, use the wider. */ - if (end1 - start1 > end - start) { - start = start1; - end = end1; - map = map1; - } - mask = ~(start ^ end); - /* We don't support remapping with a discontiguous mask. */ - BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && - mask != ~((mask & -mask) - 1)); - gt64120_mem_resource.start = start; - gt64120_mem_resource.end = end; - gt64120_controller.mem_offset = (start & mask) - (map & mask); - /* Addresses are 36-bit, so do shifts in the destinations. */ - gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; - gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; - gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; - gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; - - start = GT_READ(GT_PCI0IOLD_OFS); - end = GT_READ(GT_PCI0IOHD_OFS); - map = GT_READ(GT_PCI0IOREMAP_OFS); - end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); - mask = ~(start ^ end); - /* We don't support remapping with a discontiguous mask. */ - BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && - mask != ~((mask & -mask) - 1)); - gt64120_io_resource.start = map & mask; - gt64120_io_resource.end = (map & mask) | ~mask; - gt64120_controller.io_offset = 0; - /* Addresses are 36-bit, so do shifts in the destinations. */ - gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; - gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; - gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; - - controller = >64120_controller; - break; - - case MIPS_REVISION_SCON_BONITO: - /* Set up resource ranges from the controller's registers. */ - map = BONITO_PCIMAP; - map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> - BONITO_PCIMAP_PCIMAP_LO0_SHIFT; - map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> - BONITO_PCIMAP_PCIMAP_LO1_SHIFT; - map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> - BONITO_PCIMAP_PCIMAP_LO2_SHIFT; - /* Combine as many adjacent windows as possible. */ - map = map1; - start = BONITO_PCILO0_BASE; - end = 1; - if (map3 == map2 + 1) { - map = map2; - start = BONITO_PCILO1_BASE; - end++; - } - if (map2 == map1 + 1) { - map = map1; - start = BONITO_PCILO0_BASE; - end++; - } - bonito64_mem_resource.start = start; - bonito64_mem_resource.end = start + - BONITO_PCIMAP_WINBASE(end) - 1; - bonito64_controller.mem_offset = start - - BONITO_PCIMAP_WINBASE(map); - - controller = &bonito64_controller; - break; - - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - /* Set up resource ranges from the controller's registers. */ - MSC_READ(MSC01_PCI_SC2PMBASL, start); - MSC_READ(MSC01_PCI_SC2PMMSKL, mask); - MSC_READ(MSC01_PCI_SC2PMMAPL, map); - msc_mem_resource.start = start & mask; - msc_mem_resource.end = (start & mask) | ~mask; - msc_controller.mem_offset = (start & mask) - (map & mask); - - MSC_READ(MSC01_PCI_SC2PIOBASL, start); - MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); - MSC_READ(MSC01_PCI_SC2PIOMAPL, map); - msc_io_resource.start = map & mask; - msc_io_resource.end = (map & mask) | ~mask; - msc_controller.io_offset = 0; - ioport_resource.end = ~mask; - - /* If ranges overlap I/O takes precedence. */ - start = start & mask; - end = start | ~mask; - if ((start >= msc_mem_resource.start && - start <= msc_mem_resource.end) || - (end >= msc_mem_resource.start && - end <= msc_mem_resource.end)) { - /* Use the larger space. */ - start = max(start, msc_mem_resource.start); - end = min(end, msc_mem_resource.end); - if (start - msc_mem_resource.start >= - msc_mem_resource.end - end) - msc_mem_resource.end = start - 1; - else - msc_mem_resource.start = end + 1; - } - - controller = &msc_controller; - break; - default: - return; - } - - if (controller->io_resource->start < 0x00001000UL) /* FIXME */ - controller->io_resource->start = 0x00001000UL; - - iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ - ioport_resource.end = controller->io_resource->end; - - register_pci_controller(controller); -} diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c deleted file mode 100644 index 42dee4da37ba..000000000000 --- a/arch/mips/mips-boards/generic/reset.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Reset the MIPS boards. - * - */ -#include - -#include -#include -#include - -static void mips_machine_restart(char *command); -static void mips_machine_halt(void); - -static void mips_machine_restart(char *command) -{ - unsigned int __iomem *softres_reg = - ioremap(SOFTRES_REG, sizeof(unsigned int)); - - __raw_writel(GORESET, softres_reg); -} - -static void mips_machine_halt(void) -{ - unsigned int __iomem *softres_reg = - ioremap(SOFTRES_REG, sizeof(unsigned int)); - - __raw_writel(GORESET, softres_reg); -} - - -void mips_reboot_setup(void) -{ - _machine_restart = mips_machine_restart; - _machine_halt = mips_machine_halt; - pm_power_off = mips_machine_halt; -} diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c deleted file mode 100644 index 0b97d47691fc..000000000000 --- a/arch/mips/mips-boards/generic/time.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Setting up the clock on the MIPS boards. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -unsigned long cpu_khz; - -static int mips_cpu_timer_irq; -static int mips_cpu_perf_irq; -extern int cp0_perfcount_irq; - -static void mips_timer_dispatch(void) -{ - do_IRQ(mips_cpu_timer_irq); -} - -static void mips_perf_dispatch(void) -{ - do_IRQ(mips_cpu_perf_irq); -} - -/* - * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect - */ -static unsigned int __init estimate_cpu_frequency(void) -{ - unsigned int prid = read_c0_prid() & 0xffff00; - unsigned int count; - - unsigned long flags; - unsigned int start; - - local_irq_save(flags); - - /* Start counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - /* Start r4k counter. */ - start = read_c0_count(); - - /* Read counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - count = read_c0_count() - start; - - /* restore interrupts */ - local_irq_restore(flags); - - mips_hpt_frequency = count; - if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && - (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) - count *= 2; - - count += 5000; /* round */ - count -= count%10000; - - return count; -} - -unsigned long read_persistent_clock(void) -{ - return mc146818_get_cmos_time(); -} - -static void __init plat_perf_setup(void) -{ -#ifdef MSC01E_INT_BASE - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); - mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; - } else -#endif - if (cp0_perfcount_irq >= 0) { - if (cpu_has_vint) - set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); - mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; -#ifdef CONFIG_SMP - set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); -#endif - } -} - -unsigned int __cpuinit get_c0_compare_int(void) -{ -#ifdef MSC01E_INT_BASE - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); - mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; - } else -#endif - { - if (cpu_has_vint) - set_vi_handler(cp0_compare_irq, mips_timer_dispatch); - mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; - } - - return mips_cpu_timer_irq; -} - -void __init plat_time_init(void) -{ - unsigned int est_freq; - - /* Set Data mode - binary. */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - - est_freq = estimate_cpu_frequency(); - - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, - (est_freq%1000000)*100/1000000); - - cpu_khz = est_freq / 1000; - - mips_scroll_message(); -#ifdef CONFIG_I8253 /* Only Malta has a PIT */ - setup_pit_timer(); -#endif - - plat_perf_setup(); -} diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile deleted file mode 100644 index db4ad654a6d3..000000000000 --- a/arch/mips/mips-boards/malta/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# Makefile for the MIPS Malta specific kernel interface routines -# under Linux. -# - -obj-y := malta_int.o malta_mtd.o malta_platform.o malta_setup.o - -# FIXME FIXME FIXME -obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c deleted file mode 100644 index ea176113fea9..000000000000 --- a/arch/mips/mips-boards/malta/malta_int.c +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. - * Copyright (C) 2001 Ralf Baechle - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Routines for generic manipulation of the interrupts found on the MIPS - * Malta board. - * The interrupt controller is located in the South Bridge a PIIX4 device - * with two internal 82C95 interrupt controllers. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int gcmp_present = -1; -int gic_present; -static unsigned long _msc01_biu_base; -static unsigned long _gcmp_base; -static unsigned int ipi_map[NR_CPUS]; - -static DEFINE_SPINLOCK(mips_irq_lock); - -static inline int mips_pcibios_iack(void) -{ - int irq; - u32 dummy; - - /* - * Determine highest priority pending interrupt by performing - * a PCI Interrupt Acknowledge cycle. - */ - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - MSC_READ(MSC01_PCI_IACK, irq); - irq &= 0xff; - break; - case MIPS_REVISION_SCON_GT64120: - irq = GT_READ(GT_PCI0_IACK_OFS); - irq &= 0xff; - break; - case MIPS_REVISION_SCON_BONITO: - /* The following will generate a PCI IACK cycle on the - * Bonito controller. It's a little bit kludgy, but it - * was the easiest way to implement it in hardware at - * the given time. - */ - BONITO_PCIMAP_CFG = 0x20000; - - /* Flush Bonito register block */ - dummy = BONITO_PCIMAP_CFG; - iob(); /* sync */ - - irq = readl((u32 *)_pcictrl_bonito_pcicfg); - iob(); /* sync */ - irq &= 0xff; - BONITO_PCIMAP_CFG = 0; - break; - default: - printk(KERN_WARNING "Unknown system controller.\n"); - return -1; - } - return irq; -} - -static inline int get_int(void) -{ - unsigned long flags; - int irq; - spin_lock_irqsave(&mips_irq_lock, flags); - - irq = mips_pcibios_iack(); - - /* - * The only way we can decide if an interrupt is spurious - * is by checking the 8259 registers. This needs a spinlock - * on an SMP system, so leave it up to the generic code... - */ - - spin_unlock_irqrestore(&mips_irq_lock, flags); - - return irq; -} - -static void malta_hw0_irqdispatch(void) -{ - int irq; - - irq = get_int(); - if (irq < 0) { - /* interrupt has already been cleared */ - return; - } - - do_IRQ(MALTA_INT_BASE + irq); -} - -static void malta_ipi_irqdispatch(void) -{ - int irq; - - irq = gic_get_int(); - if (irq < 0) - return; /* interrupt has already been cleared */ - - do_IRQ(MIPS_GIC_IRQ_BASE + irq); -} - -static void corehi_irqdispatch(void) -{ - unsigned int intedge, intsteer, pcicmd, pcibadaddr; - unsigned int pcimstat, intisr, inten, intpol; - unsigned int intrcause, datalo, datahi; - struct pt_regs *regs = get_irq_regs(); - - printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); - printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" - "Cause : %08lx\nbadVaddr : %08lx\n", - regs->cp0_epc, regs->cp0_status, - regs->cp0_cause, regs->cp0_badvaddr); - - /* Read all the registers and then print them as there is a - problem with interspersed printk's upsetting the Bonito controller. - Do it for the others too. - */ - - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - ll_msc_irq(); - break; - case MIPS_REVISION_SCON_GT64120: - intrcause = GT_READ(GT_INTRCAUSE_OFS); - datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); - datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); - printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); - printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", - datahi, datalo); - break; - case MIPS_REVISION_SCON_BONITO: - pcibadaddr = BONITO_PCIBADADDR; - pcimstat = BONITO_PCIMSTAT; - intisr = BONITO_INTISR; - inten = BONITO_INTEN; - intpol = BONITO_INTPOL; - intedge = BONITO_INTEDGE; - intsteer = BONITO_INTSTEER; - pcicmd = BONITO_PCICMD; - printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); - printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); - printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); - printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); - printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); - printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); - printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); - printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); - break; - } - - die("CoreHi interrupt", regs); -} - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return -clz(pending) + 31 - CAUSEB_IP; -#else - unsigned int a0 = 7; - unsigned int t0; - - t0 = pending & 0xf000; - t0 = t0 < 1; - t0 = t0 << 2; - a0 = a0 - t0; - pending = pending << t0; - - t0 = pending & 0xc000; - t0 = t0 < 1; - t0 = t0 << 1; - a0 = a0 - t0; - pending = pending << t0; - - t0 = pending & 0x8000; - t0 = t0 < 1; - /* t0 = t0 << 2; */ - a0 = a0 - t0; - /* pending = pending << t0; */ - - return a0; -#endif -} - -/* - * IRQs on the Malta board look basically (barring software IRQs which we - * don't use at all and all external interrupt sources are combined together - * on hardware interrupt 0 (MIPS IRQ 2)) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Combined hardware interrupt (hw0) - * 3 Hardware (ignored) - * 4 Hardware (ignored) - * 5 Hardware (ignored) - * 6 Hardware (ignored) - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Lowest ---- Combined hardware interrupt - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq == MIPSCPU_INT_I8259A) - malta_hw0_irqdispatch(); - else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()])) - malta_ipi_irqdispatch(); - else if (irq >= 0) - do_IRQ(MIPS_CPU_IRQ_BASE + irq); - else - spurious_interrupt(); -} - -#ifdef CONFIG_MIPS_MT_SMP - - -#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 -#define GIC_MIPS_CPU_IPI_CALL_IRQ 4 - -#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ -#define C_RESCHED C_SW0 -#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ -#define C_CALL C_SW1 -static int cpu_ipi_resched_irq, cpu_ipi_call_irq; - -static void ipi_resched_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); -} - -static void ipi_call_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); -} - -static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) -{ - return IRQ_HANDLED; -} - -static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) -{ - smp_call_function_interrupt(); - - return IRQ_HANDLED; -} - -static struct irqaction irq_resched = { - .handler = ipi_resched_interrupt, - .flags = IRQF_DISABLED|IRQF_PERCPU, - .name = "IPI_resched" -}; - -static struct irqaction irq_call = { - .handler = ipi_call_interrupt, - .flags = IRQF_DISABLED|IRQF_PERCPU, - .name = "IPI_call" -}; -#endif /* CONFIG_MIPS_MT_SMP */ - -static struct irqaction i8259irq = { - .handler = no_action, - .name = "XT-PIC cascade" -}; - -static struct irqaction corehi_irqaction = { - .handler = no_action, - .name = "CoreHi" -}; - -static msc_irqmap_t __initdata msc_irqmap[] = { - {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, - {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, -}; -static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); - -static msc_irqmap_t __initdata msc_eicirqmap[] = { - {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, - {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, - {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} -}; - -static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); - -#if defined(CONFIG_MIPS_MT_SMP) -/* - * This GIC specific tabular array defines the association between External - * Interrupts and CPUs/Core Interrupts. The nature of the External - * Interrupts is also defined here - polarity/trigger. - */ -static struct gic_intr_map gic_intr_map[] = { - { GIC_EXT_INTR(0), X, X, X, X, 0 }, - { GIC_EXT_INTR(1), X, X, X, X, 0 }, - { GIC_EXT_INTR(2), X, X, X, X, 0 }, - { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(10), X, X, X, X, 0 }, - { GIC_EXT_INTR(11), X, X, X, X, 0 }, - { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(15), X, X, X, X, 0 }, - { GIC_EXT_INTR(16), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(17), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(18), 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(19), 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(20), 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(21), 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, - { GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, -}; -#endif - -/* - * GCMP needs to be detected before any SMP initialisation - */ -static int __init gcmp_probe(unsigned long addr, unsigned long size) -{ - if (gcmp_present >= 0) - return gcmp_present; - - _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); - gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; - - if (gcmp_present) - printk(KERN_DEBUG "GCMP present\n"); - return gcmp_present; -} - -#if defined(CONFIG_MIPS_MT_SMP) -static void __init fill_ipi_map(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) { - if (gic_intr_map[i].ipiflag && (gic_intr_map[i].cpunum != X)) - ipi_map[gic_intr_map[i].cpunum] |= - (1 << (gic_intr_map[i].pin + 2)); - } -} -#endif - -void __init arch_init_irq(void) -{ - int gic_present, gcmp_present; - - init_i8259_irqs(); - - if (!cpu_has_veic) - mips_cpu_irq_init(); - - gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); - if (gcmp_present) { - GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; - gic_present = 1; - } else { - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); - gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & - MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; - } - if (gic_present) - printk(KERN_DEBUG "GIC present\n"); - - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: - if (cpu_has_veic) - init_msc_irqs(MIPS_MSC01_IC_REG_BASE, - MSC01E_INT_BASE, msc_eicirqmap, - msc_nr_eicirqs); - else - init_msc_irqs(MIPS_MSC01_IC_REG_BASE, - MSC01C_INT_BASE, msc_irqmap, - msc_nr_irqs); - break; - - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: - if (cpu_has_veic) - init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, - MSC01E_INT_BASE, msc_eicirqmap, - msc_nr_eicirqs); - else - init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, - MSC01C_INT_BASE, msc_irqmap, - msc_nr_irqs); - } - - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); - set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); - setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); - setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); - } else if (cpu_has_vint) { - set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); - set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); -#ifdef CONFIG_MIPS_MT_SMTC - setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, - (0x100 << MIPSCPU_INT_I8259A)); - setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, - &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); - /* - * Temporary hack to ensure that the subsidiary device - * interrupts coing in via the i8259A, but associated - * with low IRQ numbers, will restore the Status.IM - * value associated with the i8259A. - */ - { - int i; - - for (i = 0; i < 16; i++) - irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); - } -#else /* Not SMTC */ - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, - &corehi_irqaction); -#endif /* CONFIG_MIPS_MT_SMTC */ - } else { - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, - &corehi_irqaction); - } - -#if defined(CONFIG_MIPS_MT_SMP) - if (gic_present) { - /* FIXME */ - int i; - struct { - unsigned int resched; - unsigned int call; - } ipiirq[] = { - { - .resched = GIC_IPI_EXT_INTR_RESCHED_VPE0, - .call = GIC_IPI_EXT_INTR_CALLFNC_VPE0}, - { - .resched = GIC_IPI_EXT_INTR_RESCHED_VPE1, - .call = GIC_IPI_EXT_INTR_CALLFNC_VPE1 - }, { - .resched = GIC_IPI_EXT_INTR_RESCHED_VPE2, - .call = GIC_IPI_EXT_INTR_CALLFNC_VPE2 - }, { - .resched = GIC_IPI_EXT_INTR_RESCHED_VPE3, - .call = GIC_IPI_EXT_INTR_CALLFNC_VPE3 - } - }; - fill_ipi_map(); - gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); - if (!gcmp_present) { - /* Enable the GIC */ - i = REG(_msc01_biu_base, MSC01_SC_CFG); - REG(_msc01_biu_base, MSC01_SC_CFG) = - (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); - pr_debug("GIC Enabled\n"); - } - - /* set up ipi interrupts */ - if (cpu_has_vint) { - set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); - set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); - } - /* Argh.. this really needs sorting out.. */ - printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); - write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); - printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); - write_c0_status(0x1100dc00); - printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); - for (i = 0; i < ARRAY_SIZE(ipiirq); i++) { - setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched); - setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call); - - set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, handle_percpu_irq); - set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].call, handle_percpu_irq); - } - } else { - /* set up ipi interrupts */ - if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); - set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); - cpu_ipi_resched_irq = MSC01E_INT_SW0; - cpu_ipi_call_irq = MSC01E_INT_SW1; - } else { - if (cpu_has_vint) { - set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); - set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); - } - cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; - cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; - } - - setup_irq(cpu_ipi_resched_irq, &irq_resched); - setup_irq(cpu_ipi_call_irq, &irq_call); - - set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); - set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); - } -#endif -} - -void malta_be_init(void) -{ - if (gcmp_present) { - /* Could change CM error mask register */ - } -} - - -static char *tr[8] = { - "mem", "gcr", "gic", "mmio", - "0x04", "0x05", "0x06", "0x07" -}; - -static char *mcmd[32] = { - [0x00] = "0x00", - [0x01] = "Legacy Write", - [0x02] = "Legacy Read", - [0x03] = "0x03", - [0x04] = "0x04", - [0x05] = "0x05", - [0x06] = "0x06", - [0x07] = "0x07", - [0x08] = "Coherent Read Own", - [0x09] = "Coherent Read Share", - [0x0a] = "Coherent Read Discard", - [0x0b] = "Coherent Ready Share Always", - [0x0c] = "Coherent Upgrade", - [0x0d] = "Coherent Writeback", - [0x0e] = "0x0e", - [0x0f] = "0x0f", - [0x10] = "Coherent Copyback", - [0x11] = "Coherent Copyback Invalidate", - [0x12] = "Coherent Invalidate", - [0x13] = "Coherent Write Invalidate", - [0x14] = "Coherent Completion Sync", - [0x15] = "0x15", - [0x16] = "0x16", - [0x17] = "0x17", - [0x18] = "0x18", - [0x19] = "0x19", - [0x1a] = "0x1a", - [0x1b] = "0x1b", - [0x1c] = "0x1c", - [0x1d] = "0x1d", - [0x1e] = "0x1e", - [0x1f] = "0x1f" -}; - -static char *core[8] = { - "Invalid/OK", "Invalid/Data", - "Shared/OK", "Shared/Data", - "Modified/OK", "Modified/Data", - "Exclusive/OK", "Exclusive/Data" -}; - -static char *causes[32] = { - "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR", - "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07", - "0x08", "0x09", "0x0a", "0x0b", - "0x0c", "0x0d", "0x0e", "0x0f", - "0x10", "0x11", "0x12", "0x13", - "0x14", "0x15", "0x16", "INTVN_WR_ERR", - "INTVN_RD_ERR", "0x19", "0x1a", "0x1b", - "0x1c", "0x1d", "0x1e", "0x1f" -}; - -int malta_be_handler(struct pt_regs *regs, int is_fixup) -{ - /* This duplicates the handling in do_be which seems wrong */ - int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; - - if (gcmp_present) { - unsigned long cm_error = GCMPGCB(GCMEC); - unsigned long cm_addr = GCMPGCB(GCMEA); - unsigned long cm_other = GCMPGCB(GCMEO); - unsigned long cause, ocause; - char buf[256]; - - cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); - if (cause != 0) { - cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; - if (cause < 16) { - unsigned long cca_bits = (cm_error >> 15) & 7; - unsigned long tr_bits = (cm_error >> 12) & 7; - unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; - unsigned long stag_bits = (cm_error >> 3) & 15; - unsigned long sport_bits = (cm_error >> 0) & 7; - - snprintf(buf, sizeof(buf), - "CCA=%lu TR=%s MCmd=%s STag=%lu " - "SPort=%lu\n", - cca_bits, tr[tr_bits], mcmd[mcmd_bits], - stag_bits, sport_bits); - } else { - /* glob state & sresp together */ - unsigned long c3_bits = (cm_error >> 18) & 7; - unsigned long c2_bits = (cm_error >> 15) & 7; - unsigned long c1_bits = (cm_error >> 12) & 7; - unsigned long c0_bits = (cm_error >> 9) & 7; - unsigned long sc_bit = (cm_error >> 8) & 1; - unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; - unsigned long sport_bits = (cm_error >> 0) & 7; - snprintf(buf, sizeof(buf), - "C3=%s C2=%s C1=%s C0=%s SC=%s " - "MCmd=%s SPort=%lu\n", - core[c3_bits], core[c2_bits], - core[c1_bits], core[c0_bits], - sc_bit ? "True" : "False", - mcmd[mcmd_bits], sport_bits); - } - - ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> - GCMP_GCB_GMEO_ERROR_2ND_SHF; - - printk("CM_ERROR=%08lx %s <%s>\n", cm_error, - causes[cause], buf); - printk("CM_ADDR =%08lx\n", cm_addr); - printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); - - /* reprime cause register */ - GCMPGCB(GCMEC) = 0; - } - } - - return retval; -} diff --git a/arch/mips/mips-boards/malta/malta_mtd.c b/arch/mips/mips-boards/malta/malta_mtd.c deleted file mode 100644 index 8ad9bdf25dce..000000000000 --- a/arch/mips/mips-boards/malta/malta_mtd.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 MIPS Technologies, Inc. - * written by Ralf Baechle - */ - -#include -#include -#include -#include -#include - -static struct mtd_partition malta_mtd_partitions[] = { - { - .name = "YAMON", - .offset = 0x0, - .size = 0x100000, - .mask_flags = MTD_WRITEABLE - }, { - .name = "User FS", - .offset = 0x100000, - .size = 0x2e0000 - }, { - .name = "Board Config", - .offset = 0x3e0000, - .size = 0x020000, - .mask_flags = MTD_WRITEABLE - } -}; - -static struct physmap_flash_data malta_flash_data = { - .width = 4, - .nr_parts = ARRAY_SIZE(malta_mtd_partitions), - .parts = malta_mtd_partitions -}; - -static struct resource malta_flash_resource = { - .start = 0x1e000000, - .end = 0x1e3fffff, - .flags = IORESOURCE_MEM -}; - -static struct platform_device malta_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &malta_flash_data, - }, - .num_resources = 1, - .resource = &malta_flash_resource, -}; - -static int __init malta_mtd_init(void) -{ - platform_device_register(&malta_flash); - - return 0; -} - -module_init(malta_mtd_init) diff --git a/arch/mips/mips-boards/malta/malta_platform.c b/arch/mips/mips-boards/malta/malta_platform.c deleted file mode 100644 index 83b9bab3cd3f..000000000000 --- a/arch/mips/mips-boards/malta/malta_platform.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 MIPS Technologies, Inc. - * written by Ralf Baechle (ralf@linux-mips.org) - * - * Probe driver for the Malta's UART ports: - * - * o 2 ports in the SMC SuperIO - * o 1 port in the CBUS UART, a discrete 16550 which normally is only used - * for bringups. - * - * We don't use 8250_platform.c on Malta as it would result in the CBUS - * UART becoming ttyS0. - */ -#include -#include -#include - -#define SMC_PORT(base, int) \ -{ \ - .iobase = base, \ - .irq = int, \ - .uartclk = 1843200, \ - .iotype = UPIO_PORT, \ - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ - .regshift = 0, \ -} - -#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) - -static struct plat_serial8250_port uart8250_data[] = { - SMC_PORT(0x3F8, 4), - SMC_PORT(0x2F8, 3), - { - .mapbase = 0x1f000900, /* The CBUS UART */ - .irq = MIPS_CPU_IRQ_BASE + 2, - .uartclk = 3686400, /* Twice the usual clk! */ - .iotype = UPIO_MEM32, - .flags = CBUS_UART_FLAGS, - .regshift = 3, - }, - { }, -}; - -static struct platform_device uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = uart8250_data, - }, -}; - -static int __init uart8250_init(void) -{ - return platform_device_register(&uart8250_device); -} - -module_init(uart8250_init); - -MODULE_AUTHOR("Ralf Baechle "); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("8250 UART probe driver for the Malta CBUS UART"); diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c deleted file mode 100644 index e7cad54936ca..000000000000 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2008 Dmitri Vorobiev - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_VT -#include -#endif - -extern void malta_be_init(void); -extern int malta_be_handler(struct pt_regs *regs, int is_fixup); - -static struct resource standard_io_resources[] = { - { - .name = "dma1", - .start = 0x00, - .end = 0x1f, - .flags = IORESOURCE_BUSY - }, - { - .name = "timer", - .start = 0x40, - .end = 0x5f, - .flags = IORESOURCE_BUSY - }, - { - .name = "keyboard", - .start = 0x60, - .end = 0x6f, - .flags = IORESOURCE_BUSY - }, - { - .name = "dma page reg", - .start = 0x80, - .end = 0x8f, - .flags = IORESOURCE_BUSY - }, - { - .name = "dma2", - .start = 0xc0, - .end = 0xdf, - .flags = IORESOURCE_BUSY - }, -}; - -const char *get_system_type(void) -{ - return "MIPS Malta"; -} - -#if defined(CONFIG_MIPS_MT_SMTC) -const char display_string[] = " SMTC LINUX ON MALTA "; -#else -const char display_string[] = " LINUX ON MALTA "; -#endif /* CONFIG_MIPS_MT_SMTC */ - -#ifdef CONFIG_BLK_DEV_FD -static void __init fd_activate(void) -{ - /* - * Activate Floppy Controller in the SMSC FDC37M817 Super I/O - * Controller. - * Done by YAMON 2.00 onwards - */ - /* Entering config state. */ - SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); - - /* Activate floppy controller. */ - SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); - SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); - SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); - SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); - - /* Exit config state. */ - SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); -} -#endif - -#ifdef CONFIG_BLK_DEV_IDE -static void __init pci_clock_check(void) -{ - unsigned int __iomem *jmpr_p = - (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); - int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; - static const int pciclocks[] __initdata = { - 33, 20, 25, 30, 12, 16, 37, 10 - }; - int pciclock = pciclocks[jmpr]; - char *argptr = prom_getcmdline(); - - if (pciclock != 33 && !strstr(argptr, "idebus=")) { - printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " - "setting idebus\n", pciclock); - argptr += strlen(argptr); - sprintf(argptr, " idebus=%d", pciclock); - if (pciclock < 20 || pciclock > 66) - printk(KERN_WARNING "WARNING: IDE timing " - "calculations will be incorrect\n"); - } -} -#endif - -#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) -static void __init screen_info_setup(void) -{ - screen_info = (struct screen_info) { - .orig_x = 0, - .orig_y = 25, - .ext_mem_k = 0, - .orig_video_page = 0, - .orig_video_mode = 0, - .orig_video_cols = 80, - .unused2 = 0, - .orig_video_ega_bx = 0, - .unused3 = 0, - .orig_video_lines = 25, - .orig_video_isVGA = VIDEO_TYPE_VGAC, - .orig_video_points = 16 - }; -} -#endif - -static void __init bonito_quirks_setup(void) -{ - char *argptr; - - argptr = prom_getcmdline(); - if (strstr(argptr, "debug")) { - BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; - printk(KERN_INFO "Enabled Bonito debug mode\n"); - } else - BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; - -#ifdef CONFIG_DMA_COHERENT - if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { - BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; - printk(KERN_INFO "Enabled Bonito CPU coherency\n"); - - argptr = prom_getcmdline(); - if (strstr(argptr, "iobcuncached")) { - BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & - ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); - } else { - BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG |= - (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); - } - } else - panic("Hardware DMA cache coherency not supported"); -#endif -} - -void __init plat_mem_setup(void) -{ - unsigned int i; - - mips_pcibios_init(); - - /* Request I/O space for devices used on the Malta board. */ - for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) - request_resource(&ioport_resource, standard_io_resources+i); - - /* - * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. - */ - enable_dma(4); - -#ifdef CONFIG_KGDB - kgdb_config(); -#endif - -#ifdef CONFIG_DMA_COHERENT - if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) - panic("Hardware DMA cache coherency not supported"); -#endif - - if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) - bonito_quirks_setup(); - -#ifdef CONFIG_BLK_DEV_IDE - pci_clock_check(); -#endif - -#ifdef CONFIG_BLK_DEV_FD - fd_activate(); -#endif - -#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) - screen_info_setup(); -#endif - mips_reboot_setup(); - - board_be_init = malta_be_init; - board_be_handler = malta_be_handler; -} diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c deleted file mode 100644 index 5ea705e49454..000000000000 --- a/arch/mips/mips-boards/malta/malta_smtc.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Malta Platform-specific hooks for SMP operation - */ -#include -#include - -#include -#include -#include -#include - -/* VPE/SMP Prototype implements platform interfaces directly */ - -/* - * Cause the specified action to be performed on a targeted "CPU" - */ - -static void msmtc_send_ipi_single(int cpu, unsigned int action) -{ - /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ - smtc_send_ipi(cpu, LINUX_SMP_IPI, action); -} - -static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; - - for_each_cpu_mask(i, mask) - msmtc_send_ipi_single(i, action); -} - -/* - * Post-config but pre-boot cleanup entry point - */ -static void __cpuinit msmtc_init_secondary(void) -{ - void smtc_init_secondary(void); - int myvpe; - - /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ - myvpe = read_c0_tcbind() & TCBIND_CURVPE; - if (myvpe != 0) { - /* Ideally, this should be done only once per VPE, but... */ - clear_c0_status(ST0_IM); - set_c0_status((0x100 << cp0_compare_irq) - | (0x100 << MIPS_CPU_IPI_IRQ)); - if (cp0_perfcount_irq >= 0) - set_c0_status(0x100 << cp0_perfcount_irq); - } - - smtc_init_secondary(); -} - -/* - * Platform "CPU" startup hook - */ -static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) -{ - smtc_boot_secondary(cpu, idle); -} - -/* - * SMP initialization finalization entry point - */ -static void __cpuinit msmtc_smp_finish(void) -{ - smtc_smp_finish(); -} - -/* - * Hook for after all CPUs are online - */ - -static void msmtc_cpus_done(void) -{ -} - -/* - * Platform SMP pre-initialization - * - * As noted above, we can assume a single CPU for now - * but it may be multithreaded. - */ - -static void __init msmtc_smp_setup(void) -{ - mipsmt_build_cpu_map(0); -} - -static void __init msmtc_prepare_cpus(unsigned int max_cpus) -{ - mipsmt_prepare_cpus(); -} - -struct plat_smp_ops msmtc_smp_ops = { - .send_ipi_single = msmtc_send_ipi_single, - .send_ipi_mask = msmtc_send_ipi_mask, - .init_secondary = msmtc_init_secondary, - .smp_finish = msmtc_smp_finish, - .cpus_done = msmtc_cpus_done, - .boot_secondary = msmtc_boot_secondary, - .smp_setup = msmtc_smp_setup, - .prepare_cpus = msmtc_prepare_cpus, -}; - -#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF -/* - * IRQ affinity hook - */ - - -void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity) -{ - cpumask_t tmask = affinity; - int cpu = 0; - void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); - - /* - * On the legacy Malta development board, all I/O interrupts - * are routed through the 8259 and combined in a single signal - * to the CPU daughterboard, and on the CoreFPGA2/3 34K models, - * that signal is brought to IP2 of both VPEs. To avoid racing - * concurrent interrupt service events, IP2 is enabled only on - * one VPE, by convention VPE0. So long as no bits are ever - * cleared in the affinity mask, there will never be any - * interrupt forwarding. But as soon as a program or operator - * sets affinity for one of the related IRQs, we need to make - * sure that we don't ever try to forward across the VPE boundry, - * at least not until we engineer a system where the interrupt - * _ack() or _end() function can somehow know that it corresponds - * to an interrupt taken on another VPE, and perform the appropriate - * restoration of Status.IM state using MFTR/MTTR instead of the - * normal local behavior. We also ensure that no attempt will - * be made to forward to an offline "CPU". - */ - - for_each_cpu_mask(cpu, affinity) { - if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) - cpu_clear(cpu, tmask); - } - irq_desc[irq].affinity = tmask; - - if (cpus_empty(tmask)) - /* - * We could restore a default mask here, but the - * runtime code can anyway deal with the null set - */ - printk(KERN_WARNING - "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); - - /* Do any generic SMTC IRQ affinity setup */ - smtc_set_irq_affinity(irq, tmask); -} -#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile new file mode 100644 index 000000000000..f8064446e812 --- /dev/null +++ b/arch/mips/mti-malta/Makefile @@ -0,0 +1,21 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Copyright (C) 2008 Wind River Systems, Inc. +# written by Ralf Baechle +# +obj-y := malta-amon.o malta-cmdline.o \ + malta-display.o malta-init.o malta-int.o \ + malta-memory.o malta-mtd.o \ + malta-platform.o malta-reset.o \ + malta-setup.o malta-time.o + +obj-$(CONFIG_EARLY_PRINTK) += malta-console.o +obj-$(CONFIG_PCI) += malta-pci.o +obj-$(CONFIG_KGDB) += malta-kgdb.o + +# FIXME FIXME FIXME +obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c new file mode 100644 index 000000000000..96236bf33838 --- /dev/null +++ b/arch/mips/mti-malta/malta-amon.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2007 MIPS Technologies, Inc. + * All rights reserved. + + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Arbitrary Monitor interface + */ + +#include +#include +#include + +#include +#include +#include + +int amon_cpu_avail(int cpu) +{ + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); + + if (cpu < 0 || cpu >= NCPULAUNCH) { + pr_debug("avail: cpu%d is out of range\n", cpu); + return 0; + } + + launch += cpu; + if (!(launch->flags & LAUNCH_FREADY)) { + pr_debug("avail: cpu%d is not ready\n", cpu); + return 0; + } + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) { + pr_debug("avail: too late.. cpu%d is already gone\n", cpu); + return 0; + } + + return 1; +} + +void amon_cpu_start(int cpu, + unsigned long pc, unsigned long sp, + unsigned long gp, unsigned long a0) +{ + volatile struct cpulaunch *launch = + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); + + if (!amon_cpu_avail(cpu)) + return; + if (cpu == smp_processor_id()) { + pr_debug("launch: I am cpu%d!\n", cpu); + return; + } + launch += cpu; + + pr_debug("launch: starting cpu%d\n", cpu); + + launch->pc = pc; + launch->gp = gp; + launch->sp = sp; + launch->a0 = a0; + + /* Make sure target sees parameters before the go bit */ + smp_mb(); + + launch->flags |= LAUNCH_FGO; + while ((launch->flags & LAUNCH_FGONE) == 0) + ; + pr_debug("launch: cpu%d gone!\n", cpu); +} diff --git a/arch/mips/mti-malta/malta-cmdline.c b/arch/mips/mti-malta/malta-cmdline.c new file mode 100644 index 000000000000..1871c30ed2eb --- /dev/null +++ b/arch/mips/mti-malta/malta-cmdline.c @@ -0,0 +1,59 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Kernel command line creation using the prom monitor (YAMON) argc/argv. + */ +#include +#include + +#include + +extern int prom_argc; +extern int *_prom_argv; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) { + /* get rid of trailing space */ + --cp; + *cp = '\0'; + } +} diff --git a/arch/mips/mti-malta/malta-console.c b/arch/mips/mti-malta/malta-console.c new file mode 100644 index 000000000000..43bcfb4f8167 --- /dev/null +++ b/arch/mips/mti-malta/malta-console.c @@ -0,0 +1,47 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Putting things on the screen/serial line using YAMONs facilities. + */ +#include +#include +#include +#include + + +#define PORT(offset) (0x3f8 + (offset)) + + +static inline unsigned int serial_in(int offset) +{ + return inb(PORT(offset)); +} + +static inline void serial_out(int offset, int value) +{ + outb(value, PORT(offset)); +} + +int prom_putchar(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c); + + return 1; +} diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c new file mode 100644 index 000000000000..7c8828fcb0ad --- /dev/null +++ b/arch/mips/mti-malta/malta-display.c @@ -0,0 +1,64 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Display routines for display messages in MIPS boards ascii display. + */ + +#include +#include +#include +#include +#include + +extern const char display_string[]; +static unsigned int display_count; +static unsigned int max_display_count; + +void mips_display_message(const char *str) +{ + static unsigned int __iomem *display = NULL; + int i; + + if (unlikely(display == NULL)) + display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int)); + + for (i = 0; i <= 14; i=i+2) { + if (*str) + __raw_writel(*str++, display + i); + else + __raw_writel(' ', display + i); + } +} + +static void scroll_display_message(unsigned long data); +static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0); + +static void scroll_display_message(unsigned long data) +{ + mips_display_message(&display_string[display_count++]); + if (display_count == max_display_count) + display_count = 0; + + mod_timer(&mips_scroll_timer, jiffies + HZ); +} + +void mips_scroll_message(void) +{ + del_timer_sync(&mips_scroll_timer); + max_display_count = strlen(display_string) + 1 - 8; + mod_timer(&mips_scroll_timer, jiffies + 1); +} diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c new file mode 100644 index 000000000000..c0653021a171 --- /dev/null +++ b/arch/mips/mti-malta/malta-init.c @@ -0,0 +1,424 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library initialisation code. + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_KGDB +extern int rs_kgdb_hook(int, int); +extern int rs_putDebugChar(char); +extern char rs_getDebugChar(void); +extern int saa9730_kgdb_hook(int); +extern int saa9730_putDebugChar(char); +extern char saa9730_getDebugChar(void); +#endif + +int prom_argc; +int *_prom_argv, *_prom_envp; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +int init_debug = 0; + +int mips_revision_corid; +int mips_revision_sconid; + +/* Bonito64 system controller register base. */ +unsigned long _pcictrl_bonito; +unsigned long _pcictrl_bonito_pcicfg; + +/* GT64120 system controller register base */ +unsigned long _pcictrl_gt64120; + +/* MIPS System controller register base */ +unsigned long _pcictrl_msc; + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index=0; + + i = strlen(envname); + + while (prom_envp(index)) { + if(strncmp(envname, prom_envp(index), i) == 0) { + return(prom_envp(index+1)); + } + index += 2; + } + + return NULL; +} + +static inline unsigned char str2hexnum(unsigned char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + + if (init_debug > 1) { + int i; + printk("get_ethernet_addr: "); + for (i=0; i<5; i++) + printk("%02x:", (unsigned char)*(ethernet_addr+i)); + printk("%02x\n", *(ethernet_addr+i)); + } + + return 0; +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static void __init console_config(void) +{ + char console_string[40]; + int baud = 0; + char parity = '\0', bits = '\0', flow = '\0'; + char *s; + + if ((strstr(prom_getcmdline(), "console=")) == NULL) { + s = prom_getenv("modetty0"); + if (s) { + while (*s >= '0' && *s <= '9') + baud = baud*10 + *s++ - '0'; + if (*s == ',') s++; + if (*s) parity = *s++; + if (*s == ',') s++; + if (*s) bits = *s++; + if (*s == ',') s++; + if (*s == 'h') flow = 'r'; + } + if (baud == 0) + baud = 38400; + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + if (flow == '\0') + flow = 'r'; + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); + strcat(prom_getcmdline(), console_string); + pr_info("Config serial console:%s\n", console_string); + } +} +#endif + +#ifdef CONFIG_KGDB +void __init kgdb_config(void) +{ + extern int (*generic_putDebugChar)(char); + extern char (*generic_getDebugChar)(void); + char *argptr; + int line, speed; + + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { + argptr += strlen("kgdb=ttyS"); + if (*argptr != '0' && *argptr != '1') + printk("KGDB: Unknown serial line /dev/ttyS%c, " + "falling back to /dev/ttyS1\n", *argptr); + line = *argptr == '0' ? 0 : 1; + printk("KGDB: Using serial line /dev/ttyS%d for session\n", line); + + speed = 0; + if (*++argptr == ',') + { + int c; + while ((c = *++argptr) && ('0' <= c && c <= '9')) + speed = speed * 10 + c - '0'; + } + { + speed = rs_kgdb_hook(line, speed); + generic_putDebugChar = rs_putDebugChar; + generic_getDebugChar = rs_getDebugChar; + } + + pr_info("KGDB: Using serial line /dev/ttyS%d at %d for " + "session, please connect your debugger\n", + line ? 1 : 0, speed); + + { + char *s; + for (s = "Please connect GDB to this port\r\n"; *s; ) + generic_putDebugChar(*s++); + } + + /* Breakpoint is invoked after interrupts are initialised */ + } +} +#endif + +static void __init mips_nmi_setup(void) +{ + void *base; + extern char except_vec_nmi; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + extern char except_vec_ejtag_debug; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); + memcpy(base, &except_vec_ejtag_debug, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +extern struct plat_smp_ops msmtc_smp_ops; + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + _prom_argv = (int *) fw_arg1; + _prom_envp = (int *) fw_arg2; + + mips_display_message("LINUX"); + + /* + * early setup of _pcictrl_bonito so that we can determine + * the system controller on a CORE_EMUL board + */ + _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); + + mips_revision_corid = MIPS_REVISION_CORID; + + if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { + if (BONITO_PCIDID == 0x0001df53 || + BONITO_PCIDID == 0x0003df53) + mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; + else + mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; + } + + mips_revision_sconid = MIPS_REVISION_SCONID; + if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_FPGAR2: + mips_revision_sconid = MIPS_REVISION_SCON_GT64120; + break; + case MIPS_REVISION_CORID_CORE_EMUL_BON: + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + mips_revision_sconid = MIPS_REVISION_SCON_BONITO; + break; + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_24K: + /* + * SOCit/ROCit support is essentially identical + * but make an attempt to distinguish them + */ + mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; + break; + case MIPS_REVISION_CORID_CORE_FPGA3: + case MIPS_REVISION_CORID_CORE_FPGA4: + case MIPS_REVISION_CORID_CORE_FPGA5: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + default: + /* See above */ + mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; + break; + } + } + + switch (mips_revision_sconid) { + u32 start, map, mask, data; + + case MIPS_REVISION_SCON_GT64120: + /* + * Setup the North bridge to do Master byte-lane swapping + * when running in bigendian. + */ + _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); + +#ifdef CONFIG_CPU_LITTLE_ENDIAN + GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | + GT_PCI0_CMD_SBYTESWAP_BIT); +#else + GT_WRITE(GT_PCI0_CMD_OFS, 0); +#endif + /* Fix up PCI I/O mapping if necessary (for Atlas). */ + start = GT_READ(GT_PCI0IOLD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + if ((start & map) != 0) { + map &= ~start; + GT_WRITE(GT_PCI0IOREMAP_OFS, map); + } + + set_io_port_base(MALTA_GT_PORT_BASE); + break; + + case MIPS_REVISION_SCON_BONITO: + _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); + + /* + * Disable Bonito IOBC. + */ + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + + /* + * Setup the North bridge to do Master byte-lane swapping + * when running in bigendian. + */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN + BONITO_BONGENCFG = BONITO_BONGENCFG & + ~(BONITO_BONGENCFG_MSTRBYTESWAP | + BONITO_BONGENCFG_BYTESWAP); +#else + BONITO_BONGENCFG = BONITO_BONGENCFG | + BONITO_BONGENCFG_MSTRBYTESWAP | + BONITO_BONGENCFG_BYTESWAP; +#endif + + set_io_port_base(MALTA_BONITO_PORT_BASE); + break; + + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); + mips_pci_controller: + mb(); + MSC_READ(MSC01_PCI_CFG, data); + MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); + wmb(); + + /* Fix up lane swapping. */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN + MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); +#else + MSC_WRITE(MSC01_PCI_SWAP, + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); +#endif + /* Fix up target memory mapping. */ + MSC_READ(MSC01_PCI_BAR0, mask); + MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); + + /* Don't handle target retries indefinitely. */ + if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == + MSC01_PCI_CFG_MAXRTRY_MSK) + data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << + MSC01_PCI_CFG_MAXRTRY_SHF)) | + ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << + MSC01_PCI_CFG_MAXRTRY_SHF); + + wmb(); + MSC_WRITE(MSC01_PCI_CFG, data); + mb(); + + set_io_port_base(MALTA_MSC_PORT_BASE); + break; + + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); + goto mips_pci_controller; + + default: + /* Unknown system controller */ + mips_display_message("SC Error"); + while (1); /* We die here... */ + } + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + pr_info("\nLINUX started...\n"); + prom_init_cmdline(); + prom_meminit(); +#ifdef CONFIG_SERIAL_8250_CONSOLE + console_config(); +#endif +#ifdef CONFIG_MIPS_CMP + register_smp_ops(&cmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMP + register_smp_ops(&vsmp_smp_ops); +#endif +#ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msmtc_smp_ops); +#endif +} diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c new file mode 100644 index 000000000000..ea176113fea9 --- /dev/null +++ b/arch/mips/mti-malta/malta-int.c @@ -0,0 +1,712 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the MIPS + * Malta board. + * The interrupt controller is located in the South Bridge a PIIX4 device + * with two internal 82C95 interrupt controllers. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int gcmp_present = -1; +int gic_present; +static unsigned long _msc01_biu_base; +static unsigned long _gcmp_base; +static unsigned int ipi_map[NR_CPUS]; + +static DEFINE_SPINLOCK(mips_irq_lock); + +static inline int mips_pcibios_iack(void) +{ + int irq; + u32 dummy; + + /* + * Determine highest priority pending interrupt by performing + * a PCI Interrupt Acknowledge cycle. + */ + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + MSC_READ(MSC01_PCI_IACK, irq); + irq &= 0xff; + break; + case MIPS_REVISION_SCON_GT64120: + irq = GT_READ(GT_PCI0_IACK_OFS); + irq &= 0xff; + break; + case MIPS_REVISION_SCON_BONITO: + /* The following will generate a PCI IACK cycle on the + * Bonito controller. It's a little bit kludgy, but it + * was the easiest way to implement it in hardware at + * the given time. + */ + BONITO_PCIMAP_CFG = 0x20000; + + /* Flush Bonito register block */ + dummy = BONITO_PCIMAP_CFG; + iob(); /* sync */ + + irq = readl((u32 *)_pcictrl_bonito_pcicfg); + iob(); /* sync */ + irq &= 0xff; + BONITO_PCIMAP_CFG = 0; + break; + default: + printk(KERN_WARNING "Unknown system controller.\n"); + return -1; + } + return irq; +} + +static inline int get_int(void) +{ + unsigned long flags; + int irq; + spin_lock_irqsave(&mips_irq_lock, flags); + + irq = mips_pcibios_iack(); + + /* + * The only way we can decide if an interrupt is spurious + * is by checking the 8259 registers. This needs a spinlock + * on an SMP system, so leave it up to the generic code... + */ + + spin_unlock_irqrestore(&mips_irq_lock, flags); + + return irq; +} + +static void malta_hw0_irqdispatch(void) +{ + int irq; + + irq = get_int(); + if (irq < 0) { + /* interrupt has already been cleared */ + return; + } + + do_IRQ(MALTA_INT_BASE + irq); +} + +static void malta_ipi_irqdispatch(void) +{ + int irq; + + irq = gic_get_int(); + if (irq < 0) + return; /* interrupt has already been cleared */ + + do_IRQ(MIPS_GIC_IRQ_BASE + irq); +} + +static void corehi_irqdispatch(void) +{ + unsigned int intedge, intsteer, pcicmd, pcibadaddr; + unsigned int pcimstat, intisr, inten, intpol; + unsigned int intrcause, datalo, datahi; + struct pt_regs *regs = get_irq_regs(); + + printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); + printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" + "Cause : %08lx\nbadVaddr : %08lx\n", + regs->cp0_epc, regs->cp0_status, + regs->cp0_cause, regs->cp0_badvaddr); + + /* Read all the registers and then print them as there is a + problem with interspersed printk's upsetting the Bonito controller. + Do it for the others too. + */ + + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + ll_msc_irq(); + break; + case MIPS_REVISION_SCON_GT64120: + intrcause = GT_READ(GT_INTRCAUSE_OFS); + datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); + datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); + printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); + printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", + datahi, datalo); + break; + case MIPS_REVISION_SCON_BONITO: + pcibadaddr = BONITO_PCIBADADDR; + pcimstat = BONITO_PCIMSTAT; + intisr = BONITO_INTISR; + inten = BONITO_INTEN; + intpol = BONITO_INTPOL; + intedge = BONITO_INTEDGE; + intsteer = BONITO_INTSTEER; + pcicmd = BONITO_PCICMD; + printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); + printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); + printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); + printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); + printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); + printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); + printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); + printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); + break; + } + + die("CoreHi interrupt", regs); +} + +static inline int clz(unsigned long x) +{ + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +/* + * Version of ffs that only looks at bits 12..15. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return -clz(pending) + 31 - CAUSEB_IP; +#else + unsigned int a0 = 7; + unsigned int t0; + + t0 = pending & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0x8000; + t0 = t0 < 1; + /* t0 = t0 << 2; */ + a0 = a0 - t0; + /* pending = pending << t0; */ + + return a0; +#endif +} + +/* + * IRQs on the Malta board look basically (barring software IRQs which we + * don't use at all and all external interrupt sources are combined together + * on hardware interrupt 0 (MIPS IRQ 2)) like: + * + * MIPS IRQ Source + * -------- ------ + * 0 Software (ignored) + * 1 Software (ignored) + * 2 Combined hardware interrupt (hw0) + * 3 Hardware (ignored) + * 4 Hardware (ignored) + * 5 Hardware (ignored) + * 6 Hardware (ignored) + * 7 R4k timer (what we use) + * + * We handle the IRQ according to _our_ priority which is: + * + * Highest ---- R4k Timer + * Lowest ---- Combined hardware interrupt + * + * then we just return, if multiple IRQs are pending then we will just take + * another exception, big deal. + */ + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq == MIPSCPU_INT_I8259A) + malta_hw0_irqdispatch(); + else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()])) + malta_ipi_irqdispatch(); + else if (irq >= 0) + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + else + spurious_interrupt(); +} + +#ifdef CONFIG_MIPS_MT_SMP + + +#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 +#define GIC_MIPS_CPU_IPI_CALL_IRQ 4 + +#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ +#define C_RESCHED C_SW0 +#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ +#define C_CALL C_SW1 +static int cpu_ipi_resched_irq, cpu_ipi_call_irq; + +static void ipi_resched_dispatch(void) +{ + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); +} + +static void ipi_call_dispatch(void) +{ + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); +} + +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) +{ + smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +static struct irqaction irq_resched = { + .handler = ipi_resched_interrupt, + .flags = IRQF_DISABLED|IRQF_PERCPU, + .name = "IPI_resched" +}; + +static struct irqaction irq_call = { + .handler = ipi_call_interrupt, + .flags = IRQF_DISABLED|IRQF_PERCPU, + .name = "IPI_call" +}; +#endif /* CONFIG_MIPS_MT_SMP */ + +static struct irqaction i8259irq = { + .handler = no_action, + .name = "XT-PIC cascade" +}; + +static struct irqaction corehi_irqaction = { + .handler = no_action, + .name = "CoreHi" +}; + +static msc_irqmap_t __initdata msc_irqmap[] = { + {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, + {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, +}; +static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); + +static msc_irqmap_t __initdata msc_eicirqmap[] = { + {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, + {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} +}; + +static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); + +#if defined(CONFIG_MIPS_MT_SMP) +/* + * This GIC specific tabular array defines the association between External + * Interrupts and CPUs/Core Interrupts. The nature of the External + * Interrupts is also defined here - polarity/trigger. + */ +static struct gic_intr_map gic_intr_map[] = { + { GIC_EXT_INTR(0), X, X, X, X, 0 }, + { GIC_EXT_INTR(1), X, X, X, X, 0 }, + { GIC_EXT_INTR(2), X, X, X, X, 0 }, + { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(10), X, X, X, X, 0 }, + { GIC_EXT_INTR(11), X, X, X, X, 0 }, + { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, + { GIC_EXT_INTR(15), X, X, X, X, 0 }, + { GIC_EXT_INTR(16), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(17), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(18), 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(19), 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(20), 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(21), 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, + { GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 }, +}; +#endif + +/* + * GCMP needs to be detected before any SMP initialisation + */ +static int __init gcmp_probe(unsigned long addr, unsigned long size) +{ + if (gcmp_present >= 0) + return gcmp_present; + + _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); + _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); + gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; + + if (gcmp_present) + printk(KERN_DEBUG "GCMP present\n"); + return gcmp_present; +} + +#if defined(CONFIG_MIPS_MT_SMP) +static void __init fill_ipi_map(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) { + if (gic_intr_map[i].ipiflag && (gic_intr_map[i].cpunum != X)) + ipi_map[gic_intr_map[i].cpunum] |= + (1 << (gic_intr_map[i].pin + 2)); + } +} +#endif + +void __init arch_init_irq(void) +{ + int gic_present, gcmp_present; + + init_i8259_irqs(); + + if (!cpu_has_veic) + mips_cpu_irq_init(); + + gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); + if (gcmp_present) { + GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; + gic_present = 1; + } else { + _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); + gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & + MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; + } + if (gic_present) + printk(KERN_DEBUG "GIC present\n"); + + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + if (cpu_has_veic) + init_msc_irqs(MIPS_MSC01_IC_REG_BASE, + MSC01E_INT_BASE, msc_eicirqmap, + msc_nr_eicirqs); + else + init_msc_irqs(MIPS_MSC01_IC_REG_BASE, + MSC01C_INT_BASE, msc_irqmap, + msc_nr_irqs); + break; + + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + if (cpu_has_veic) + init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, + MSC01E_INT_BASE, msc_eicirqmap, + msc_nr_eicirqs); + else + init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, + MSC01C_INT_BASE, msc_irqmap, + msc_nr_irqs); + } + + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); + setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); + setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); + } else if (cpu_has_vint) { + set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); +#ifdef CONFIG_MIPS_MT_SMTC + setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, + (0x100 << MIPSCPU_INT_I8259A)); + setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, + &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); + /* + * Temporary hack to ensure that the subsidiary device + * interrupts coing in via the i8259A, but associated + * with low IRQ numbers, will restore the Status.IM + * value associated with the i8259A. + */ + { + int i; + + for (i = 0; i < 16; i++) + irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); + } +#else /* Not SMTC */ + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, + &corehi_irqaction); +#endif /* CONFIG_MIPS_MT_SMTC */ + } else { + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, + &corehi_irqaction); + } + +#if defined(CONFIG_MIPS_MT_SMP) + if (gic_present) { + /* FIXME */ + int i; + struct { + unsigned int resched; + unsigned int call; + } ipiirq[] = { + { + .resched = GIC_IPI_EXT_INTR_RESCHED_VPE0, + .call = GIC_IPI_EXT_INTR_CALLFNC_VPE0}, + { + .resched = GIC_IPI_EXT_INTR_RESCHED_VPE1, + .call = GIC_IPI_EXT_INTR_CALLFNC_VPE1 + }, { + .resched = GIC_IPI_EXT_INTR_RESCHED_VPE2, + .call = GIC_IPI_EXT_INTR_CALLFNC_VPE2 + }, { + .resched = GIC_IPI_EXT_INTR_RESCHED_VPE3, + .call = GIC_IPI_EXT_INTR_CALLFNC_VPE3 + } + }; + fill_ipi_map(); + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); + if (!gcmp_present) { + /* Enable the GIC */ + i = REG(_msc01_biu_base, MSC01_SC_CFG); + REG(_msc01_biu_base, MSC01_SC_CFG) = + (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); + pr_debug("GIC Enabled\n"); + } + + /* set up ipi interrupts */ + if (cpu_has_vint) { + set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); + set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); + } + /* Argh.. this really needs sorting out.. */ + printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); + write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); + printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); + write_c0_status(0x1100dc00); + printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); + for (i = 0; i < ARRAY_SIZE(ipiirq); i++) { + setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched); + setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call); + + set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, handle_percpu_irq); + set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].call, handle_percpu_irq); + } + } else { + /* set up ipi interrupts */ + if (cpu_has_veic) { + set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); + set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); + cpu_ipi_resched_irq = MSC01E_INT_SW0; + cpu_ipi_call_irq = MSC01E_INT_SW1; + } else { + if (cpu_has_vint) { + set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); + set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); + } + cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; + cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; + } + + setup_irq(cpu_ipi_resched_irq, &irq_resched); + setup_irq(cpu_ipi_call_irq, &irq_call); + + set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); + set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); + } +#endif +} + +void malta_be_init(void) +{ + if (gcmp_present) { + /* Could change CM error mask register */ + } +} + + +static char *tr[8] = { + "mem", "gcr", "gic", "mmio", + "0x04", "0x05", "0x06", "0x07" +}; + +static char *mcmd[32] = { + [0x00] = "0x00", + [0x01] = "Legacy Write", + [0x02] = "Legacy Read", + [0x03] = "0x03", + [0x04] = "0x04", + [0x05] = "0x05", + [0x06] = "0x06", + [0x07] = "0x07", + [0x08] = "Coherent Read Own", + [0x09] = "Coherent Read Share", + [0x0a] = "Coherent Read Discard", + [0x0b] = "Coherent Ready Share Always", + [0x0c] = "Coherent Upgrade", + [0x0d] = "Coherent Writeback", + [0x0e] = "0x0e", + [0x0f] = "0x0f", + [0x10] = "Coherent Copyback", + [0x11] = "Coherent Copyback Invalidate", + [0x12] = "Coherent Invalidate", + [0x13] = "Coherent Write Invalidate", + [0x14] = "Coherent Completion Sync", + [0x15] = "0x15", + [0x16] = "0x16", + [0x17] = "0x17", + [0x18] = "0x18", + [0x19] = "0x19", + [0x1a] = "0x1a", + [0x1b] = "0x1b", + [0x1c] = "0x1c", + [0x1d] = "0x1d", + [0x1e] = "0x1e", + [0x1f] = "0x1f" +}; + +static char *core[8] = { + "Invalid/OK", "Invalid/Data", + "Shared/OK", "Shared/Data", + "Modified/OK", "Modified/Data", + "Exclusive/OK", "Exclusive/Data" +}; + +static char *causes[32] = { + "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR", + "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07", + "0x08", "0x09", "0x0a", "0x0b", + "0x0c", "0x0d", "0x0e", "0x0f", + "0x10", "0x11", "0x12", "0x13", + "0x14", "0x15", "0x16", "INTVN_WR_ERR", + "INTVN_RD_ERR", "0x19", "0x1a", "0x1b", + "0x1c", "0x1d", "0x1e", "0x1f" +}; + +int malta_be_handler(struct pt_regs *regs, int is_fixup) +{ + /* This duplicates the handling in do_be which seems wrong */ + int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; + + if (gcmp_present) { + unsigned long cm_error = GCMPGCB(GCMEC); + unsigned long cm_addr = GCMPGCB(GCMEA); + unsigned long cm_other = GCMPGCB(GCMEO); + unsigned long cause, ocause; + char buf[256]; + + cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); + if (cause != 0) { + cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; + if (cause < 16) { + unsigned long cca_bits = (cm_error >> 15) & 7; + unsigned long tr_bits = (cm_error >> 12) & 7; + unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; + unsigned long stag_bits = (cm_error >> 3) & 15; + unsigned long sport_bits = (cm_error >> 0) & 7; + + snprintf(buf, sizeof(buf), + "CCA=%lu TR=%s MCmd=%s STag=%lu " + "SPort=%lu\n", + cca_bits, tr[tr_bits], mcmd[mcmd_bits], + stag_bits, sport_bits); + } else { + /* glob state & sresp together */ + unsigned long c3_bits = (cm_error >> 18) & 7; + unsigned long c2_bits = (cm_error >> 15) & 7; + unsigned long c1_bits = (cm_error >> 12) & 7; + unsigned long c0_bits = (cm_error >> 9) & 7; + unsigned long sc_bit = (cm_error >> 8) & 1; + unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; + unsigned long sport_bits = (cm_error >> 0) & 7; + snprintf(buf, sizeof(buf), + "C3=%s C2=%s C1=%s C0=%s SC=%s " + "MCmd=%s SPort=%lu\n", + core[c3_bits], core[c2_bits], + core[c1_bits], core[c0_bits], + sc_bit ? "True" : "False", + mcmd[mcmd_bits], sport_bits); + } + + ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> + GCMP_GCB_GMEO_ERROR_2ND_SHF; + + printk("CM_ERROR=%08lx %s <%s>\n", cm_error, + causes[cause], buf); + printk("CM_ADDR =%08lx\n", cm_addr); + printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); + + /* reprime cause register */ + GCMPGCB(GCMEC) = 0; + } + } + + return retval; +} diff --git a/arch/mips/mti-malta/malta-kgdb.c b/arch/mips/mti-malta/malta-kgdb.c new file mode 100644 index 000000000000..6a1854de4579 --- /dev/null +++ b/arch/mips/mti-malta/malta-kgdb.c @@ -0,0 +1,133 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * This is the interface to the remote debugger stub. + */ +#include +#include +#include +#include + +#include +#include + +static struct serial_state rs_table[] = { + SERIAL_PORT_DFNS /* Defined in serial.h */ +}; + +static struct async_struct kdb_port_info = {0}; + +int (*generic_putDebugChar)(char); +char (*generic_getDebugChar)(void); + +static __inline__ unsigned int serial_in(struct async_struct *info, int offset) +{ + return inb(info->port + offset); +} + +static __inline__ void serial_out(struct async_struct *info, int offset, + int value) +{ + outb(value, info->port+offset); +} + +int rs_kgdb_hook(int tty_no, int speed) { + int t; + struct serial_state *ser = &rs_table[tty_no]; + + kdb_port_info.state = ser; + kdb_port_info.magic = SERIAL_MAGIC; + kdb_port_info.port = ser->port; + kdb_port_info.flags = ser->flags; + + /* + * Clear all interrupts + */ + serial_in(&kdb_port_info, UART_LSR); + serial_in(&kdb_port_info, UART_RX); + serial_in(&kdb_port_info, UART_IIR); + serial_in(&kdb_port_info, UART_MSR); + + /* + * Now, initialize the UART + */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ + if (kdb_port_info.flags & ASYNC_FOURPORT) { + kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS; + t = UART_MCR_DTR | UART_MCR_OUT1; + } else { + kdb_port_info.MCR + = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; + t = UART_MCR_DTR | UART_MCR_RTS; + } + + kdb_port_info.MCR = t; /* no interrupts, please */ + serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR); + + /* + * and set the speed of the serial port + */ + if (speed == 0) + speed = 9600; + + t = kdb_port_info.state->baud_base / speed; + /* set DLAB */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB); + serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */ + serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */ + /* reset DLAB */ + serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); + + return speed; +} + +int putDebugChar(char c) +{ + return generic_putDebugChar(c); +} + +char getDebugChar(void) +{ + return generic_getDebugChar(); +} + +int rs_putDebugChar(char c) +{ + + if (!kdb_port_info.state) { /* need to init device first */ + return 0; + } + + while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(&kdb_port_info, UART_TX, c); + + return 1; +} + +char rs_getDebugChar(void) +{ + if (!kdb_port_info.state) { /* need to init device first */ + return 0; + } + + while (!(serial_in(&kdb_port_info, UART_LSR) & 1)) + ; + + return serial_in(&kdb_port_info, UART_RX); +} diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c new file mode 100644 index 000000000000..61888ff72c87 --- /dev/null +++ b/arch/mips/mti-malta/malta-memory.c @@ -0,0 +1,177 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library functions for acquiring/using memory descriptors given to + * us from the YAMON. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/*#define DEBUG*/ + +enum yamon_memtypes { + yamon_dontuse, + yamon_prom, + yamon_free, +}; +static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; + +#ifdef DEBUG +static char *mtypes[3] = { + "Dont use memory", + "YAMON PROM memory", + "Free memmory", +}; +#endif + +/* determined physical memory size, not overridden by command line args */ +unsigned long physical_memsize = 0L; + +static struct prom_pmemblock * __init prom_getmdesc(void) +{ + char *memsize_str; + unsigned int memsize; + char cmdline[CL_SIZE], *ptr; + + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + printk(KERN_WARNING + "memsize not set in boot prom, set to default (32Mb)\n"); + physical_memsize = 0x02000000; + } else { +#ifdef DEBUG + pr_debug("prom_memsize = %s\n", memsize_str); +#endif + physical_memsize = simple_strtol(memsize_str, NULL, 0); + } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + word of physical memory */ + physical_memsize -= PAGE_SIZE; +#endif + + /* Check the command line for a memsize directive that overrides + the physical/default amount */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) + memsize = memparse(ptr + 8, &ptr); + else + memsize = physical_memsize; + + memset(mdesc, 0, sizeof(mdesc)); + + mdesc[0].type = yamon_dontuse; + mdesc[0].base = 0x00000000; + mdesc[0].size = 0x00001000; + + mdesc[1].type = yamon_prom; + mdesc[1].base = 0x00001000; + mdesc[1].size = 0x000ef000; + + /* + * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the + * south bridge and PCI access always forwarded to the ISA Bus and + * BIOSCS# is always generated. + * This mean that this area can't be used as DMA memory for PCI + * devices. + */ + mdesc[2].type = yamon_dontuse; + mdesc[2].base = 0x000f0000; + mdesc[2].size = 0x00010000; + + mdesc[3].type = yamon_dontuse; + mdesc[3].base = 0x00100000; + mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - mdesc[3].base; + + mdesc[4].type = yamon_free; + mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); + mdesc[4].size = memsize - mdesc[4].base; + + return &mdesc[0]; +} + +static int __init prom_memtype_classify(unsigned int type) +{ + switch (type) { + case yamon_free: + return BOOT_MEM_RAM; + case yamon_prom: + return BOOT_MEM_ROM_DATA; + default: + return BOOT_MEM_RESERVED; + } +} + +void __init prom_meminit(void) +{ + struct prom_pmemblock *p; + +#ifdef DEBUG + pr_debug("YAMON MEMORY DESCRIPTOR dump:\n"); + p = prom_getmdesc(); + while (p->size) { + int i = 0; + pr_debug("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", + i, p, p->base, p->size, mtypes[p->type]); + p++; + i++; + } +#endif + p = prom_getmdesc(); + + while (p->size) { + long type; + unsigned long base, size; + + type = prom_memtype_classify(p->type); + base = p->base; + size = p->size; + + add_memory_region(base, size, type); + p++; + } +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/mti-malta/malta-mtd.c b/arch/mips/mti-malta/malta-mtd.c new file mode 100644 index 000000000000..8ad9bdf25dce --- /dev/null +++ b/arch/mips/mti-malta/malta-mtd.c @@ -0,0 +1,63 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 MIPS Technologies, Inc. + * written by Ralf Baechle + */ + +#include +#include +#include +#include +#include + +static struct mtd_partition malta_mtd_partitions[] = { + { + .name = "YAMON", + .offset = 0x0, + .size = 0x100000, + .mask_flags = MTD_WRITEABLE + }, { + .name = "User FS", + .offset = 0x100000, + .size = 0x2e0000 + }, { + .name = "Board Config", + .offset = 0x3e0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE + } +}; + +static struct physmap_flash_data malta_flash_data = { + .width = 4, + .nr_parts = ARRAY_SIZE(malta_mtd_partitions), + .parts = malta_mtd_partitions +}; + +static struct resource malta_flash_resource = { + .start = 0x1e000000, + .end = 0x1e3fffff, + .flags = IORESOURCE_MEM +}; + +static struct platform_device malta_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &malta_flash_data, + }, + .num_resources = 1, + .resource = &malta_flash_resource, +}; + +static int __init malta_mtd_init(void) +{ + platform_device_register(&malta_flash); + + return 0; +} + +module_init(malta_mtd_init) diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c new file mode 100644 index 000000000000..b9743190609a --- /dev/null +++ b/arch/mips/mti-malta/malta-pci.c @@ -0,0 +1,243 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * MIPS boards specific PCI support. + */ +#include +#include +#include +#include + +#include + +#include +#include +#include + +static struct resource bonito64_mem_resource = { + .name = "Bonito PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource bonito64_io_resource = { + .name = "Bonito PCI I/O", + .start = 0x00000000UL, + .end = 0x000fffffUL, + .flags = IORESOURCE_IO, +}; + +static struct resource gt64120_mem_resource = { + .name = "GT-64120 PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource gt64120_io_resource = { + .name = "GT-64120 PCI I/O", + .flags = IORESOURCE_IO, +}; + +static struct resource msc_mem_resource = { + .name = "MSC PCI MEM", + .flags = IORESOURCE_MEM, +}; + +static struct resource msc_io_resource = { + .name = "MSC PCI I/O", + .flags = IORESOURCE_IO, +}; + +extern struct pci_ops bonito64_pci_ops; +extern struct pci_ops gt64xxx_pci0_ops; +extern struct pci_ops msc_pci_ops; + +static struct pci_controller bonito64_controller = { + .pci_ops = &bonito64_pci_ops, + .io_resource = &bonito64_io_resource, + .mem_resource = &bonito64_mem_resource, + .io_offset = 0x00000000UL, +}; + +static struct pci_controller gt64120_controller = { + .pci_ops = >64xxx_pci0_ops, + .io_resource = >64120_io_resource, + .mem_resource = >64120_mem_resource, +}; + +static struct pci_controller msc_controller = { + .pci_ops = &msc_pci_ops, + .io_resource = &msc_io_resource, + .mem_resource = &msc_mem_resource, +}; + +void __init mips_pcibios_init(void) +{ + struct pci_controller *controller; + resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; + + switch (mips_revision_sconid) { + case MIPS_REVISION_SCON_GT64120: + /* + * Due to a bug in the Galileo system controller, we need + * to setup the PCI BAR for the Galileo internal registers. + * This should be done in the bios/bootprom and will be + * fixed in a later revision of YAMON (the MIPS boards + * boot prom). + */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ + (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ + ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + /* Perform the write */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); + + /* Set up resource ranges from the controller's registers. */ + start = GT_READ(GT_PCI0M0LD_OFS); + end = GT_READ(GT_PCI0M0HD_OFS); + map = GT_READ(GT_PCI0M0REMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + start1 = GT_READ(GT_PCI0M1LD_OFS); + end1 = GT_READ(GT_PCI0M1HD_OFS); + map1 = GT_READ(GT_PCI0M1REMAP_OFS); + end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); + /* Cannot support multiple windows, use the wider. */ + if (end1 - start1 > end - start) { + start = start1; + end = end1; + map = map1; + } + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_mem_resource.start = start; + gt64120_mem_resource.end = end; + gt64120_controller.mem_offset = (start & mask) - (map & mask); + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; + + start = GT_READ(GT_PCI0IOLD_OFS); + end = GT_READ(GT_PCI0IOHD_OFS); + map = GT_READ(GT_PCI0IOREMAP_OFS); + end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); + mask = ~(start ^ end); + /* We don't support remapping with a discontiguous mask. */ + BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && + mask != ~((mask & -mask) - 1)); + gt64120_io_resource.start = map & mask; + gt64120_io_resource.end = (map & mask) | ~mask; + gt64120_controller.io_offset = 0; + /* Addresses are 36-bit, so do shifts in the destinations. */ + gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; + gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; + + controller = >64120_controller; + break; + + case MIPS_REVISION_SCON_BONITO: + /* Set up resource ranges from the controller's registers. */ + map = BONITO_PCIMAP; + map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> + BONITO_PCIMAP_PCIMAP_LO0_SHIFT; + map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> + BONITO_PCIMAP_PCIMAP_LO1_SHIFT; + map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> + BONITO_PCIMAP_PCIMAP_LO2_SHIFT; + /* Combine as many adjacent windows as possible. */ + map = map1; + start = BONITO_PCILO0_BASE; + end = 1; + if (map3 == map2 + 1) { + map = map2; + start = BONITO_PCILO1_BASE; + end++; + } + if (map2 == map1 + 1) { + map = map1; + start = BONITO_PCILO0_BASE; + end++; + } + bonito64_mem_resource.start = start; + bonito64_mem_resource.end = start + + BONITO_PCIMAP_WINBASE(end) - 1; + bonito64_controller.mem_offset = start - + BONITO_PCIMAP_WINBASE(map); + + controller = &bonito64_controller; + break; + + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: + /* Set up resource ranges from the controller's registers. */ + MSC_READ(MSC01_PCI_SC2PMBASL, start); + MSC_READ(MSC01_PCI_SC2PMMSKL, mask); + MSC_READ(MSC01_PCI_SC2PMMAPL, map); + msc_mem_resource.start = start & mask; + msc_mem_resource.end = (start & mask) | ~mask; + msc_controller.mem_offset = (start & mask) - (map & mask); + + MSC_READ(MSC01_PCI_SC2PIOBASL, start); + MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); + MSC_READ(MSC01_PCI_SC2PIOMAPL, map); + msc_io_resource.start = map & mask; + msc_io_resource.end = (map & mask) | ~mask; + msc_controller.io_offset = 0; + ioport_resource.end = ~mask; + + /* If ranges overlap I/O takes precedence. */ + start = start & mask; + end = start | ~mask; + if ((start >= msc_mem_resource.start && + start <= msc_mem_resource.end) || + (end >= msc_mem_resource.start && + end <= msc_mem_resource.end)) { + /* Use the larger space. */ + start = max(start, msc_mem_resource.start); + end = min(end, msc_mem_resource.end); + if (start - msc_mem_resource.start >= + msc_mem_resource.end - end) + msc_mem_resource.end = start - 1; + else + msc_mem_resource.start = end + 1; + } + + controller = &msc_controller; + break; + default: + return; + } + + if (controller->io_resource->start < 0x00001000UL) /* FIXME */ + controller->io_resource->start = 0x00001000UL; + + iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ + ioport_resource.end = controller->io_resource->end; + + register_pci_controller(controller); +} diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c new file mode 100644 index 000000000000..83b9bab3cd3f --- /dev/null +++ b/arch/mips/mti-malta/malta-platform.c @@ -0,0 +1,65 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 MIPS Technologies, Inc. + * written by Ralf Baechle (ralf@linux-mips.org) + * + * Probe driver for the Malta's UART ports: + * + * o 2 ports in the SMC SuperIO + * o 1 port in the CBUS UART, a discrete 16550 which normally is only used + * for bringups. + * + * We don't use 8250_platform.c on Malta as it would result in the CBUS + * UART becoming ttyS0. + */ +#include +#include +#include + +#define SMC_PORT(base, int) \ +{ \ + .iobase = base, \ + .irq = int, \ + .uartclk = 1843200, \ + .iotype = UPIO_PORT, \ + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ + .regshift = 0, \ +} + +#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) + +static struct plat_serial8250_port uart8250_data[] = { + SMC_PORT(0x3F8, 4), + SMC_PORT(0x2F8, 3), + { + .mapbase = 0x1f000900, /* The CBUS UART */ + .irq = MIPS_CPU_IRQ_BASE + 2, + .uartclk = 3686400, /* Twice the usual clk! */ + .iotype = UPIO_MEM32, + .flags = CBUS_UART_FLAGS, + .regshift = 3, + }, + { }, +}; + +static struct platform_device uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = uart8250_data, + }, +}; + +static int __init uart8250_init(void) +{ + return platform_device_register(&uart8250_device); +} + +module_init(uart8250_init); + +MODULE_AUTHOR("Ralf Baechle "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("8250 UART probe driver for the Malta CBUS UART"); diff --git a/arch/mips/mti-malta/malta-reset.c b/arch/mips/mti-malta/malta-reset.c new file mode 100644 index 000000000000..42dee4da37ba --- /dev/null +++ b/arch/mips/mti-malta/malta-reset.c @@ -0,0 +1,56 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Reset the MIPS boards. + * + */ +#include + +#include +#include +#include + +static void mips_machine_restart(char *command); +static void mips_machine_halt(void); + +static void mips_machine_restart(char *command) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + +static void mips_machine_halt(void) +{ + unsigned int __iomem *softres_reg = + ioremap(SOFTRES_REG, sizeof(unsigned int)); + + __raw_writel(GORESET, softres_reg); +} + + +void mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; + pm_power_off = mips_machine_halt; +} diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c new file mode 100644 index 000000000000..e7cad54936ca --- /dev/null +++ b/arch/mips/mti-malta/malta-setup.c @@ -0,0 +1,229 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2008 Dmitri Vorobiev + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_VT +#include +#endif + +extern void malta_be_init(void); +extern int malta_be_handler(struct pt_regs *regs, int is_fixup); + +static struct resource standard_io_resources[] = { + { + .name = "dma1", + .start = 0x00, + .end = 0x1f, + .flags = IORESOURCE_BUSY + }, + { + .name = "timer", + .start = 0x40, + .end = 0x5f, + .flags = IORESOURCE_BUSY + }, + { + .name = "keyboard", + .start = 0x60, + .end = 0x6f, + .flags = IORESOURCE_BUSY + }, + { + .name = "dma page reg", + .start = 0x80, + .end = 0x8f, + .flags = IORESOURCE_BUSY + }, + { + .name = "dma2", + .start = 0xc0, + .end = 0xdf, + .flags = IORESOURCE_BUSY + }, +}; + +const char *get_system_type(void) +{ + return "MIPS Malta"; +} + +#if defined(CONFIG_MIPS_MT_SMTC) +const char display_string[] = " SMTC LINUX ON MALTA "; +#else +const char display_string[] = " LINUX ON MALTA "; +#endif /* CONFIG_MIPS_MT_SMTC */ + +#ifdef CONFIG_BLK_DEV_FD +static void __init fd_activate(void) +{ + /* + * Activate Floppy Controller in the SMSC FDC37M817 Super I/O + * Controller. + * Done by YAMON 2.00 onwards + */ + /* Entering config state. */ + SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); + + /* Activate floppy controller. */ + SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); + SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); + SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); + SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); + + /* Exit config state. */ + SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); +} +#endif + +#ifdef CONFIG_BLK_DEV_IDE +static void __init pci_clock_check(void) +{ + unsigned int __iomem *jmpr_p = + (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); + int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; + static const int pciclocks[] __initdata = { + 33, 20, 25, 30, 12, 16, 37, 10 + }; + int pciclock = pciclocks[jmpr]; + char *argptr = prom_getcmdline(); + + if (pciclock != 33 && !strstr(argptr, "idebus=")) { + printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " + "setting idebus\n", pciclock); + argptr += strlen(argptr); + sprintf(argptr, " idebus=%d", pciclock); + if (pciclock < 20 || pciclock > 66) + printk(KERN_WARNING "WARNING: IDE timing " + "calculations will be incorrect\n"); + } +} +#endif + +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) +static void __init screen_info_setup(void) +{ + screen_info = (struct screen_info) { + .orig_x = 0, + .orig_y = 25, + .ext_mem_k = 0, + .orig_video_page = 0, + .orig_video_mode = 0, + .orig_video_cols = 80, + .unused2 = 0, + .orig_video_ega_bx = 0, + .unused3 = 0, + .orig_video_lines = 25, + .orig_video_isVGA = VIDEO_TYPE_VGAC, + .orig_video_points = 16 + }; +} +#endif + +static void __init bonito_quirks_setup(void) +{ + char *argptr; + + argptr = prom_getcmdline(); + if (strstr(argptr, "debug")) { + BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; + printk(KERN_INFO "Enabled Bonito debug mode\n"); + } else + BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; + +#ifdef CONFIG_DMA_COHERENT + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + printk(KERN_INFO "Enabled Bonito CPU coherency\n"); + + argptr = prom_getcmdline(); + if (strstr(argptr, "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); + } + } else + panic("Hardware DMA cache coherency not supported"); +#endif +} + +void __init plat_mem_setup(void) +{ + unsigned int i; + + mips_pcibios_init(); + + /* Request I/O space for devices used on the Malta board. */ + for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) + request_resource(&ioport_resource, standard_io_resources+i); + + /* + * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. + */ + enable_dma(4); + +#ifdef CONFIG_KGDB + kgdb_config(); +#endif + +#ifdef CONFIG_DMA_COHERENT + if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) + panic("Hardware DMA cache coherency not supported"); +#endif + + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) + bonito_quirks_setup(); + +#ifdef CONFIG_BLK_DEV_IDE + pci_clock_check(); +#endif + +#ifdef CONFIG_BLK_DEV_FD + fd_activate(); +#endif + +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) + screen_info_setup(); +#endif + mips_reboot_setup(); + + board_be_init = malta_be_init; + board_be_handler = malta_be_handler; +} diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c new file mode 100644 index 000000000000..5ea705e49454 --- /dev/null +++ b/arch/mips/mti-malta/malta-smtc.c @@ -0,0 +1,154 @@ +/* + * Malta Platform-specific hooks for SMP operation + */ +#include +#include + +#include +#include +#include +#include + +/* VPE/SMP Prototype implements platform interfaces directly */ + +/* + * Cause the specified action to be performed on a targeted "CPU" + */ + +static void msmtc_send_ipi_single(int cpu, unsigned int action) +{ + /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ + smtc_send_ipi(cpu, LINUX_SMP_IPI, action); +} + +static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + msmtc_send_ipi_single(i, action); +} + +/* + * Post-config but pre-boot cleanup entry point + */ +static void __cpuinit msmtc_init_secondary(void) +{ + void smtc_init_secondary(void); + int myvpe; + + /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ + myvpe = read_c0_tcbind() & TCBIND_CURVPE; + if (myvpe != 0) { + /* Ideally, this should be done only once per VPE, but... */ + clear_c0_status(ST0_IM); + set_c0_status((0x100 << cp0_compare_irq) + | (0x100 << MIPS_CPU_IPI_IRQ)); + if (cp0_perfcount_irq >= 0) + set_c0_status(0x100 << cp0_perfcount_irq); + } + + smtc_init_secondary(); +} + +/* + * Platform "CPU" startup hook + */ +static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); +} + +/* + * SMP initialization finalization entry point + */ +static void __cpuinit msmtc_smp_finish(void) +{ + smtc_smp_finish(); +} + +/* + * Hook for after all CPUs are online + */ + +static void msmtc_cpus_done(void) +{ +} + +/* + * Platform SMP pre-initialization + * + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. + */ + +static void __init msmtc_smp_setup(void) +{ + mipsmt_build_cpu_map(0); +} + +static void __init msmtc_prepare_cpus(unsigned int max_cpus) +{ + mipsmt_prepare_cpus(); +} + +struct plat_smp_ops msmtc_smp_ops = { + .send_ipi_single = msmtc_send_ipi_single, + .send_ipi_mask = msmtc_send_ipi_mask, + .init_secondary = msmtc_init_secondary, + .smp_finish = msmtc_smp_finish, + .cpus_done = msmtc_cpus_done, + .boot_secondary = msmtc_boot_secondary, + .smp_setup = msmtc_smp_setup, + .prepare_cpus = msmtc_prepare_cpus, +}; + +#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * IRQ affinity hook + */ + + +void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity) +{ + cpumask_t tmask = affinity; + int cpu = 0; + void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); + + /* + * On the legacy Malta development board, all I/O interrupts + * are routed through the 8259 and combined in a single signal + * to the CPU daughterboard, and on the CoreFPGA2/3 34K models, + * that signal is brought to IP2 of both VPEs. To avoid racing + * concurrent interrupt service events, IP2 is enabled only on + * one VPE, by convention VPE0. So long as no bits are ever + * cleared in the affinity mask, there will never be any + * interrupt forwarding. But as soon as a program or operator + * sets affinity for one of the related IRQs, we need to make + * sure that we don't ever try to forward across the VPE boundry, + * at least not until we engineer a system where the interrupt + * _ack() or _end() function can somehow know that it corresponds + * to an interrupt taken on another VPE, and perform the appropriate + * restoration of Status.IM state using MFTR/MTTR instead of the + * normal local behavior. We also ensure that no attempt will + * be made to forward to an offline "CPU". + */ + + for_each_cpu_mask(cpu, affinity) { + if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) + cpu_clear(cpu, tmask); + } + irq_desc[irq].affinity = tmask; + + if (cpus_empty(tmask)) + /* + * We could restore a default mask here, but the + * runtime code can anyway deal with the null set + */ + printk(KERN_WARNING + "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); + + /* Do any generic SMTC IRQ affinity setup */ + smtc_set_irq_affinity(irq, tmask); +} +#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c new file mode 100644 index 000000000000..0b97d47691fc --- /dev/null +++ b/arch/mips/mti-malta/malta-time.c @@ -0,0 +1,163 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Setting up the clock on the MIPS boards. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +unsigned long cpu_khz; + +static int mips_cpu_timer_irq; +static int mips_cpu_perf_irq; +extern int cp0_perfcount_irq; + +static void mips_timer_dispatch(void) +{ + do_IRQ(mips_cpu_timer_irq); +} + +static void mips_perf_dispatch(void) +{ + do_IRQ(mips_cpu_perf_irq); +} + +/* + * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect + */ +static unsigned int __init estimate_cpu_frequency(void) +{ + unsigned int prid = read_c0_prid() & 0xffff00; + unsigned int count; + + unsigned long flags; + unsigned int start; + + local_irq_save(flags); + + /* Start counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + /* Start r4k counter. */ + start = read_c0_count(); + + /* Read counter exactly on falling edge of update flag */ + while (CMOS_READ(RTC_REG_A) & RTC_UIP); + while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + + count = read_c0_count() - start; + + /* restore interrupts */ + local_irq_restore(flags); + + mips_hpt_frequency = count; + if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && + (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) + count *= 2; + + count += 5000; /* round */ + count -= count%10000; + + return count; +} + +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} + +static void __init plat_perf_setup(void) +{ +#ifdef MSC01E_INT_BASE + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); + mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; + } else +#endif + if (cp0_perfcount_irq >= 0) { + if (cpu_has_vint) + set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); + mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; +#ifdef CONFIG_SMP + set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); +#endif + } +} + +unsigned int __cpuinit get_c0_compare_int(void) +{ +#ifdef MSC01E_INT_BASE + if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; + } else +#endif + { + if (cpu_has_vint) + set_vi_handler(cp0_compare_irq, mips_timer_dispatch); + mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; + } + + return mips_cpu_timer_irq; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq; + + /* Set Data mode - binary. */ + CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); + + est_freq = estimate_cpu_frequency(); + + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + (est_freq%1000000)*100/1000000); + + cpu_khz = est_freq / 1000; + + mips_scroll_message(); +#ifdef CONFIG_I8253 /* Only Malta has a PIT */ + setup_pit_timer(); +#endif + + plat_perf_setup(); +} diff --git a/include/asm-mips/mach-malta/cpu-feature-overrides.h b/include/asm-mips/mach-malta/cpu-feature-overrides.h new file mode 100644 index 000000000000..7f3e3f9bd23a --- /dev/null +++ b/include/asm-mips/mach-malta/cpu-feature-overrides.h @@ -0,0 +1,72 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Chris Dearman + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H + + +/* + * CPU feature overrides for MIPS boards + */ +#ifdef CONFIG_CPU_MIPS32 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#ifdef CONFIG_CPU_HAS_LLSC +#define cpu_has_llsc 1 +#else +#define cpu_has_llsc 0 +#endif +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#ifdef CONFIG_CPU_MIPS64 +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +/* #define cpu_has_fpu ? */ +/* #define cpu_has_32fpr ? */ +#define cpu_has_counter 1 +/* #define cpu_has_watch ? */ +#define cpu_has_divec 1 +#define cpu_has_vce 0 +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +/* #define cpu_has_prefetch ? */ +#define cpu_has_mcheck 1 +/* #define cpu_has_ejtag ? */ +#define cpu_has_llsc 1 +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +#define cpu_has_nofpuex 0 +/* #define cpu_has_64bits ? */ +/* #define cpu_has_64bit_zero_reg ? */ +/* #define cpu_has_inclusive_pcaches ? */ +#define cpu_icache_snoops_remote_store 1 +#endif + +#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-malta/irq.h b/include/asm-mips/mach-malta/irq.h new file mode 100644 index 000000000000..9b9da26683c2 --- /dev/null +++ b/include/asm-mips/mach-malta/irq.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_MIPS_IRQ_H +#define __ASM_MACH_MIPS_IRQ_H + + +#define NR_IRQS 256 + +#include_next + +#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/include/asm-mips/mach-malta/kernel-entry-init.h b/include/asm-mips/mach-malta/kernel-entry-init.h new file mode 100644 index 000000000000..0b793e7bf67e --- /dev/null +++ b/include/asm-mips/mach-malta/kernel-entry-init.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Chris Dearman (chris@mips.com) + * Copyright (C) 2007 Mips Technologies, Inc. + */ +#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H + + .macro kernel_entry_setup +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 t0, CP0_CONFIG + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 3 + and t0, 1<<2 + bnez t0, 0f +9: + /* Assume we came from YAMON... */ + PTR_LA v0, 0x9fc00534 /* YAMON print */ + lw v0, (v0) + move a0, zero + PTR_LA a1, nonmt_processor + jal v0 + + PTR_LA v0, 0x9fc00520 /* YAMON exit */ + lw v0, (v0) + li a0, 1 + jal v0 + +1: b 1b + + __INITDATA +nonmt_processor: + .asciz "SMTC kernel requires the MT ASE to run\n" + __FINIT +0: +#endif + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute C code. + */ + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/include/asm-mips/mach-malta/mach-gt64120.h b/include/asm-mips/mach-malta/mach-gt64120.h new file mode 100644 index 000000000000..0f863148f3b6 --- /dev/null +++ b/include/asm-mips/mach-malta/mach-gt64120.h @@ -0,0 +1,19 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H +#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H + +#define MIPS_GT_BASE 0x1be00000 + +extern unsigned long _pcictrl_gt64120; +/* + * GT64120 config space base address + */ +#define GT64120_BASE _pcictrl_gt64120 + +#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-malta/mc146818rtc.h b/include/asm-mips/mach-malta/mc146818rtc.h new file mode 100644 index 000000000000..ea612f37f614 --- /dev/null +++ b/include/asm-mips/mach-malta/mc146818rtc.h @@ -0,0 +1,48 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2003 by Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * RTC routines for Malta style attached PIIX4 device, which contains a + * Motorola MC146818A-compatible Real Time Clock. + */ +#ifndef __ASM_MACH_MALTA_MC146818RTC_H +#define __ASM_MACH_MALTA_MC146818RTC_H + +#include +#include +#include + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb(addr, MALTA_RTC_ADR_REG); + return inb(MALTA_RTC_DAT_REG); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb(addr, MALTA_RTC_ADR_REG); + outb(data, MALTA_RTC_DAT_REG); +} + +#define RTC_ALWAYS_BCD 0 + +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) + +#endif /* __ASM_MACH_MALTA_MC146818RTC_H */ diff --git a/include/asm-mips/mach-malta/war.h b/include/asm-mips/mach-malta/war.h new file mode 100644 index 000000000000..7c6931d5f45f --- /dev/null +++ b/include/asm-mips/mach-malta/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h deleted file mode 100644 index 7f3e3f9bd23a..000000000000 --- a/include/asm-mips/mach-mips/cpu-feature-overrides.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Chris Dearman - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H - - -/* - * CPU feature overrides for MIPS boards - */ -#ifdef CONFIG_CPU_MIPS32 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -/* #define cpu_has_fpu ? */ -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#ifdef CONFIG_CPU_HAS_LLSC -#define cpu_has_llsc 1 -#else -#define cpu_has_llsc 0 -#endif -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#define cpu_icache_snoops_remote_store 1 -#endif - -#ifdef CONFIG_CPU_MIPS64 -#define cpu_has_tlb 1 -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -/* #define cpu_has_fpu ? */ -/* #define cpu_has_32fpr ? */ -#define cpu_has_counter 1 -/* #define cpu_has_watch ? */ -#define cpu_has_divec 1 -#define cpu_has_vce 0 -/* #define cpu_has_cache_cdex_p ? */ -/* #define cpu_has_cache_cdex_s ? */ -/* #define cpu_has_prefetch ? */ -#define cpu_has_mcheck 1 -/* #define cpu_has_ejtag ? */ -#define cpu_has_llsc 1 -/* #define cpu_has_vtag_icache ? */ -/* #define cpu_has_dc_aliases ? */ -/* #define cpu_has_ic_fills_f_dc ? */ -#define cpu_has_nofpuex 0 -/* #define cpu_has_64bits ? */ -/* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_inclusive_pcaches ? */ -#define cpu_icache_snoops_remote_store 1 -#endif - -#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-mips/irq.h deleted file mode 100644 index 9b9da26683c2..000000000000 --- a/include/asm-mips/mach-mips/irq.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ASM_MACH_MIPS_IRQ_H -#define __ASM_MACH_MIPS_IRQ_H - - -#define NR_IRQS 256 - -#include_next - -#endif /* __ASM_MACH_MIPS_IRQ_H */ diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-mips/kernel-entry-init.h deleted file mode 100644 index 0b793e7bf67e..000000000000 --- a/include/asm-mips/mach-mips/kernel-entry-init.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Chris Dearman (chris@mips.com) - * Copyright (C) 2007 Mips Technologies, Inc. - */ -#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H -#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H - - .macro kernel_entry_setup -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 t0, CP0_CONFIG - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 1 - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 2 - bgez t0, 9f - mfc0 t0, CP0_CONFIG, 3 - and t0, 1<<2 - bnez t0, 0f -9: - /* Assume we came from YAMON... */ - PTR_LA v0, 0x9fc00534 /* YAMON print */ - lw v0, (v0) - move a0, zero - PTR_LA a1, nonmt_processor - jal v0 - - PTR_LA v0, 0x9fc00520 /* YAMON exit */ - lw v0, (v0) - li a0, 1 - jal v0 - -1: b 1b - - __INITDATA -nonmt_processor: - .asciz "SMTC kernel requires the MT ASE to run\n" - __FINIT -0: -#endif - .endm - -/* - * Do SMP slave processor setup necessary before we can safely execute C code. - */ - .macro smp_slave_setup - .endm - -#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h deleted file mode 100644 index 0f863148f3b6..000000000000 --- a/include/asm-mips/mach-mips/mach-gt64120.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H -#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H - -#define MIPS_GT_BASE 0x1be00000 - -extern unsigned long _pcictrl_gt64120; -/* - * GT64120 config space base address - */ -#define GT64120_BASE _pcictrl_gt64120 - -#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-mips/mc146818rtc.h b/include/asm-mips/mach-mips/mc146818rtc.h deleted file mode 100644 index ea612f37f614..000000000000 --- a/include/asm-mips/mach-mips/mc146818rtc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2003 by Ralf Baechle - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * RTC routines for Malta style attached PIIX4 device, which contains a - * Motorola MC146818A-compatible Real Time Clock. - */ -#ifndef __ASM_MACH_MALTA_MC146818RTC_H -#define __ASM_MACH_MALTA_MC146818RTC_H - -#include -#include -#include - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - outb(addr, MALTA_RTC_ADR_REG); - return inb(MALTA_RTC_DAT_REG); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - outb(addr, MALTA_RTC_ADR_REG); - outb(data, MALTA_RTC_DAT_REG); -} - -#define RTC_ALWAYS_BCD 0 - -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900) - -#endif /* __ASM_MACH_MALTA_MC146818RTC_H */ diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-mips/war.h deleted file mode 100644 index 7c6931d5f45f..000000000000 --- a/include/asm-mips/mach-mips/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_MIPS_WAR_H -#define __ASM_MIPS_MACH_MIPS_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 1 -#define MIPS_CACHE_SYNC_WAR 1 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ -- cgit v1.2.3 From 22b1d707ffc99faebd86257ad19d5bb9fc624734 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 11 Jul 2008 00:31:36 +0900 Subject: [MIPS] TXx9: Reorganize code Move arch/mips/{jmr3927,tx4927,tx4938} into arch/mips/txx9/ tree. This will help more code sharing and maintainance. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 +- arch/mips/Makefile | 12 +- arch/mips/jmr3927/common/Makefile | 7 - arch/mips/jmr3927/common/prom.c | 72 -- arch/mips/jmr3927/common/puts.c | 60 -- arch/mips/jmr3927/rbhma3100/Makefile | 8 - arch/mips/jmr3927/rbhma3100/init.c | 57 - arch/mips/jmr3927/rbhma3100/irq.c | 174 --- arch/mips/jmr3927/rbhma3100/kgdb_io.c | 105 -- arch/mips/jmr3927/rbhma3100/setup.c | 445 -------- arch/mips/pci/Makefile | 2 +- arch/mips/pci/fixup-jmr3927.c | 2 +- arch/mips/pci/fixup-rbtx4927.c | 2 +- arch/mips/pci/fixup-rbtx4938.c | 92 ++ arch/mips/pci/fixup-tx4938.c | 92 -- arch/mips/pci/ops-tx3927.c | 2 +- arch/mips/pci/ops-tx4927.c | 2 +- arch/mips/pci/ops-tx4938.c | 2 +- arch/mips/pci/pci-jmr3927.c | 2 +- arch/mips/tx4927/Kconfig | 3 - arch/mips/tx4927/common/Makefile | 10 - arch/mips/tx4927/common/smsc_fdc37m81x.c | 172 --- arch/mips/tx4927/common/tx4927_dbgio.c | 43 - arch/mips/tx4927/common/tx4927_irq.c | 65 -- arch/mips/tx4927/common/tx4927_prom.c | 142 --- arch/mips/tx4927/toshiba_rbtx4927/Makefile | 5 - .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 216 ---- .../toshiba_rbtx4927/toshiba_rbtx4927_prom.c | 91 -- .../toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 703 ------------ arch/mips/tx4938/Kconfig | 24 - arch/mips/tx4938/common/Makefile | 8 - arch/mips/tx4938/common/dbgio.c | 48 - arch/mips/tx4938/common/irq.c | 48 - arch/mips/tx4938/common/prom.c | 124 --- arch/mips/tx4938/toshiba_rbtx4938/Makefile | 7 - arch/mips/tx4938/toshiba_rbtx4938/irq.c | 161 --- arch/mips/tx4938/toshiba_rbtx4938/prom.c | 74 -- arch/mips/tx4938/toshiba_rbtx4938/setup.c | 1124 -------------------- arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c | 99 -- arch/mips/txx9/Kconfig | 28 + arch/mips/txx9/generic/Makefile | 10 + arch/mips/txx9/generic/dbgio.c | 48 + arch/mips/txx9/generic/irq_tx4927.c | 64 ++ arch/mips/txx9/generic/irq_tx4938.c | 48 + arch/mips/txx9/generic/mem_tx4927.c | 141 +++ arch/mips/txx9/generic/mem_tx4938.c | 124 +++ arch/mips/txx9/generic/smsc_fdc37m81x.c | 172 +++ arch/mips/txx9/jmr3927/Makefile | 8 + arch/mips/txx9/jmr3927/init.c | 57 + arch/mips/txx9/jmr3927/irq.c | 174 +++ arch/mips/txx9/jmr3927/kgdb_io.c | 105 ++ arch/mips/txx9/jmr3927/prom.c | 98 ++ arch/mips/txx9/jmr3927/setup.c | 445 ++++++++ arch/mips/txx9/rbtx4927/Makefile | 3 + arch/mips/txx9/rbtx4927/irq.c | 214 ++++ arch/mips/txx9/rbtx4927/prom.c | 91 ++ arch/mips/txx9/rbtx4927/setup.c | 703 ++++++++++++ arch/mips/txx9/rbtx4938/Makefile | 3 + arch/mips/txx9/rbtx4938/irq.c | 159 +++ arch/mips/txx9/rbtx4938/prom.c | 72 ++ arch/mips/txx9/rbtx4938/setup.c | 1122 +++++++++++++++++++ arch/mips/txx9/rbtx4938/spi_eeprom.c | 99 ++ include/asm-mips/jmr3927/jmr3927.h | 177 --- include/asm-mips/jmr3927/tx3927.h | 319 ------ include/asm-mips/jmr3927/txx927.h | 121 --- include/asm-mips/tx4927/smsc_fdc37m81x.h | 69 -- include/asm-mips/tx4927/toshiba_rbtx4927.h | 49 - include/asm-mips/tx4927/tx4927.h | 280 ----- include/asm-mips/tx4938/rbtx4938.h | 168 --- include/asm-mips/tx4938/spi.h | 20 - include/asm-mips/tx4938/tx4938.h | 628 ----------- include/asm-mips/txx9/jmr3927.h | 177 +++ include/asm-mips/txx9/rbtx4927.h | 49 + include/asm-mips/txx9/rbtx4938.h | 167 +++ include/asm-mips/txx9/smsc_fdc37m81x.h | 67 ++ include/asm-mips/txx9/spi.h | 19 + include/asm-mips/txx9/tx3927.h | 319 ++++++ include/asm-mips/txx9/tx4927.h | 280 +++++ include/asm-mips/txx9/tx4938.h | 627 +++++++++++ include/asm-mips/txx9/txx927.h | 121 +++ 80 files changed, 5920 insertions(+), 6033 deletions(-) delete mode 100644 arch/mips/jmr3927/common/Makefile delete mode 100644 arch/mips/jmr3927/common/prom.c delete mode 100644 arch/mips/jmr3927/common/puts.c delete mode 100644 arch/mips/jmr3927/rbhma3100/Makefile delete mode 100644 arch/mips/jmr3927/rbhma3100/init.c delete mode 100644 arch/mips/jmr3927/rbhma3100/irq.c delete mode 100644 arch/mips/jmr3927/rbhma3100/kgdb_io.c delete mode 100644 arch/mips/jmr3927/rbhma3100/setup.c create mode 100644 arch/mips/pci/fixup-rbtx4938.c delete mode 100644 arch/mips/pci/fixup-tx4938.c delete mode 100644 arch/mips/tx4927/Kconfig delete mode 100644 arch/mips/tx4927/common/Makefile delete mode 100644 arch/mips/tx4927/common/smsc_fdc37m81x.c delete mode 100644 arch/mips/tx4927/common/tx4927_dbgio.c delete mode 100644 arch/mips/tx4927/common/tx4927_irq.c delete mode 100644 arch/mips/tx4927/common/tx4927_prom.c delete mode 100644 arch/mips/tx4927/toshiba_rbtx4927/Makefile delete mode 100644 arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c delete mode 100644 arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c delete mode 100644 arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c delete mode 100644 arch/mips/tx4938/Kconfig delete mode 100644 arch/mips/tx4938/common/Makefile delete mode 100644 arch/mips/tx4938/common/dbgio.c delete mode 100644 arch/mips/tx4938/common/irq.c delete mode 100644 arch/mips/tx4938/common/prom.c delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/Makefile delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/irq.c delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/prom.c delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/setup.c delete mode 100644 arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c create mode 100644 arch/mips/txx9/Kconfig create mode 100644 arch/mips/txx9/generic/Makefile create mode 100644 arch/mips/txx9/generic/dbgio.c create mode 100644 arch/mips/txx9/generic/irq_tx4927.c create mode 100644 arch/mips/txx9/generic/irq_tx4938.c create mode 100644 arch/mips/txx9/generic/mem_tx4927.c create mode 100644 arch/mips/txx9/generic/mem_tx4938.c create mode 100644 arch/mips/txx9/generic/smsc_fdc37m81x.c create mode 100644 arch/mips/txx9/jmr3927/Makefile create mode 100644 arch/mips/txx9/jmr3927/init.c create mode 100644 arch/mips/txx9/jmr3927/irq.c create mode 100644 arch/mips/txx9/jmr3927/kgdb_io.c create mode 100644 arch/mips/txx9/jmr3927/prom.c create mode 100644 arch/mips/txx9/jmr3927/setup.c create mode 100644 arch/mips/txx9/rbtx4927/Makefile create mode 100644 arch/mips/txx9/rbtx4927/irq.c create mode 100644 arch/mips/txx9/rbtx4927/prom.c create mode 100644 arch/mips/txx9/rbtx4927/setup.c create mode 100644 arch/mips/txx9/rbtx4938/Makefile create mode 100644 arch/mips/txx9/rbtx4938/irq.c create mode 100644 arch/mips/txx9/rbtx4938/prom.c create mode 100644 arch/mips/txx9/rbtx4938/setup.c create mode 100644 arch/mips/txx9/rbtx4938/spi_eeprom.c delete mode 100644 include/asm-mips/jmr3927/jmr3927.h delete mode 100644 include/asm-mips/jmr3927/tx3927.h delete mode 100644 include/asm-mips/jmr3927/txx927.h delete mode 100644 include/asm-mips/tx4927/smsc_fdc37m81x.h delete mode 100644 include/asm-mips/tx4927/toshiba_rbtx4927.h delete mode 100644 include/asm-mips/tx4927/tx4927.h delete mode 100644 include/asm-mips/tx4938/rbtx4938.h delete mode 100644 include/asm-mips/tx4938/spi.h delete mode 100644 include/asm-mips/tx4938/tx4938.h create mode 100644 include/asm-mips/txx9/jmr3927.h create mode 100644 include/asm-mips/txx9/rbtx4927.h create mode 100644 include/asm-mips/txx9/rbtx4938.h create mode 100644 include/asm-mips/txx9/smsc_fdc37m81x.h create mode 100644 include/asm-mips/txx9/spi.h create mode 100644 include/asm-mips/txx9/tx3927.h create mode 100644 include/asm-mips/txx9/tx4927.h create mode 100644 include/asm-mips/txx9/tx4938.h create mode 100644 include/asm-mips/txx9/txx927.h (limited to 'include/asm-mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a0381427ec5c..3202960f7597 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -642,8 +642,7 @@ source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" -source "arch/mips/tx4927/Kconfig" -source "arch/mips/tx4938/Kconfig" +source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 36aa690484c8..8e1e49c5186b 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -553,8 +553,8 @@ all-$(CONFIG_SNI_RM) := vmlinux.ecoff # # Toshiba JMR-TX3927 board # -core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/jmr3927/rbhma3100/ \ - arch/mips/jmr3927/common/ +core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ \ + arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_JMR3927) += -Iinclude/asm-mips/mach-jmr3927 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 @@ -562,16 +562,16 @@ load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 # Toshiba RBTX4927 board or # Toshiba RBTX4937 board # -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ +core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ +core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_RBTX4927) += -Iinclude/asm-mips/mach-tx49xx load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 # # Toshiba RBTX4938 board # -core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/ -core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ +core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/generic/ cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 diff --git a/arch/mips/jmr3927/common/Makefile b/arch/mips/jmr3927/common/Makefile deleted file mode 100644 index 8fd4fcccf10e..000000000000 --- a/arch/mips/jmr3927/common/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for the common code of TOSHIBA JMR-TX3927 board -# - -obj-y += prom.o puts.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jmr3927/common/prom.c b/arch/mips/jmr3927/common/prom.c deleted file mode 100644 index 5398813e50e6..000000000000 --- a/arch/mips/jmr3927/common/prom.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * PROM library initialisation code, assuming a version of - * pmon is the boot code. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Based on arch/mips/au1000/common/prom.c - * - * This file was derived from Carsten Langgaard's - * arch/mips/mips-boards/xx files. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -#include - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - int prom_argc = fw_arg0; - char **prom_argv = (char **) fw_arg1; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/jmr3927/common/puts.c b/arch/mips/jmr3927/common/puts.c deleted file mode 100644 index c611ab497888..000000000000 --- a/arch/mips/jmr3927/common/puts.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Low level uart routines to directly access a TX[34]927 SIO. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com or source@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * Based on arch/mips/au1000/common/puts.c - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -#define TIMEOUT 0xffffff - -void -prom_putchar(char c) -{ - int i = 0; - - do { - i++; - if (i>TIMEOUT) - break; - } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); - tx3927_sioptr(1)->tfifo = c; - return; -} - -void -puts(const char *cp) -{ - while (*cp) - prom_putchar(*cp++); - prom_putchar('\r'); - prom_putchar('\n'); -} diff --git a/arch/mips/jmr3927/rbhma3100/Makefile b/arch/mips/jmr3927/rbhma3100/Makefile deleted file mode 100644 index d86e30dca8f3..000000000000 --- a/arch/mips/jmr3927/rbhma3100/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for TOSHIBA JMR-TX3927 board -# - -obj-y += init.o irq.o setup.o -obj-$(CONFIG_KGDB) += kgdb_io.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/jmr3927/rbhma3100/init.c b/arch/mips/jmr3927/rbhma3100/init.c deleted file mode 100644 index 700b9cf8eb9d..000000000000 --- a/arch/mips/jmr3927/rbhma3100/init.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * arch/mips/jmr3927/common/init.c - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -extern void __init prom_init_cmdline(void); - -const char *get_system_type(void) -{ - return "Toshiba" -#ifdef CONFIG_TOSHIBA_JMR3927 - " JMR_TX3927" -#endif - ; -} - -extern void puts(const char *cp); - -void __init prom_init(void) -{ -#ifdef CONFIG_TOSHIBA_JMR3927 - /* CCFG */ - if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) - puts("Warning: TX3927 TLB off\n"); -#endif - - prom_init_cmdline(); - add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); -} diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c deleted file mode 100644 index 3a47e8ce1196..000000000000 --- a/arch/mips/jmr3927/rbhma3100/irq.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#if JMR3927_IRQ_END > NR_IRQS -#error JMR3927_IRQ_END > NR_IRQS -#endif - -static unsigned char irc_level[TX3927_NUM_IR] = { - 5, 5, 5, 5, 5, 5, /* INT[5:0] */ - 7, 7, /* SIO */ - 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ - 6, 6, 6 /* TMR */ -}; - -/* - * CP0_STATUS is a thread's resource (saved/restored on context switch). - * So disable_irq/enable_irq MUST handle IOC/IRC registers. - */ -static void mask_irq_ioc(unsigned int irq) -{ - /* 0: mask */ - unsigned int irq_nr = irq - JMR3927_IRQ_IOC; - unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); - unsigned int bit = 1 << irq_nr; - jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); - /* flush write buffer */ - (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); -} -static void unmask_irq_ioc(unsigned int irq) -{ - /* 0: mask */ - unsigned int irq_nr = irq - JMR3927_IRQ_IOC; - unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); - unsigned int bit = 1 << irq_nr; - jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); - /* flush write buffer */ - (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long cp0_cause = read_c0_cause(); - int irq; - - if ((cp0_cause & CAUSEF_IP7) == 0) - return; - irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; - - do_IRQ(irq + JMR3927_IRQ_IRC); -} - -static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) -{ - unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); - int i; - - for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { - if (istat & (1 << i)) { - irq = JMR3927_IRQ_IOC + i; - do_IRQ(irq); - } - } - return IRQ_HANDLED; -} - -static struct irqaction ioc_action = { - .handler = jmr3927_ioc_interrupt, - .mask = CPU_MASK_NONE, - .name = "IOC", -}; - -static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) -{ - printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); - printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", - tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); - - return IRQ_HANDLED; -} -static struct irqaction pcierr_action = { - .handler = jmr3927_pcierr_interrupt, - .mask = CPU_MASK_NONE, - .name = "PCI error", -}; - -static void __init jmr3927_irq_init(void); - -void __init arch_init_irq(void) -{ - /* Now, interrupt control disabled, */ - /* all IRC interrupts are masked, */ - /* all IRC interrupt mode are Low Active. */ - - /* mask all IOC interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); - /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ - jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); - - /* clear PCI Soft interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); - /* clear PCI Reset interrupts */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - jmr3927_irq_init(); - - /* setup IOC interrupt 1 (PCI, MODEM) */ - setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); - -#ifdef CONFIG_PCI - setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); -#endif - - /* enable all CPU interrupt bits. */ - set_c0_status(ST0_IM); /* IE bit is still 0. */ -} - -static struct irq_chip jmr3927_irq_ioc = { - .name = "jmr3927_ioc", - .ack = mask_irq_ioc, - .mask = mask_irq_ioc, - .mask_ack = mask_irq_ioc, - .unmask = unmask_irq_ioc, -}; - -static void __init jmr3927_irq_init(void) -{ - u32 i; - - txx9_irq_init(TX3927_IRC_REG); - for (i = 0; i < TXx9_MAX_IR; i++) - txx9_irq_set_pri(i, irc_level[i]); - for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) - set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); -} diff --git a/arch/mips/jmr3927/rbhma3100/kgdb_io.c b/arch/mips/jmr3927/rbhma3100/kgdb_io.c deleted file mode 100644 index 342579cfdc01..000000000000 --- a/arch/mips/jmr3927/rbhma3100/kgdb_io.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Low level uart routines to directly access a TX[34]927 SIO. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com or source@mvista.com - * - * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -#define TIMEOUT 0xffffff - -static int remoteDebugInitialized = 0; -static void debugInit(int baud); - -int putDebugChar(unsigned char c) -{ - int i = 0; - - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(38400); - } - - do { - slow_down(); - i++; - if (i>TIMEOUT) { - break; - } - } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS)); - tx3927_sioptr(0)->tfifo = c; - - return 1; -} - -unsigned char getDebugChar(void) -{ - int i = 0; - int dicr; - char c; - - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(38400); - } - - /* diable RX int. */ - dicr = tx3927_sioptr(0)->dicr; - tx3927_sioptr(0)->dicr = 0; - - do { - slow_down(); - i++; - if (i>TIMEOUT) { - break; - } - } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID) - ; - c = tx3927_sioptr(0)->rfifo; - - /* clear RX int. status */ - tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS; - /* enable RX int. */ - tx3927_sioptr(0)->dicr = dicr; - - return c; -} - -static void debugInit(int baud) -{ - tx3927_sioptr(0)->lcr = 0x020; - tx3927_sioptr(0)->dicr = 0; - tx3927_sioptr(0)->disr = 0x4100; - tx3927_sioptr(0)->cisr = 0x014; - tx3927_sioptr(0)->fcr = 0; - tx3927_sioptr(0)->flcr = 0x02; - tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | - TXx927_SIBGR_BCLK_T0; -} diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c deleted file mode 100644 index f39c444e42d4..000000000000 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif - -#include -#include -#include -#include -#include - -extern void puts(const char *cp); - -/* don't enable - see errata */ -static int jmr3927_ccfg_toeon; - -static inline void do_reset(void) -{ -#if 1 /* Resetting PCI bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); - (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ - mdelay(1); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); -#endif - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); -} - -static void jmr3927_machine_restart(char *command) -{ - local_irq_disable(); - puts("Rebooting..."); - do_reset(); -} - -static void jmr3927_machine_halt(void) -{ - puts("JMR-TX3927 halted.\n"); - while (1); -} - -static void jmr3927_machine_power_off(void) -{ - puts("JMR-TX3927 halted. Please turn off the power.\n"); - while (1); -} - -void __init plat_time_init(void) -{ - txx9_clockevent_init(TX3927_TMR_REG(0), - TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), - JMR3927_IMCLK); - txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK); -} - -#define DO_WRITE_THROUGH -#define DO_ENABLE_CACHE - -extern char * __init prom_getcmdline(void); -static void jmr3927_board_init(void); -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -void __init plat_mem_setup(void) -{ - char *argptr; - - set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); - - _machine_restart = jmr3927_machine_restart; - _machine_halt = jmr3927_machine_halt; - pm_power_off = jmr3927_machine_power_off; - - /* - * IO/MEM resources. - */ - ioport_resource.start = pci_io_resource.start; - ioport_resource.end = pci_io_resource.end; - iomem_resource.start = 0; - iomem_resource.end = 0xffffffff; - - /* Reboot on panic */ - panic_timeout = 180; - - /* cache setup */ - { - unsigned int conf; -#ifdef DO_ENABLE_CACHE - int mips_ic_disable = 0, mips_dc_disable = 0; -#else - int mips_ic_disable = 1, mips_dc_disable = 1; -#endif -#ifdef DO_WRITE_THROUGH - int mips_config_cwfon = 0; - int mips_config_wbon = 0; -#else - int mips_config_cwfon = 1; - int mips_config_wbon = 1; -#endif - - conf = read_c0_conf(); - conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); - conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; - conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; - conf |= mips_config_wbon ? TX39_CONF_WBON : 0; - conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; - - write_c0_conf(conf); - write_c0_cache(0); - } - - /* initialize board */ - jmr3927_board_init(); - - argptr = prom_getcmdline(); - - if ((argptr = strstr(argptr, "toeon")) != NULL) - jmr3927_ccfg_toeon = 1; - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "ip=")) == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " ip=bootp"); - } - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - int i; - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); - req.mapbase = TX3927_SIO_REG(i); - req.irq = i == 0 ? - JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; - if (i == 0) - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = JMR3927_IMCLK; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "console=")) == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS1,115200"); - } -#endif -#endif -} - -static void tx3927_setup(void); - -static void __init jmr3927_board_init(void) -{ - tx3927_setup(); - - /* SIO0 DTR on */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); - - jmr3927_led_set(0); - - printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", - jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, - jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, - jmr3927_dipsw1(), jmr3927_dipsw2(), - jmr3927_dipsw3(), jmr3927_dipsw4()); -} - -static void __init tx3927_setup(void) -{ - int i; -#ifdef CONFIG_PCI - unsigned long mips_pci_io_base = JMR3927_PCIIO; - unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; - unsigned long mips_pci_mem_base = JMR3927_PCIMEM; - unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; - /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ - unsigned long mips_pci_io_pciaddr = 0; -#endif - - /* SDRAMC are configured by PROM */ - - /* ROMC */ - tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; - tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; - tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; - tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; - - /* CCFG */ - /* enable Timeout BusError */ - if (jmr3927_ccfg_toeon) - tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; - - /* clear BusErrorOnWrite flag */ - tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; - /* Disable PCI snoop */ - tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; - /* do reset on watchdog */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; - -#ifdef DO_WRITE_THROUGH - /* Enable PCI SNOOP - with write through only */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; -#endif - - /* Pin selection */ - tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; - tx3927_ccfgptr->pcfg |= - TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | - (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); - - printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", - tx3927_ccfgptr->crir, - tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); - - /* TMR */ - for (i = 0; i < TX3927_NR_TMR; i++) - txx9_tmr_init(TX3927_TMR_REG(i)); - - /* DMA */ - tx3927_dmaptr->mcr = 0; - for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { - /* reset channel */ - tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; - tx3927_dmaptr->ch[i].ccr = 0; - } - /* enable DMA */ -#ifdef __BIG_ENDIAN - tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; -#else - tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; -#endif - -#ifdef CONFIG_PCI - /* PCIC */ - printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", - tx3927_pcicptr->did, tx3927_pcicptr->vid, - tx3927_pcicptr->rid); - if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { - printk("External\n"); - /* XXX */ - } else { - printk("Internal\n"); - - /* Reset PCI Bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, - JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - - /* Disable External PCI Config. Access */ - tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; -#ifdef __BIG_ENDIAN - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | - TX3927_PCIC_LBC_TIBSE | - TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; -#endif - /* LB->PCI mappings */ - tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); - tx3927_pcicptr->ilbioma = mips_pci_io_base; - tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; - tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->ilbmma = mips_pci_mem_base; - tx3927_pcicptr->ipbmma = mips_pci_mem_base; - /* PCI->LB mappings */ - tx3927_pcicptr->iobas = 0xffffffff; - tx3927_pcicptr->ioba = 0; - tx3927_pcicptr->tlbioma = 0; - tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->mba = 0; - tx3927_pcicptr->tlbmma = 0; - /* Enable Direct mapping Address Space Decoder */ - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; - - /* Clear All Local Bus Status */ - tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; - /* Enable All Local Bus Interrupts */ - tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; - /* Clear All PCI Status Error */ - tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; - /* Enable All PCI Status Error Interrupts */ - tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; - - /* PCIC Int => IRC IRQ10 */ - tx3927_pcicptr->il = TX3927_IR_PCI; - /* Target Control (per errata) */ - tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; - - /* Enable Bus Arbiter */ - tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; - - tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - } -#endif /* CONFIG_PCI */ - - /* PIO */ - /* PIO[15:12] connected to LEDs */ - __raw_writel(0x0000f000, &tx3927_pioptr->dir); - __raw_writel(0, &tx3927_pioptr->maskcpu); - __raw_writel(0, &tx3927_pioptr->maskext); - txx9_gpio_init(TX3927_PIO_REG, 0, 16); - gpio_request(11, "dipsw1"); - gpio_request(10, "dipsw2"); - { - unsigned int conf; - - conf = read_c0_conf(); - if (!(conf & TX39_CONF_ICE)) - printk("TX3927 I-Cache disabled.\n"); - if (!(conf & TX39_CONF_DCE)) - printk("TX3927 D-Cache disabled.\n"); - else if (!(conf & TX39_CONF_WBON)) - printk("TX3927 D-Cache WriteThrough.\n"); - else if (!(conf & TX39_CONF_CWFON)) - printk("TX3927 D-Cache WriteBack.\n"); - else - printk("TX3927 D-Cache WriteBack (CWF) .\n"); - } -} - -/* This trick makes rtc-ds1742 driver usable as is. */ -unsigned long __swizzle_addr_b(unsigned long port) -{ - if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) - return port; - port = (port & 0xffff0000) | (port & 0x7fff << 1); -#ifdef __BIG_ENDIAN - return port; -#else - return port | 1; -#endif -} -EXPORT_SYMBOL(__swizzle_addr_b); - -static int __init jmr3927_rtc_init(void) -{ - static struct resource __initdata res = { - .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, - .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev; - dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(jmr3927_rtc_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init jmr3927_wdt_init(void) -{ - return txx9_wdt_init(TX3927_TMR_REG(2)); -} -device_initcall(jmr3927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)JMR3927_IMCLK; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 80fa5abb25d4..4608e43de28c 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ops-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index e974394be7bc..41dcd6a3aae5 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -31,7 +31,7 @@ #include #include -#include +#include int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 2d234ca017db..26013badfe1f 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -37,7 +37,7 @@ #include #include -#include +#include #undef DEBUG #ifdef DEBUG diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c new file mode 100644 index 000000000000..64d4510c0265 --- /dev/null +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -0,0 +1,92 @@ +/* + * Toshiba rbtx4938 pci routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include + +#include + +extern struct pci_controller tx4938_pci_controller[]; + +static int pci_get_irq(const struct pci_dev *dev, int pin) +{ + int irq = pin; + u8 slot = PCI_SLOT(dev->devfn); + struct pci_controller *controller = (struct pci_controller *)dev->sysdata; + + if (controller == &tx4938_pci_controller[1]) { + /* TX4938 PCIC1 */ + switch (slot) { + case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; + break; + case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) + return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; + break; + } + return 0; + } + + /* IRQ rotation */ + irq--; /* 0-3 */ + if (dev->bus->parent == NULL && + (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA (IDSEL=A23) */ + irq = (irq + 0 + slot) % 4; + } else { + /* PCI Backplane */ + irq = (irq + 33 - slot) % 4; + } + irq++; /* 1-4 */ + + switch (irq) { + case 1: + irq = RBTX4938_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4938_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4938_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4938_IRQ_IOC_PCID; + break; + } + return irq; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned char irq = 0; + + irq = pci_get_irq(dev, pin); + + printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", + dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), irq); + + return irq; +} + +/* + * Do platform specific device initialization at pci_enable_device() time + */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c deleted file mode 100644 index f2ba06ee0c10..000000000000 --- a/arch/mips/pci/fixup-tx4938.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Toshiba rbtx4938 pci routines - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include - -#include - -extern struct pci_controller tx4938_pci_controller[]; - -static int pci_get_irq(const struct pci_dev *dev, int pin) -{ - int irq = pin; - u8 slot = PCI_SLOT(dev->devfn); - struct pci_controller *controller = (struct pci_controller *)dev->sysdata; - - if (controller == &tx4938_pci_controller[1]) { - /* TX4938 PCIC1 */ - switch (slot) { - case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; - break; - case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; - break; - } - return 0; - } - - /* IRQ rotation */ - irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { - /* PCI CardSlot (IDSEL=A23) */ - /* PCIA => PCIA (IDSEL=A23) */ - irq = (irq + 0 + slot) % 4; - } else { - /* PCI Backplane */ - irq = (irq + 33 - slot) % 4; - } - irq++; /* 1-4 */ - - switch (irq) { - case 1: - irq = RBTX4938_IRQ_IOC_PCIA; - break; - case 2: - irq = RBTX4938_IRQ_IOC_PCIB; - break; - case 3: - irq = RBTX4938_IRQ_IOC_PCIC; - break; - case 4: - irq = RBTX4938_IRQ_IOC_PCID; - break; - } - return irq; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq = 0; - - irq = pci_get_irq(dev, pin); - - printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", - dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), irq); - - return irq; -} - -/* - * Do platform specific device initialization at pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c index aa698bd0d5e3..5d398f694682 100644 --- a/arch/mips/pci/ops-tx3927.c +++ b/arch/mips/pci/ops-tx3927.c @@ -39,7 +39,7 @@ #include #include -#include +#include static inline int mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where) diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 1bbafeb4a774..54730eee451b 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -40,7 +40,7 @@ #include #include #include -#include +#include /* initialize in setup */ struct resource pci_io_resource = { diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c index a450c4062031..34494b82cb22 100644 --- a/arch/mips/pci/ops-tx4938.c +++ b/arch/mips/pci/ops-tx4938.c @@ -15,7 +15,7 @@ #include #include -#include +#include /* initialize in setup */ struct resource pci_io_resource = { diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c index cb84f4e8ccae..7fb6bd71901a 100644 --- a/arch/mips/pci/pci-jmr3927.c +++ b/arch/mips/pci/pci-jmr3927.c @@ -31,7 +31,7 @@ #include #include -#include +#include #include struct resource pci_io_resource = { diff --git a/arch/mips/tx4927/Kconfig b/arch/mips/tx4927/Kconfig deleted file mode 100644 index 5fbbe12e0fc1..000000000000 --- a/arch/mips/tx4927/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config TOSHIBA_FPCIB0 - bool "FPCIB0 Backplane Support" - depends on TOSHIBA_RBTX4927 diff --git a/arch/mips/tx4927/common/Makefile b/arch/mips/tx4927/common/Makefile deleted file mode 100644 index a7fe76a64964..000000000000 --- a/arch/mips/tx4927/common/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += tx4927_prom.o tx4927_irq.o - -obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o -obj-$(CONFIG_KGDB) += tx4927_dbgio.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4927/common/smsc_fdc37m81x.c b/arch/mips/tx4927/common/smsc_fdc37m81x.c deleted file mode 100644 index 33f517bc9a08..000000000000 --- a/arch/mips/tx4927/common/smsc_fdc37m81x.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Interface for smsc fdc48m81x Super IO chip - * - * Author: MontaVista Software, Inc. source@mvista.com - * - * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright 2004 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include - -#define DEBUG - -/* Common Registers */ -#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 -#define SMSC_FDC37M81X_CONFIG_DATA 0x01 -#define SMSC_FDC37M81X_CONF 0x02 -#define SMSC_FDC37M81X_INDEX 0x03 -#define SMSC_FDC37M81X_DNUM 0x07 -#define SMSC_FDC37M81X_DID 0x20 -#define SMSC_FDC37M81X_DREV 0x21 -#define SMSC_FDC37M81X_PCNT 0x22 -#define SMSC_FDC37M81X_PMGT 0x23 -#define SMSC_FDC37M81X_OSC 0x24 -#define SMSC_FDC37M81X_CONFPA0 0x26 -#define SMSC_FDC37M81X_CONFPA1 0x27 -#define SMSC_FDC37M81X_TEST4 0x2B -#define SMSC_FDC37M81X_TEST5 0x2C -#define SMSC_FDC37M81X_TEST1 0x2D -#define SMSC_FDC37M81X_TEST2 0x2E -#define SMSC_FDC37M81X_TEST3 0x2F - -/* Logical device numbers */ -#define SMSC_FDC37M81X_FDD 0x00 -#define SMSC_FDC37M81X_SERIAL1 0x04 -#define SMSC_FDC37M81X_SERIAL2 0x05 -#define SMSC_FDC37M81X_KBD 0x07 - -/* Logical device Config Registers */ -#define SMSC_FDC37M81X_ACTIVE 0x30 -#define SMSC_FDC37M81X_BASEADDR0 0x60 -#define SMSC_FDC37M81X_BASEADDR1 0x61 -#define SMSC_FDC37M81X_INT 0x70 -#define SMSC_FDC37M81X_INT2 0x72 -#define SMSC_FDC37M81X_MODE 0xF0 - -/* Chip Config Values */ -#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 -#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa -#define SMSC_FDC37M81X_CHIP_ID 0x4d - -static unsigned long g_smsc_fdc37m81x_base = 0; - -static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) -{ - outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - - return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); -} - -static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data) -{ - outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); -} - -void smsc_fdc37m81x_config_beg(void) -{ - if (g_smsc_fdc37m81x_base) { - outb(SMSC_FDC37M81X_CONFIG_ENTER, - g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); - } -} - -void smsc_fdc37m81x_config_end(void) -{ - if (g_smsc_fdc37m81x_base) - outb(SMSC_FDC37M81X_CONFIG_EXIT, - g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); -} - -u8 smsc_fdc37m81x_config_get(u8 reg) -{ - u8 val = 0; - - if (g_smsc_fdc37m81x_base) - val = smsc_fdc37m81x_rd(reg); - - return val; -} - -void smsc_fdc37m81x_config_set(u8 reg, u8 val) -{ - if (g_smsc_fdc37m81x_base) - smsc_dc37m81x_wr(reg, val); -} - -unsigned long __init smsc_fdc37m81x_init(unsigned long port) -{ - const int field = sizeof(unsigned long) * 2; - u8 chip_id; - - if (g_smsc_fdc37m81x_base) - printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", - field, g_smsc_fdc37m81x_base); - - g_smsc_fdc37m81x_base = port; - - smsc_fdc37m81x_config_beg(); - - chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID); - if (chip_id == SMSC_FDC37M81X_CHIP_ID) - smsc_fdc37m81x_config_end(); - else { - printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", - chip_id); - g_smsc_fdc37m81x_base = 0; - } - - return g_smsc_fdc37m81x_base; -} - -#ifdef DEBUG -void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) -{ - printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, - smsc_fdc37m81x_rd(reg)); -} - -void smsc_fdc37m81x_config_dump(void) -{ - u8 orig; - char *fname = "smsc_fdc37m81x_config_dump()"; - - smsc_fdc37m81x_config_beg(); - - orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); - - printk("%s: common\n", fname); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DNUM); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DID); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_DREV); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_PCNT); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, - SMSC_FDC37M81X_PMGT); - - printk("%s: keyboard\n", fname); - smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_ACTIVE); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_INT); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_INT2); - smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, - SMSC_FDC37M81X_LDCR_F0); - - smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig); - - smsc_fdc37m81x_config_end(); -} -#endif diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c deleted file mode 100644 index ea1ff23f4b72..000000000000 --- a/arch/mips/tx4927/common/tx4927_dbgio.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/arch/mips/tx4927/common/tx4927_dbgio.c - * - * kgdb interface for gdb - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include - -u8 getDebugChar(void) -{ - extern u8 txx9_sio_kdbg_rd(void); - return (txx9_sio_kdbg_rd()); -} - -int putDebugChar(u8 byte) -{ - extern int txx9_sio_kdbg_wr( u8 ch ); - return (txx9_sio_kdbg_wr(byte)); -} diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c deleted file mode 100644 index 0aabd57fdad2..000000000000 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Common tx4927 irq handler - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_RBTX4927 -#include -#endif - -void __init tx4927_irq_init(void) -{ - mips_cpu_irq_init(); - txx9_irq_init(TX4927_IRC_REG); - set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) /* cpu timer */ - do_IRQ(TX4927_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { /* tx4927 pic */ - int irq = txx9_irq(); -#ifdef CONFIG_TOSHIBA_RBTX4927 - if (irq == TX4927_IRQ_NEST_EXT_ON_PIC) - irq = toshiba_rbtx4927_irq_nested(irq); -#endif - if (unlikely(irq < 0)) { - spurious_interrupt(); - return; - } - do_IRQ(irq); - } else if (pending & STATUSF_IP0) /* user line 0 */ - do_IRQ(TX4927_IRQ_USER0); - else if (pending & STATUSF_IP1) /* user line 1 */ - do_IRQ(TX4927_IRQ_USER1); - else - spurious_interrupt(); -} diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c deleted file mode 100644 index cc2aa9d63e82..000000000000 --- a/arch/mips/tx4927/common/tx4927_prom.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linux/arch/mips/tx4927/common/tx4927_prom.c - * - * common tx4927 memory interface - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include - -static unsigned int __init tx4927_process_sdccr(unsigned long addr) -{ - u64 val; - unsigned int sdccr_ce; - unsigned int sdccr_bs; - unsigned int sdccr_rs; - unsigned int sdccr_cs; - unsigned int sdccr_mw; - unsigned int bs = 0; - unsigned int rs = 0; - unsigned int cs = 0; - unsigned int mw = 0; - unsigned int msize = 0; - - val = __raw_readq((void __iomem *)addr); - - /* MVMCP -- need #defs for these bits masks */ - sdccr_ce = ((val & (1 << 10)) >> 10); - sdccr_bs = ((val & (1 << 8)) >> 8); - sdccr_rs = ((val & (3 << 5)) >> 5); - sdccr_cs = ((val & (3 << 2)) >> 2); - sdccr_mw = ((val & (1 << 0)) >> 0); - - if (sdccr_ce) { - switch (sdccr_bs) { - case 0:{ - bs = 2; - break; - } - case 1:{ - bs = 4; - break; - } - } - switch (sdccr_rs) { - case 0:{ - rs = 2048; - break; - } - case 1:{ - rs = 4096; - break; - } - case 2:{ - rs = 8192; - break; - } - case 3:{ - rs = 0; - break; - } - } - switch (sdccr_cs) { - case 0:{ - cs = 256; - break; - } - case 1:{ - cs = 512; - break; - } - case 2:{ - cs = 1024; - break; - } - case 3:{ - cs = 2048; - break; - } - } - switch (sdccr_mw) { - case 0:{ - mw = 8; - break; - } /* 8 bytes = 64 bits */ - case 1:{ - mw = 4; - break; - } /* 4 bytes = 32 bits */ - } - } - - /* bytes per chip MB per chip num chips */ - msize = (((rs * cs * mw) / (1024 * 1024)) * bs); - - return (msize); -} - - -unsigned int __init tx4927_get_mem_size(void) -{ - unsigned int c0; - unsigned int c1; - unsigned int c2; - unsigned int c3; - unsigned int total; - - /* MVMCP -- need #defs for these registers */ - c0 = tx4927_process_sdccr(0xff1f8000); - c1 = tx4927_process_sdccr(0xff1f8008); - c2 = tx4927_process_sdccr(0xff1f8010); - c3 = tx4927_process_sdccr(0xff1f8018); - total = c0 + c1 + c2 + c3; - - return (total); -} diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile deleted file mode 100644 index 13f96725d772..000000000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -obj-y += toshiba_rbtx4927_prom.o -obj-y += toshiba_rbtx4927_setup.o -obj-y += toshiba_rbtx4927_irq.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c deleted file mode 100644 index c18901a75cc4..000000000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c - * - * Toshiba RBTX4927 specific interrupt handlers - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -/* -IRQ Device -00 RBTX4927-ISA/00 -01 RBTX4927-ISA/01 PS2/Keyboard -02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) -03 RBTX4927-ISA/03 -04 RBTX4927-ISA/04 -05 RBTX4927-ISA/05 -06 RBTX4927-ISA/06 -07 RBTX4927-ISA/07 -08 RBTX4927-ISA/08 -09 RBTX4927-ISA/09 -10 RBTX4927-ISA/10 -11 RBTX4927-ISA/11 -12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) -13 RBTX4927-ISA/13 -14 RBTX4927-ISA/14 IDE -15 RBTX4927-ISA/15 - -16 TX4927-CP0/00 Software 0 -17 TX4927-CP0/01 Software 1 -18 TX4927-CP0/02 Cascade TX4927-CP0 -19 TX4927-CP0/03 Multiplexed -- do not use -20 TX4927-CP0/04 Multiplexed -- do not use -21 TX4927-CP0/05 Multiplexed -- do not use -22 TX4927-CP0/06 Multiplexed -- do not use -23 TX4927-CP0/07 CPU TIMER - -24 TX4927-PIC/00 -25 TX4927-PIC/01 -26 TX4927-PIC/02 -27 TX4927-PIC/03 Cascade RBTX4927-IOC -28 TX4927-PIC/04 -29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet -30 TX4927-PIC/06 -31 TX4927-PIC/07 -32 TX4927-PIC/08 TX4927 SerialIO Channel 0 -33 TX4927-PIC/09 TX4927 SerialIO Channel 1 -34 TX4927-PIC/10 -35 TX4927-PIC/11 -36 TX4927-PIC/12 -37 TX4927-PIC/13 -38 TX4927-PIC/14 -39 TX4927-PIC/15 -40 TX4927-PIC/16 TX4927 PCI PCI-C -41 TX4927-PIC/17 -42 TX4927-PIC/18 -43 TX4927-PIC/19 -44 TX4927-PIC/20 -45 TX4927-PIC/21 -46 TX4927-PIC/22 TX4927 PCI PCI-ERR -47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) -48 TX4927-PIC/24 -49 TX4927-PIC/25 -50 TX4927-PIC/26 -51 TX4927-PIC/27 -52 TX4927-PIC/28 -53 TX4927-PIC/29 -54 TX4927-PIC/30 -55 TX4927-PIC/31 - -56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] -57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] -58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] -59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] -60 RBTX4927-IOC/04 -61 RBTX4927-IOC/05 -62 RBTX4927-IOC/06 -63 RBTX4927-IOC/07 - -NOTES: -SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 -SouthBridge/ISA/pin=0 no pci irq used by this device -SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 -SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 -SouthBridge/PMC/pin=0 no pci irq used by this device -SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 -SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) -JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 -*/ - -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif -#include - -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ - -#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC -#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) - -extern int tx4927_using_backplane; - -static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); -static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); - -#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" -static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { - .name = TOSHIBA_RBTX4927_IOC_NAME, - .ack = toshiba_rbtx4927_irq_ioc_disable, - .mask = toshiba_rbtx4927_irq_ioc_disable, - .mask_ack = toshiba_rbtx4927_irq_ioc_disable, - .unmask = toshiba_rbtx4927_irq_ioc_enable, -}; -#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL -#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL - -int toshiba_rbtx4927_irq_nested(int sw_irq) -{ - u8 level3; - - level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; - if (level3) { - sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && - tx4927_using_backplane) { - int irq = i8259_irq(); - if (irq >= 0) - sw_irq = irq; - } -#endif - } - return (sw_irq); -} - -static struct irqaction toshiba_rbtx4927_irq_ioc_action = { - .handler = no_action, - .flags = IRQF_SHARED, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4927_IOC_NAME -}; - -static void __init toshiba_rbtx4927_irq_ioc_init(void) -{ - int i; - - for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) - set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, - handle_level_irq); - - setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, - &toshiba_rbtx4927_irq_ioc_action); -} - -static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) -{ - unsigned char v; - - v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); -} - -static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) -{ - unsigned char v; - - v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); - writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); - mmiowb(); -} - -void __init arch_init_irq(void) -{ - extern void tx4927_irq_init(void); - - tx4927_irq_init(); - toshiba_rbtx4927_irq_ioc_init(); -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) - init_i8259_irqs(); -#endif - /* Onboard 10M Ether: High Active */ - set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); -} diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c deleted file mode 100644 index fdbad4bc6021..000000000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * rbtx4927 specific prom routines - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include - -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; /* Always ignore the "-c" at argv[0] */ - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} - -void __init prom_init(void) -{ - extern int tx4927_get_mem_size(void); - extern char* toshiba_name; - int msize; - - prom_init_cmdline(); - - if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { - mips_machtype = MACH_TOSHIBA_RBTX4927; - toshiba_name = "TX4927"; - } else { - mips_machtype = MACH_TOSHIBA_RBTX4937; - toshiba_name = "TX4937"; - } - - msize = tx4927_get_mem_size(); - add_memory_region(0, msize << 20, BOOT_MEM_RAM); -} - -void __init prom_free_prom_memory(void) -{ -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4927/RBTX4937"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c deleted file mode 100644 index 185f303c0e2a..000000000000 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ /dev/null @@ -1,703 +0,0 @@ -/* - * Toshiba rbtx4927 specific setup - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2002 MontaVista Software Inc. - * Author: Michael Pruznick, michael_pruznick@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif - -/* These functions are used for rebooting or halting the machine*/ -extern void toshiba_rbtx4927_restart(char *command); -extern void toshiba_rbtx4927_halt(void); -extern void toshiba_rbtx4927_power_off(void); - -int tx4927_using_backplane = 0; - -extern void toshiba_rbtx4927_irq_setup(void); - -char *prom_getcmdline(void); - -#ifdef CONFIG_PCI -#undef TX4927_SUPPORT_COMMAND_IO -#undef TX4927_SUPPORT_PCI_66 -int tx4927_cpu_clock = 100000000; /* 100MHz */ -unsigned long mips_pci_io_base; -unsigned long mips_pci_io_size; -unsigned long mips_pci_mem_base; -unsigned long mips_pci_mem_size; -/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ -unsigned long mips_pci_io_pciaddr = 0; -unsigned long mips_memory_upper; -static int tx4927_ccfg_toeon = 1; -static int tx4927_pcic_trdyto = 0; /* default: disabled */ -unsigned long tx4927_ce_base[8]; -int tx4927_pci66 = 0; /* 0:auto */ -#endif - -char *toshiba_name = ""; - -#ifdef CONFIG_PCI -extern struct pci_controller tx4927_controller; - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = (void *)hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, dword, u32) - -static int __init tx4927_pcibios_init(void) -{ - unsigned int id; - u32 pci_devfn; - int devfn_start = 0; - int devfn_stop = 0xff; - int busno = 0; /* One bus on the Toshiba */ - struct pci_controller *hose = &tx4927_controller; - - for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { - early_read_config_dword(hose, busno, busno, pci_devfn, - PCI_VENDOR_ID, &id); - - if (id == 0xffffffff) { - continue; - } - - if (id == 0x94601055) { - u8 v08_64; - u32 v32_b0; - u8 v08_e1; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x64, &v08_64); - early_read_config_dword(hose, busno, busno, - pci_devfn, 0xb0, &v32_b0); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0xe1, &v08_e1); - - /* serial irq control */ - v08_64 = 0xd0; - - /* serial irq pin */ - v32_b0 |= 0x00010000; - - /* ide irq on isa14 */ - v08_e1 &= 0xf0; - v08_e1 |= 0x0d; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x64, v08_64); - early_write_config_dword(hose, busno, busno, - pci_devfn, 0xb0, v32_b0); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0xe1, v08_e1); - } - - if (id == 0x91301055) { - u8 v08_04; - u8 v08_09; - u8 v08_41; - u8 v08_43; - u8 v08_5c; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x04, &v08_04); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x09, &v08_09); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x41, &v08_41); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x43, &v08_43); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x5c, &v08_5c); - - /* enable ide master/io */ - v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); - - /* enable ide native mode */ - v08_09 |= 0x05; - - /* enable primary ide */ - v08_41 |= 0x80; - - /* enable secondary ide */ - v08_43 |= 0x80; - - /* - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - * - * This line of code is intended to provide the user with a work - * around solution to the anomalies cited in SMSC's anomaly sheet - * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". - * - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - */ - v08_5c |= 0x01; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x5c, v08_5c); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x04, v08_04); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x09, v08_09); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x41, v08_41); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x43, v08_43); - } - - } - - register_pci_controller(&tx4927_controller); - return 0; -} - -arch_initcall(tx4927_pcibios_init); - -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -void __init tx4927_pci_setup(void) -{ - static int called = 0; - extern unsigned int tx4927_get_mem_size(void); - - mips_memory_upper = tx4927_get_mem_size() << 20; - mips_memory_upper += KSEG0; - mips_pci_io_base = TX4927_PCIIO; - mips_pci_io_size = TX4927_PCIIO_SIZE; - mips_pci_mem_base = TX4927_PCIMEM; - mips_pci_mem_size = TX4927_PCIMEM_SIZE; - - if (!called) { - printk - ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - toshiba_name, - (unsigned short) (tx4927_pcicptr->pciid >> 16), - (unsigned short) (tx4927_pcicptr->pciid & 0xffff), - (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), - (!(tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIXARB)) ? "External" : - "Internal"); - called = 1; - } - printk("%s PCIC --%s PCICLK:", toshiba_name, - (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); - if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { - int pciclk = 0; - if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_4: - pciclk = tx4927_cpu_clock / 4; - break; - case TX4937_CCFG_PCIDIVMODE_4_5: - pciclk = tx4927_cpu_clock * 2 / 9; - break; - case TX4937_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4937_CCFG_PCIDIVMODE_5_5: - pciclk = tx4927_cpu_clock * 2 / 11; - break; - case TX4937_CCFG_PCIDIVMODE_8: - pciclk = tx4927_cpu_clock / 8; - break; - case TX4937_CCFG_PCIDIVMODE_9: - pciclk = tx4927_cpu_clock / 9; - break; - case TX4937_CCFG_PCIDIVMODE_10: - pciclk = tx4927_cpu_clock / 10; - break; - case TX4937_CCFG_PCIDIVMODE_11: - pciclk = tx4927_cpu_clock / 11; - break; - } - - else - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - pciclk = tx4927_cpu_clock * 2 / 5; - break; - case TX4927_CCFG_PCIDIVMODE_3: - pciclk = tx4927_cpu_clock / 3; - break; - case TX4927_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4927_CCFG_PCIDIVMODE_6: - pciclk = tx4927_cpu_clock / 6; - break; - } - - printk("Internal(%dMHz)", pciclk / 1000000); - } else - printk("External"); - printk("\n"); - - /* GB->PCI mappings */ - tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; - tx4927_pcicptr->g2piogbase = mips_pci_io_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PIOGBASE_ECHG -#else - TX4927_PCIC_G2PIOGBASE_BSDIS -#endif - ; - - tx4927_pcicptr->g2piopbase = 0; - - tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; - tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PMnGBASE_ECHG -#else - TX4927_PCIC_G2PMnGBASE_BSDIS -#endif - ; - tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; - - tx4927_pcicptr->g2pmmask[1] = 0; - tx4927_pcicptr->g2pmgbase[1] = 0; - tx4927_pcicptr->g2pmpbase[1] = 0; - tx4927_pcicptr->g2pmmask[2] = 0; - tx4927_pcicptr->g2pmgbase[2] = 0; - tx4927_pcicptr->g2pmpbase[2] = 0; - - - /* PCI->GB mappings (I/O 256B) */ - tx4927_pcicptr->p2giopbase = 0; /* 256B */ - - /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ - tx4927_pcicptr->p2gm0plbase = 0; - tx4927_pcicptr->p2gm0pubase = 0; - tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4927_PCIC_P2GMnGBASE_TECHG -#else - TX4927_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - - /* PCI->GB mappings (MEM 16MB) -not used */ - tx4927_pcicptr->p2gm1plbase = 0xffffffff; - tx4927_pcicptr->p2gm1pubase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[1] = 0; - - /* PCI->GB mappings (MEM 1MB) -not used */ - tx4927_pcicptr->p2gm2pbase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[2] = 0; - - - /* Enable Initiator Memory 0 Space, I/O Space, Config */ - tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; - tx4927_pcicptr->pciccfg |= - TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | - TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; - - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - tx4927_pcicptr->pcicfg1 = 0; - - if (tx4927_pcic_trdyto >= 0) { - tx4927_pcicptr->g2ptocnt &= ~0xff; - tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); - } - - /* Clear All Local Bus Status */ - tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr->pcistatus & 0x0000ffff) | - (TX4927_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; - - /* PCIC Int => IRC IRQ16 */ - tx4927_pcicptr->pcicfg2 = - (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; - - if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { - /* XXX */ - } else { - /* Reset Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; - /* Enable Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; - } - - tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; -} -#endif /* CONFIG_PCI */ - -static void __noreturn wait_forever(void) -{ - while (1) - if (cpu_wait) - (*cpu_wait)(); -} - -void toshiba_rbtx4927_restart(char *command) -{ - printk(KERN_NOTICE "System Rebooting...\n"); - - /* enable the s/w reset register */ - writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); - - /* wait for enable to be seen */ - while ((readb(RBTX4927_SW_RESET_ENABLE) & - RBTX4927_SW_RESET_ENABLE_SET) == 0x00); - - /* do a s/w reset */ - writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); - - /* do something passive while waiting for reset */ - local_irq_disable(); - wait_forever(); - /* no return */ -} - -void toshiba_rbtx4927_halt(void) -{ - printk(KERN_NOTICE "System Halted\n"); - local_irq_disable(); - wait_forever(); - /* no return */ -} - -void toshiba_rbtx4927_power_off(void) -{ - toshiba_rbtx4927_halt(); - /* no return */ -} - -void __init plat_mem_setup(void) -{ - int i; - u32 cp0_config; - char *argptr; - - printk("CPU is %s\n", toshiba_name); - - /* f/w leaves this on at startup */ - clear_c0_status(ST0_ERL); - - /* enable caches -- HCP5 does this, pmon does not */ - cp0_config = read_c0_config(); - cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); - write_c0_config(cp0_config); - - set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); - - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; - - _machine_restart = toshiba_rbtx4927_restart; - _machine_halt = toshiba_rbtx4927_halt; - pm_power_off = toshiba_rbtx4927_power_off; - - for (i = 0; i < TX4927_NR_TMR; i++) - txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); - -#ifdef CONFIG_PCI - - /* PCIC */ - /* - * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. - * - * For TX4927: - * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). - * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) - * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) - * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) - * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) - * i.e. S9[3]: ON (83MHz), OFF (100MHz) - * - * For TX4937: - * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) - * PCIDIVMODE[10] is 0. - * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) - * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) - * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) - * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) - * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) - * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) - * - */ - if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_8: - case TX4937_CCFG_PCIDIVMODE_4: - tx4927_cpu_clock = 266666666; /* 266MHz */ - break; - case TX4937_CCFG_PCIDIVMODE_9: - case TX4937_CCFG_PCIDIVMODE_4_5: - tx4927_cpu_clock = 300000000; /* 300MHz */ - break; - default: - tx4927_cpu_clock = 333333333; /* 333MHz */ - } - else - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - case TX4927_CCFG_PCIDIVMODE_5: - tx4927_cpu_clock = 166666666; /* 166MHz */ - break; - default: - tx4927_cpu_clock = 200000000; /* 200MHz */ - } - - /* CCFG */ - /* do reset on watchdog */ - tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; - /* enable Timeout BusError */ - if (tx4927_ccfg_toeon) - tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; - - tx4927_pci_setup(); - if (tx4927_using_backplane == 1) - printk("backplane board IS installed\n"); - else - printk("No Backplane \n"); - - /* this is on ISA bus behind PCI bus, so need PCI up first */ -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) { - smsc_fdc37m81x_init(0x3f0); - smsc_fdc37m81x_config_beg(); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, - SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, - 1); - smsc_fdc37m81x_config_end(); - } -#endif -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (char *)(0xff1ff300 + i * 0x100); - req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = TX4927_IRQ_PIC_BEG + 8 + i; - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = 50000000; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (strstr(argptr, "console=") == NULL) { - strcat(argptr, " console=ttyS0,38400"); - } -#endif -#endif - -#ifdef CONFIG_ROOT_NFS - argptr = prom_getcmdline(); - if (strstr(argptr, "root=") == NULL) { - strcat(argptr, " root=/dev/nfs rw"); - } -#endif - -#ifdef CONFIG_IP_PNP - argptr = prom_getcmdline(); - if (strstr(argptr, "ip=") == NULL) { - strcat(argptr, " ip=any"); - } -#endif -} - -void __init plat_time_init(void) -{ - mips_hpt_frequency = tx4927_cpu_clock / 2; - if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) - txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, - TXX9_IRQ_BASE + 17, - 50000000); -} - -static int __init toshiba_rbtx4927_rtc_init(void) -{ - static struct resource __initdata res = { - .start = 0x1c010000, - .end = 0x1c010000 + 0x800 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("rtc-ds1742", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(toshiba_rbtx4927_rtc_init); - -static int __init rbtx4927_ne_init(void) -{ - static struct resource __initdata res[] = { - { - .start = RBTX4927_RTL_8019_BASE, - .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, - .flags = IORESOURCE_IO, - }, { - .start = RBTX4927_RTL_8019_IRQ, - .flags = IORESOURCE_IRQ, - } - }; - struct platform_device *dev = - platform_device_register_simple("ne", -1, - res, ARRAY_SIZE(res)); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(rbtx4927_ne_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init rbtx4927_wdt_init(void) -{ - return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); -} -device_initcall(rbtx4927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)50000000; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/tx4938/Kconfig b/arch/mips/tx4938/Kconfig deleted file mode 100644 index d90e9cd85138..000000000000 --- a/arch/mips/tx4938/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -if TOSHIBA_RBTX4938 - -comment "Multiplex Pin Select" -choice - prompt "PIO[58:61]" - default TOSHIBA_RBTX4938_MPLEX_PIO58_61 - -config TOSHIBA_RBTX4938_MPLEX_PIO58_61 - bool "PIO" -config TOSHIBA_RBTX4938_MPLEX_NAND - bool "NAND" -config TOSHIBA_RBTX4938_MPLEX_ATA - bool "ATA" - -endchoice - -config TX4938_NAND_BOOT - depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND - bool "NAND Boot Support (EXPERIMENTAL)" - help - This is only for Toshiba RBTX4938 reference board, which has NAND IPL. - Select this option if you need to use NAND boot. - -endif diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile deleted file mode 100644 index 56aa1ed1ee0c..000000000000 --- a/arch/mips/tx4938/common/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += prom.o irq.o -obj-$(CONFIG_KGDB) += dbgio.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4938/common/dbgio.c b/arch/mips/tx4938/common/dbgio.c deleted file mode 100644 index 33b9c672a322..000000000000 --- a/arch/mips/tx4938/common/dbgio.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/dbgio.c - * - * kgdb interface for gdb - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2005 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Support for TX4938 in 2.6 - Hiroshi DOYU - */ - -#include - -extern u8 txx9_sio_kdbg_rd(void); -extern int txx9_sio_kdbg_wr( u8 ch ); - -u8 getDebugChar(void) -{ - return (txx9_sio_kdbg_rd()); -} - -int putDebugChar(u8 byte) -{ - return (txx9_sio_kdbg_wr(byte)); -} - diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c deleted file mode 100644 index c059b899d120..000000000000 --- a/arch/mips/tx4938/common/irq.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/irq.c - * - * Common tx4938 irq handler - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include - -void __init -tx4938_irq_init(void) -{ - mips_cpu_irq_init(); - txx9_irq_init(TX4938_IRC_REG); - set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -int toshiba_rbtx4938_irq_nested(int irq); - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP7) - do_IRQ(TX4938_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { - int irq = txx9_irq(); - if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0)) - irq = toshiba_rbtx4938_irq_nested(irq); - if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); - } else if (pending & STATUSF_IP1) - do_IRQ(TX4938_IRQ_USER1); - else if (pending & STATUSF_IP0) - do_IRQ(TX4938_IRQ_USER0); -} diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c deleted file mode 100644 index 20baeaeba4cd..000000000000 --- a/arch/mips/tx4938/common/prom.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/prom.c - * - * common tx4938 memory interface - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -#include -#include -#include - -static unsigned int __init -tx4938_process_sdccr(u64 * addr) -{ - u64 val; - unsigned int sdccr_ce; - unsigned int sdccr_rs; - unsigned int sdccr_cs; - unsigned int sdccr_mw; - unsigned int rs = 0; - unsigned int cs = 0; - unsigned int mw = 0; - unsigned int bc = 4; - unsigned int msize = 0; - - val = ____raw_readq((void __iomem *)addr); - - /* MVMCP -- need #defs for these bits masks */ - sdccr_ce = ((val & (1 << 10)) >> 10); - sdccr_rs = ((val & (3 << 5)) >> 5); - sdccr_cs = ((val & (7 << 2)) >> 2); - sdccr_mw = ((val & (1 << 0)) >> 0); - - if (sdccr_ce) { - switch (sdccr_rs) { - case 0:{ - rs = 2048; - break; - } - case 1:{ - rs = 4096; - break; - } - case 2:{ - rs = 8192; - break; - } - default:{ - rs = 0; - break; - } - } - switch (sdccr_cs) { - case 0:{ - cs = 256; - break; - } - case 1:{ - cs = 512; - break; - } - case 2:{ - cs = 1024; - break; - } - case 3:{ - cs = 2048; - break; - } - case 4:{ - cs = 4096; - break; - } - default:{ - cs = 0; - break; - } - } - switch (sdccr_mw) { - case 0:{ - mw = 8; - break; - } /* 8 bytes = 64 bits */ - case 1:{ - mw = 4; - break; - } /* 4 bytes = 32 bits */ - } - } - - /* bytes per chip MB per chip bank count */ - msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); - - /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ - /* boad supports bc=2 but no way to detect */ - - return (msize); -} - -unsigned int __init -tx4938_get_mem_size(void) -{ - unsigned int c0; - unsigned int c1; - unsigned int c2; - unsigned int c3; - unsigned int total; - - /* MVMCP -- need #defs for these registers */ - c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); - c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); - c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); - c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); - total = c0 + c1 + c2 + c3; - - return (total); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/Makefile b/arch/mips/tx4938/toshiba_rbtx4938/Makefile deleted file mode 100644 index 2316dd7dd1bd..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for common code for Toshiba TX4927 based systems -# - -obj-y += prom.o setup.o irq.o spi_eeprom.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c deleted file mode 100644 index 4d6a8dc46c76..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c - * - * Toshiba RBTX4938 specific interrupt handlers - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -/* -IRQ Device - -16 TX4938-CP0/00 Software 0 -17 TX4938-CP0/01 Software 1 -18 TX4938-CP0/02 Cascade TX4938-CP0 -19 TX4938-CP0/03 Multiplexed -- do not use -20 TX4938-CP0/04 Multiplexed -- do not use -21 TX4938-CP0/05 Multiplexed -- do not use -22 TX4938-CP0/06 Multiplexed -- do not use -23 TX4938-CP0/07 CPU TIMER - -24 TX4938-PIC/00 -25 TX4938-PIC/01 -26 TX4938-PIC/02 Cascade RBTX4938-IOC -27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet -28 TX4938-PIC/04 -29 TX4938-PIC/05 TX4938 ETH1 -30 TX4938-PIC/06 TX4938 ETH0 -31 TX4938-PIC/07 -32 TX4938-PIC/08 TX4938 SIO 0 -33 TX4938-PIC/09 TX4938 SIO 1 -34 TX4938-PIC/10 TX4938 DMA0 -35 TX4938-PIC/11 TX4938 DMA1 -36 TX4938-PIC/12 TX4938 DMA2 -37 TX4938-PIC/13 TX4938 DMA3 -38 TX4938-PIC/14 -39 TX4938-PIC/15 -40 TX4938-PIC/16 TX4938 PCIC -41 TX4938-PIC/17 TX4938 TMR0 -42 TX4938-PIC/18 TX4938 TMR1 -43 TX4938-PIC/19 TX4938 TMR2 -44 TX4938-PIC/20 -45 TX4938-PIC/21 -46 TX4938-PIC/22 TX4938 PCIERR -47 TX4938-PIC/23 -48 TX4938-PIC/24 -49 TX4938-PIC/25 -50 TX4938-PIC/26 -51 TX4938-PIC/27 -52 TX4938-PIC/28 -53 TX4938-PIC/29 -54 TX4938-PIC/30 -55 TX4938-PIC/31 TX4938 SPI - -56 RBTX4938-IOC/00 PCI-D -57 RBTX4938-IOC/01 PCI-C -58 RBTX4938-IOC/02 PCI-B -59 RBTX4938-IOC/03 PCI-A -60 RBTX4938-IOC/04 RTC -61 RBTX4938-IOC/05 ATA -62 RBTX4938-IOC/06 MODEM -63 RBTX4938-IOC/07 SWINT -*/ -#include -#include -#include - -static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); -static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); - -#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" -static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { - .name = TOSHIBA_RBTX4938_IOC_NAME, - .ack = toshiba_rbtx4938_irq_ioc_disable, - .mask = toshiba_rbtx4938_irq_ioc_disable, - .mask_ack = toshiba_rbtx4938_irq_ioc_disable, - .unmask = toshiba_rbtx4938_irq_ioc_enable, -}; - -int -toshiba_rbtx4938_irq_nested(int sw_irq) -{ - u8 level3; - - level3 = readb(rbtx4938_imstat_addr); - if (level3) - /* must use fls so onboard ATA has priority */ - sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; - - return sw_irq; -} - -static struct irqaction toshiba_rbtx4938_irq_ioc_action = { - .handler = no_action, - .flags = 0, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4938_IOC_NAME, -}; - -/**********************************************************************************/ -/* Functions for ioc */ -/**********************************************************************************/ -static void __init -toshiba_rbtx4938_irq_ioc_init(void) -{ - int i; - - for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) - set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, - handle_level_irq); - - setup_irq(RBTX4938_IRQ_IOCINT, - &toshiba_rbtx4938_irq_ioc_action); -} - -static void -toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) -{ - unsigned char v; - - v = readb(rbtx4938_imask_addr); - v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); - writeb(v, rbtx4938_imask_addr); - mmiowb(); -} - -static void -toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) -{ - unsigned char v; - - v = readb(rbtx4938_imask_addr); - v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); - writeb(v, rbtx4938_imask_addr); - mmiowb(); -} - -void __init arch_init_irq(void) -{ - extern void tx4938_irq_init(void); - - /* Now, interrupt control disabled, */ - /* all IRC interrupts are masked, */ - /* all IRC interrupt mode are Low Active. */ - - /* mask all IOC interrupts */ - writeb(0, rbtx4938_imask_addr); - - /* clear SoftInt interrupts */ - writeb(0, rbtx4938_softint_addr); - tx4938_irq_init(); - toshiba_rbtx4938_irq_ioc_init(); - /* Onboard 10M Ether: High Active */ - set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c deleted file mode 100644 index 1644bffa501a..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/prom.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c - * - * rbtx4938 specific prom routines - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -#include -#include -#include -#include - -#include -#include -#include - -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} - -void __init prom_init(void) -{ - extern int tx4938_get_mem_size(void); - int msize; -#ifndef CONFIG_TX4938_NAND_BOOT - prom_init_cmdline(); -#endif - - msize = tx4938_get_mem_size(); - add_memory_region(0, msize << 20, BOOT_MEM_RAM); - - return; -} - -void __init prom_free_prom_memory(void) -{ -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ - return; -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4938"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c deleted file mode 100644 index 3a3659e8633a..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ /dev/null @@ -1,1124 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c - * - * Setup pointers to hardware-dependent routines. - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif -#include -#include -#include - -extern char * __init prom_getcmdline(void); -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); - -/* These functions are used for rebooting or halting the machine*/ -extern void rbtx4938_machine_restart(char *command); -extern void rbtx4938_machine_halt(void); -extern void rbtx4938_machine_power_off(void); - -/* clocks */ -unsigned int txx9_master_clock; -unsigned int txx9_cpu_clock; -unsigned int txx9_gbus_clock; - -unsigned long rbtx4938_ce_base[8]; -unsigned long rbtx4938_ce_size[8]; -int txboard_pci66_mode; -static int tx4938_pcic_trdyto; /* default: disabled */ -static int tx4938_pcic_retryto; /* default: disabled */ -static int tx4938_ccfg_toeon = 1; - -struct tx4938_pcic_reg *pcicptrs[4] = { - tx4938_pcicptr /* default setting for TX4938 */ -}; - -static struct { - unsigned long base; - unsigned long size; -} phys_regions[16] __initdata; -static int num_phys_regions __initdata; - -#define PHYS_REGION_MINSIZE 0x10000 - -void rbtx4938_machine_halt(void) -{ - printk(KERN_NOTICE "System Halted\n"); - local_irq_disable(); - - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void rbtx4938_machine_power_off(void) -{ - rbtx4938_machine_halt(); - /* no return */ -} - -void rbtx4938_machine_restart(char *command) -{ - local_irq_disable(); - - printk("Rebooting..."); - writeb(1, rbtx4938_softresetlock_addr); - writeb(1, rbtx4938_sfvol_addr); - writeb(1, rbtx4938_softreset_addr); - while(1) - ; -} - -void __init -txboard_add_phys_region(unsigned long base, unsigned long size) -{ - if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { - printk("phys_region overflow\n"); - return; - } - phys_regions[num_phys_regions].base = base; - phys_regions[num_phys_regions].size = size; - num_phys_regions++; -} -unsigned long __init -txboard_find_free_phys_region(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - int i; - - for (base = begin / size * size; base < end; base += size) { - for (i = 0; i < num_phys_regions; i++) { - if (phys_regions[i].size && - base <= phys_regions[i].base + (phys_regions[i].size - 1) && - base + (size - 1) >= phys_regions[i].base) - break; - } - if (i == num_phys_regions) - return base; - } - return 0; -} -unsigned long __init -txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, - unsigned long *size) -{ - unsigned long sz, base; - for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { - base = txboard_find_free_phys_region(begin, end, sz); - if (base) { - *size = sz; - return base; - } - } - return 0; -} -unsigned long __init -txboard_request_phys_region_range(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region(unsigned long size) -{ - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region_shrink(unsigned long *size) -{ - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region_shrink(begin, end, size); - if (base) - txboard_add_phys_region(base, *size); - return base; -} - -#ifdef CONFIG_PCI -void __init -tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, - struct pci_controller *channel, - unsigned long pci_io_base, - int extarb) -{ - int i; - - /* Disable All Initiator Space */ - pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| - TX4938_PCIC_PCICCFG_G2PMEN(1)| - TX4938_PCIC_PCICCFG_G2PMEN(2)| - TX4938_PCIC_PCICCFG_G2PIOEN); - - /* GB->PCI mappings */ - pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; - pcicptr->g2piogbase = pci_io_base | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PIOGBASE_ECHG -#else - TX4938_PCIC_G2PIOGBASE_BSDIS -#endif - ; - pcicptr->g2piopbase = 0; - for (i = 0; i < 3; i++) { - pcicptr->g2pmmask[i] = 0; - pcicptr->g2pmgbase[i] = 0; - pcicptr->g2pmpbase[i] = 0; - } - if (channel->mem_resource->end) { - pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; - pcicptr->g2pmgbase[0] = channel->mem_resource->start | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PMnGBASE_ECHG -#else - TX4938_PCIC_G2PMnGBASE_BSDIS -#endif - ; - pcicptr->g2pmpbase[0] = channel->mem_resource->start; - } - /* PCI->GB mappings (I/O 256B) */ - pcicptr->p2giopbase = 0; /* 256B */ - pcicptr->p2giogbase = 0; - /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ - pcicptr->p2gm0plbase = 0; - pcicptr->p2gm0pubase = 0; - pcicptr->p2gmgbase[0] = 0 | - TX4938_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4938_PCIC_P2GMnGBASE_TECHG -#else - TX4938_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - /* PCI->GB mappings (MEM 16MB) */ - pcicptr->p2gm1plbase = 0xffffffff; - pcicptr->p2gm1pubase = 0xffffffff; - pcicptr->p2gmgbase[1] = 0; - /* PCI->GB mappings (MEM 1MB) */ - pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ - pcicptr->p2gmgbase[2] = 0; - - pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; - /* Enable Initiator Memory Space */ - if (channel->mem_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); - /* Enable Initiator I/O Space */ - if (channel->io_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; - /* Enable Initiator Config */ - pcicptr->pciccfg |= - TX4938_PCIC_PCICCFG_ICAEN | - TX4938_PCIC_PCICCFG_TCAR; - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - pcicptr->pcicfg1 = 0; - - pcicptr->g2ptocnt &= ~0xffff; - - if (tx4938_pcic_trdyto >= 0) { - pcicptr->g2ptocnt &= ~0xff; - pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); - } - - if (tx4938_pcic_retryto >= 0) { - pcicptr->g2ptocnt &= ~0xff00; - pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); - } - - /* Clear All Local Bus Status */ - pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - pcicptr->pcistatus = - (pcicptr->pcistatus & 0x0000ffff) | - (TX4938_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; - - if (!extarb) { - /* Reset Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; - pcicptr->pbabm = 0; - /* Enable Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; - } - - /* PCIC Int => IRC IRQ16 */ - pcicptr->pcicfg2 = - (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; - - pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; -} - -int __init -tx4938_report_pciclk(void) -{ - unsigned long pcode = TX4938_REV_PCODE(); - int pciclk = 0; - printk("TX%lx PCIC --%s PCICLK:", - pcode, - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - - switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { - case TX4938_CCFG_PCIDIVMODE_4: - pciclk = txx9_cpu_clock / 4; break; - case TX4938_CCFG_PCIDIVMODE_4_5: - pciclk = txx9_cpu_clock * 2 / 9; break; - case TX4938_CCFG_PCIDIVMODE_5: - pciclk = txx9_cpu_clock / 5; break; - case TX4938_CCFG_PCIDIVMODE_5_5: - pciclk = txx9_cpu_clock * 2 / 11; break; - case TX4938_CCFG_PCIDIVMODE_8: - pciclk = txx9_cpu_clock / 8; break; - case TX4938_CCFG_PCIDIVMODE_9: - pciclk = txx9_cpu_clock / 9; break; - case TX4938_CCFG_PCIDIVMODE_10: - pciclk = txx9_cpu_clock / 10; break; - case TX4938_CCFG_PCIDIVMODE_11: - pciclk = txx9_cpu_clock / 11; break; - } - printk("Internal(%dMHz)", pciclk / 1000000); - } else { - printk("External"); - pciclk = -1; - } - printk("\n"); - return pciclk; -} - -void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) -{ - pcicptrs[ch] = pcicptr; -} - -struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) -{ - return pcicptrs[ch]; -} - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = bus.sysdata = hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, word, u16 *) - -int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) -{ - u32 pci_devfn; - unsigned short vid; - int devfn_start = 0; - int devfn_stop = 0xff; - int cap66 = -1; - u16 stat; - - printk("PCI: Checking 66MHz capabilities...\n"); - - for (pci_devfn=devfn_start; pci_devfn 0; -} - -int __init -tx4938_pciclk66_setup(void) -{ - int pciclk; - - /* Assert M66EN */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; - /* Double PCICLK (if possible) */ - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - unsigned int pcidivmode = - tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; - switch (pcidivmode) { - case TX4938_CCFG_PCIDIVMODE_8: - case TX4938_CCFG_PCIDIVMODE_4: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4; - pciclk = txx9_cpu_clock / 4; - break; - case TX4938_CCFG_PCIDIVMODE_9: - case TX4938_CCFG_PCIDIVMODE_4_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; - pciclk = txx9_cpu_clock * 2 / 9; - break; - case TX4938_CCFG_PCIDIVMODE_10: - case TX4938_CCFG_PCIDIVMODE_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5; - pciclk = txx9_cpu_clock / 5; - break; - case TX4938_CCFG_PCIDIVMODE_11: - case TX4938_CCFG_PCIDIVMODE_5_5: - default: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; - pciclk = txx9_cpu_clock * 2 / 11; - break; - } - tx4938_ccfgptr->ccfg = - (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) - | pcidivmode; - printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", - (unsigned long)tx4938_ccfgptr->ccfg); - } else { - pciclk = -1; - } - return pciclk; -} - -extern struct pci_controller tx4938_pci_controller[]; -static int __init tx4938_pcibios_init(void) -{ - unsigned long mem_base[2]; - unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ - unsigned long io_base[2]; - unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ - /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ - int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); - - PCIBIOS_MIN_IO = 0x00001000UL; - - mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); - io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); - - printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - (unsigned short)(tx4938_pcicptr->pciid >> 16), - (unsigned short)(tx4938_pcicptr->pciid & 0xffff), - (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), - extarb ? "External" : "Internal"); - - /* setup PCI area */ - tx4938_pci_controller[0].io_resource->start = io_base[0]; - tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; - tx4938_pci_controller[0].mem_resource->start = mem_base[0]; - tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; - - set_tx4938_pcicptr(0, tx4938_pcicptr); - - register_pci_controller(&tx4938_pci_controller[0]); - - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { - printk("TX4938_CCFG_PCI66 already configured\n"); - txboard_pci66_mode = -1; /* already configured */ - } - - /* Reset PCI Bus */ - writeb(0, rbtx4938_pcireset_addr); - /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; - if (txboard_pci66_mode > 0) - tx4938_pciclk66_setup(); - mdelay(10); - /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; - writeb(1, rbtx4938_pcireset_addr); - mmiowb(); - tx4938_report_pcic_status1(tx4938_pcicptr); - - tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); - if (txboard_pci66_mode == 0 && - txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { - /* Reset PCI Bus */ - writeb(0, rbtx4938_pcireset_addr); - /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; - tx4938_pciclk66_setup(); - mdelay(10); - /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; - writeb(1, rbtx4938_pcireset_addr); - mmiowb(); - /* Reinitialize PCIC */ - tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); - } - - mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); - io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); - /* Reset PCIC1 */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; - /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; - else - tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; - mdelay(10); - /* clear PCIC1 reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; - tx4938_report_pcic_status1(tx4938_pcic1ptr); - - printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", - (unsigned short)(tx4938_pcic1ptr->pciid >> 16), - (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), - (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); - printk("%s PCICLK:%dMHz\n", - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", - txx9_gbus_clock / - ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / - 1000000); - - /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ - tx4938_pci_controller[1].io_resource->start = - io_base[1] - io_base[0]; - tx4938_pci_controller[1].io_resource->end = - io_base[1] - io_base[0] + io_size[1] - 1; - tx4938_pci_controller[1].mem_resource->start = mem_base[1]; - tx4938_pci_controller[1].mem_resource->end = - mem_base[1] + mem_size[1] - 1; - set_tx4938_pcicptr(1, tx4938_pcic1ptr); - - register_pci_controller(&tx4938_pci_controller[1]); - - tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); - - /* map ioport 0 to PCI I/O space address 0 */ - set_io_port_base(KSEG1 + io_base[0]); - - return 0; -} - -arch_initcall(tx4938_pcibios_init); - -#endif /* CONFIG_PCI */ - -/* SPI support */ - -/* chip select for SPI devices */ -#define SEEPROM1_CS 7 /* PIO7 */ -#define SEEPROM2_CS 0 /* IOC */ -#define SEEPROM3_CS 1 /* IOC */ -#define SRTC_CS 2 /* IOC */ - -#ifdef CONFIG_PCI -static int __init rbtx4938_ethaddr_init(void) -{ - unsigned char dat[17]; - unsigned char sum; - int i; - - /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ - if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) { - printk(KERN_ERR "seeprom: read error.\n"); - return -ENODEV; - } else { - if (strcmp(dat, "MAC") != 0) - printk(KERN_WARNING "seeprom: bad signature.\n"); - for (i = 0, sum = 0; i < sizeof(dat); i++) - sum += dat[i]; - if (sum) - printk(KERN_WARNING "seeprom: bad checksum.\n"); - } - for (i = 0; i < 2; i++) { - unsigned int id = - TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); - struct platform_device *pdev; - if (!(tx4938_ccfgptr->pcfg & - (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) - continue; - pdev = platform_device_alloc("tc35815-mac", id); - if (!pdev || - platform_device_add_data(pdev, &dat[4 + 6 * i], 6) || - platform_device_add(pdev)) - platform_device_put(pdev); - } - return 0; -} -device_initcall(rbtx4938_ethaddr_init); -#endif /* CONFIG_PCI */ - -static void __init rbtx4938_spi_setup(void) -{ - /* set SPI_SEL */ - tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; -} - -static struct resource rbtx4938_fpga_resource; - -static char pcode_str[8]; -static struct resource tx4938_reg_resource = { - .start = TX4938_REG_BASE, - .end = TX4938_REG_BASE + TX4938_REG_SIZE, - .name = pcode_str, - .flags = IORESOURCE_MEM -}; - -void __init tx4938_board_setup(void) -{ - int i; - unsigned long divmode; - int cpuclk = 0; - unsigned long pcode = TX4938_REV_PCODE(); - - ioport_resource.start = 0x1000; - ioport_resource.end = 0xffffffff; - iomem_resource.start = 0x1000; - iomem_resource.end = 0xffffffff; /* expand to 4GB */ - - sprintf(pcode_str, "TX%lx", pcode); - /* SDRAMC,EBUSC are configured by PROM */ - for (i = 0; i < 8; i++) { - if (!(tx4938_ebuscptr->cr[i] & 0x8)) - continue; /* disabled */ - rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); - txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); - } - - /* clocks */ - if (txx9_master_clock) { - /* calculate gbus_clock and cpu_clock_freq from master_clock */ - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; - switch (divmode) { - case TX4938_CCFG_DIVMODE_8: - case TX4938_CCFG_DIVMODE_10: - case TX4938_CCFG_DIVMODE_12: - case TX4938_CCFG_DIVMODE_16: - case TX4938_CCFG_DIVMODE_18: - txx9_gbus_clock = txx9_master_clock * 4; break; - default: - txx9_gbus_clock = txx9_master_clock; - } - switch (divmode) { - case TX4938_CCFG_DIVMODE_2: - case TX4938_CCFG_DIVMODE_8: - cpuclk = txx9_gbus_clock * 2; break; - case TX4938_CCFG_DIVMODE_2_5: - case TX4938_CCFG_DIVMODE_10: - cpuclk = txx9_gbus_clock * 5 / 2; break; - case TX4938_CCFG_DIVMODE_3: - case TX4938_CCFG_DIVMODE_12: - cpuclk = txx9_gbus_clock * 3; break; - case TX4938_CCFG_DIVMODE_4: - case TX4938_CCFG_DIVMODE_16: - cpuclk = txx9_gbus_clock * 4; break; - case TX4938_CCFG_DIVMODE_4_5: - case TX4938_CCFG_DIVMODE_18: - cpuclk = txx9_gbus_clock * 9 / 2; break; - } - txx9_cpu_clock = cpuclk; - } else { - if (txx9_cpu_clock == 0) { - txx9_cpu_clock = 300000000; /* 300MHz */ - } - /* calculate gbus_clock and master_clock from cpu_clock_freq */ - cpuclk = txx9_cpu_clock; - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; - switch (divmode) { - case TX4938_CCFG_DIVMODE_2: - case TX4938_CCFG_DIVMODE_8: - txx9_gbus_clock = cpuclk / 2; break; - case TX4938_CCFG_DIVMODE_2_5: - case TX4938_CCFG_DIVMODE_10: - txx9_gbus_clock = cpuclk * 2 / 5; break; - case TX4938_CCFG_DIVMODE_3: - case TX4938_CCFG_DIVMODE_12: - txx9_gbus_clock = cpuclk / 3; break; - case TX4938_CCFG_DIVMODE_4: - case TX4938_CCFG_DIVMODE_16: - txx9_gbus_clock = cpuclk / 4; break; - case TX4938_CCFG_DIVMODE_4_5: - case TX4938_CCFG_DIVMODE_18: - txx9_gbus_clock = cpuclk * 2 / 9; break; - } - switch (divmode) { - case TX4938_CCFG_DIVMODE_8: - case TX4938_CCFG_DIVMODE_10: - case TX4938_CCFG_DIVMODE_12: - case TX4938_CCFG_DIVMODE_16: - case TX4938_CCFG_DIVMODE_18: - txx9_master_clock = txx9_gbus_clock / 4; break; - default: - txx9_master_clock = txx9_gbus_clock; - } - } - /* change default value to udelay/mdelay take reasonable time */ - loops_per_jiffy = txx9_cpu_clock / HZ / 2; - - /* CCFG */ - /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; - /* do reset on watchdog */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; - /* clear PCIC1 reset */ - if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; - - /* enable Timeout BusError */ - if (tx4938_ccfg_toeon) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; - - /* DMA selection */ - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; - - /* Use external clock for external arbiter */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; - - printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", - pcode_str, - cpuclk / 1000000, txx9_master_clock / 1000000, - (unsigned long)tx4938_ccfgptr->crir, - tx4938_ccfgptr->ccfg, - tx4938_ccfgptr->pcfg); - - printk("%s SDRAMC --", pcode_str); - for (i = 0; i < 4; i++) { - unsigned long long cr = tx4938_sdramcptr->cr[i]; - unsigned long ram_base, ram_size; - if (!((unsigned long)cr & 0x00000400)) - continue; /* disabled */ - ram_base = (unsigned long)(cr >> 49) << 21; - ram_size = ((unsigned long)(cr >> 33) + 1) << 21; - if (ram_base >= 0x20000000) - continue; /* high memory (ignore) */ - printk(" CR%d:%016Lx", i, cr); - txboard_add_phys_region(ram_base, ram_size); - } - printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); - - /* SRAM */ - if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { - unsigned int size = 0x800; - unsigned long base = - (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); - txboard_add_phys_region(base, size); - } - - /* TMR */ - for (i = 0; i < TX4938_NR_TMR; i++) - txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); - - /* enable DMA */ - for (i = 0; i < 2; i++) - ____raw_writeq(TX4938_DMA_MCR_MSTEN, - (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); - - /* PIO */ - __raw_writel(0, &tx4938_pioptr->maskcpu); - __raw_writel(0, &tx4938_pioptr->maskext); - - /* TX4938 internal registers */ - if (request_resource(&iomem_resource, &tx4938_reg_resource)) - printk("request resource for internal registers failed\n"); -} - -#ifdef CONFIG_PCI -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) -{ - unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); - unsigned long g2pstatus = pcicptr->g2pstatus; - unsigned long pcicstatus = pcicptr->pcicstatus; - static struct { - unsigned long flag; - const char *str; - } pcistat_tbl[] = { - { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, - { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, - { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, - { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, - { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, - { PCI_STATUS_PARITY, "MasterParityError" }, - }, g2pstat_tbl[] = { - { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, - { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, - }, pcicstat_tbl[] = { - { TX4938_PCIC_PCICSTATUS_PME, "PME" }, - { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, - { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, - { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, - { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, - { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, - { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, - { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, - }; - int i; - - printk("pcistat:%04x(", pcistatus); - for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) - if (pcistatus & pcistat_tbl[i].flag) - printk("%s ", pcistat_tbl[i].str); - printk("), g2pstatus:%08lx(", g2pstatus); - for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) - if (g2pstatus & g2pstat_tbl[i].flag) - printk("%s ", g2pstat_tbl[i].str); - printk("), pcicstatus:%08lx(", pcicstatus); - for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) - if (pcicstatus & pcicstat_tbl[i].flag) - printk("%s ", pcicstat_tbl[i].str); - printk(")\n"); -} - -void tx4938_report_pcic_status(void) -{ - int i; - struct tx4938_pcic_reg *pcicptr; - for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) - tx4938_report_pcic_status1(pcicptr); -} - -#endif /* CONFIG_PCI */ - -void __init plat_time_init(void) -{ - mips_hpt_frequency = txx9_cpu_clock / 2; - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) - txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, - TXX9_IRQ_BASE + TX4938_IR_TMR(0), - txx9_gbus_clock / 2); -} - -void __init plat_mem_setup(void) -{ - unsigned long long pcfg; - char *argptr; - - iomem_resource.end = 0xffffffff; /* 4GB */ - - if (txx9_master_clock == 0) - txx9_master_clock = 25000000; /* 25MHz */ - tx4938_board_setup(); -#ifndef CONFIG_PCI - set_io_port_base(RBTX4938_ETHER_BASE); -#endif - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - int i; - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (char *)(0xff1ff300 + i * 0x100); - req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = RBTX4938_IRQ_IRC_SIO(i); - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = 50000000; - early_serial_txx9_setup(&req); - } - } -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (strstr(argptr, "console=") == NULL) { - strcat(argptr, " console=ttyS0,38400"); - } -#endif -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 - printk("PIOSEL: disabling both ata and nand selection\n"); - local_irq_disable(); - tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND - printk("PIOSEL: enabling nand selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; -#endif - -#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA - printk("PIOSEL: enabling ata selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; -#endif - -#ifdef CONFIG_IP_PNP - argptr = prom_getcmdline(); - if (strstr(argptr, "ip=") == NULL) { - strcat(argptr, " ip=any"); - } -#endif - - -#ifdef CONFIG_FB - { - conswitchp = &dummy_con; - } -#endif - - rbtx4938_spi_setup(); - pcfg = tx4938_ccfgptr->pcfg; /* updated */ - /* fixup piosel */ - if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == - TX4938_PCFG_ATA_SEL) - writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, - rbtx4938_piosel_addr); - else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == - TX4938_PCFG_NDF_SEL) - writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, - rbtx4938_piosel_addr); - else - writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), - rbtx4938_piosel_addr); - - rbtx4938_fpga_resource.name = "FPGA Registers"; - rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); - rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; - rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; - if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) - printk("request resource for fpga failed\n"); - - _machine_restart = rbtx4938_machine_restart; - _machine_halt = rbtx4938_machine_halt; - pm_power_off = rbtx4938_machine_power_off; - - writeb(0xff, rbtx4938_led_addr); - printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", - readb(rbtx4938_fpga_rev_addr), - readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); -} - -static int __init rbtx4938_ne_init(void) -{ - struct resource res[] = { - { - .start = RBTX4938_RTL_8019_BASE, - .end = RBTX4938_RTL_8019_BASE + 0x20 - 1, - .flags = IORESOURCE_IO, - }, { - .start = RBTX4938_RTL_8019_IRQ, - .flags = IORESOURCE_IRQ, - } - }; - struct platform_device *dev = - platform_device_register_simple("ne", -1, - res, ARRAY_SIZE(res)); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} -device_initcall(rbtx4938_ne_init); - -/* GPIO support */ - -int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); - -static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - u8 val; - unsigned long flags; - spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags); - val = readb(rbtx4938_spics_addr); - if (value) - val |= 1 << offset; - else - val &= ~(1 << offset); - writeb(val, rbtx4938_spics_addr); - mmiowb(); - spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags); -} - -static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip, - unsigned int offset, int value) -{ - rbtx4938_spi_gpio_set(chip, offset, value); - return 0; -} - -static struct gpio_chip rbtx4938_spi_gpio_chip = { - .set = rbtx4938_spi_gpio_set, - .direction_output = rbtx4938_spi_gpio_dir_out, - .label = "RBTX4938-SPICS", - .base = 16, - .ngpio = 3, -}; - -/* SPI support */ - -static void __init txx9_spi_init(unsigned long base, int irq) -{ - struct resource res[] = { - { - .start = base, - .end = base + 0x20 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .flags = IORESOURCE_IRQ, - }, - }; - platform_device_register_simple("spi_txx9", 0, - res, ARRAY_SIZE(res)); -} - -static int __init rbtx4938_spi_init(void) -{ - struct spi_board_info srtc_info = { - .modalias = "rtc-rs5c348", - .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */ - .bus_num = 0, - .chip_select = 16 + SRTC_CS, - /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */ - .mode = SPI_MODE_1 | SPI_CS_HIGH, - }; - spi_register_board_info(&srtc_info, 1); - spi_eeprom_register(SEEPROM1_CS); - spi_eeprom_register(16 + SEEPROM2_CS); - spi_eeprom_register(16 + SEEPROM3_CS); - gpio_request(16 + SRTC_CS, "rtc-rs5c348"); - gpio_direction_output(16 + SRTC_CS, 0); - gpio_request(SEEPROM1_CS, "seeprom1"); - gpio_direction_output(SEEPROM1_CS, 1); - gpio_request(16 + SEEPROM2_CS, "seeprom2"); - gpio_direction_output(16 + SEEPROM2_CS, 1); - gpio_request(16 + SEEPROM3_CS, "seeprom3"); - gpio_direction_output(16 + SEEPROM3_CS, 1); - txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI); - return 0; -} - -static int __init rbtx4938_arch_init(void) -{ - txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); - gpiochip_add(&rbtx4938_spi_gpio_chip); - return rbtx4938_spi_init(); -} -arch_initcall(rbtx4938_arch_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init rbtx4938_wdt_init(void) -{ - return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); -} -device_initcall(rbtx4938_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "spi-baseclk")) - return (struct clk *)(txx9_gbus_clock / 2 / 4); - if (!strcmp(id, "imbus_clk")) - return (struct clk *)(txx9_gbus_clock / 2); - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c deleted file mode 100644 index 4d6b4ade5e8c..000000000000 --- a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include - -#define AT250X0_PAGE_SIZE 8 - -/* register board information for at25 driver */ -int __init spi_eeprom_register(int chipid) -{ - static struct spi_eeprom eeprom = { - .name = "at250x0", - .byte_len = 128, - .page_size = AT250X0_PAGE_SIZE, - .flags = EE_ADDR1, - }; - struct spi_board_info info = { - .modalias = "at25", - .max_speed_hz = 1500000, /* 1.5Mbps */ - .bus_num = 0, - .chip_select = chipid, - .platform_data = &eeprom, - /* Mode 0: High-Active, Sample-Then-Shift */ - }; - - return spi_register_board_info(&info, 1); -} - -/* simple temporary spi driver to provide early access to seeprom. */ - -static struct read_param { - int chipid; - int address; - unsigned char *buf; - int len; -} *read_param; - -static int __init early_seeprom_probe(struct spi_device *spi) -{ - int stat = 0; - u8 cmd[2]; - int len = read_param->len; - char *buf = read_param->buf; - int address = read_param->address; - - dev_info(&spi->dev, "spiclk %u KHz.\n", - (spi->max_speed_hz + 500) / 1000); - if (read_param->chipid != spi->chip_select) - return -ENODEV; - while (len > 0) { - /* spi_write_then_read can only work with small chunk */ - int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE; - cmd[0] = 0x03; /* AT25_READ */ - cmd[1] = address; - stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c); - buf += c; - len -= c; - address += c; - } - return stat; -} - -static struct spi_driver early_seeprom_driver __initdata = { - .driver = { - .name = "at25", - .owner = THIS_MODULE, - }, - .probe = early_seeprom_probe, -}; - -int __init spi_eeprom_read(int chipid, int address, - unsigned char *buf, int len) -{ - int ret; - struct read_param param = { - .chipid = chipid, - .address = address, - .buf = buf, - .len = len - }; - - read_param = ¶m; - ret = spi_register_driver(&early_seeprom_driver); - if (!ret) - spi_unregister_driver(&early_seeprom_driver); - return ret; -} diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig new file mode 100644 index 000000000000..98d103402b10 --- /dev/null +++ b/arch/mips/txx9/Kconfig @@ -0,0 +1,28 @@ +config TOSHIBA_FPCIB0 + bool "FPCIB0 Backplane Support" + depends on TOSHIBA_RBTX4927 + +if TOSHIBA_RBTX4938 + +comment "Multiplex Pin Select" +choice + prompt "PIO[58:61]" + default TOSHIBA_RBTX4938_MPLEX_PIO58_61 + +config TOSHIBA_RBTX4938_MPLEX_PIO58_61 + bool "PIO" +config TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND" +config TOSHIBA_RBTX4938_MPLEX_ATA + bool "ATA" + +endchoice + +config TX4938_NAND_BOOT + depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND + bool "NAND Boot Support (EXPERIMENTAL)" + help + This is only for Toshiba RBTX4938 reference board, which has NAND IPL. + Select this option if you need to use NAND boot. + +endif diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile new file mode 100644 index 000000000000..8cb4a7e81473 --- /dev/null +++ b/arch/mips/txx9/generic/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for common code for TXx9 based systems +# + +obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o +obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o +obj-$(CONFIG_KGDB) += dbgio.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/generic/dbgio.c b/arch/mips/txx9/generic/dbgio.c new file mode 100644 index 000000000000..33b9c672a322 --- /dev/null +++ b/arch/mips/txx9/generic/dbgio.c @@ -0,0 +1,48 @@ +/* + * linux/arch/mips/tx4938/common/dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2005 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Support for TX4938 in 2.6 - Hiroshi DOYU + */ + +#include + +extern u8 txx9_sio_kdbg_rd(void); +extern int txx9_sio_kdbg_wr( u8 ch ); + +u8 getDebugChar(void) +{ + return (txx9_sio_kdbg_rd()); +} + +int putDebugChar(u8 byte) +{ + return (txx9_sio_kdbg_wr(byte)); +} + diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c new file mode 100644 index 000000000000..685ecc2ed551 --- /dev/null +++ b/arch/mips/txx9/generic/irq_tx4927.c @@ -0,0 +1,64 @@ +/* + * Common tx4927 irq handler + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_RBTX4927 +#include +#endif + +void __init tx4927_irq_init(void) +{ + mips_cpu_irq_init(); + txx9_irq_init(TX4927_IRC_REG); + set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) /* cpu timer */ + do_IRQ(TX4927_IRQ_CPU_TIMER); + else if (pending & STATUSF_IP2) { /* tx4927 pic */ + int irq = txx9_irq(); +#ifdef CONFIG_TOSHIBA_RBTX4927 + if (irq == TX4927_IRQ_NEST_EXT_ON_PIC) + irq = toshiba_rbtx4927_irq_nested(irq); +#endif + if (unlikely(irq < 0)) { + spurious_interrupt(); + return; + } + do_IRQ(irq); + } else if (pending & STATUSF_IP0) /* user line 0 */ + do_IRQ(TX4927_IRQ_USER0); + else if (pending & STATUSF_IP1) /* user line 1 */ + do_IRQ(TX4927_IRQ_USER1); + else + spurious_interrupt(); +} diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c new file mode 100644 index 000000000000..0886d9138818 --- /dev/null +++ b/arch/mips/txx9/generic/irq_tx4938.c @@ -0,0 +1,48 @@ +/* + * linux/arch/mips/tx4938/common/irq.c + * + * Common tx4938 irq handler + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +void __init +tx4938_irq_init(void) +{ + mips_cpu_irq_init(); + txx9_irq_init(TX4938_IRC_REG); + set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); +} + +int toshiba_rbtx4938_irq_nested(int irq); + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status(); + + if (pending & STATUSF_IP7) + do_IRQ(TX4938_IRQ_CPU_TIMER); + else if (pending & STATUSF_IP2) { + int irq = txx9_irq(); + if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0)) + irq = toshiba_rbtx4938_irq_nested(irq); + if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); + } else if (pending & STATUSF_IP1) + do_IRQ(TX4938_IRQ_USER1); + else if (pending & STATUSF_IP0) + do_IRQ(TX4938_IRQ_USER0); +} diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c new file mode 100644 index 000000000000..12dfc377bf2f --- /dev/null +++ b/arch/mips/txx9/generic/mem_tx4927.c @@ -0,0 +1,141 @@ +/* + * linux/arch/mips/tx4927/common/tx4927_prom.c + * + * common tx4927 memory interface + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +static unsigned int __init tx4927_process_sdccr(unsigned long addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_bs; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int bs = 0; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int msize = 0; + + val = __raw_readq((void __iomem *)addr); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_bs = ((val & (1 << 8)) >> 8); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (3 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_bs) { + case 0:{ + bs = 2; + break; + } + case 1:{ + bs = 4; + break; + } + } + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + case 3:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip num chips */ + msize = (((rs * cs * mw) / (1024 * 1024)) * bs); + + return (msize); +} + + +unsigned int __init tx4927_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4927_process_sdccr(0xff1f8000); + c1 = tx4927_process_sdccr(0xff1f8008); + c2 = tx4927_process_sdccr(0xff1f8010); + c3 = tx4927_process_sdccr(0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} diff --git a/arch/mips/txx9/generic/mem_tx4938.c b/arch/mips/txx9/generic/mem_tx4938.c new file mode 100644 index 000000000000..20baeaeba4cd --- /dev/null +++ b/arch/mips/txx9/generic/mem_tx4938.c @@ -0,0 +1,124 @@ +/* + * linux/arch/mips/tx4938/common/prom.c + * + * common tx4938 memory interface + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include + +static unsigned int __init +tx4938_process_sdccr(u64 * addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int bc = 4; + unsigned int msize = 0; + + val = ____raw_readq((void __iomem *)addr); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (7 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + default:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + case 4:{ + cs = 4096; + break; + } + default:{ + cs = 0; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip bank count */ + msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); + + /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ + /* boad supports bc=2 but no way to detect */ + + return (msize); +} + +unsigned int __init +tx4938_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); + c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); + c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); + c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c new file mode 100644 index 000000000000..69e487467fa5 --- /dev/null +++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c @@ -0,0 +1,172 @@ +/* + * Interface for smsc fdc48m81x Super IO chip + * + * Author: MontaVista Software, Inc. source@mvista.com + * + * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright 2004 (c) MontaVista Software, Inc. + */ +#include +#include +#include +#include + +#define DEBUG + +/* Common Registers */ +#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 +#define SMSC_FDC37M81X_CONFIG_DATA 0x01 +#define SMSC_FDC37M81X_CONF 0x02 +#define SMSC_FDC37M81X_INDEX 0x03 +#define SMSC_FDC37M81X_DNUM 0x07 +#define SMSC_FDC37M81X_DID 0x20 +#define SMSC_FDC37M81X_DREV 0x21 +#define SMSC_FDC37M81X_PCNT 0x22 +#define SMSC_FDC37M81X_PMGT 0x23 +#define SMSC_FDC37M81X_OSC 0x24 +#define SMSC_FDC37M81X_CONFPA0 0x26 +#define SMSC_FDC37M81X_CONFPA1 0x27 +#define SMSC_FDC37M81X_TEST4 0x2B +#define SMSC_FDC37M81X_TEST5 0x2C +#define SMSC_FDC37M81X_TEST1 0x2D +#define SMSC_FDC37M81X_TEST2 0x2E +#define SMSC_FDC37M81X_TEST3 0x2F + +/* Logical device numbers */ +#define SMSC_FDC37M81X_FDD 0x00 +#define SMSC_FDC37M81X_SERIAL1 0x04 +#define SMSC_FDC37M81X_SERIAL2 0x05 +#define SMSC_FDC37M81X_KBD 0x07 + +/* Logical device Config Registers */ +#define SMSC_FDC37M81X_ACTIVE 0x30 +#define SMSC_FDC37M81X_BASEADDR0 0x60 +#define SMSC_FDC37M81X_BASEADDR1 0x61 +#define SMSC_FDC37M81X_INT 0x70 +#define SMSC_FDC37M81X_INT2 0x72 +#define SMSC_FDC37M81X_MODE 0xF0 + +/* Chip Config Values */ +#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 +#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa +#define SMSC_FDC37M81X_CHIP_ID 0x4d + +static unsigned long g_smsc_fdc37m81x_base = 0; + +static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) +{ + outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + + return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); +} + +static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data) +{ + outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); +} + +void smsc_fdc37m81x_config_beg(void) +{ + if (g_smsc_fdc37m81x_base) { + outb(SMSC_FDC37M81X_CONFIG_ENTER, + g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); + } +} + +void smsc_fdc37m81x_config_end(void) +{ + if (g_smsc_fdc37m81x_base) + outb(SMSC_FDC37M81X_CONFIG_EXIT, + g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); +} + +u8 smsc_fdc37m81x_config_get(u8 reg) +{ + u8 val = 0; + + if (g_smsc_fdc37m81x_base) + val = smsc_fdc37m81x_rd(reg); + + return val; +} + +void smsc_fdc37m81x_config_set(u8 reg, u8 val) +{ + if (g_smsc_fdc37m81x_base) + smsc_dc37m81x_wr(reg, val); +} + +unsigned long __init smsc_fdc37m81x_init(unsigned long port) +{ + const int field = sizeof(unsigned long) * 2; + u8 chip_id; + + if (g_smsc_fdc37m81x_base) + printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", + field, g_smsc_fdc37m81x_base); + + g_smsc_fdc37m81x_base = port; + + smsc_fdc37m81x_config_beg(); + + chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID); + if (chip_id == SMSC_FDC37M81X_CHIP_ID) + smsc_fdc37m81x_config_end(); + else { + printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", + chip_id); + g_smsc_fdc37m81x_base = 0; + } + + return g_smsc_fdc37m81x_base; +} + +#ifdef DEBUG +void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) +{ + printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, + smsc_fdc37m81x_rd(reg)); +} + +void smsc_fdc37m81x_config_dump(void) +{ + u8 orig; + char *fname = "smsc_fdc37m81x_config_dump()"; + + smsc_fdc37m81x_config_beg(); + + orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); + + printk("%s: common\n", fname); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DNUM); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DID); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_DREV); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_PCNT); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, + SMSC_FDC37M81X_PMGT); + + printk("%s: keyboard\n", fname); + smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_ACTIVE); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_INT); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_INT2); + smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, + SMSC_FDC37M81X_LDCR_F0); + + smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig); + + smsc_fdc37m81x_config_end(); +} +#endif diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile new file mode 100644 index 000000000000..5f83ea375225 --- /dev/null +++ b/arch/mips/txx9/jmr3927/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for TOSHIBA JMR-TX3927 board +# + +obj-y += prom.o init.o irq.o setup.o +obj-$(CONFIG_KGDB) += kgdb_io.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/jmr3927/init.c b/arch/mips/txx9/jmr3927/init.c new file mode 100644 index 000000000000..1bbb5343baf4 --- /dev/null +++ b/arch/mips/txx9/jmr3927/init.c @@ -0,0 +1,57 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * arch/mips/jmr3927/common/init.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +extern void __init prom_init_cmdline(void); + +const char *get_system_type(void) +{ + return "Toshiba" +#ifdef CONFIG_TOSHIBA_JMR3927 + " JMR_TX3927" +#endif + ; +} + +extern void puts(const char *cp); + +void __init prom_init(void) +{ +#ifdef CONFIG_TOSHIBA_JMR3927 + /* CCFG */ + if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) + puts("Warning: TX3927 TLB off\n"); +#endif + + prom_init_cmdline(); + add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); +} diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c new file mode 100644 index 000000000000..85e1daf15c7b --- /dev/null +++ b/arch/mips/txx9/jmr3927/irq.c @@ -0,0 +1,174 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#if JMR3927_IRQ_END > NR_IRQS +#error JMR3927_IRQ_END > NR_IRQS +#endif + +static unsigned char irc_level[TX3927_NUM_IR] = { + 5, 5, 5, 5, 5, 5, /* INT[5:0] */ + 7, 7, /* SIO */ + 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ + 6, 6, 6 /* TMR */ +}; + +/* + * CP0_STATUS is a thread's resource (saved/restored on context switch). + * So disable_irq/enable_irq MUST handle IOC/IRC registers. + */ +static void mask_irq_ioc(unsigned int irq) +{ + /* 0: mask */ + unsigned int irq_nr = irq - JMR3927_IRQ_IOC; + unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} +static void unmask_irq_ioc(unsigned int irq) +{ + /* 0: mask */ + unsigned int irq_nr = irq - JMR3927_IRQ_IOC; + unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long cp0_cause = read_c0_cause(); + int irq; + + if ((cp0_cause & CAUSEF_IP7) == 0) + return; + irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; + + do_IRQ(irq + JMR3927_IRQ_IRC); +} + +static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) +{ + unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); + int i; + + for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { + if (istat & (1 << i)) { + irq = JMR3927_IRQ_IOC + i; + do_IRQ(irq); + } + } + return IRQ_HANDLED; +} + +static struct irqaction ioc_action = { + .handler = jmr3927_ioc_interrupt, + .mask = CPU_MASK_NONE, + .name = "IOC", +}; + +static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) +{ + printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); + printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", + tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); + + return IRQ_HANDLED; +} +static struct irqaction pcierr_action = { + .handler = jmr3927_pcierr_interrupt, + .mask = CPU_MASK_NONE, + .name = "PCI error", +}; + +static void __init jmr3927_irq_init(void); + +void __init arch_init_irq(void) +{ + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + /* mask all IOC interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); + /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ + jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); + + /* clear PCI Soft interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); + /* clear PCI Reset interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + + jmr3927_irq_init(); + + /* setup IOC interrupt 1 (PCI, MODEM) */ + setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); + +#ifdef CONFIG_PCI + setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); +#endif + + /* enable all CPU interrupt bits. */ + set_c0_status(ST0_IM); /* IE bit is still 0. */ +} + +static struct irq_chip jmr3927_irq_ioc = { + .name = "jmr3927_ioc", + .ack = mask_irq_ioc, + .mask = mask_irq_ioc, + .mask_ack = mask_irq_ioc, + .unmask = unmask_irq_ioc, +}; + +static void __init jmr3927_irq_init(void) +{ + u32 i; + + txx9_irq_init(TX3927_IRC_REG); + for (i = 0; i < TXx9_MAX_IR; i++) + txx9_irq_set_pri(i, irc_level[i]); + for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) + set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); +} diff --git a/arch/mips/txx9/jmr3927/kgdb_io.c b/arch/mips/txx9/jmr3927/kgdb_io.c new file mode 100644 index 000000000000..5bd757e56f79 --- /dev/null +++ b/arch/mips/txx9/jmr3927/kgdb_io.c @@ -0,0 +1,105 @@ +/* + * BRIEF MODULE DESCRIPTION + * Low level uart routines to directly access a TX[34]927 SIO. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com or source@mvista.com + * + * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#define TIMEOUT 0xffffff + +static int remoteDebugInitialized = 0; +static void debugInit(int baud); + +int putDebugChar(unsigned char c) +{ + int i = 0; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(0)->tfifo = c; + + return 1; +} + +unsigned char getDebugChar(void) +{ + int i = 0; + int dicr; + char c; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + /* diable RX int. */ + dicr = tx3927_sioptr(0)->dicr; + tx3927_sioptr(0)->dicr = 0; + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID) + ; + c = tx3927_sioptr(0)->rfifo; + + /* clear RX int. status */ + tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS; + /* enable RX int. */ + tx3927_sioptr(0)->dicr = dicr; + + return c; +} + +static void debugInit(int baud) +{ + tx3927_sioptr(0)->lcr = 0x020; + tx3927_sioptr(0)->dicr = 0; + tx3927_sioptr(0)->disr = 0x4100; + tx3927_sioptr(0)->cisr = 0x014; + tx3927_sioptr(0)->fcr = 0; + tx3927_sioptr(0)->flcr = 0x02; + tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | + TXx927_SIBGR_BCLK_T0; +} diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c new file mode 100644 index 000000000000..8bc1049b622e --- /dev/null +++ b/arch/mips/txx9/jmr3927/prom.c @@ -0,0 +1,98 @@ +/* + * BRIEF MODULE DESCRIPTION + * PROM library initialisation code, assuming a version of + * pmon is the boot code. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Based on arch/mips/au1000/common/prom.c + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/xx files. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +#include +#include + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + int prom_argc = fw_arg0; + char **prom_argv = (char **) fw_arg1; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv[actr]); + cp += strlen(prom_argv[actr]); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + --cp; + *cp = '\0'; +} + +void __init prom_free_prom_memory(void) +{ +} + +#define TIMEOUT 0xffffff + +void +prom_putchar(char c) +{ + int i = 0; + + do { + i++; + if (i>TIMEOUT) + break; + } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(1)->tfifo = c; + return; +} + +void +puts(const char *cp) +{ + while (*cp) + prom_putchar(*cp++); + prom_putchar('\r'); + prom_putchar('\n'); +} diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c new file mode 100644 index 000000000000..41e0f3b3af2c --- /dev/null +++ b/arch/mips/txx9/jmr3927/setup.c @@ -0,0 +1,445 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif + +#include +#include +#include +#include +#include + +extern void puts(const char *cp); + +/* don't enable - see errata */ +static int jmr3927_ccfg_toeon; + +static inline void do_reset(void) +{ +#if 1 /* Resetting PCI bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); + (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ + mdelay(1); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); +#endif + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); +} + +static void jmr3927_machine_restart(char *command) +{ + local_irq_disable(); + puts("Rebooting..."); + do_reset(); +} + +static void jmr3927_machine_halt(void) +{ + puts("JMR-TX3927 halted.\n"); + while (1); +} + +static void jmr3927_machine_power_off(void) +{ + puts("JMR-TX3927 halted. Please turn off the power.\n"); + while (1); +} + +void __init plat_time_init(void) +{ + txx9_clockevent_init(TX3927_TMR_REG(0), + TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), + JMR3927_IMCLK); + txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK); +} + +#define DO_WRITE_THROUGH +#define DO_ENABLE_CACHE + +extern char * __init prom_getcmdline(void); +static void jmr3927_board_init(void); +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +void __init plat_mem_setup(void) +{ + char *argptr; + + set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); + + _machine_restart = jmr3927_machine_restart; + _machine_halt = jmr3927_machine_halt; + pm_power_off = jmr3927_machine_power_off; + + /* + * IO/MEM resources. + */ + ioport_resource.start = pci_io_resource.start; + ioport_resource.end = pci_io_resource.end; + iomem_resource.start = 0; + iomem_resource.end = 0xffffffff; + + /* Reboot on panic */ + panic_timeout = 180; + + /* cache setup */ + { + unsigned int conf; +#ifdef DO_ENABLE_CACHE + int mips_ic_disable = 0, mips_dc_disable = 0; +#else + int mips_ic_disable = 1, mips_dc_disable = 1; +#endif +#ifdef DO_WRITE_THROUGH + int mips_config_cwfon = 0; + int mips_config_wbon = 0; +#else + int mips_config_cwfon = 1; + int mips_config_wbon = 1; +#endif + + conf = read_c0_conf(); + conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); + conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; + conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; + conf |= mips_config_wbon ? TX39_CONF_WBON : 0; + conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; + + write_c0_conf(conf); + write_c0_cache(0); + } + + /* initialize board */ + jmr3927_board_init(); + + argptr = prom_getcmdline(); + + if ((argptr = strstr(argptr, "toeon")) != NULL) + jmr3927_ccfg_toeon = 1; + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "ip=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " ip=bootp"); + } + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); + req.mapbase = TX3927_SIO_REG(i); + req.irq = i == 0 ? + JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; + if (i == 0) + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = JMR3927_IMCLK; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS1,115200"); + } +#endif +#endif +} + +static void tx3927_setup(void); + +static void __init jmr3927_board_init(void) +{ + tx3927_setup(); + + /* SIO0 DTR on */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); + + jmr3927_led_set(0); + + printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", + jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, + jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, + jmr3927_dipsw1(), jmr3927_dipsw2(), + jmr3927_dipsw3(), jmr3927_dipsw4()); +} + +static void __init tx3927_setup(void) +{ + int i; +#ifdef CONFIG_PCI + unsigned long mips_pci_io_base = JMR3927_PCIIO; + unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; + unsigned long mips_pci_mem_base = JMR3927_PCIMEM; + unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; + /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ + unsigned long mips_pci_io_pciaddr = 0; +#endif + + /* SDRAMC are configured by PROM */ + + /* ROMC */ + tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; + tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; + tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; + tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; + + /* CCFG */ + /* enable Timeout BusError */ + if (jmr3927_ccfg_toeon) + tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; + + /* clear BusErrorOnWrite flag */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; + /* Disable PCI snoop */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; + /* do reset on watchdog */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; + +#ifdef DO_WRITE_THROUGH + /* Enable PCI SNOOP - with write through only */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; +#endif + + /* Pin selection */ + tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; + tx3927_ccfgptr->pcfg |= + TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | + (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); + + printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", + tx3927_ccfgptr->crir, + tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); + + /* TMR */ + for (i = 0; i < TX3927_NR_TMR; i++) + txx9_tmr_init(TX3927_TMR_REG(i)); + + /* DMA */ + tx3927_dmaptr->mcr = 0; + for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) { + /* reset channel */ + tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; + tx3927_dmaptr->ch[i].ccr = 0; + } + /* enable DMA */ +#ifdef __BIG_ENDIAN + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; +#else + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; +#endif + +#ifdef CONFIG_PCI + /* PCIC */ + printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", + tx3927_pcicptr->did, tx3927_pcicptr->vid, + tx3927_pcicptr->rid); + if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { + printk("External\n"); + /* XXX */ + } else { + printk("Internal\n"); + + /* Reset PCI Bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, + JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + + + /* Disable External PCI Config. Access */ + tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; +#ifdef __BIG_ENDIAN + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | + TX3927_PCIC_LBC_TIBSE | + TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; +#endif + /* LB->PCI mappings */ + tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); + tx3927_pcicptr->ilbioma = mips_pci_io_base; + tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; + tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); + tx3927_pcicptr->ilbmma = mips_pci_mem_base; + tx3927_pcicptr->ipbmma = mips_pci_mem_base; + /* PCI->LB mappings */ + tx3927_pcicptr->iobas = 0xffffffff; + tx3927_pcicptr->ioba = 0; + tx3927_pcicptr->tlbioma = 0; + tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); + tx3927_pcicptr->mba = 0; + tx3927_pcicptr->tlbmma = 0; + /* Enable Direct mapping Address Space Decoder */ + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; + + /* Clear All Local Bus Status */ + tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; + /* Enable All Local Bus Interrupts */ + tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; + /* Clear All PCI Status Error */ + tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; + /* Enable All PCI Status Error Interrupts */ + tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; + + /* PCIC Int => IRC IRQ10 */ + tx3927_pcicptr->il = TX3927_IR_PCI; + /* Target Control (per errata) */ + tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; + + /* Enable Bus Arbiter */ + tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; + + tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + } +#endif /* CONFIG_PCI */ + + /* PIO */ + /* PIO[15:12] connected to LEDs */ + __raw_writel(0x0000f000, &tx3927_pioptr->dir); + __raw_writel(0, &tx3927_pioptr->maskcpu); + __raw_writel(0, &tx3927_pioptr->maskext); + txx9_gpio_init(TX3927_PIO_REG, 0, 16); + gpio_request(11, "dipsw1"); + gpio_request(10, "dipsw2"); + { + unsigned int conf; + + conf = read_c0_conf(); + if (!(conf & TX39_CONF_ICE)) + printk("TX3927 I-Cache disabled.\n"); + if (!(conf & TX39_CONF_DCE)) + printk("TX3927 D-Cache disabled.\n"); + else if (!(conf & TX39_CONF_WBON)) + printk("TX3927 D-Cache WriteThrough.\n"); + else if (!(conf & TX39_CONF_CWFON)) + printk("TX3927 D-Cache WriteBack.\n"); + else + printk("TX3927 D-Cache WriteBack (CWF) .\n"); + } +} + +/* This trick makes rtc-ds1742 driver usable as is. */ +unsigned long __swizzle_addr_b(unsigned long port) +{ + if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) + return port; + port = (port & 0xffff0000) | (port & 0x7fff << 1); +#ifdef __BIG_ENDIAN + return port; +#else + return port | 1; +#endif +} +EXPORT_SYMBOL(__swizzle_addr_b); + +static int __init jmr3927_rtc_init(void) +{ + static struct resource __initdata res = { + .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, + .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev; + dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(jmr3927_rtc_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init jmr3927_wdt_init(void) +{ + return txx9_wdt_init(TX3927_TMR_REG(2)); +} +device_initcall(jmr3927_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "imbus_clk")) + return (struct clk *)JMR3927_IMCLK; + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4927/Makefile b/arch/mips/txx9/rbtx4927/Makefile new file mode 100644 index 000000000000..f3e1f597b4f1 --- /dev/null +++ b/arch/mips/txx9/rbtx4927/Makefile @@ -0,0 +1,3 @@ +obj-y += prom.o setup.o irq.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c new file mode 100644 index 000000000000..936e50e91d95 --- /dev/null +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -0,0 +1,214 @@ +/* + * Toshiba RBTX4927 specific interrupt handlers + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* +IRQ Device +00 RBTX4927-ISA/00 +01 RBTX4927-ISA/01 PS2/Keyboard +02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) +03 RBTX4927-ISA/03 +04 RBTX4927-ISA/04 +05 RBTX4927-ISA/05 +06 RBTX4927-ISA/06 +07 RBTX4927-ISA/07 +08 RBTX4927-ISA/08 +09 RBTX4927-ISA/09 +10 RBTX4927-ISA/10 +11 RBTX4927-ISA/11 +12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) +13 RBTX4927-ISA/13 +14 RBTX4927-ISA/14 IDE +15 RBTX4927-ISA/15 + +16 TX4927-CP0/00 Software 0 +17 TX4927-CP0/01 Software 1 +18 TX4927-CP0/02 Cascade TX4927-CP0 +19 TX4927-CP0/03 Multiplexed -- do not use +20 TX4927-CP0/04 Multiplexed -- do not use +21 TX4927-CP0/05 Multiplexed -- do not use +22 TX4927-CP0/06 Multiplexed -- do not use +23 TX4927-CP0/07 CPU TIMER + +24 TX4927-PIC/00 +25 TX4927-PIC/01 +26 TX4927-PIC/02 +27 TX4927-PIC/03 Cascade RBTX4927-IOC +28 TX4927-PIC/04 +29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet +30 TX4927-PIC/06 +31 TX4927-PIC/07 +32 TX4927-PIC/08 TX4927 SerialIO Channel 0 +33 TX4927-PIC/09 TX4927 SerialIO Channel 1 +34 TX4927-PIC/10 +35 TX4927-PIC/11 +36 TX4927-PIC/12 +37 TX4927-PIC/13 +38 TX4927-PIC/14 +39 TX4927-PIC/15 +40 TX4927-PIC/16 TX4927 PCI PCI-C +41 TX4927-PIC/17 +42 TX4927-PIC/18 +43 TX4927-PIC/19 +44 TX4927-PIC/20 +45 TX4927-PIC/21 +46 TX4927-PIC/22 TX4927 PCI PCI-ERR +47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) +48 TX4927-PIC/24 +49 TX4927-PIC/25 +50 TX4927-PIC/26 +51 TX4927-PIC/27 +52 TX4927-PIC/28 +53 TX4927-PIC/29 +54 TX4927-PIC/30 +55 TX4927-PIC/31 + +56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] +57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] +58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] +59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] +60 RBTX4927-IOC/04 +61 RBTX4927-IOC/05 +62 RBTX4927-IOC/06 +63 RBTX4927-IOC/07 + +NOTES: +SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 +SouthBridge/ISA/pin=0 no pci irq used by this device +SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 +SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 +SouthBridge/PMC/pin=0 no pci irq used by this device +SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 +SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) +JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 +*/ + +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#endif +#include + +#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ + +#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC +#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) + +extern int tx4927_using_backplane; + +static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); + +#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" +static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { + .name = TOSHIBA_RBTX4927_IOC_NAME, + .ack = toshiba_rbtx4927_irq_ioc_disable, + .mask = toshiba_rbtx4927_irq_ioc_disable, + .mask_ack = toshiba_rbtx4927_irq_ioc_disable, + .unmask = toshiba_rbtx4927_irq_ioc_enable, +}; +#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL +#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL + +int toshiba_rbtx4927_irq_nested(int sw_irq) +{ + u8 level3; + + level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + if (level3) { + sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && + tx4927_using_backplane) { + int irq = i8259_irq(); + if (irq >= 0) + sw_irq = irq; + } +#endif + } + return (sw_irq); +} + +static struct irqaction toshiba_rbtx4927_irq_ioc_action = { + .handler = no_action, + .flags = IRQF_SHARED, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4927_IOC_NAME +}; + +static void __init toshiba_rbtx4927_irq_ioc_init(void) +{ + int i; + + for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) + set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, + handle_level_irq); + + setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, + &toshiba_rbtx4927_irq_ioc_action); +} + +static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) +{ + unsigned char v; + + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); +} + +static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) +{ + unsigned char v; + + v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); + mmiowb(); +} + +void __init arch_init_irq(void) +{ + extern void tx4927_irq_init(void); + + tx4927_irq_init(); + toshiba_rbtx4927_irq_ioc_init(); +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (tx4927_using_backplane) + init_i8259_irqs(); +#endif + /* Onboard 10M Ether: High Active */ + set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); +} diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c new file mode 100644 index 000000000000..0020bbee838b --- /dev/null +++ b/arch/mips/txx9/rbtx4927/prom.c @@ -0,0 +1,91 @@ +/* + * rbtx4927 specific prom routines + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; /* Always ignore the "-c" at argv[0] */ + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4927_get_mem_size(void); + extern char* toshiba_name; + int msize; + + prom_init_cmdline(); + + if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { + mips_machtype = MACH_TOSHIBA_RBTX4927; + toshiba_name = "TX4927"; + } else { + mips_machtype = MACH_TOSHIBA_RBTX4937; + toshiba_name = "TX4937"; + } + + msize = tx4927_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4927/RBTX4937"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c new file mode 100644 index 000000000000..df1b6e99b666 --- /dev/null +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -0,0 +1,703 @@ +/* + * Toshiba rbtx4927 specific setup + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2002 MontaVista Software Inc. + * Author: Michael Pruznick, michael_pruznick@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Manish Lachwani, mlachwani@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#endif +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif + +/* These functions are used for rebooting or halting the machine*/ +extern void toshiba_rbtx4927_restart(char *command); +extern void toshiba_rbtx4927_halt(void); +extern void toshiba_rbtx4927_power_off(void); + +int tx4927_using_backplane = 0; + +extern void toshiba_rbtx4927_irq_setup(void); + +char *prom_getcmdline(void); + +#ifdef CONFIG_PCI +#undef TX4927_SUPPORT_COMMAND_IO +#undef TX4927_SUPPORT_PCI_66 +int tx4927_cpu_clock = 100000000; /* 100MHz */ +unsigned long mips_pci_io_base; +unsigned long mips_pci_io_size; +unsigned long mips_pci_mem_base; +unsigned long mips_pci_mem_size; +/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ +unsigned long mips_pci_io_pciaddr = 0; +unsigned long mips_memory_upper; +static int tx4927_ccfg_toeon = 1; +static int tx4927_pcic_trdyto = 0; /* default: disabled */ +unsigned long tx4927_ce_base[8]; +int tx4927_pci66 = 0; /* 0:auto */ +#endif + +char *toshiba_name = ""; + +#ifdef CONFIG_PCI +extern struct pci_controller tx4927_controller; + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = (void *)hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, byte, u8 *) +EARLY_PCI_OP(read, dword, u32 *) +EARLY_PCI_OP(write, byte, u8) +EARLY_PCI_OP(write, dword, u32) + +static int __init tx4927_pcibios_init(void) +{ + unsigned int id; + u32 pci_devfn; + int devfn_start = 0; + int devfn_stop = 0xff; + int busno = 0; /* One bus on the Toshiba */ + struct pci_controller *hose = &tx4927_controller; + + for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { + early_read_config_dword(hose, busno, busno, pci_devfn, + PCI_VENDOR_ID, &id); + + if (id == 0xffffffff) { + continue; + } + + if (id == 0x94601055) { + u8 v08_64; + u32 v32_b0; + u8 v08_e1; + + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x64, &v08_64); + early_read_config_dword(hose, busno, busno, + pci_devfn, 0xb0, &v32_b0); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0xe1, &v08_e1); + + /* serial irq control */ + v08_64 = 0xd0; + + /* serial irq pin */ + v32_b0 |= 0x00010000; + + /* ide irq on isa14 */ + v08_e1 &= 0xf0; + v08_e1 |= 0x0d; + + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x64, v08_64); + early_write_config_dword(hose, busno, busno, + pci_devfn, 0xb0, v32_b0); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0xe1, v08_e1); + } + + if (id == 0x91301055) { + u8 v08_04; + u8 v08_09; + u8 v08_41; + u8 v08_43; + u8 v08_5c; + + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x04, &v08_04); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x09, &v08_09); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x41, &v08_41); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x43, &v08_43); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x5c, &v08_5c); + + /* enable ide master/io */ + v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* enable ide native mode */ + v08_09 |= 0x05; + + /* enable primary ide */ + v08_41 |= 0x80; + + /* enable secondary ide */ + v08_43 |= 0x80; + + /* + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + * + * This line of code is intended to provide the user with a work + * around solution to the anomalies cited in SMSC's anomaly sheet + * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". + * + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + */ + v08_5c |= 0x01; + + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x5c, v08_5c); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x04, v08_04); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x09, v08_09); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x41, v08_41); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x43, v08_43); + } + + } + + register_pci_controller(&tx4927_controller); + return 0; +} + +arch_initcall(tx4927_pcibios_init); + +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +void __init tx4927_pci_setup(void) +{ + static int called = 0; + extern unsigned int tx4927_get_mem_size(void); + + mips_memory_upper = tx4927_get_mem_size() << 20; + mips_memory_upper += KSEG0; + mips_pci_io_base = TX4927_PCIIO; + mips_pci_io_size = TX4927_PCIIO_SIZE; + mips_pci_mem_base = TX4927_PCIMEM; + mips_pci_mem_size = TX4927_PCIMEM_SIZE; + + if (!called) { + printk + ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + toshiba_name, + (unsigned short) (tx4927_pcicptr->pciid >> 16), + (unsigned short) (tx4927_pcicptr->pciid & 0xffff), + (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), + (!(tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIXARB)) ? "External" : + "Internal"); + called = 1; + } + printk("%s PCIC --%s PCICLK:", toshiba_name, + (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); + if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { + int pciclk = 0; + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { + case TX4937_CCFG_PCIDIVMODE_4: + pciclk = tx4927_cpu_clock / 4; + break; + case TX4937_CCFG_PCIDIVMODE_4_5: + pciclk = tx4927_cpu_clock * 2 / 9; + break; + case TX4937_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4937_CCFG_PCIDIVMODE_5_5: + pciclk = tx4927_cpu_clock * 2 / 11; + break; + case TX4937_CCFG_PCIDIVMODE_8: + pciclk = tx4927_cpu_clock / 8; + break; + case TX4937_CCFG_PCIDIVMODE_9: + pciclk = tx4927_cpu_clock / 9; + break; + case TX4937_CCFG_PCIDIVMODE_10: + pciclk = tx4927_cpu_clock / 10; + break; + case TX4937_CCFG_PCIDIVMODE_11: + pciclk = tx4927_cpu_clock / 11; + break; + } + + else + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + pciclk = tx4927_cpu_clock * 2 / 5; + break; + case TX4927_CCFG_PCIDIVMODE_3: + pciclk = tx4927_cpu_clock / 3; + break; + case TX4927_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4927_CCFG_PCIDIVMODE_6: + pciclk = tx4927_cpu_clock / 6; + break; + } + + printk("Internal(%dMHz)", pciclk / 1000000); + } else + printk("External"); + printk("\n"); + + /* GB->PCI mappings */ + tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; + tx4927_pcicptr->g2piogbase = mips_pci_io_base | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PIOGBASE_ECHG +#else + TX4927_PCIC_G2PIOGBASE_BSDIS +#endif + ; + + tx4927_pcicptr->g2piopbase = 0; + + tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; + tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PMnGBASE_ECHG +#else + TX4927_PCIC_G2PMnGBASE_BSDIS +#endif + ; + tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; + + tx4927_pcicptr->g2pmmask[1] = 0; + tx4927_pcicptr->g2pmgbase[1] = 0; + tx4927_pcicptr->g2pmpbase[1] = 0; + tx4927_pcicptr->g2pmmask[2] = 0; + tx4927_pcicptr->g2pmgbase[2] = 0; + tx4927_pcicptr->g2pmpbase[2] = 0; + + + /* PCI->GB mappings (I/O 256B) */ + tx4927_pcicptr->p2giopbase = 0; /* 256B */ + + /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ + tx4927_pcicptr->p2gm0plbase = 0; + tx4927_pcicptr->p2gm0pubase = 0; + tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4927_PCIC_P2GMnGBASE_TECHG +#else + TX4927_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + + /* PCI->GB mappings (MEM 16MB) -not used */ + tx4927_pcicptr->p2gm1plbase = 0xffffffff; + tx4927_pcicptr->p2gm1pubase = 0xffffffff; + tx4927_pcicptr->p2gmgbase[1] = 0; + + /* PCI->GB mappings (MEM 1MB) -not used */ + tx4927_pcicptr->p2gm2pbase = 0xffffffff; + tx4927_pcicptr->p2gmgbase[2] = 0; + + + /* Enable Initiator Memory 0 Space, I/O Space, Config */ + tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; + tx4927_pcicptr->pciccfg |= + TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | + TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; + + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + tx4927_pcicptr->pcicfg1 = 0; + + if (tx4927_pcic_trdyto >= 0) { + tx4927_pcicptr->g2ptocnt &= ~0xff; + tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); + } + + /* Clear All Local Bus Status */ + tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + tx4927_pcicptr->pcistatus = + (tx4927_pcicptr->pcistatus & 0x0000ffff) | + (TX4927_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; + + /* PCIC Int => IRC IRQ16 */ + tx4927_pcicptr->pcicfg2 = + (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; + + if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { + /* XXX */ + } else { + /* Reset Bus Arbiter */ + tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; + /* Enable Bus Arbiter */ + tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; + } + + tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} +#endif /* CONFIG_PCI */ + +static void __noreturn wait_forever(void) +{ + while (1) + if (cpu_wait) + (*cpu_wait)(); +} + +void toshiba_rbtx4927_restart(char *command) +{ + printk(KERN_NOTICE "System Rebooting...\n"); + + /* enable the s/w reset register */ + writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); + + /* wait for enable to be seen */ + while ((readb(RBTX4927_SW_RESET_ENABLE) & + RBTX4927_SW_RESET_ENABLE_SET) == 0x00); + + /* do a s/w reset */ + writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); + + /* do something passive while waiting for reset */ + local_irq_disable(); + wait_forever(); + /* no return */ +} + +void toshiba_rbtx4927_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + wait_forever(); + /* no return */ +} + +void toshiba_rbtx4927_power_off(void) +{ + toshiba_rbtx4927_halt(); + /* no return */ +} + +void __init plat_mem_setup(void) +{ + int i; + u32 cp0_config; + char *argptr; + + printk("CPU is %s\n", toshiba_name); + + /* f/w leaves this on at startup */ + clear_c0_status(ST0_ERL); + + /* enable caches -- HCP5 does this, pmon does not */ + cp0_config = read_c0_config(); + cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); + write_c0_config(cp0_config); + + set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); + + ioport_resource.end = 0xffffffff; + iomem_resource.end = 0xffffffff; + + _machine_restart = toshiba_rbtx4927_restart; + _machine_halt = toshiba_rbtx4927_halt; + pm_power_off = toshiba_rbtx4927_power_off; + + for (i = 0; i < TX4927_NR_TMR; i++) + txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); + +#ifdef CONFIG_PCI + + /* PCIC */ + /* + * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. + * + * For TX4927: + * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). + * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) + * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) + * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) + * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) + * i.e. S9[3]: ON (83MHz), OFF (100MHz) + * + * For TX4937: + * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) + * PCIDIVMODE[10] is 0. + * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) + * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) + * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) + * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) + * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) + * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) + * + */ + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + switch ((unsigned long)tx4927_ccfgptr-> + ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { + case TX4937_CCFG_PCIDIVMODE_8: + case TX4937_CCFG_PCIDIVMODE_4: + tx4927_cpu_clock = 266666666; /* 266MHz */ + break; + case TX4937_CCFG_PCIDIVMODE_9: + case TX4937_CCFG_PCIDIVMODE_4_5: + tx4927_cpu_clock = 300000000; /* 300MHz */ + break; + default: + tx4927_cpu_clock = 333333333; /* 333MHz */ + } + else + switch ((unsigned long)tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + case TX4927_CCFG_PCIDIVMODE_5: + tx4927_cpu_clock = 166666666; /* 166MHz */ + break; + default: + tx4927_cpu_clock = 200000000; /* 200MHz */ + } + + /* CCFG */ + /* do reset on watchdog */ + tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; + /* enable Timeout BusError */ + if (tx4927_ccfg_toeon) + tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; + + tx4927_pci_setup(); + if (tx4927_using_backplane == 1) + printk("backplane board IS installed\n"); + else + printk("No Backplane \n"); + + /* this is on ISA bus behind PCI bus, so need PCI up first */ +#ifdef CONFIG_TOSHIBA_FPCIB0 + if (tx4927_using_backplane) { + smsc_fdc37m81x_init(0x3f0); + smsc_fdc37m81x_config_beg(); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + smsc_fdc37m81x_config_end(); + } +#endif +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = TX4927_IRQ_PIC_BEG + 8 + i; + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif +#endif + +#ifdef CONFIG_ROOT_NFS + argptr = prom_getcmdline(); + if (strstr(argptr, "root=") == NULL) { + strcat(argptr, " root=/dev/nfs rw"); + } +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = tx4927_cpu_clock / 2; + if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) + txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, + TXX9_IRQ_BASE + 17, + 50000000); +} + +static int __init toshiba_rbtx4927_rtc_init(void) +{ + static struct resource __initdata res = { + .start = 0x1c010000, + .end = 0x1c010000 + 0x800 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("rtc-ds1742", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(toshiba_rbtx4927_rtc_init); + +static int __init rbtx4927_ne_init(void) +{ + static struct resource __initdata res[] = { + { + .start = RBTX4927_RTL_8019_BASE, + .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, { + .start = RBTX4927_RTL_8019_IRQ, + .flags = IORESOURCE_IRQ, + } + }; + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(rbtx4927_ne_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init rbtx4927_wdt_init(void) +{ + return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); +} +device_initcall(rbtx4927_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "imbus_clk")) + return (struct clk *)50000000; + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile new file mode 100644 index 000000000000..9dcc52ae5b9d --- /dev/null +++ b/arch/mips/txx9/rbtx4938/Makefile @@ -0,0 +1,3 @@ +obj-y += prom.o setup.o irq.o spi_eeprom.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c new file mode 100644 index 000000000000..f4984820251a --- /dev/null +++ b/arch/mips/txx9/rbtx4938/irq.c @@ -0,0 +1,159 @@ +/* + * Toshiba RBTX4938 specific interrupt handlers + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +/* +IRQ Device + +16 TX4938-CP0/00 Software 0 +17 TX4938-CP0/01 Software 1 +18 TX4938-CP0/02 Cascade TX4938-CP0 +19 TX4938-CP0/03 Multiplexed -- do not use +20 TX4938-CP0/04 Multiplexed -- do not use +21 TX4938-CP0/05 Multiplexed -- do not use +22 TX4938-CP0/06 Multiplexed -- do not use +23 TX4938-CP0/07 CPU TIMER + +24 TX4938-PIC/00 +25 TX4938-PIC/01 +26 TX4938-PIC/02 Cascade RBTX4938-IOC +27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet +28 TX4938-PIC/04 +29 TX4938-PIC/05 TX4938 ETH1 +30 TX4938-PIC/06 TX4938 ETH0 +31 TX4938-PIC/07 +32 TX4938-PIC/08 TX4938 SIO 0 +33 TX4938-PIC/09 TX4938 SIO 1 +34 TX4938-PIC/10 TX4938 DMA0 +35 TX4938-PIC/11 TX4938 DMA1 +36 TX4938-PIC/12 TX4938 DMA2 +37 TX4938-PIC/13 TX4938 DMA3 +38 TX4938-PIC/14 +39 TX4938-PIC/15 +40 TX4938-PIC/16 TX4938 PCIC +41 TX4938-PIC/17 TX4938 TMR0 +42 TX4938-PIC/18 TX4938 TMR1 +43 TX4938-PIC/19 TX4938 TMR2 +44 TX4938-PIC/20 +45 TX4938-PIC/21 +46 TX4938-PIC/22 TX4938 PCIERR +47 TX4938-PIC/23 +48 TX4938-PIC/24 +49 TX4938-PIC/25 +50 TX4938-PIC/26 +51 TX4938-PIC/27 +52 TX4938-PIC/28 +53 TX4938-PIC/29 +54 TX4938-PIC/30 +55 TX4938-PIC/31 TX4938 SPI + +56 RBTX4938-IOC/00 PCI-D +57 RBTX4938-IOC/01 PCI-C +58 RBTX4938-IOC/02 PCI-B +59 RBTX4938-IOC/03 PCI-A +60 RBTX4938-IOC/04 RTC +61 RBTX4938-IOC/05 ATA +62 RBTX4938-IOC/06 MODEM +63 RBTX4938-IOC/07 SWINT +*/ +#include +#include +#include + +static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); + +#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" +static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { + .name = TOSHIBA_RBTX4938_IOC_NAME, + .ack = toshiba_rbtx4938_irq_ioc_disable, + .mask = toshiba_rbtx4938_irq_ioc_disable, + .mask_ack = toshiba_rbtx4938_irq_ioc_disable, + .unmask = toshiba_rbtx4938_irq_ioc_enable, +}; + +int +toshiba_rbtx4938_irq_nested(int sw_irq) +{ + u8 level3; + + level3 = readb(rbtx4938_imstat_addr); + if (level3) + /* must use fls so onboard ATA has priority */ + sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; + + return sw_irq; +} + +static struct irqaction toshiba_rbtx4938_irq_ioc_action = { + .handler = no_action, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = TOSHIBA_RBTX4938_IOC_NAME, +}; + +/**********************************************************************************/ +/* Functions for ioc */ +/**********************************************************************************/ +static void __init +toshiba_rbtx4938_irq_ioc_init(void) +{ + int i; + + for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) + set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, + handle_level_irq); + + setup_irq(RBTX4938_IRQ_IOCINT, + &toshiba_rbtx4938_irq_ioc_action); +} + +static void +toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) +{ + unsigned char v; + + v = readb(rbtx4938_imask_addr); + v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + writeb(v, rbtx4938_imask_addr); + mmiowb(); +} + +static void +toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) +{ + unsigned char v; + + v = readb(rbtx4938_imask_addr); + v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + writeb(v, rbtx4938_imask_addr); + mmiowb(); +} + +void __init arch_init_irq(void) +{ + extern void tx4938_irq_init(void); + + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + /* mask all IOC interrupts */ + writeb(0, rbtx4938_imask_addr); + + /* clear SoftInt interrupts */ + writeb(0, rbtx4938_softint_addr); + tx4938_irq_init(); + toshiba_rbtx4938_irq_ioc_init(); + /* Onboard 10M Ether: High Active */ + set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); +} diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c new file mode 100644 index 000000000000..134fcc2dc7d2 --- /dev/null +++ b/arch/mips/txx9/rbtx4938/prom.c @@ -0,0 +1,72 @@ +/* + * rbtx4938 specific prom routines + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ + +#include +#include +#include +#include + +#include +#include +#include + +void __init prom_init_cmdline(void) +{ + int argc = (int) fw_arg0; + char **argv = (char **) fw_arg1; + int i; + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + extern int tx4938_get_mem_size(void); + int msize; +#ifndef CONFIG_TX4938_NAND_BOOT + prom_init_cmdline(); +#endif + + msize = tx4938_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); + + return; +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ + return; +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4938"; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c new file mode 100644 index 000000000000..bbd572c9675b --- /dev/null +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -0,0 +1,1122 @@ +/* + * Setup pointers to hardware-dependent routines. + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SERIAL_TXX9 +#include +#endif +#include +#include +#include + +extern char * __init prom_getcmdline(void); +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); + +/* These functions are used for rebooting or halting the machine*/ +extern void rbtx4938_machine_restart(char *command); +extern void rbtx4938_machine_halt(void); +extern void rbtx4938_machine_power_off(void); + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; + +unsigned long rbtx4938_ce_base[8]; +unsigned long rbtx4938_ce_size[8]; +int txboard_pci66_mode; +static int tx4938_pcic_trdyto; /* default: disabled */ +static int tx4938_pcic_retryto; /* default: disabled */ +static int tx4938_ccfg_toeon = 1; + +struct tx4938_pcic_reg *pcicptrs[4] = { + tx4938_pcicptr /* default setting for TX4938 */ +}; + +static struct { + unsigned long base; + unsigned long size; +} phys_regions[16] __initdata; +static int num_phys_regions __initdata; + +#define PHYS_REGION_MINSIZE 0x10000 + +void rbtx4938_machine_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + local_irq_disable(); + + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void rbtx4938_machine_power_off(void) +{ + rbtx4938_machine_halt(); + /* no return */ +} + +void rbtx4938_machine_restart(char *command) +{ + local_irq_disable(); + + printk("Rebooting..."); + writeb(1, rbtx4938_softresetlock_addr); + writeb(1, rbtx4938_sfvol_addr); + writeb(1, rbtx4938_softreset_addr); + while(1) + ; +} + +void __init +txboard_add_phys_region(unsigned long base, unsigned long size) +{ + if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { + printk("phys_region overflow\n"); + return; + } + phys_regions[num_phys_regions].base = base; + phys_regions[num_phys_regions].size = size; + num_phys_regions++; +} +unsigned long __init +txboard_find_free_phys_region(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + int i; + + for (base = begin / size * size; base < end; base += size) { + for (i = 0; i < num_phys_regions; i++) { + if (phys_regions[i].size && + base <= phys_regions[i].base + (phys_regions[i].size - 1) && + base + (size - 1) >= phys_regions[i].base) + break; + } + if (i == num_phys_regions) + return base; + } + return 0; +} +unsigned long __init +txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, + unsigned long *size) +{ + unsigned long sz, base; + for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { + base = txboard_find_free_phys_region(begin, end, sz); + if (base) { + *size = sz; + return base; + } + } + return 0; +} +unsigned long __init +txboard_request_phys_region_range(unsigned long begin, unsigned long end, + unsigned long size) +{ + unsigned long base; + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region(unsigned long size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region(begin, end, size); + if (base) + txboard_add_phys_region(base, size); + return base; +} +unsigned long __init +txboard_request_phys_region_shrink(unsigned long *size) +{ + unsigned long base; + unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ + base = txboard_find_free_phys_region_shrink(begin, end, size); + if (base) + txboard_add_phys_region(base, *size); + return base; +} + +#ifdef CONFIG_PCI +void __init +tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, + struct pci_controller *channel, + unsigned long pci_io_base, + int extarb) +{ + int i; + + /* Disable All Initiator Space */ + pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| + TX4938_PCIC_PCICCFG_G2PMEN(1)| + TX4938_PCIC_PCICCFG_G2PMEN(2)| + TX4938_PCIC_PCICCFG_G2PIOEN); + + /* GB->PCI mappings */ + pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; + pcicptr->g2piogbase = pci_io_base | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PIOGBASE_ECHG +#else + TX4938_PCIC_G2PIOGBASE_BSDIS +#endif + ; + pcicptr->g2piopbase = 0; + for (i = 0; i < 3; i++) { + pcicptr->g2pmmask[i] = 0; + pcicptr->g2pmgbase[i] = 0; + pcicptr->g2pmpbase[i] = 0; + } + if (channel->mem_resource->end) { + pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; + pcicptr->g2pmgbase[0] = channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4938_PCIC_G2PMnGBASE_ECHG +#else + TX4938_PCIC_G2PMnGBASE_BSDIS +#endif + ; + pcicptr->g2pmpbase[0] = channel->mem_resource->start; + } + /* PCI->GB mappings (I/O 256B) */ + pcicptr->p2giopbase = 0; /* 256B */ + pcicptr->p2giogbase = 0; + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + pcicptr->p2gm0plbase = 0; + pcicptr->p2gm0pubase = 0; + pcicptr->p2gmgbase[0] = 0 | + TX4938_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4938_PCIC_P2GMnGBASE_TECHG +#else + TX4938_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + /* PCI->GB mappings (MEM 16MB) */ + pcicptr->p2gm1plbase = 0xffffffff; + pcicptr->p2gm1pubase = 0xffffffff; + pcicptr->p2gmgbase[1] = 0; + /* PCI->GB mappings (MEM 1MB) */ + pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ + pcicptr->p2gmgbase[2] = 0; + + pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; + /* Enable Initiator Config */ + pcicptr->pciccfg |= + TX4938_PCIC_PCICCFG_ICAEN | + TX4938_PCIC_PCICCFG_TCAR; + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + pcicptr->pcicfg1 = 0; + + pcicptr->g2ptocnt &= ~0xffff; + + if (tx4938_pcic_trdyto >= 0) { + pcicptr->g2ptocnt &= ~0xff; + pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); + } + + if (tx4938_pcic_retryto >= 0) { + pcicptr->g2ptocnt &= ~0xff00; + pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); + } + + /* Clear All Local Bus Status */ + pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + pcicptr->pcistatus = + (pcicptr->pcistatus & 0x0000ffff) | + (TX4938_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; + + if (!extarb) { + /* Reset Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; + pcicptr->pbabm = 0; + /* Enable Bus Arbiter */ + pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; + } + + /* PCIC Int => IRC IRQ16 */ + pcicptr->pcicfg2 = + (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; + + pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; +} + +int __init +tx4938_report_pciclk(void) +{ + unsigned long pcode = TX4938_REV_PCODE(); + int pciclk = 0; + printk("TX%lx PCIC --%s PCICLK:", + pcode, + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + + switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%dMHz)", pciclk / 1000000); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) +{ + pcicptrs[ch] = pcicptr; +} + +struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) +{ + return pcicptrs[ch]; +} + +static struct pci_dev *fake_pci_dev(struct pci_controller *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.sysdata = bus.sysdata = hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + bus.parent = NULL; + dev.bus = &bus; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_controller *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, word, u16 *) + +int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int devfn_start = 0; + int devfn_stop = 0xff; + int cap66 = -1; + u16 stat; + + printk("PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn=devfn_start; pci_devfn 0; +} + +int __init +tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; + /* Double PCICLK (if possible) */ + if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = + tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfgptr->ccfg = + (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) + | pcidivmode; + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)tx4938_ccfgptr->ccfg); + } else { + pciclk = -1; + } + return pciclk; +} + +extern struct pci_controller tx4938_pci_controller[]; +static int __init tx4938_pcibios_init(void) +{ + unsigned long mem_base[2]; + unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ + unsigned long io_base[2]; + unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ + /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ + int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); + + PCIBIOS_MIN_IO = 0x00001000UL; + + mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); + io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); + + printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + (unsigned short)(tx4938_pcicptr->pciid >> 16), + (unsigned short)(tx4938_pcicptr->pciid & 0xffff), + (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), + extarb ? "External" : "Internal"); + + /* setup PCI area */ + tx4938_pci_controller[0].io_resource->start = io_base[0]; + tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; + tx4938_pci_controller[0].mem_resource->start = mem_base[0]; + tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; + + set_tx4938_pcicptr(0, tx4938_pcicptr); + + register_pci_controller(&tx4938_pci_controller[0]); + + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { + printk("TX4938_CCFG_PCI66 already configured\n"); + txboard_pci66_mode = -1; /* already configured */ + } + + /* Reset PCI Bus */ + writeb(0, rbtx4938_pcireset_addr); + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + if (txboard_pci66_mode > 0) + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + writeb(1, rbtx4938_pcireset_addr); + mmiowb(); + tx4938_report_pcic_status1(tx4938_pcicptr); + + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + if (txboard_pci66_mode == 0 && + txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { + /* Reset PCI Bus */ + writeb(0, rbtx4938_pcireset_addr); + /* Reset PCIC */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + writeb(1, rbtx4938_pcireset_addr); + mmiowb(); + /* Reinitialize PCIC */ + tx4938_report_pciclk(); + tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + } + + mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); + io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); + /* Reset PCIC1 */ + tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; + /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; + else + tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; + mdelay(10); + /* clear PCIC1 reset */ + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + tx4938_report_pcic_status1(tx4938_pcic1ptr); + + printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", + (unsigned short)(tx4938_pcic1ptr->pciid >> 16), + (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), + (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); + printk("%s PCICLK:%dMHz\n", + (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", + txx9_gbus_clock / + ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / + 1000000); + + /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ + tx4938_pci_controller[1].io_resource->start = + io_base[1] - io_base[0]; + tx4938_pci_controller[1].io_resource->end = + io_base[1] - io_base[0] + io_size[1] - 1; + tx4938_pci_controller[1].mem_resource->start = mem_base[1]; + tx4938_pci_controller[1].mem_resource->end = + mem_base[1] + mem_size[1] - 1; + set_tx4938_pcicptr(1, tx4938_pcic1ptr); + + register_pci_controller(&tx4938_pci_controller[1]); + + tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); + + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(KSEG1 + io_base[0]); + + return 0; +} + +arch_initcall(tx4938_pcibios_init); + +#endif /* CONFIG_PCI */ + +/* SPI support */ + +/* chip select for SPI devices */ +#define SEEPROM1_CS 7 /* PIO7 */ +#define SEEPROM2_CS 0 /* IOC */ +#define SEEPROM3_CS 1 /* IOC */ +#define SRTC_CS 2 /* IOC */ + +#ifdef CONFIG_PCI +static int __init rbtx4938_ethaddr_init(void) +{ + unsigned char dat[17]; + unsigned char sum; + int i; + + /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ + if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) { + printk(KERN_ERR "seeprom: read error.\n"); + return -ENODEV; + } else { + if (strcmp(dat, "MAC") != 0) + printk(KERN_WARNING "seeprom: bad signature.\n"); + for (i = 0, sum = 0; i < sizeof(dat); i++) + sum += dat[i]; + if (sum) + printk(KERN_WARNING "seeprom: bad checksum.\n"); + } + for (i = 0; i < 2; i++) { + unsigned int id = + TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); + struct platform_device *pdev; + if (!(tx4938_ccfgptr->pcfg & + (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) + continue; + pdev = platform_device_alloc("tc35815-mac", id); + if (!pdev || + platform_device_add_data(pdev, &dat[4 + 6 * i], 6) || + platform_device_add(pdev)) + platform_device_put(pdev); + } + return 0; +} +device_initcall(rbtx4938_ethaddr_init); +#endif /* CONFIG_PCI */ + +static void __init rbtx4938_spi_setup(void) +{ + /* set SPI_SEL */ + tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; +} + +static struct resource rbtx4938_fpga_resource; + +static char pcode_str[8]; +static struct resource tx4938_reg_resource = { + .start = TX4938_REG_BASE, + .end = TX4938_REG_BASE + TX4938_REG_SIZE, + .name = pcode_str, + .flags = IORESOURCE_MEM +}; + +void __init tx4938_board_setup(void) +{ + int i; + unsigned long divmode; + int cpuclk = 0; + unsigned long pcode = TX4938_REV_PCODE(); + + ioport_resource.start = 0x1000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x1000; + iomem_resource.end = 0xffffffff; /* expand to 4GB */ + + sprintf(pcode_str, "TX%lx", pcode); + /* SDRAMC,EBUSC are configured by PROM */ + for (i = 0; i < 8; i++) { + if (!(tx4938_ebuscptr->cr[i] & 0x8)) + continue; /* disabled */ + rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); + txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); + } + + /* clocks */ + if (txx9_master_clock) { + /* calculate gbus_clock and cpu_clock_freq from master_clock */ + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = txx9_master_clock * 4; break; + default: + txx9_gbus_clock = txx9_master_clock; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + cpuclk = txx9_gbus_clock * 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + cpuclk = txx9_gbus_clock * 5 / 2; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + cpuclk = txx9_gbus_clock * 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + cpuclk = txx9_gbus_clock * 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + cpuclk = txx9_gbus_clock * 9 / 2; break; + } + txx9_cpu_clock = cpuclk; + } else { + if (txx9_cpu_clock == 0) { + txx9_cpu_clock = 300000000; /* 300MHz */ + } + /* calculate gbus_clock and master_clock from cpu_clock_freq */ + cpuclk = txx9_cpu_clock; + divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + txx9_gbus_clock = cpuclk / 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + txx9_gbus_clock = cpuclk * 2 / 5; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + txx9_gbus_clock = cpuclk / 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + txx9_gbus_clock = cpuclk / 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = cpuclk * 2 / 9; break; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_master_clock = txx9_gbus_clock / 4; break; + default: + txx9_master_clock = txx9_gbus_clock; + } + } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; + + /* CCFG */ + /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; + /* do reset on watchdog */ + tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; + /* clear PCIC1 reset */ + if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) + tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + + /* enable Timeout BusError */ + if (tx4938_ccfg_toeon) + tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; + + /* DMA selection */ + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; + + /* Use external clock for external arbiter */ + if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; + + printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", + pcode_str, + cpuclk / 1000000, txx9_master_clock / 1000000, + (unsigned long)tx4938_ccfgptr->crir, + tx4938_ccfgptr->ccfg, + tx4938_ccfgptr->pcfg); + + printk("%s SDRAMC --", pcode_str); + for (i = 0; i < 4; i++) { + unsigned long long cr = tx4938_sdramcptr->cr[i]; + unsigned long ram_base, ram_size; + if (!((unsigned long)cr & 0x00000400)) + continue; /* disabled */ + ram_base = (unsigned long)(cr >> 49) << 21; + ram_size = ((unsigned long)(cr >> 33) + 1) << 21; + if (ram_base >= 0x20000000) + continue; /* high memory (ignore) */ + printk(" CR%d:%016Lx", i, cr); + txboard_add_phys_region(ram_base, ram_size); + } + printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); + + /* SRAM */ + if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { + unsigned int size = 0x800; + unsigned long base = + (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); + txboard_add_phys_region(base, size); + } + + /* TMR */ + for (i = 0; i < TX4938_NR_TMR; i++) + txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); + + /* enable DMA */ + for (i = 0; i < 2; i++) + ____raw_writeq(TX4938_DMA_MCR_MSTEN, + (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); + + /* PIO */ + __raw_writel(0, &tx4938_pioptr->maskcpu); + __raw_writel(0, &tx4938_pioptr->maskext); + + /* TX4938 internal registers */ + if (request_resource(&iomem_resource, &tx4938_reg_resource)) + printk("request resource for internal registers failed\n"); +} + +#ifdef CONFIG_PCI +static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) +{ + unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); + unsigned long g2pstatus = pcicptr->g2pstatus; + unsigned long pcicstatus = pcicptr->pcicstatus; + static struct { + unsigned long flag; + const char *str; + } pcistat_tbl[] = { + { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, + { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, + { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, + { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, + { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, + { PCI_STATUS_PARITY, "MasterParityError" }, + }, g2pstat_tbl[] = { + { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, + { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, + }, pcicstat_tbl[] = { + { TX4938_PCIC_PCICSTATUS_PME, "PME" }, + { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, + { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, + { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, + { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, + { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, + { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, + { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, + }; + int i; + + printk("pcistat:%04x(", pcistatus); + for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) + if (pcistatus & pcistat_tbl[i].flag) + printk("%s ", pcistat_tbl[i].str); + printk("), g2pstatus:%08lx(", g2pstatus); + for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) + if (g2pstatus & g2pstat_tbl[i].flag) + printk("%s ", g2pstat_tbl[i].str); + printk("), pcicstatus:%08lx(", pcicstatus); + for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) + if (pcicstatus & pcicstat_tbl[i].flag) + printk("%s ", pcicstat_tbl[i].str); + printk(")\n"); +} + +void tx4938_report_pcic_status(void) +{ + int i; + struct tx4938_pcic_reg *pcicptr; + for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) + tx4938_report_pcic_status1(pcicptr); +} + +#endif /* CONFIG_PCI */ + +void __init plat_time_init(void) +{ + mips_hpt_frequency = txx9_cpu_clock / 2; + if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) + txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, + TXX9_IRQ_BASE + TX4938_IR_TMR(0), + txx9_gbus_clock / 2); +} + +void __init plat_mem_setup(void) +{ + unsigned long long pcfg; + char *argptr; + + iomem_resource.end = 0xffffffff; /* 4GB */ + + if (txx9_master_clock == 0) + txx9_master_clock = 25000000; /* 25MHz */ + tx4938_board_setup(); +#ifndef CONFIG_PCI + set_io_port_base(RBTX4938_ETHER_BASE); +#endif + +#ifdef CONFIG_SERIAL_TXX9 + { + extern int early_serial_txx9_setup(struct uart_port *port); + int i; + struct uart_port req; + for(i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (char *)(0xff1ff300 + i * 0x100); + req.mapbase = 0xff1ff300 + i * 0x100; + req.irq = RBTX4938_IRQ_IRC_SIO(i); + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = 50000000; + early_serial_txx9_setup(&req); + } + } +#ifdef CONFIG_SERIAL_TXX9_CONSOLE + argptr = prom_getcmdline(); + if (strstr(argptr, "console=") == NULL) { + strcat(argptr, " console=ttyS0,38400"); + } +#endif +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 + printk("PIOSEL: disabling both ata and nand selection\n"); + local_irq_disable(); + tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND + printk("PIOSEL: enabling nand selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; +#endif + +#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA + printk("PIOSEL: enabling ata selection\n"); + tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; + tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; +#endif + +#ifdef CONFIG_IP_PNP + argptr = prom_getcmdline(); + if (strstr(argptr, "ip=") == NULL) { + strcat(argptr, " ip=any"); + } +#endif + + +#ifdef CONFIG_FB + { + conswitchp = &dummy_con; + } +#endif + + rbtx4938_spi_setup(); + pcfg = tx4938_ccfgptr->pcfg; /* updated */ + /* fixup piosel */ + if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_ATA_SEL) + writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, + rbtx4938_piosel_addr); + else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_NDF_SEL) + writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, + rbtx4938_piosel_addr); + else + writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), + rbtx4938_piosel_addr); + + rbtx4938_fpga_resource.name = "FPGA Registers"; + rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); + rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; + rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) + printk("request resource for fpga failed\n"); + + _machine_restart = rbtx4938_machine_restart; + _machine_halt = rbtx4938_machine_halt; + pm_power_off = rbtx4938_machine_power_off; + + writeb(0xff, rbtx4938_led_addr); + printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", + readb(rbtx4938_fpga_rev_addr), + readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); +} + +static int __init rbtx4938_ne_init(void) +{ + struct resource res[] = { + { + .start = RBTX4938_RTL_8019_BASE, + .end = RBTX4938_RTL_8019_BASE + 0x20 - 1, + .flags = IORESOURCE_IO, + }, { + .start = RBTX4938_RTL_8019_IRQ, + .flags = IORESOURCE_IRQ, + } + }; + struct platform_device *dev = + platform_device_register_simple("ne", -1, + res, ARRAY_SIZE(res)); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} +device_initcall(rbtx4938_ne_init); + +/* GPIO support */ + +int gpio_to_irq(unsigned gpio) +{ + return -EINVAL; +} + +int irq_to_gpio(unsigned irq) +{ + return -EINVAL; +} + +static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); + +static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + u8 val; + unsigned long flags; + spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags); + val = readb(rbtx4938_spics_addr); + if (value) + val |= 1 << offset; + else + val &= ~(1 << offset); + writeb(val, rbtx4938_spics_addr); + mmiowb(); + spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags); +} + +static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip, + unsigned int offset, int value) +{ + rbtx4938_spi_gpio_set(chip, offset, value); + return 0; +} + +static struct gpio_chip rbtx4938_spi_gpio_chip = { + .set = rbtx4938_spi_gpio_set, + .direction_output = rbtx4938_spi_gpio_dir_out, + .label = "RBTX4938-SPICS", + .base = 16, + .ngpio = 3, +}; + +/* SPI support */ + +static void __init txx9_spi_init(unsigned long base, int irq) +{ + struct resource res[] = { + { + .start = base, + .end = base + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .flags = IORESOURCE_IRQ, + }, + }; + platform_device_register_simple("spi_txx9", 0, + res, ARRAY_SIZE(res)); +} + +static int __init rbtx4938_spi_init(void) +{ + struct spi_board_info srtc_info = { + .modalias = "rtc-rs5c348", + .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */ + .bus_num = 0, + .chip_select = 16 + SRTC_CS, + /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */ + .mode = SPI_MODE_1 | SPI_CS_HIGH, + }; + spi_register_board_info(&srtc_info, 1); + spi_eeprom_register(SEEPROM1_CS); + spi_eeprom_register(16 + SEEPROM2_CS); + spi_eeprom_register(16 + SEEPROM3_CS); + gpio_request(16 + SRTC_CS, "rtc-rs5c348"); + gpio_direction_output(16 + SRTC_CS, 0); + gpio_request(SEEPROM1_CS, "seeprom1"); + gpio_direction_output(SEEPROM1_CS, 1); + gpio_request(16 + SEEPROM2_CS, "seeprom2"); + gpio_direction_output(16 + SEEPROM2_CS, 1); + gpio_request(16 + SEEPROM3_CS, "seeprom3"); + gpio_direction_output(16 + SEEPROM3_CS, 1); + txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI); + return 0; +} + +static int __init rbtx4938_arch_init(void) +{ + txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); + gpiochip_add(&rbtx4938_spi_gpio_chip); + return rbtx4938_spi_init(); +} +arch_initcall(rbtx4938_arch_init); + +/* Watchdog support */ + +static int __init txx9_wdt_init(unsigned long base) +{ + struct resource res = { + .start = base, + .end = base + 0x100 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *dev = + platform_device_register_simple("txx9wdt", -1, &res, 1); + return IS_ERR(dev) ? PTR_ERR(dev) : 0; +} + +static int __init rbtx4938_wdt_init(void) +{ + return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); +} +device_initcall(rbtx4938_wdt_init); + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "spi-baseclk")) + return (struct clk *)(txx9_gbus_clock / 2 / 4); + if (!strcmp(id, "imbus_clk")) + return (struct clk *)(txx9_gbus_clock / 2); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/arch/mips/txx9/rbtx4938/spi_eeprom.c b/arch/mips/txx9/rbtx4938/spi_eeprom.c new file mode 100644 index 000000000000..a7ea8b041c1d --- /dev/null +++ b/arch/mips/txx9/rbtx4938/spi_eeprom.c @@ -0,0 +1,99 @@ +/* + * spi_eeprom.c + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#include +#include +#include +#include +#include + +#define AT250X0_PAGE_SIZE 8 + +/* register board information for at25 driver */ +int __init spi_eeprom_register(int chipid) +{ + static struct spi_eeprom eeprom = { + .name = "at250x0", + .byte_len = 128, + .page_size = AT250X0_PAGE_SIZE, + .flags = EE_ADDR1, + }; + struct spi_board_info info = { + .modalias = "at25", + .max_speed_hz = 1500000, /* 1.5Mbps */ + .bus_num = 0, + .chip_select = chipid, + .platform_data = &eeprom, + /* Mode 0: High-Active, Sample-Then-Shift */ + }; + + return spi_register_board_info(&info, 1); +} + +/* simple temporary spi driver to provide early access to seeprom. */ + +static struct read_param { + int chipid; + int address; + unsigned char *buf; + int len; +} *read_param; + +static int __init early_seeprom_probe(struct spi_device *spi) +{ + int stat = 0; + u8 cmd[2]; + int len = read_param->len; + char *buf = read_param->buf; + int address = read_param->address; + + dev_info(&spi->dev, "spiclk %u KHz.\n", + (spi->max_speed_hz + 500) / 1000); + if (read_param->chipid != spi->chip_select) + return -ENODEV; + while (len > 0) { + /* spi_write_then_read can only work with small chunk */ + int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE; + cmd[0] = 0x03; /* AT25_READ */ + cmd[1] = address; + stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c); + buf += c; + len -= c; + address += c; + } + return stat; +} + +static struct spi_driver early_seeprom_driver __initdata = { + .driver = { + .name = "at25", + .owner = THIS_MODULE, + }, + .probe = early_seeprom_probe, +}; + +int __init spi_eeprom_read(int chipid, int address, + unsigned char *buf, int len) +{ + int ret; + struct read_param param = { + .chipid = chipid, + .address = address, + .buf = buf, + .len = len + }; + + read_param = ¶m; + ret = spi_register_driver(&early_seeprom_driver); + if (!ret) + spi_unregister_driver(&early_seeprom_driver); + return ret; +} diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h deleted file mode 100644 index a162268f17df..000000000000 --- a/include/asm-mips/jmr3927/jmr3927.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Defines for the TJSYS JMR-TX3927 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - */ -#ifndef __ASM_TX3927_JMR3927_H -#define __ASM_TX3927_JMR3927_H - -#include -#include -#include -#include - -/* CS */ -#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ -#define JMR3927_ROMCE1 0x1e000000 /* 4M */ -#define JMR3927_ROMCE2 0x14000000 /* 16M */ -#define JMR3927_ROMCE3 0x10000000 /* 64M */ -#define JMR3927_ROMCE5 0x1d000000 /* 4M */ -#define JMR3927_SDCS0 0x00000000 /* 32M */ -#define JMR3927_SDCS1 0x02000000 /* 32M */ -/* PCI Direct Mappings */ - -#define JMR3927_PCIMEM 0x08000000 -#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ -#define JMR3927_PCIIO 0x15000000 -#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ - -#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ -#define JMR3927_PORT_BASE KSEG1 - -/* Address map (virtual address) */ -#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) -#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) -#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) -#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) -#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) - -#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) -#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) -#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) -#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) -#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) -#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) -#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) -#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) -#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) -#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) -#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) - -/* Flash ROM */ -#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) -#define JMR3927_FLASH_SIZE 0x00400000 - -/* bits for IOC_REV/IOC_BREV (high byte) */ -#define JMR3927_IDT_MASK 0xfc -#define JMR3927_REV_MASK 0x03 -#define JMR3927_IOC_IDT 0xe0 - -/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ -#define JMR3927_IOC_INTB_PCIA 0 -#define JMR3927_IOC_INTB_PCIB 1 -#define JMR3927_IOC_INTB_PCIC 2 -#define JMR3927_IOC_INTB_PCID 3 -#define JMR3927_IOC_INTB_MODEM 4 -#define JMR3927_IOC_INTB_INT6 5 -#define JMR3927_IOC_INTB_INT7 6 -#define JMR3927_IOC_INTB_SOFT 7 -#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) -#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) -#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) -#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) -#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) -#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) -#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) -#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) - -/* bits for IOC_RESET (high byte) */ -#define JMR3927_IOC_RESET_CPU 1 -#define JMR3927_IOC_RESET_PCI 2 - -#if defined(__BIG_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) -#elif defined(__LITTLE_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) -#else -#error "No Endian" -#endif - -/* LED macro */ -#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) - -#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) - -/* DIPSW4 macro */ -#define jmr3927_dipsw1() (gpio_get_value(11) == 0) -#define jmr3927_dipsw2() (gpio_get_value(10) == 0) -#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) -#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) - -/* - * IRQ mappings - */ - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an JMR machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ -#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ - -#define JMR3927_IRQ_IRC TXX9_IRQ_BASE -#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) -#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) - -#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) -#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) -#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) -#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) -#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) -#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) -#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) -#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) -#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) -#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) -#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) -#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) -#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) -#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) -#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) -#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) -#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) -#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) -#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) -#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) -#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) - -/* IOC (PCI, MODEM) */ -#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 -/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ -#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 - -/* Clocks */ -#define JMR3927_CORECLK 132710400 /* 132.7MHz */ -#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ -#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ - -/* - * TX3927 Pin Configuration: - * - * PCFG bits Avail Dead - * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] - * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] - * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, - * GDBGE* PIO[2:1] - * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] - * SELTMR[2:0]:000 TIMER[1:0] - * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], - * DMAREQ[1],DMAACK[1] - * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] - * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] - * SELDONE:1 DMADONE PIO[7] - * - * Usable pins are: - * RXD[1;0],TXD[1:0],CTS[0],RTS[0], - * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] - * INT[3:0] - */ - -#endif /* __ASM_TX3927_JMR3927_H */ diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h deleted file mode 100644 index fb580333c102..000000000000 --- a/include/asm-mips/jmr3927/tx3927.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Toshiba Corporation - */ -#ifndef __ASM_TX3927_H -#define __ASM_TX3927_H - -#include - -#define TX3927_SDRAMC_REG 0xfffe8000 -#define TX3927_ROMC_REG 0xfffe9000 -#define TX3927_DMA_REG 0xfffeb000 -#define TX3927_IRC_REG 0xfffec000 -#define TX3927_PCIC_REG 0xfffed000 -#define TX3927_CCFG_REG 0xfffee000 -#define TX3927_NR_TMR 3 -#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) -#define TX3927_NR_SIO 2 -#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) -#define TX3927_PIO_REG 0xfffef500 - -struct tx3927_sdramc_reg { - volatile unsigned long cr[8]; - volatile unsigned long tr[3]; - volatile unsigned long cmd; - volatile unsigned long smrs[2]; -}; - -struct tx3927_romc_reg { - volatile unsigned long cr[8]; -}; - -struct tx3927_dma_reg { - struct tx3927_dma_ch_reg { - volatile unsigned long cha; - volatile unsigned long sar; - volatile unsigned long dar; - volatile unsigned long cntr; - volatile unsigned long sair; - volatile unsigned long dair; - volatile unsigned long ccr; - volatile unsigned long csr; - } ch[4]; - volatile unsigned long dbr[8]; - volatile unsigned long tdhr; - volatile unsigned long mcr; - volatile unsigned long unused0; -}; - -#include - -#ifdef __BIG_ENDIAN -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - -struct tx3927_pcic_reg { - endian_def_s2(did, vid); - endian_def_s2(pcistat, pcicmd); - endian_def_b4(cc, scc, rpli, rid); - endian_def_b4(unused0, ht, mlt, cls); - volatile unsigned long ioba; /* +10 */ - volatile unsigned long mba; - volatile unsigned long unused1[5]; - endian_def_s2(svid, ssvid); - volatile unsigned long unused2; /* +30 */ - endian_def_sb2(unused3, unused4, capptr); - volatile unsigned long unused5; - endian_def_b4(ml, mg, ip, il); - volatile unsigned long unused6; /* +40 */ - volatile unsigned long istat; - volatile unsigned long iim; - volatile unsigned long rrt; - volatile unsigned long unused7[3]; /* +50 */ - volatile unsigned long ipbmma; - volatile unsigned long ipbioma; /* +60 */ - volatile unsigned long ilbmma; - volatile unsigned long ilbioma; - volatile unsigned long unused8[9]; - volatile unsigned long tc; /* +90 */ - volatile unsigned long tstat; - volatile unsigned long tim; - volatile unsigned long tccmd; - volatile unsigned long pcirrt; /* +a0 */ - volatile unsigned long pcirrt_cmd; - volatile unsigned long pcirrdt; - volatile unsigned long unused9[3]; - volatile unsigned long tlboap; - volatile unsigned long tlbiap; - volatile unsigned long tlbmma; /* +c0 */ - volatile unsigned long tlbioma; - volatile unsigned long sc_msg; - volatile unsigned long sc_be; - volatile unsigned long tbl; /* +d0 */ - volatile unsigned long unused10[3]; - volatile unsigned long pwmng; /* +e0 */ - volatile unsigned long pwmngs; - volatile unsigned long unused11[6]; - volatile unsigned long req_trace; /* +100 */ - volatile unsigned long pbapmc; - volatile unsigned long pbapms; - volatile unsigned long pbapmim; - volatile unsigned long bm; /* +110 */ - volatile unsigned long cpcibrs; - volatile unsigned long cpcibgs; - volatile unsigned long pbacs; - volatile unsigned long iobas; /* +120 */ - volatile unsigned long mbas; - volatile unsigned long lbc; - volatile unsigned long lbstat; - volatile unsigned long lbim; /* +130 */ - volatile unsigned long pcistatim; - volatile unsigned long ica; - volatile unsigned long icd; - volatile unsigned long iiadp; /* +140 */ - volatile unsigned long iscdp; - volatile unsigned long mmas; - volatile unsigned long iomas; - volatile unsigned long ipciaddr; /* +150 */ - volatile unsigned long ipcidata; - volatile unsigned long ipcibe; -}; - -struct tx3927_ccfg_reg { - volatile unsigned long ccfg; - volatile unsigned long crir; - volatile unsigned long pcfg; - volatile unsigned long tear; - volatile unsigned long pdcr; -}; - -/* - * SDRAMC - */ - -/* - * ROMC - */ - -/* - * DMA - */ -/* bits for MCR */ -#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX3927_DMA_MCR_RSFIF 0x00000080 -#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX3927_DMA_MCR_LE 0x00000004 -#define TX3927_DMA_MCR_RPRT 0x00000002 -#define TX3927_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX3927_DMA_CCR_DBINH 0x04000000 -#define TX3927_DMA_CCR_SBINH 0x02000000 -#define TX3927_DMA_CCR_CHRST 0x01000000 -#define TX3927_DMA_CCR_RVBYTE 0x00800000 -#define TX3927_DMA_CCR_ACKPOL 0x00400000 -#define TX3927_DMA_CCR_REQPL 0x00200000 -#define TX3927_DMA_CCR_EGREQ 0x00100000 -#define TX3927_DMA_CCR_CHDN 0x00080000 -#define TX3927_DMA_CCR_DNCTL 0x00060000 -#define TX3927_DMA_CCR_EXTRQ 0x00010000 -#define TX3927_DMA_CCR_INTRQD 0x0000e000 -#define TX3927_DMA_CCR_INTENE 0x00001000 -#define TX3927_DMA_CCR_INTENC 0x00000800 -#define TX3927_DMA_CCR_INTENT 0x00000400 -#define TX3927_DMA_CCR_CHNEN 0x00000200 -#define TX3927_DMA_CCR_XFACT 0x00000100 -#define TX3927_DMA_CCR_SNOP 0x00000080 -#define TX3927_DMA_CCR_DSTINC 0x00000040 -#define TX3927_DMA_CCR_SRCINC 0x00000020 -#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) -#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) -#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) -#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) -#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) -#define TX3927_DMA_CCR_MEMIO 0x00000002 -#define TX3927_DMA_CCR_ONEAD 0x00000001 - -/* bits for CSRn */ -#define TX3927_DMA_CSR_CHNACT 0x00000100 -#define TX3927_DMA_CSR_ABCHC 0x00000080 -#define TX3927_DMA_CSR_NCHNC 0x00000040 -#define TX3927_DMA_CSR_NTRNFC 0x00000020 -#define TX3927_DMA_CSR_EXTDN 0x00000010 -#define TX3927_DMA_CSR_CFERR 0x00000008 -#define TX3927_DMA_CSR_CHERR 0x00000004 -#define TX3927_DMA_CSR_DESERR 0x00000002 -#define TX3927_DMA_CSR_SORERR 0x00000001 - -/* - * IRC - */ -#define TX3927_IR_INT0 0 -#define TX3927_IR_INT1 1 -#define TX3927_IR_INT2 2 -#define TX3927_IR_INT3 3 -#define TX3927_IR_INT4 4 -#define TX3927_IR_INT5 5 -#define TX3927_IR_SIO0 6 -#define TX3927_IR_SIO1 7 -#define TX3927_IR_SIO(ch) (6 + (ch)) -#define TX3927_IR_DMA 8 -#define TX3927_IR_PIO 9 -#define TX3927_IR_PCI 10 -#define TX3927_IR_TMR(ch) (13 + (ch)) -#define TX3927_NUM_IR 16 - -/* - * PCIC - */ -/* bits for PCICMD */ -/* see PCI_COMMAND_XXX in linux/pci.h */ - -/* bits for PCISTAT */ -/* see PCI_STATUS_XXX in linux/pci.h */ -#define PCI_STATUS_NEW_CAP 0x0010 - -/* bits for TC */ -#define TX3927_PCIC_TC_OF16E 0x00000020 -#define TX3927_PCIC_TC_IF8E 0x00000010 -#define TX3927_PCIC_TC_OF8E 0x00000008 - -/* bits for IOBA/MBA */ -/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ - -/* bits for PBAPMC */ -#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 -#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 -#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 - -/* bits for LBSTAT/LBIM */ -#define TX3927_PCIC_LBIM_ALL 0x0000003e - -/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 - -/* bits for LBC */ -#define TX3927_PCIC_LBC_IBSE 0x00004000 -#define TX3927_PCIC_LBC_TIBSE 0x00002000 -#define TX3927_PCIC_LBC_TMFBSE 0x00001000 -#define TX3927_PCIC_LBC_HRST 0x00000800 -#define TX3927_PCIC_LBC_SRST 0x00000400 -#define TX3927_PCIC_LBC_EPCAD 0x00000200 -#define TX3927_PCIC_LBC_MSDSE 0x00000100 -#define TX3927_PCIC_LBC_CRR 0x00000080 -#define TX3927_PCIC_LBC_ILMDE 0x00000040 -#define TX3927_PCIC_LBC_ILIDE 0x00000020 - -#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX3927_CCFG_TLBOFF 0x00020000 -#define TX3927_CCFG_BEOW 0x00010000 -#define TX3927_CCFG_WR 0x00008000 -#define TX3927_CCFG_TOE 0x00004000 -#define TX3927_CCFG_PCIXARB 0x00002000 -#define TX3927_CCFG_PCI3 0x00001000 -#define TX3927_CCFG_PSNP 0x00000800 -#define TX3927_CCFG_PPRI 0x00000400 -#define TX3927_CCFG_PLLM 0x00000030 -#define TX3927_CCFG_ENDIAN 0x00000004 -#define TX3927_CCFG_HALT 0x00000002 -#define TX3927_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX3927_PCFG_SYSCLKEN 0x08000000 -#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 -#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) -#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 -#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) -#define TX3927_PCFG_SELALL 0x0003ffff -#define TX3927_PCFG_SELCS 0x00020000 -#define TX3927_PCFG_SELDSF 0x00010000 -#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 -#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) -#define TX3927_PCFG_SELSIO_ALL 0x00003000 -#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) -#define TX3927_PCFG_SELTMR_ALL 0x00000e00 -#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) -#define TX3927_PCFG_SELDONE 0x00000100 -#define TX3927_PCFG_INTDMA_ALL 0x000000f0 -#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) -#define TX3927_PCFG_SELDMA_ALL 0x0000000f -#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) - -#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) -#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) -#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) -#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) -#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) -#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) -#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) -#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) - -#endif /* __ASM_TX3927_H */ diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h deleted file mode 100644 index 25dcf2feb095..000000000000 --- a/include/asm-mips/jmr3927/txx927.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Common definitions for TX3927/TX4927 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Toshiba Corporation - */ -#ifndef __ASM_TXX927_H -#define __ASM_TXX927_H - -struct txx927_sio_reg { - volatile unsigned long lcr; - volatile unsigned long dicr; - volatile unsigned long disr; - volatile unsigned long cisr; - volatile unsigned long fcr; - volatile unsigned long flcr; - volatile unsigned long bgr; - volatile unsigned long tfifo; - volatile unsigned long rfifo; -}; - -/* - * SIO - */ -/* SILCR : Line Control */ -#define TXx927_SILCR_SCS_MASK 0x00000060 -#define TXx927_SILCR_SCS_IMCLK 0x00000000 -#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 -#define TXx927_SILCR_SCS_SCLK 0x00000040 -#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 -#define TXx927_SILCR_UEPS 0x00000010 -#define TXx927_SILCR_UPEN 0x00000008 -#define TXx927_SILCR_USBL_MASK 0x00000004 -#define TXx927_SILCR_USBL_1BIT 0x00000004 -#define TXx927_SILCR_USBL_2BIT 0x00000000 -#define TXx927_SILCR_UMODE_MASK 0x00000003 -#define TXx927_SILCR_UMODE_8BIT 0x00000000 -#define TXx927_SILCR_UMODE_7BIT 0x00000001 - -/* SIDICR : DMA/Int. Control */ -#define TXx927_SIDICR_TDE 0x00008000 -#define TXx927_SIDICR_RDE 0x00004000 -#define TXx927_SIDICR_TIE 0x00002000 -#define TXx927_SIDICR_RIE 0x00001000 -#define TXx927_SIDICR_SPIE 0x00000800 -#define TXx927_SIDICR_CTSAC 0x00000600 -#define TXx927_SIDICR_STIE_MASK 0x0000003f -#define TXx927_SIDICR_STIE_OERS 0x00000020 -#define TXx927_SIDICR_STIE_CTSS 0x00000010 -#define TXx927_SIDICR_STIE_RBRKD 0x00000008 -#define TXx927_SIDICR_STIE_TRDY 0x00000004 -#define TXx927_SIDICR_STIE_TXALS 0x00000002 -#define TXx927_SIDICR_STIE_UBRKD 0x00000001 - -/* SIDISR : DMA/Int. Status */ -#define TXx927_SIDISR_UBRK 0x00008000 -#define TXx927_SIDISR_UVALID 0x00004000 -#define TXx927_SIDISR_UFER 0x00002000 -#define TXx927_SIDISR_UPER 0x00001000 -#define TXx927_SIDISR_UOER 0x00000800 -#define TXx927_SIDISR_ERI 0x00000400 -#define TXx927_SIDISR_TOUT 0x00000200 -#define TXx927_SIDISR_TDIS 0x00000100 -#define TXx927_SIDISR_RDIS 0x00000080 -#define TXx927_SIDISR_STIS 0x00000040 -#define TXx927_SIDISR_RFDN_MASK 0x0000001f - -/* SICISR : Change Int. Status */ -#define TXx927_SICISR_OERS 0x00000020 -#define TXx927_SICISR_CTSS 0x00000010 -#define TXx927_SICISR_RBRKD 0x00000008 -#define TXx927_SICISR_TRDY 0x00000004 -#define TXx927_SICISR_TXALS 0x00000002 -#define TXx927_SICISR_UBRKD 0x00000001 - -/* SIFCR : FIFO Control */ -#define TXx927_SIFCR_SWRST 0x00008000 -#define TXx927_SIFCR_RDIL_MASK 0x00000180 -#define TXx927_SIFCR_RDIL_1 0x00000000 -#define TXx927_SIFCR_RDIL_4 0x00000080 -#define TXx927_SIFCR_RDIL_8 0x00000100 -#define TXx927_SIFCR_RDIL_12 0x00000180 -#define TXx927_SIFCR_RDIL_MAX 0x00000180 -#define TXx927_SIFCR_TDIL_MASK 0x00000018 -#define TXx927_SIFCR_TDIL_MASK 0x00000018 -#define TXx927_SIFCR_TDIL_1 0x00000000 -#define TXx927_SIFCR_TDIL_4 0x00000001 -#define TXx927_SIFCR_TDIL_8 0x00000010 -#define TXx927_SIFCR_TDIL_MAX 0x00000010 -#define TXx927_SIFCR_TFRST 0x00000004 -#define TXx927_SIFCR_RFRST 0x00000002 -#define TXx927_SIFCR_FRSTE 0x00000001 -#define TXx927_SIO_TX_FIFO 8 -#define TXx927_SIO_RX_FIFO 16 - -/* SIFLCR : Flow Control */ -#define TXx927_SIFLCR_RCS 0x00001000 -#define TXx927_SIFLCR_TES 0x00000800 -#define TXx927_SIFLCR_RTSSC 0x00000200 -#define TXx927_SIFLCR_RSDE 0x00000100 -#define TXx927_SIFLCR_TSDE 0x00000080 -#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e -#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e -#define TXx927_SIFLCR_TBRK 0x00000001 - -/* SIBGR : Baudrate Control */ -#define TXx927_SIBGR_BCLK_MASK 0x00000300 -#define TXx927_SIBGR_BCLK_T0 0x00000000 -#define TXx927_SIBGR_BCLK_T2 0x00000100 -#define TXx927_SIBGR_BCLK_T4 0x00000200 -#define TXx927_SIBGR_BCLK_T6 0x00000300 -#define TXx927_SIBGR_BRD_MASK 0x000000ff - -/* - * PIO - */ - -#endif /* __ASM_TXX927_H */ diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/tx4927/smsc_fdc37m81x.h deleted file mode 100644 index 5d93bab51254..000000000000 --- a/include/asm-mips/tx4927/smsc_fdc37m81x.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h - * - * Interface for smsc fdc48m81x Super IO chip - * - * Author: MontaVista Software, Inc. source@mvista.com - * - * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Manish Lachwani, mlachwani@mvista.com - */ - -#ifndef _SMSC_FDC37M81X_H_ -#define _SMSC_FDC37M81X_H_ - -/* Common Registers */ -#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 -#define SMSC_FDC37M81X_CONFIG_DATA 0x01 -#define SMSC_FDC37M81X_CONF 0x02 -#define SMSC_FDC37M81X_INDEX 0x03 -#define SMSC_FDC37M81X_DNUM 0x07 -#define SMSC_FDC37M81X_DID 0x20 -#define SMSC_FDC37M81X_DREV 0x21 -#define SMSC_FDC37M81X_PCNT 0x22 -#define SMSC_FDC37M81X_PMGT 0x23 -#define SMSC_FDC37M81X_OSC 0x24 -#define SMSC_FDC37M81X_CONFPA0 0x26 -#define SMSC_FDC37M81X_CONFPA1 0x27 -#define SMSC_FDC37M81X_TEST4 0x2B -#define SMSC_FDC37M81X_TEST5 0x2C -#define SMSC_FDC37M81X_TEST1 0x2D -#define SMSC_FDC37M81X_TEST2 0x2E -#define SMSC_FDC37M81X_TEST3 0x2F - -/* Logical device numbers */ -#define SMSC_FDC37M81X_FDD 0x00 -#define SMSC_FDC37M81X_PARALLEL 0x03 -#define SMSC_FDC37M81X_SERIAL1 0x04 -#define SMSC_FDC37M81X_SERIAL2 0x05 -#define SMSC_FDC37M81X_KBD 0x07 -#define SMSC_FDC37M81X_AUXIO 0x08 -#define SMSC_FDC37M81X_NONE 0xff - -/* Logical device Config Registers */ -#define SMSC_FDC37M81X_ACTIVE 0x30 -#define SMSC_FDC37M81X_BASEADDR0 0x60 -#define SMSC_FDC37M81X_BASEADDR1 0x61 -#define SMSC_FDC37M81X_INT 0x70 -#define SMSC_FDC37M81X_INT2 0x72 -#define SMSC_FDC37M81X_LDCR_F0 0xF0 - -/* Chip Config Values */ -#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 -#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa -#define SMSC_FDC37M81X_CHIP_ID 0x4d - -unsigned long __init smsc_fdc37m81x_init(unsigned long port); - -void smsc_fdc37m81x_config_beg(void); - -void smsc_fdc37m81x_config_end(void); - -void smsc_fdc37m81x_config_set(u8 reg, u8 val); - -#endif diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h deleted file mode 100644 index d6b32acd6b7b..000000000000 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H -#define __ASM_TX4927_TOSHIBA_RBTX4927_H - -#include - -#ifdef CONFIG_PCI -#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO -#else -#define TBTX4927_ISA_IO_OFFSET 0 -#endif - -#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL -#define RBTX4927_SW_RESET_DO_SET 0x01 - -#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL -#define RBTX4927_SW_RESET_ENABLE_SET 0x01 - -#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) -#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) - -int toshiba_rbtx4927_irq_nested(int sw_irq); - -#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h deleted file mode 100644 index 1d4816f3266f..000000000000 --- a/include/asm-mips/tx4927/tx4927.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2001-2006 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_TX4927_TX4927_H -#define __ASM_TX4927_TX4927_H - -#include - -#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) - - -#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) -#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) -#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) -#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) - -#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) - -#define TX4927_CCFG_TOE 0x00004000 -#define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TINTDIS 0x01000000 - -#define TX4927_PCIMEM 0x08000000 -#define TX4927_PCIMEM_SIZE 0x08000000 -#define TX4927_PCIIO 0x16000000 -#define TX4927_PCIIO_SIZE 0x01000000 - -#define TX4927_SDRAMC_REG 0xff1f8000 -#define TX4927_EBUSC_REG 0xff1f9000 -#define TX4927_PCIC_REG 0xff1fd000 -#define TX4927_CCFG_REG 0xff1fe000 -#define TX4927_IRC_REG 0xff1ff600 -#define TX4927_NR_TMR 3 -#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) - -/* bits for ISTAT3/IMASK3/IMSTAT3 */ -#define TX4927_INT3B_PCID 0 -#define TX4927_INT3B_PCIC 1 -#define TX4927_INT3B_PCIB 2 -#define TX4927_INT3B_PCIA 3 -#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) -#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) -#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) -#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) - -#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG -#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ - -#define TX4927_IR_PCIC 16 -#define TX4927_IR_PCIERR 22 -#define TX4927_IR_PCIPMA 23 -#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) -#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) -#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) -#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) -#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) -#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) -#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) - -#ifdef _LANGUAGE_ASSEMBLY -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include - -struct tx4927_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; -}; - -struct tx4927_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4927_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; -}; - -struct tx4927_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmcut; - volatile unsigned long long pdmcnt; /* +220 */ - volatile unsigned long long pdmsts; - volatile unsigned long long unused8[2]; - volatile unsigned long long pdmdb[4]; /* +240 */ - volatile unsigned long long pdmtdh; /* +260 */ - volatile unsigned long long pdmdms; -}; - -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * PCIC - */ - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 -#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc - -/* bits for PCICCFG */ -#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 -#define TX4927_PCIC_PCICCFG_HRST 0x00000800 -#define TX4927_PCIC_PCICCFG_SRST 0x00000400 -#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 -#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 -#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 -#define TX4927_PCIC_PCICCFG_IISE 0x00000020 -#define TX4927_PCIC_PCICCFG_ATR 0x00000010 -#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4927_CCFG_PCI66 0x00800000 -#define TX4927_CCFG_PCIMIDE 0x00400000 -#define TX4927_CCFG_PCIXARB 0x00002000 -#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 -#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 -#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 -#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 -#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 - -#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 -#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 -#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 -#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 -#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 -#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 -#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 -#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 - -/* PCFG : Pin Configuration */ -#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) - -/* CLKCTR : Clock Control */ -#define TX4927_CLKCTR_PCICKD 0x00400000 -#define TX4927_CLKCTR_PCIRST 0x00000040 - -#ifndef _LANGUAGE_ASSEMBLY - -#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) -#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) -#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) -#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) - -#endif /* _LANGUAGE_ASSEMBLY */ - -#endif /* __ASM_TX4927_TX4927_H */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h deleted file mode 100644 index dfed7beb533f..000000000000 --- a/include/asm-mips/tx4938/rbtx4938.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/rbtx4938.h - * Definitions for TX4937/TX4938 - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_RBTX4938_H -#define __ASM_TX_BOARDS_RBTX4938_H - -#include -#include -#include - -/* CS */ -#define RBTX4938_CE0 0x1c000000 /* 64M */ -#define RBTX4938_CE2 0x17f00000 /* 1M */ - -/* Address map */ -#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) -#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) -#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) -#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) -#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) -#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) -#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) -#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) -#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) -#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) -#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) -#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) -#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) -#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) -#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) -#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) -#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) -#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) -#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) -#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) -#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) -#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) -#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) -#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) - -/* Ethernet port address (Jumperless Mode (W12:Open)) */ -#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) - -/* bits for ISTAT/IMASK/IMSTAT */ -#define RBTX4938_INTB_PCID 0 -#define RBTX4938_INTB_PCIC 1 -#define RBTX4938_INTB_PCIB 2 -#define RBTX4938_INTB_PCIA 3 -#define RBTX4938_INTB_RTC 4 -#define RBTX4938_INTB_ATA 5 -#define RBTX4938_INTB_MODEM 6 -#define RBTX4938_INTB_SWINT 7 -#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) -#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) -#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) -#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) -#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) -#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) -#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) -#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) - -#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) -#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) -#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) -#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) -#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) -#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) -#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) -#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) -#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) -#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) -#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) -#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) -#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) -#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) -#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) -#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) -#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) -#define rbtx4938_softresetlock_addr \ - ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) -#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) - -/* - * IRQ mappings - */ - -#define RBTX4938_SOFT_INT0 0 /* not used */ -#define RBTX4938_SOFT_INT1 1 /* not used */ -#define RBTX4938_IRC_INT 2 -#define RBTX4938_TIMER_INT 7 - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define RBTX4938_NR_IRQ_LOCAL 8 -#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ -#define RBTX4938_NR_IRQ_IOC 8 - -#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) -#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) -#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) -#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) -#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) -#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) - -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ -#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG -#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) -#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) -#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) - -#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) -#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) -#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) -#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) -#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) -#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) -#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) -#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) -#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) -#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) -#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) -#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) -#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) -#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) -#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) -#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) -#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) -#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) -#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) -#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) -#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) -#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) -#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) -#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) -#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) -#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) -#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) -#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) - - -/* IOC (PCI, etc) */ -#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) -/* Onboard 10M Ether */ -#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) - -#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) -#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) - -#endif /* __ASM_TX_BOARDS_RBTX4938_H */ diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h deleted file mode 100644 index 6a60c83e152b..000000000000 --- a/include/asm-mips/tx4938/spi.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/spi.h - * Definitions for TX4937/TX4938 SPI - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_TX4938_SPI_H -#define __ASM_TX_BOARDS_TX4938_SPI_H - -extern int spi_eeprom_register(int chipid); -extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); - -#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h deleted file mode 100644 index e8807f5c61e9..000000000000 --- a/include/asm-mips/tx4938/tx4938.h +++ /dev/null @@ -1,628 +0,0 @@ -/* - * linux/include/asm-mips/tx4938/tx4938.h - * Definitions for TX4937/TX4938 - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TX_BOARDS_TX4938_H -#define __ASM_TX_BOARDS_TX4938_H - -#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) -#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) - -#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG - -#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) -#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) - -#define TX4938_PCIIO_0 0x10000000 -#define TX4938_PCIIO_1 0x01010000 -#define TX4938_PCIMEM_0 0x08000000 -#define TX4938_PCIMEM_1 0x11000000 - -#define TX4938_PCIIO_SIZE_0 0x01000000 -#define TX4938_PCIIO_SIZE_1 0x00010000 -#define TX4938_PCIMEM_SIZE_0 0x08000000 -#define TX4938_PCIMEM_SIZE_1 0x00010000 - -#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ -#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ - -/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ -#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) -#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) -#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) -#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) -#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) -#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) -#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) -#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) -#define TX4938_NR_TMR 3 -#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) -#define TX4938_NR_SIO 2 -#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) -#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) -#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) -#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) -#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) - -#ifdef __ASSEMBLY__ -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include - -#ifdef __BIG_ENDIAN -#define endian_def_l2(e1, e2) \ - volatile unsigned long e1, e2 -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_l2(e1, e2) \ - volatile unsigned long e2, e1 -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - - -struct tx4938_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; - volatile unsigned long long sfcmd; -}; - -struct tx4938_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4938_dma_reg { - struct tx4938_dma_ch_reg { - volatile unsigned long long cha; - volatile unsigned long long sar; - volatile unsigned long long dar; - endian_def_l2(unused0, cntr); - endian_def_l2(unused1, sair); - endian_def_l2(unused2, dair); - endian_def_l2(unused3, ccr); - endian_def_l2(unused4, csr); - } ch[4]; - volatile unsigned long long dbr[8]; - volatile unsigned long long tdhr; - volatile unsigned long long midr; - endian_def_l2(unused0, mcr); -}; - -struct tx4938_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmctr; - volatile unsigned long long pdmcfg; /* +220 */ - volatile unsigned long long pdmsts; -}; - -struct tx4938_aclc_reg { - volatile unsigned long acctlen; - volatile unsigned long acctldis; - volatile unsigned long acregacc; - volatile unsigned long unused0; - volatile unsigned long acintsts; - volatile unsigned long acintmsts; - volatile unsigned long acinten; - volatile unsigned long acintdis; - volatile unsigned long acsemaph; - volatile unsigned long unused1[7]; - volatile unsigned long acgpidat; - volatile unsigned long acgpodat; - volatile unsigned long acslten; - volatile unsigned long acsltdis; - volatile unsigned long acfifosts; - volatile unsigned long unused2[11]; - volatile unsigned long acdmasts; - volatile unsigned long acdmasel; - volatile unsigned long unused3[6]; - volatile unsigned long acaudodat; - volatile unsigned long acsurrdat; - volatile unsigned long accentdat; - volatile unsigned long aclfedat; - volatile unsigned long acaudiat; - volatile unsigned long unused4; - volatile unsigned long acmodoat; - volatile unsigned long acmodidat; - volatile unsigned long unused5[15]; - volatile unsigned long acrevid; -}; - - -struct tx4938_tmr_reg { - volatile unsigned long tcr; - volatile unsigned long tisr; - volatile unsigned long cpra; - volatile unsigned long cprb; - volatile unsigned long itmr; - volatile unsigned long unused0[3]; - volatile unsigned long ccdr; - volatile unsigned long unused1[3]; - volatile unsigned long pgmr; - volatile unsigned long unused2[3]; - volatile unsigned long wtmr; - volatile unsigned long unused3[43]; - volatile unsigned long trr; -}; - -struct tx4938_sio_reg { - volatile unsigned long lcr; - volatile unsigned long dicr; - volatile unsigned long disr; - volatile unsigned long cisr; - volatile unsigned long fcr; - volatile unsigned long flcr; - volatile unsigned long bgr; - volatile unsigned long tfifo; - volatile unsigned long rfifo; -}; - -struct tx4938_ndfmc_reg { - endian_def_l2(unused0, dtr); - endian_def_l2(unused1, mcr); - endian_def_l2(unused2, sr); - endian_def_l2(unused3, isr); - endian_def_l2(unused4, imr); - endian_def_l2(unused5, spr); - endian_def_l2(unused6, rstr); -}; - -struct tx4938_spi_reg { - volatile unsigned long mcr; - volatile unsigned long cr0; - volatile unsigned long cr1; - volatile unsigned long fs; - volatile unsigned long unused1; - volatile unsigned long sr; - volatile unsigned long dr; - volatile unsigned long unused2; -}; - -struct tx4938_sramc_reg { - volatile unsigned long long cr; -}; - -struct tx4938_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; - volatile unsigned long long unused3; - volatile unsigned long long jmpadr; -}; - -#undef endian_def_l2 -#undef endian_def_s2 -#undef endian_def_sb2 -#undef endian_def_b2s -#undef endian_def_b4 - -#endif /* __ASSEMBLY__ */ - -/* - * NDFMC - */ - -/* NDFMCR : NDFMC Mode Control */ -#define TX4938_NDFMCR_WE 0x80 -#define TX4938_NDFMCR_ECC_ALL 0x60 -#define TX4938_NDFMCR_ECC_RESET 0x60 -#define TX4938_NDFMCR_ECC_READ 0x40 -#define TX4938_NDFMCR_ECC_ON 0x20 -#define TX4938_NDFMCR_ECC_OFF 0x00 -#define TX4938_NDFMCR_CE 0x10 -#define TX4938_NDFMCR_BSPRT 0x04 -#define TX4938_NDFMCR_ALE 0x02 -#define TX4938_NDFMCR_CLE 0x01 - -/* NDFMCR : NDFMC Status */ -#define TX4938_NDFSR_BUSY 0x80 - -/* NDFMCR : NDFMC Reset */ -#define TX4938_NDFRSTR_RST 0x01 - -/* - * IRC - */ - -#define TX4938_IR_ECCERR 0 -#define TX4938_IR_WTOERR 1 -#define TX4938_NUM_IR_INT 6 -#define TX4938_IR_INT(n) (2 + (n)) -#define TX4938_NUM_IR_SIO 2 -#define TX4938_IR_SIO(n) (8 + (n)) -#define TX4938_NUM_IR_DMA 4 -#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ -#define TX4938_IR_PIO 14 -#define TX4938_IR_PDMAC 15 -#define TX4938_IR_PCIC 16 -#define TX4938_NUM_IR_TMR 3 -#define TX4938_IR_TMR(n) (17 + (n)) -#define TX4938_IR_NDFMC 21 -#define TX4938_IR_PCIERR 22 -#define TX4938_IR_PCIPME 23 -#define TX4938_IR_ACLC 24 -#define TX4938_IR_ACLCPME 25 -#define TX4938_IR_PCIC1 26 -#define TX4938_IR_SPI 31 -#define TX4938_NUM_IR 32 -/* multiplex */ -#define TX4938_IR_ETH0 TX4938_IR_INT(4) -#define TX4938_IR_ETH1 TX4938_IR_INT(3) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) -#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) -#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) -#define TX4938_CCFG_TINTDIS 0x01000000 -#define TX4938_CCFG_PCI66 0x00800000 -#define TX4938_CCFG_PCIMODE 0x00400000 -#define TX4938_CCFG_PCI1_66 0x00200000 -#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 -#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) -#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) -#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) -#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) -#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) -#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) -#define TX4938_CCFG_DIVMODE_10 (0xb << 17) -#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) -#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) -#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) -#define TX4938_CCFG_BEOW 0x00010000 -#define TX4938_CCFG_WR 0x00008000 -#define TX4938_CCFG_TOE 0x00004000 -#define TX4938_CCFG_PCIXARB 0x00002000 -#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) -#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) -#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) -#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) -#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) -#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) -#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) -#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) -#define TX4938_CCFG_PCI1DMD 0x00000100 -#define TX4938_CCFG_SYSSP_MASK 0x000000c0 -#define TX4938_CCFG_ENDIAN 0x00000004 -#define TX4938_CCFG_HALT 0x00000002 -#define TX4938_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) -#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) -#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) -#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) -#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) -#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) -#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 -#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) -#define TX4938_PCFG_SYSCLKEN 0x08000000 -#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 -#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) -#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 -#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) -#define TX4938_PCFG_SEL2 0x00000200 -#define TX4938_PCFG_SEL1 0x00000100 -#define TX4938_PCFG_DMASEL_ALL 0x0000000f -#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 -#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 -#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 -#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 -#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 -#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 -#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 -#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 - -/* CLKCTR : Clock Control */ -#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) -#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) -#define TX4938_CLKCTR_ETH1CKD 0x80000000 -#define TX4938_CLKCTR_ETH0CKD 0x40000000 -#define TX4938_CLKCTR_SPICKD 0x20000000 -#define TX4938_CLKCTR_SRAMCKD 0x10000000 -#define TX4938_CLKCTR_PCIC1CKD 0x08000000 -#define TX4938_CLKCTR_DMA1CKD 0x04000000 -#define TX4938_CLKCTR_ACLCKD 0x02000000 -#define TX4938_CLKCTR_PIOCKD 0x01000000 -#define TX4938_CLKCTR_DMACKD 0x00800000 -#define TX4938_CLKCTR_PCICKD 0x00400000 -#define TX4938_CLKCTR_TM0CKD 0x00100000 -#define TX4938_CLKCTR_TM1CKD 0x00080000 -#define TX4938_CLKCTR_TM2CKD 0x00040000 -#define TX4938_CLKCTR_SIO0CKD 0x00020000 -#define TX4938_CLKCTR_SIO1CKD 0x00010000 -#define TX4938_CLKCTR_ETH1RST 0x00008000 -#define TX4938_CLKCTR_ETH0RST 0x00004000 -#define TX4938_CLKCTR_SPIRST 0x00002000 -#define TX4938_CLKCTR_SRAMRST 0x00001000 -#define TX4938_CLKCTR_PCIC1RST 0x00000800 -#define TX4938_CLKCTR_DMA1RST 0x00000400 -#define TX4938_CLKCTR_ACLRST 0x00000200 -#define TX4938_CLKCTR_PIORST 0x00000100 -#define TX4938_CLKCTR_DMARST 0x00000080 -#define TX4938_CLKCTR_PCIRST 0x00000040 -#define TX4938_CLKCTR_TM0RST 0x00000010 -#define TX4938_CLKCTR_TM1RST 0x00000008 -#define TX4938_CLKCTR_TM2RST 0x00000004 -#define TX4938_CLKCTR_SIO0RST 0x00000002 -#define TX4938_CLKCTR_SIO1RST 0x00000001 - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 -#define TX4938_PCIC_PBACFG_RPBA 0x00000004 -#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 -#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 -#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 -#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 -#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 -#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 -#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 -#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 -#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 -#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 - -/* bits for PCICCFG */ -#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 -#define TX4938_PCIC_PCICCFG_HRST 0x00000800 -#define TX4938_PCIC_PCICCFG_SRST 0x00000400 -#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) -#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 -#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 -#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 -#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 -#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 -#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) - -/* bits for PDMCFG */ -#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 -#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 -#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 -#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) -#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 -#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 -#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 -#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 -#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 -#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 -#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c -#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 -#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 -#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 -#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 -#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 - -/* bits for PDMSTS */ -#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 -#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 -#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 -#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 -#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 -#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 -#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 -#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 -#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 -#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 -#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 -#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 -#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 -#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 -#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 -#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 -#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f - -/* - * DMA - */ -/* bits for MCR */ -#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX4938_DMA_MCR_RSFIF 0x00000080 -#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX4938_DMA_MCR_RPRT 0x00000002 -#define TX4938_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX4938_DMA_CCR_IMMCHN 0x20000000 -#define TX4938_DMA_CCR_USEXFSZ 0x10000000 -#define TX4938_DMA_CCR_LE 0x08000000 -#define TX4938_DMA_CCR_DBINH 0x04000000 -#define TX4938_DMA_CCR_SBINH 0x02000000 -#define TX4938_DMA_CCR_CHRST 0x01000000 -#define TX4938_DMA_CCR_RVBYTE 0x00800000 -#define TX4938_DMA_CCR_ACKPOL 0x00400000 -#define TX4938_DMA_CCR_REQPL 0x00200000 -#define TX4938_DMA_CCR_EGREQ 0x00100000 -#define TX4938_DMA_CCR_CHDN 0x00080000 -#define TX4938_DMA_CCR_DNCTL 0x00060000 -#define TX4938_DMA_CCR_EXTRQ 0x00010000 -#define TX4938_DMA_CCR_INTRQD 0x0000e000 -#define TX4938_DMA_CCR_INTENE 0x00001000 -#define TX4938_DMA_CCR_INTENC 0x00000800 -#define TX4938_DMA_CCR_INTENT 0x00000400 -#define TX4938_DMA_CCR_CHNEN 0x00000200 -#define TX4938_DMA_CCR_XFACT 0x00000100 -#define TX4938_DMA_CCR_SMPCHN 0x00000020 -#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) -#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) -#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) -#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) -#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) -#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) -#define TX4938_DMA_CCR_MEMIO 0x00000002 -#define TX4938_DMA_CCR_SNGAD 0x00000001 - -/* bits for CSRn */ -#define TX4938_DMA_CSR_CHNEN 0x00000400 -#define TX4938_DMA_CSR_STLXFER 0x00000200 -#define TX4938_DMA_CSR_CHNACT 0x00000100 -#define TX4938_DMA_CSR_ABCHC 0x00000080 -#define TX4938_DMA_CSR_NCHNC 0x00000040 -#define TX4938_DMA_CSR_NTRNFC 0x00000020 -#define TX4938_DMA_CSR_EXTDN 0x00000010 -#define TX4938_DMA_CSR_CFERR 0x00000008 -#define TX4938_DMA_CSR_CHERR 0x00000004 -#define TX4938_DMA_CSR_DESERR 0x00000002 -#define TX4938_DMA_CSR_SORERR 0x00000001 - -#ifndef __ASSEMBLY__ - -#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) -#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) -#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) -#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) -#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) -#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) -#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) -#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) -#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) -#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) -#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) -#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) - - -#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) -#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) - -#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) -#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) - -#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) -#define TX4938_EBUSC_SIZE(ch) \ - (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) - - -#endif /* !__ASSEMBLY__ */ - -#endif diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h new file mode 100644 index 000000000000..29e54981a86e --- /dev/null +++ b/include/asm-mips/txx9/jmr3927.h @@ -0,0 +1,177 @@ +/* + * Defines for the TJSYS JMR-TX3927 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Toshiba Corporation + */ +#ifndef __ASM_TXX9_JMR3927_H +#define __ASM_TXX9_JMR3927_H + +#include +#include +#include +#include + +/* CS */ +#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ +#define JMR3927_ROMCE1 0x1e000000 /* 4M */ +#define JMR3927_ROMCE2 0x14000000 /* 16M */ +#define JMR3927_ROMCE3 0x10000000 /* 64M */ +#define JMR3927_ROMCE5 0x1d000000 /* 4M */ +#define JMR3927_SDCS0 0x00000000 /* 32M */ +#define JMR3927_SDCS1 0x02000000 /* 32M */ +/* PCI Direct Mappings */ + +#define JMR3927_PCIMEM 0x08000000 +#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ +#define JMR3927_PCIIO 0x15000000 +#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ + +#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ +#define JMR3927_PORT_BASE KSEG1 + +/* Address map (virtual address) */ +#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) +#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) +#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) +#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) +#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) + +#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) +#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) +#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) +#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) +#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) +#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) +#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) +#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) +#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) +#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) +#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) + +/* Flash ROM */ +#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) +#define JMR3927_FLASH_SIZE 0x00400000 + +/* bits for IOC_REV/IOC_BREV (high byte) */ +#define JMR3927_IDT_MASK 0xfc +#define JMR3927_REV_MASK 0x03 +#define JMR3927_IOC_IDT 0xe0 + +/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ +#define JMR3927_IOC_INTB_PCIA 0 +#define JMR3927_IOC_INTB_PCIB 1 +#define JMR3927_IOC_INTB_PCIC 2 +#define JMR3927_IOC_INTB_PCID 3 +#define JMR3927_IOC_INTB_MODEM 4 +#define JMR3927_IOC_INTB_INT6 5 +#define JMR3927_IOC_INTB_INT7 6 +#define JMR3927_IOC_INTB_SOFT 7 +#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) +#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) +#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) +#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) +#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) +#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) +#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) +#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) + +/* bits for IOC_RESET (high byte) */ +#define JMR3927_IOC_RESET_CPU 1 +#define JMR3927_IOC_RESET_PCI 2 + +#if defined(__BIG_ENDIAN) +#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) +#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) +#elif defined(__LITTLE_ENDIAN) +#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) +#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) +#else +#error "No Endian" +#endif + +/* LED macro */ +#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) + +#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) + +/* DIPSW4 macro */ +#define jmr3927_dipsw1() (gpio_get_value(11) == 0) +#define jmr3927_dipsw2() (gpio_get_value(10) == 0) +#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) +#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) + +/* + * IRQ mappings + */ + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an JMR machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ +#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ + +#define JMR3927_IRQ_IRC TXX9_IRQ_BASE +#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) +#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) + +#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) +#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) +#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) +#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) +#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) +#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) +#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) +#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) +#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) +#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) +#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) +#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) +#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) +#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) +#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) +#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) +#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) +#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) +#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) +#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) +#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) + +/* IOC (PCI, MODEM) */ +#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 +/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ +#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 + +/* Clocks */ +#define JMR3927_CORECLK 132710400 /* 132.7MHz */ +#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ +#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ + +/* + * TX3927 Pin Configuration: + * + * PCFG bits Avail Dead + * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] + * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] + * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, + * GDBGE* PIO[2:1] + * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] + * SELTMR[2:0]:000 TIMER[1:0] + * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], + * DMAREQ[1],DMAACK[1] + * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] + * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] + * SELDONE:1 DMADONE PIO[7] + * + * Usable pins are: + * RXD[1;0],TXD[1:0],CTS[0],RTS[0], + * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] + * INT[3:0] + */ + +#endif /* __ASM_TXX9_JMR3927_H */ diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h new file mode 100644 index 000000000000..5531342bcc01 --- /dev/null +++ b/include/asm-mips/txx9/rbtx4927.h @@ -0,0 +1,49 @@ +/* + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_TXX9_RBTX4927_H +#define __ASM_TXX9_RBTX4927_H + +#include + +#ifdef CONFIG_PCI +#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO +#else +#define TBTX4927_ISA_IO_OFFSET 0 +#endif + +#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL +#define RBTX4927_SW_RESET_DO_SET 0x01 + +#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL +#define RBTX4927_SW_RESET_ENABLE_SET 0x01 + +#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) +#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) + +int toshiba_rbtx4927_irq_nested(int sw_irq); + +#endif /* __ASM_TXX9_RBTX4927_H */ diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h new file mode 100644 index 000000000000..8450f735d056 --- /dev/null +++ b/include/asm-mips/txx9/rbtx4938.h @@ -0,0 +1,167 @@ +/* + * Definitions for TX4937/TX4938 + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_RBTX4938_H +#define __ASM_TXX9_RBTX4938_H + +#include +#include +#include + +/* CS */ +#define RBTX4938_CE0 0x1c000000 /* 64M */ +#define RBTX4938_CE2 0x17f00000 /* 1M */ + +/* Address map */ +#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) +#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) +#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) +#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) +#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) +#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) +#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) +#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) +#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) +#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) +#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) +#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) +#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) +#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) +#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) +#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) +#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) +#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) +#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) +#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) +#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) +#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) +#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) +#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) + +/* Ethernet port address (Jumperless Mode (W12:Open)) */ +#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) + +/* bits for ISTAT/IMASK/IMSTAT */ +#define RBTX4938_INTB_PCID 0 +#define RBTX4938_INTB_PCIC 1 +#define RBTX4938_INTB_PCIB 2 +#define RBTX4938_INTB_PCIA 3 +#define RBTX4938_INTB_RTC 4 +#define RBTX4938_INTB_ATA 5 +#define RBTX4938_INTB_MODEM 6 +#define RBTX4938_INTB_SWINT 7 +#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) +#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) +#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) +#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) +#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) +#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) +#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) +#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) + +#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) +#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) +#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) +#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) +#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) +#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) +#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) +#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) +#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) +#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) +#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) +#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) +#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) +#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) +#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) +#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) +#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) +#define rbtx4938_softresetlock_addr \ + ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) +#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) + +/* + * IRQ mappings + */ + +#define RBTX4938_SOFT_INT0 0 /* not used */ +#define RBTX4938_SOFT_INT1 1 /* not used */ +#define RBTX4938_IRC_INT 2 +#define RBTX4938_TIMER_INT 7 + +/* These are the virtual IRQ numbers, we divide all IRQ's into + * 'spaces', the 'space' determines where and how to enable/disable + * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new + * IRQ hardware is supported. + */ +#define RBTX4938_NR_IRQ_LOCAL 8 +#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ +#define RBTX4938_NR_IRQ_IOC 8 + +#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) + +#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) +#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) +#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) +#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) +#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) +#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) + +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ +#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG +#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) +#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) +#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) + +#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) +#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) +#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) +#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) +#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) +#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) +#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) +#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) +#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) +#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) +#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) +#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) +#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) +#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) +#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) +#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) +#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) +#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) +#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) +#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) +#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) +#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) +#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) +#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) +#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) +#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) +#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) +#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) + + +/* IOC (PCI, etc) */ +#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) +/* Onboard 10M Ether */ +#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) + +#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) +#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) + +#endif /* __ASM_TXX9_RBTX4938_H */ diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h new file mode 100644 index 000000000000..9375e4fc2289 --- /dev/null +++ b/include/asm-mips/txx9/smsc_fdc37m81x.h @@ -0,0 +1,67 @@ +/* + * Interface for smsc fdc48m81x Super IO chip + * + * Author: MontaVista Software, Inc. source@mvista.com + * + * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2004 MontaVista Software Inc. + * Manish Lachwani, mlachwani@mvista.com + */ + +#ifndef _SMSC_FDC37M81X_H_ +#define _SMSC_FDC37M81X_H_ + +/* Common Registers */ +#define SMSC_FDC37M81X_CONFIG_INDEX 0x00 +#define SMSC_FDC37M81X_CONFIG_DATA 0x01 +#define SMSC_FDC37M81X_CONF 0x02 +#define SMSC_FDC37M81X_INDEX 0x03 +#define SMSC_FDC37M81X_DNUM 0x07 +#define SMSC_FDC37M81X_DID 0x20 +#define SMSC_FDC37M81X_DREV 0x21 +#define SMSC_FDC37M81X_PCNT 0x22 +#define SMSC_FDC37M81X_PMGT 0x23 +#define SMSC_FDC37M81X_OSC 0x24 +#define SMSC_FDC37M81X_CONFPA0 0x26 +#define SMSC_FDC37M81X_CONFPA1 0x27 +#define SMSC_FDC37M81X_TEST4 0x2B +#define SMSC_FDC37M81X_TEST5 0x2C +#define SMSC_FDC37M81X_TEST1 0x2D +#define SMSC_FDC37M81X_TEST2 0x2E +#define SMSC_FDC37M81X_TEST3 0x2F + +/* Logical device numbers */ +#define SMSC_FDC37M81X_FDD 0x00 +#define SMSC_FDC37M81X_PARALLEL 0x03 +#define SMSC_FDC37M81X_SERIAL1 0x04 +#define SMSC_FDC37M81X_SERIAL2 0x05 +#define SMSC_FDC37M81X_KBD 0x07 +#define SMSC_FDC37M81X_AUXIO 0x08 +#define SMSC_FDC37M81X_NONE 0xff + +/* Logical device Config Registers */ +#define SMSC_FDC37M81X_ACTIVE 0x30 +#define SMSC_FDC37M81X_BASEADDR0 0x60 +#define SMSC_FDC37M81X_BASEADDR1 0x61 +#define SMSC_FDC37M81X_INT 0x70 +#define SMSC_FDC37M81X_INT2 0x72 +#define SMSC_FDC37M81X_LDCR_F0 0xF0 + +/* Chip Config Values */ +#define SMSC_FDC37M81X_CONFIG_ENTER 0x55 +#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa +#define SMSC_FDC37M81X_CHIP_ID 0x4d + +unsigned long __init smsc_fdc37m81x_init(unsigned long port); + +void smsc_fdc37m81x_config_beg(void); + +void smsc_fdc37m81x_config_end(void); + +void smsc_fdc37m81x_config_set(u8 reg, u8 val); + +#endif diff --git a/include/asm-mips/txx9/spi.h b/include/asm-mips/txx9/spi.h new file mode 100644 index 000000000000..ddfb2a0dc432 --- /dev/null +++ b/include/asm-mips/txx9/spi.h @@ -0,0 +1,19 @@ +/* + * Definitions for TX4937/TX4938 SPI + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_SPI_H +#define __ASM_TXX9_SPI_H + +extern int spi_eeprom_register(int chipid); +extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); + +#endif /* __ASM_TXX9_SPI_H */ diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h new file mode 100644 index 000000000000..63b62d6061f5 --- /dev/null +++ b/include/asm-mips/txx9/tx3927.h @@ -0,0 +1,319 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Toshiba Corporation + */ +#ifndef __ASM_TXX9_TX3927_H +#define __ASM_TXX9_TX3927_H + +#include + +#define TX3927_SDRAMC_REG 0xfffe8000 +#define TX3927_ROMC_REG 0xfffe9000 +#define TX3927_DMA_REG 0xfffeb000 +#define TX3927_IRC_REG 0xfffec000 +#define TX3927_PCIC_REG 0xfffed000 +#define TX3927_CCFG_REG 0xfffee000 +#define TX3927_NR_TMR 3 +#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) +#define TX3927_NR_SIO 2 +#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) +#define TX3927_PIO_REG 0xfffef500 + +struct tx3927_sdramc_reg { + volatile unsigned long cr[8]; + volatile unsigned long tr[3]; + volatile unsigned long cmd; + volatile unsigned long smrs[2]; +}; + +struct tx3927_romc_reg { + volatile unsigned long cr[8]; +}; + +struct tx3927_dma_reg { + struct tx3927_dma_ch_reg { + volatile unsigned long cha; + volatile unsigned long sar; + volatile unsigned long dar; + volatile unsigned long cntr; + volatile unsigned long sair; + volatile unsigned long dair; + volatile unsigned long ccr; + volatile unsigned long csr; + } ch[4]; + volatile unsigned long dbr[8]; + volatile unsigned long tdhr; + volatile unsigned long mcr; + volatile unsigned long unused0; +}; + +#include + +#ifdef __BIG_ENDIAN +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 +#else +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 +#endif + +struct tx3927_pcic_reg { + endian_def_s2(did, vid); + endian_def_s2(pcistat, pcicmd); + endian_def_b4(cc, scc, rpli, rid); + endian_def_b4(unused0, ht, mlt, cls); + volatile unsigned long ioba; /* +10 */ + volatile unsigned long mba; + volatile unsigned long unused1[5]; + endian_def_s2(svid, ssvid); + volatile unsigned long unused2; /* +30 */ + endian_def_sb2(unused3, unused4, capptr); + volatile unsigned long unused5; + endian_def_b4(ml, mg, ip, il); + volatile unsigned long unused6; /* +40 */ + volatile unsigned long istat; + volatile unsigned long iim; + volatile unsigned long rrt; + volatile unsigned long unused7[3]; /* +50 */ + volatile unsigned long ipbmma; + volatile unsigned long ipbioma; /* +60 */ + volatile unsigned long ilbmma; + volatile unsigned long ilbioma; + volatile unsigned long unused8[9]; + volatile unsigned long tc; /* +90 */ + volatile unsigned long tstat; + volatile unsigned long tim; + volatile unsigned long tccmd; + volatile unsigned long pcirrt; /* +a0 */ + volatile unsigned long pcirrt_cmd; + volatile unsigned long pcirrdt; + volatile unsigned long unused9[3]; + volatile unsigned long tlboap; + volatile unsigned long tlbiap; + volatile unsigned long tlbmma; /* +c0 */ + volatile unsigned long tlbioma; + volatile unsigned long sc_msg; + volatile unsigned long sc_be; + volatile unsigned long tbl; /* +d0 */ + volatile unsigned long unused10[3]; + volatile unsigned long pwmng; /* +e0 */ + volatile unsigned long pwmngs; + volatile unsigned long unused11[6]; + volatile unsigned long req_trace; /* +100 */ + volatile unsigned long pbapmc; + volatile unsigned long pbapms; + volatile unsigned long pbapmim; + volatile unsigned long bm; /* +110 */ + volatile unsigned long cpcibrs; + volatile unsigned long cpcibgs; + volatile unsigned long pbacs; + volatile unsigned long iobas; /* +120 */ + volatile unsigned long mbas; + volatile unsigned long lbc; + volatile unsigned long lbstat; + volatile unsigned long lbim; /* +130 */ + volatile unsigned long pcistatim; + volatile unsigned long ica; + volatile unsigned long icd; + volatile unsigned long iiadp; /* +140 */ + volatile unsigned long iscdp; + volatile unsigned long mmas; + volatile unsigned long iomas; + volatile unsigned long ipciaddr; /* +150 */ + volatile unsigned long ipcidata; + volatile unsigned long ipcibe; +}; + +struct tx3927_ccfg_reg { + volatile unsigned long ccfg; + volatile unsigned long crir; + volatile unsigned long pcfg; + volatile unsigned long tear; + volatile unsigned long pdcr; +}; + +/* + * SDRAMC + */ + +/* + * ROMC + */ + +/* + * DMA + */ +/* bits for MCR */ +#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) +#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) +#define TX3927_DMA_MCR_RSFIF 0x00000080 +#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) +#define TX3927_DMA_MCR_LE 0x00000004 +#define TX3927_DMA_MCR_RPRT 0x00000002 +#define TX3927_DMA_MCR_MSTEN 0x00000001 + +/* bits for CCRn */ +#define TX3927_DMA_CCR_DBINH 0x04000000 +#define TX3927_DMA_CCR_SBINH 0x02000000 +#define TX3927_DMA_CCR_CHRST 0x01000000 +#define TX3927_DMA_CCR_RVBYTE 0x00800000 +#define TX3927_DMA_CCR_ACKPOL 0x00400000 +#define TX3927_DMA_CCR_REQPL 0x00200000 +#define TX3927_DMA_CCR_EGREQ 0x00100000 +#define TX3927_DMA_CCR_CHDN 0x00080000 +#define TX3927_DMA_CCR_DNCTL 0x00060000 +#define TX3927_DMA_CCR_EXTRQ 0x00010000 +#define TX3927_DMA_CCR_INTRQD 0x0000e000 +#define TX3927_DMA_CCR_INTENE 0x00001000 +#define TX3927_DMA_CCR_INTENC 0x00000800 +#define TX3927_DMA_CCR_INTENT 0x00000400 +#define TX3927_DMA_CCR_CHNEN 0x00000200 +#define TX3927_DMA_CCR_XFACT 0x00000100 +#define TX3927_DMA_CCR_SNOP 0x00000080 +#define TX3927_DMA_CCR_DSTINC 0x00000040 +#define TX3927_DMA_CCR_SRCINC 0x00000020 +#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) +#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) +#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) +#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) +#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) +#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) +#define TX3927_DMA_CCR_MEMIO 0x00000002 +#define TX3927_DMA_CCR_ONEAD 0x00000001 + +/* bits for CSRn */ +#define TX3927_DMA_CSR_CHNACT 0x00000100 +#define TX3927_DMA_CSR_ABCHC 0x00000080 +#define TX3927_DMA_CSR_NCHNC 0x00000040 +#define TX3927_DMA_CSR_NTRNFC 0x00000020 +#define TX3927_DMA_CSR_EXTDN 0x00000010 +#define TX3927_DMA_CSR_CFERR 0x00000008 +#define TX3927_DMA_CSR_CHERR 0x00000004 +#define TX3927_DMA_CSR_DESERR 0x00000002 +#define TX3927_DMA_CSR_SORERR 0x00000001 + +/* + * IRC + */ +#define TX3927_IR_INT0 0 +#define TX3927_IR_INT1 1 +#define TX3927_IR_INT2 2 +#define TX3927_IR_INT3 3 +#define TX3927_IR_INT4 4 +#define TX3927_IR_INT5 5 +#define TX3927_IR_SIO0 6 +#define TX3927_IR_SIO1 7 +#define TX3927_IR_SIO(ch) (6 + (ch)) +#define TX3927_IR_DMA 8 +#define TX3927_IR_PIO 9 +#define TX3927_IR_PCI 10 +#define TX3927_IR_TMR(ch) (13 + (ch)) +#define TX3927_NUM_IR 16 + +/* + * PCIC + */ +/* bits for PCICMD */ +/* see PCI_COMMAND_XXX in linux/pci.h */ + +/* bits for PCISTAT */ +/* see PCI_STATUS_XXX in linux/pci.h */ +#define PCI_STATUS_NEW_CAP 0x0010 + +/* bits for TC */ +#define TX3927_PCIC_TC_OF16E 0x00000020 +#define TX3927_PCIC_TC_IF8E 0x00000010 +#define TX3927_PCIC_TC_OF8E 0x00000008 + +/* bits for IOBA/MBA */ +/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ + +/* bits for PBAPMC */ +#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 +#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 +#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 + +/* bits for LBSTAT/LBIM */ +#define TX3927_PCIC_LBIM_ALL 0x0000003e + +/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 + +/* bits for LBC */ +#define TX3927_PCIC_LBC_IBSE 0x00004000 +#define TX3927_PCIC_LBC_TIBSE 0x00002000 +#define TX3927_PCIC_LBC_TMFBSE 0x00001000 +#define TX3927_PCIC_LBC_HRST 0x00000800 +#define TX3927_PCIC_LBC_SRST 0x00000400 +#define TX3927_PCIC_LBC_EPCAD 0x00000200 +#define TX3927_PCIC_LBC_MSDSE 0x00000100 +#define TX3927_PCIC_LBC_CRR 0x00000080 +#define TX3927_PCIC_LBC_ILMDE 0x00000040 +#define TX3927_PCIC_LBC_ILIDE 0x00000020 + +#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX3927_CCFG_TLBOFF 0x00020000 +#define TX3927_CCFG_BEOW 0x00010000 +#define TX3927_CCFG_WR 0x00008000 +#define TX3927_CCFG_TOE 0x00004000 +#define TX3927_CCFG_PCIXARB 0x00002000 +#define TX3927_CCFG_PCI3 0x00001000 +#define TX3927_CCFG_PSNP 0x00000800 +#define TX3927_CCFG_PPRI 0x00000400 +#define TX3927_CCFG_PLLM 0x00000030 +#define TX3927_CCFG_ENDIAN 0x00000004 +#define TX3927_CCFG_HALT 0x00000002 +#define TX3927_CCFG_ACEHOLD 0x00000001 + +/* PCFG : Pin Configuration */ +#define TX3927_PCFG_SYSCLKEN 0x08000000 +#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 +#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) +#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 +#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) +#define TX3927_PCFG_SELALL 0x0003ffff +#define TX3927_PCFG_SELCS 0x00020000 +#define TX3927_PCFG_SELDSF 0x00010000 +#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 +#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) +#define TX3927_PCFG_SELSIO_ALL 0x00003000 +#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) +#define TX3927_PCFG_SELTMR_ALL 0x00000e00 +#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) +#define TX3927_PCFG_SELDONE 0x00000100 +#define TX3927_PCFG_INTDMA_ALL 0x000000f0 +#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) +#define TX3927_PCFG_SELDMA_ALL 0x0000000f +#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) + +#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) +#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) +#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) +#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) +#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) +#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) +#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) +#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) + +#endif /* __ASM_TXX9_TX3927_H */ diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h new file mode 100644 index 000000000000..f21a7b1831e5 --- /dev/null +++ b/include/asm-mips/txx9/tx4927.h @@ -0,0 +1,280 @@ +/* + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2006 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_TXX9_TX4927_H +#define __ASM_TXX9_TX4927_H + +#include + +#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE +#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) + +#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE +#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) + + +#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) +#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) +#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) +#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) + +#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) + +#define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_WR 0x00008000 +#define TX4927_CCFG_TINTDIS 0x01000000 + +#define TX4927_PCIMEM 0x08000000 +#define TX4927_PCIMEM_SIZE 0x08000000 +#define TX4927_PCIIO 0x16000000 +#define TX4927_PCIIO_SIZE 0x01000000 + +#define TX4927_SDRAMC_REG 0xff1f8000 +#define TX4927_EBUSC_REG 0xff1f9000 +#define TX4927_PCIC_REG 0xff1fd000 +#define TX4927_CCFG_REG 0xff1fe000 +#define TX4927_IRC_REG 0xff1ff600 +#define TX4927_NR_TMR 3 +#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) + +/* bits for ISTAT3/IMASK3/IMSTAT3 */ +#define TX4927_INT3B_PCID 0 +#define TX4927_INT3B_PCIC 1 +#define TX4927_INT3B_PCIB 2 +#define TX4927_INT3B_PCIA 3 +#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) +#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) +#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) +#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) + +#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG +#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ + +#define TX4927_IR_PCIC 16 +#define TX4927_IR_PCIERR 22 +#define TX4927_IR_PCIPMA 23 +#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) +#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) +#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) +#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) +#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) +#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) +#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) + +#ifdef _LANGUAGE_ASSEMBLY +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +struct tx4927_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; +}; + +struct tx4927_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4927_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; +}; + +struct tx4927_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmcut; + volatile unsigned long long pdmcnt; /* +220 */ + volatile unsigned long long pdmsts; + volatile unsigned long long unused8[2]; + volatile unsigned long long pdmdb[4]; /* +240 */ + volatile unsigned long long pdmtdh; /* +260 */ + volatile unsigned long long pdmdms; +}; + +#endif /* _LANGUAGE_ASSEMBLY */ + +/* + * PCIC + */ + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4927_PCIC_PBACFG_RPBA 0x00000004 +#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc + +/* bits for PCICCFG */ +#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 +#define TX4927_PCIC_PCICCFG_HRST 0x00000800 +#define TX4927_PCIC_PCICCFG_SRST 0x00000400 +#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 +#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 +#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 +#define TX4927_PCIC_PCICCFG_IISE 0x00000020 +#define TX4927_PCIC_PCICCFG_ATR 0x00000010 +#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4927_CCFG_PCI66 0x00800000 +#define TX4927_CCFG_PCIMIDE 0x00400000 +#define TX4927_CCFG_PCIXARB 0x00002000 +#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 +#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 +#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 +#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 +#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 + +#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 +#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 +#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 +#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 +#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 +#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 +#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 + +/* PCFG : Pin Configuration */ +#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) + +/* CLKCTR : Clock Control */ +#define TX4927_CLKCTR_PCICKD 0x00400000 +#define TX4927_CLKCTR_PCIRST 0x00000040 + +#ifndef _LANGUAGE_ASSEMBLY + +#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) +#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) +#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) +#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) + +#endif /* _LANGUAGE_ASSEMBLY */ + +#endif /* __ASM_TXX9_TX4927_H */ diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h new file mode 100644 index 000000000000..7f9cfef1c6d2 --- /dev/null +++ b/include/asm-mips/txx9/tx4938.h @@ -0,0 +1,627 @@ +/* + * Definitions for TX4937/TX4938 + * Copyright (C) 2000-2001 Toshiba Corporation + * + * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) + */ +#ifndef __ASM_TXX9_TX4938_H +#define __ASM_TXX9_TX4938_H + +#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) +#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) + +#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG + +#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) +#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) + +#define TX4938_PCIIO_0 0x10000000 +#define TX4938_PCIIO_1 0x01010000 +#define TX4938_PCIMEM_0 0x08000000 +#define TX4938_PCIMEM_1 0x11000000 + +#define TX4938_PCIIO_SIZE_0 0x01000000 +#define TX4938_PCIIO_SIZE_1 0x00010000 +#define TX4938_PCIMEM_SIZE_0 0x08000000 +#define TX4938_PCIMEM_SIZE_1 0x00010000 + +#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ +#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ + +/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ +#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000) +#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000) +#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000) +#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000) +#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000) +#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) +#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000) +#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000) +#define TX4938_NR_TMR 3 +#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) +#define TX4938_NR_SIO 2 +#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) +#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500) +#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600) +#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) +#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) + +#ifdef __ASSEMBLY__ +#define _CONST64(c) c +#else +#define _CONST64(c) c##ull + +#include + +#ifdef __BIG_ENDIAN +#define endian_def_l2(e1, e2) \ + volatile unsigned long e1, e2 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e1, e2 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned short e1;volatile unsigned char e2, e3 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned char e1, e2;volatile unsigned short e3 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e1, e2, e3, e4 +#else +#define endian_def_l2(e1, e2) \ + volatile unsigned long e2, e1 +#define endian_def_s2(e1, e2) \ + volatile unsigned short e2, e1 +#define endian_def_sb2(e1, e2, e3) \ + volatile unsigned char e3, e2;volatile unsigned short e1 +#define endian_def_b2s(e1, e2, e3) \ + volatile unsigned short e3;volatile unsigned char e2, e1 +#define endian_def_b4(e1, e2, e3, e4) \ + volatile unsigned char e4, e3, e2, e1 +#endif + + +struct tx4938_sdramc_reg { + volatile unsigned long long cr[4]; + volatile unsigned long long unused0[4]; + volatile unsigned long long tr; + volatile unsigned long long unused1[2]; + volatile unsigned long long cmd; + volatile unsigned long long sfcmd; +}; + +struct tx4938_ebusc_reg { + volatile unsigned long long cr[8]; +}; + +struct tx4938_dma_reg { + struct tx4938_dma_ch_reg { + volatile unsigned long long cha; + volatile unsigned long long sar; + volatile unsigned long long dar; + endian_def_l2(unused0, cntr); + endian_def_l2(unused1, sair); + endian_def_l2(unused2, dair); + endian_def_l2(unused3, ccr); + endian_def_l2(unused4, csr); + } ch[4]; + volatile unsigned long long dbr[8]; + volatile unsigned long long tdhr; + volatile unsigned long long midr; + endian_def_l2(unused0, mcr); +}; + +struct tx4938_pcic_reg { + volatile unsigned long pciid; + volatile unsigned long pcistatus; + volatile unsigned long pciccrev; + volatile unsigned long pcicfg1; + volatile unsigned long p2gm0plbase; /* +10 */ + volatile unsigned long p2gm0pubase; + volatile unsigned long p2gm1plbase; + volatile unsigned long p2gm1pubase; + volatile unsigned long p2gm2pbase; /* +20 */ + volatile unsigned long p2giopbase; + volatile unsigned long unused0; + volatile unsigned long pcisid; + volatile unsigned long unused1; /* +30 */ + volatile unsigned long pcicapptr; + volatile unsigned long unused2; + volatile unsigned long pcicfg2; + volatile unsigned long g2ptocnt; /* +40 */ + volatile unsigned long unused3[15]; + volatile unsigned long g2pstatus; /* +80 */ + volatile unsigned long g2pmask; + volatile unsigned long pcisstatus; + volatile unsigned long pcimask; + volatile unsigned long p2gcfg; /* +90 */ + volatile unsigned long p2gstatus; + volatile unsigned long p2gmask; + volatile unsigned long p2gccmd; + volatile unsigned long unused4[24]; /* +a0 */ + volatile unsigned long pbareqport; /* +100 */ + volatile unsigned long pbacfg; + volatile unsigned long pbastatus; + volatile unsigned long pbamask; + volatile unsigned long pbabm; /* +110 */ + volatile unsigned long pbacreq; + volatile unsigned long pbacgnt; + volatile unsigned long pbacstate; + volatile unsigned long long g2pmgbase[3]; /* +120 */ + volatile unsigned long long g2piogbase; + volatile unsigned long g2pmmask[3]; /* +140 */ + volatile unsigned long g2piomask; + volatile unsigned long long g2pmpbase[3]; /* +150 */ + volatile unsigned long long g2piopbase; + volatile unsigned long pciccfg; /* +170 */ + volatile unsigned long pcicstatus; + volatile unsigned long pcicmask; + volatile unsigned long unused5; + volatile unsigned long long p2gmgbase[3]; /* +180 */ + volatile unsigned long long p2giogbase; + volatile unsigned long g2pcfgadrs; /* +1a0 */ + volatile unsigned long g2pcfgdata; + volatile unsigned long unused6[8]; + volatile unsigned long g2pintack; + volatile unsigned long g2pspc; + volatile unsigned long unused7[12]; /* +1d0 */ + volatile unsigned long long pdmca; /* +200 */ + volatile unsigned long long pdmga; + volatile unsigned long long pdmpa; + volatile unsigned long long pdmctr; + volatile unsigned long long pdmcfg; /* +220 */ + volatile unsigned long long pdmsts; +}; + +struct tx4938_aclc_reg { + volatile unsigned long acctlen; + volatile unsigned long acctldis; + volatile unsigned long acregacc; + volatile unsigned long unused0; + volatile unsigned long acintsts; + volatile unsigned long acintmsts; + volatile unsigned long acinten; + volatile unsigned long acintdis; + volatile unsigned long acsemaph; + volatile unsigned long unused1[7]; + volatile unsigned long acgpidat; + volatile unsigned long acgpodat; + volatile unsigned long acslten; + volatile unsigned long acsltdis; + volatile unsigned long acfifosts; + volatile unsigned long unused2[11]; + volatile unsigned long acdmasts; + volatile unsigned long acdmasel; + volatile unsigned long unused3[6]; + volatile unsigned long acaudodat; + volatile unsigned long acsurrdat; + volatile unsigned long accentdat; + volatile unsigned long aclfedat; + volatile unsigned long acaudiat; + volatile unsigned long unused4; + volatile unsigned long acmodoat; + volatile unsigned long acmodidat; + volatile unsigned long unused5[15]; + volatile unsigned long acrevid; +}; + + +struct tx4938_tmr_reg { + volatile unsigned long tcr; + volatile unsigned long tisr; + volatile unsigned long cpra; + volatile unsigned long cprb; + volatile unsigned long itmr; + volatile unsigned long unused0[3]; + volatile unsigned long ccdr; + volatile unsigned long unused1[3]; + volatile unsigned long pgmr; + volatile unsigned long unused2[3]; + volatile unsigned long wtmr; + volatile unsigned long unused3[43]; + volatile unsigned long trr; +}; + +struct tx4938_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +struct tx4938_ndfmc_reg { + endian_def_l2(unused0, dtr); + endian_def_l2(unused1, mcr); + endian_def_l2(unused2, sr); + endian_def_l2(unused3, isr); + endian_def_l2(unused4, imr); + endian_def_l2(unused5, spr); + endian_def_l2(unused6, rstr); +}; + +struct tx4938_spi_reg { + volatile unsigned long mcr; + volatile unsigned long cr0; + volatile unsigned long cr1; + volatile unsigned long fs; + volatile unsigned long unused1; + volatile unsigned long sr; + volatile unsigned long dr; + volatile unsigned long unused2; +}; + +struct tx4938_sramc_reg { + volatile unsigned long long cr; +}; + +struct tx4938_ccfg_reg { + volatile unsigned long long ccfg; + volatile unsigned long long crir; + volatile unsigned long long pcfg; + volatile unsigned long long tear; + volatile unsigned long long clkctr; + volatile unsigned long long unused0; + volatile unsigned long long garbc; + volatile unsigned long long unused1; + volatile unsigned long long unused2; + volatile unsigned long long ramp; + volatile unsigned long long unused3; + volatile unsigned long long jmpadr; +}; + +#undef endian_def_l2 +#undef endian_def_s2 +#undef endian_def_sb2 +#undef endian_def_b2s +#undef endian_def_b4 + +#endif /* __ASSEMBLY__ */ + +/* + * NDFMC + */ + +/* NDFMCR : NDFMC Mode Control */ +#define TX4938_NDFMCR_WE 0x80 +#define TX4938_NDFMCR_ECC_ALL 0x60 +#define TX4938_NDFMCR_ECC_RESET 0x60 +#define TX4938_NDFMCR_ECC_READ 0x40 +#define TX4938_NDFMCR_ECC_ON 0x20 +#define TX4938_NDFMCR_ECC_OFF 0x00 +#define TX4938_NDFMCR_CE 0x10 +#define TX4938_NDFMCR_BSPRT 0x04 +#define TX4938_NDFMCR_ALE 0x02 +#define TX4938_NDFMCR_CLE 0x01 + +/* NDFMCR : NDFMC Status */ +#define TX4938_NDFSR_BUSY 0x80 + +/* NDFMCR : NDFMC Reset */ +#define TX4938_NDFRSTR_RST 0x01 + +/* + * IRC + */ + +#define TX4938_IR_ECCERR 0 +#define TX4938_IR_WTOERR 1 +#define TX4938_NUM_IR_INT 6 +#define TX4938_IR_INT(n) (2 + (n)) +#define TX4938_NUM_IR_SIO 2 +#define TX4938_IR_SIO(n) (8 + (n)) +#define TX4938_NUM_IR_DMA 4 +#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ +#define TX4938_IR_PIO 14 +#define TX4938_IR_PDMAC 15 +#define TX4938_IR_PCIC 16 +#define TX4938_NUM_IR_TMR 3 +#define TX4938_IR_TMR(n) (17 + (n)) +#define TX4938_IR_NDFMC 21 +#define TX4938_IR_PCIERR 22 +#define TX4938_IR_PCIPME 23 +#define TX4938_IR_ACLC 24 +#define TX4938_IR_ACLCPME 25 +#define TX4938_IR_PCIC1 26 +#define TX4938_IR_SPI 31 +#define TX4938_NUM_IR 32 +/* multiplex */ +#define TX4938_IR_ETH0 TX4938_IR_INT(4) +#define TX4938_IR_ETH1 TX4938_IR_INT(3) + +/* + * CCFG + */ +/* CCFG : Chip Configuration */ +#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) +#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) +#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) +#define TX4938_CCFG_TINTDIS 0x01000000 +#define TX4938_CCFG_PCI66 0x00800000 +#define TX4938_CCFG_PCIMODE 0x00400000 +#define TX4938_CCFG_PCI1_66 0x00200000 +#define TX4938_CCFG_DIVMODE_MASK 0x001e0000 +#define TX4938_CCFG_DIVMODE_2 (0x4 << 17) +#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17) +#define TX4938_CCFG_DIVMODE_3 (0x5 << 17) +#define TX4938_CCFG_DIVMODE_4 (0x6 << 17) +#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17) +#define TX4938_CCFG_DIVMODE_8 (0x0 << 17) +#define TX4938_CCFG_DIVMODE_10 (0xb << 17) +#define TX4938_CCFG_DIVMODE_12 (0x1 << 17) +#define TX4938_CCFG_DIVMODE_16 (0x2 << 17) +#define TX4938_CCFG_DIVMODE_18 (0x9 << 17) +#define TX4938_CCFG_BEOW 0x00010000 +#define TX4938_CCFG_WR 0x00008000 +#define TX4938_CCFG_TOE 0x00004000 +#define TX4938_CCFG_PCIXARB 0x00002000 +#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) +#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) +#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10) +#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10) +#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10) +#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10) +#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10) +#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10) +#define TX4938_CCFG_PCI1DMD 0x00000100 +#define TX4938_CCFG_SYSSP_MASK 0x000000c0 +#define TX4938_CCFG_ENDIAN 0x00000004 +#define TX4938_CCFG_HALT 0x00000002 +#define TX4938_CCFG_ACEHOLD 0x00000001 + +/* PCFG : Pin Configuration */ +#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) +#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) +#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) +#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) +#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) +#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) +#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 +#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4938_PCFG_SYSCLKEN 0x08000000 +#define TX4938_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) +#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000 +#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) +#define TX4938_PCFG_SEL2 0x00000200 +#define TX4938_PCFG_SEL1 0x00000100 +#define TX4938_PCFG_DMASEL_ALL 0x0000000f +#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000 +#define TX4938_PCFG_DMASEL0_SIO1 0x00000001 +#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000 +#define TX4938_PCFG_DMASEL1_SIO1 0x00000002 +#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000 +#define TX4938_PCFG_DMASEL2_SIO0 0x00000004 +#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000 +#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 + +/* CLKCTR : Clock Control */ +#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) +#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) +#define TX4938_CLKCTR_ETH1CKD 0x80000000 +#define TX4938_CLKCTR_ETH0CKD 0x40000000 +#define TX4938_CLKCTR_SPICKD 0x20000000 +#define TX4938_CLKCTR_SRAMCKD 0x10000000 +#define TX4938_CLKCTR_PCIC1CKD 0x08000000 +#define TX4938_CLKCTR_DMA1CKD 0x04000000 +#define TX4938_CLKCTR_ACLCKD 0x02000000 +#define TX4938_CLKCTR_PIOCKD 0x01000000 +#define TX4938_CLKCTR_DMACKD 0x00800000 +#define TX4938_CLKCTR_PCICKD 0x00400000 +#define TX4938_CLKCTR_TM0CKD 0x00100000 +#define TX4938_CLKCTR_TM1CKD 0x00080000 +#define TX4938_CLKCTR_TM2CKD 0x00040000 +#define TX4938_CLKCTR_SIO0CKD 0x00020000 +#define TX4938_CLKCTR_SIO1CKD 0x00010000 +#define TX4938_CLKCTR_ETH1RST 0x00008000 +#define TX4938_CLKCTR_ETH0RST 0x00004000 +#define TX4938_CLKCTR_SPIRST 0x00002000 +#define TX4938_CLKCTR_SRAMRST 0x00001000 +#define TX4938_CLKCTR_PCIC1RST 0x00000800 +#define TX4938_CLKCTR_DMA1RST 0x00000400 +#define TX4938_CLKCTR_ACLRST 0x00000200 +#define TX4938_CLKCTR_PIORST 0x00000100 +#define TX4938_CLKCTR_DMARST 0x00000080 +#define TX4938_CLKCTR_PCIRST 0x00000040 +#define TX4938_CLKCTR_TM0RST 0x00000010 +#define TX4938_CLKCTR_TM1RST 0x00000008 +#define TX4938_CLKCTR_TM2RST 0x00000004 +#define TX4938_CLKCTR_SIO0RST 0x00000002 +#define TX4938_CLKCTR_SIO1RST 0x00000001 + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ +#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 +#define TX4938_PCIC_PBACFG_RPBA 0x00000004 +#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for G2PIOGBASE */ +#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 +#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 +#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 +#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 +#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 +#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 +#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 +#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 +#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 +#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 + +/* bits for PCICCFG */ +#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 +#define TX4938_PCIC_PCICCFG_HRST 0x00000800 +#define TX4938_PCIC_PCICCFG_SRST 0x00000400 +#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) +#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 +#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 +#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 +#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 +#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 +#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) + +/* bits for P2GIOGBASE */ +#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) +#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) +#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) + +#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) + +/* bits for PDMCFG */ +#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 +#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 +#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 +#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) +#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) +#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 +#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 +#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 +#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 +#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 +#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 +#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c +#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 +#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 +#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 +#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 +#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 + +/* bits for PDMSTS */ +#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 +#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 +#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 +#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 +#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 +#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 +#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 +#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 +#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 +#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 +#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 +#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 +#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 +#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 +#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 +#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 +#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f + +/* + * DMA + */ +/* bits for MCR */ +#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) +#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) +#define TX4938_DMA_MCR_RSFIF 0x00000080 +#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) +#define TX4938_DMA_MCR_RPRT 0x00000002 +#define TX4938_DMA_MCR_MSTEN 0x00000001 + +/* bits for CCRn */ +#define TX4938_DMA_CCR_IMMCHN 0x20000000 +#define TX4938_DMA_CCR_USEXFSZ 0x10000000 +#define TX4938_DMA_CCR_LE 0x08000000 +#define TX4938_DMA_CCR_DBINH 0x04000000 +#define TX4938_DMA_CCR_SBINH 0x02000000 +#define TX4938_DMA_CCR_CHRST 0x01000000 +#define TX4938_DMA_CCR_RVBYTE 0x00800000 +#define TX4938_DMA_CCR_ACKPOL 0x00400000 +#define TX4938_DMA_CCR_REQPL 0x00200000 +#define TX4938_DMA_CCR_EGREQ 0x00100000 +#define TX4938_DMA_CCR_CHDN 0x00080000 +#define TX4938_DMA_CCR_DNCTL 0x00060000 +#define TX4938_DMA_CCR_EXTRQ 0x00010000 +#define TX4938_DMA_CCR_INTRQD 0x0000e000 +#define TX4938_DMA_CCR_INTENE 0x00001000 +#define TX4938_DMA_CCR_INTENC 0x00000800 +#define TX4938_DMA_CCR_INTENT 0x00000400 +#define TX4938_DMA_CCR_CHNEN 0x00000200 +#define TX4938_DMA_CCR_XFACT 0x00000100 +#define TX4938_DMA_CCR_SMPCHN 0x00000020 +#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) +#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2) +#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3) +#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4) +#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5) +#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6) +#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7) +#define TX4938_DMA_CCR_MEMIO 0x00000002 +#define TX4938_DMA_CCR_SNGAD 0x00000001 + +/* bits for CSRn */ +#define TX4938_DMA_CSR_CHNEN 0x00000400 +#define TX4938_DMA_CSR_STLXFER 0x00000200 +#define TX4938_DMA_CSR_CHNACT 0x00000100 +#define TX4938_DMA_CSR_ABCHC 0x00000080 +#define TX4938_DMA_CSR_NCHNC 0x00000040 +#define TX4938_DMA_CSR_NTRNFC 0x00000020 +#define TX4938_DMA_CSR_EXTDN 0x00000010 +#define TX4938_DMA_CSR_CFERR 0x00000008 +#define TX4938_DMA_CSR_CHERR 0x00000004 +#define TX4938_DMA_CSR_DESERR 0x00000002 +#define TX4938_DMA_CSR_SORERR 0x00000001 + +#ifndef __ASSEMBLY__ + +#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) +#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) +#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) +#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) +#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) +#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) +#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) +#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) +#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) +#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) +#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) +#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) + + +#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) +#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) + +#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) +#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) + +#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) +#define TX4938_EBUSC_SIZE(ch) \ + (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) + + +#endif /* !__ASSEMBLY__ */ + +#endif diff --git a/include/asm-mips/txx9/txx927.h b/include/asm-mips/txx9/txx927.h new file mode 100644 index 000000000000..97dd7ad1a890 --- /dev/null +++ b/include/asm-mips/txx9/txx927.h @@ -0,0 +1,121 @@ +/* + * Common definitions for TX3927/TX4927 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Toshiba Corporation + */ +#ifndef __ASM_TXX9_TXX927_H +#define __ASM_TXX9_TXX927_H + +struct txx927_sio_reg { + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; +}; + +/* + * SIO + */ +/* SILCR : Line Control */ +#define TXx927_SILCR_SCS_MASK 0x00000060 +#define TXx927_SILCR_SCS_IMCLK 0x00000000 +#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020 +#define TXx927_SILCR_SCS_SCLK 0x00000040 +#define TXx927_SILCR_SCS_SCLK_BG 0x00000060 +#define TXx927_SILCR_UEPS 0x00000010 +#define TXx927_SILCR_UPEN 0x00000008 +#define TXx927_SILCR_USBL_MASK 0x00000004 +#define TXx927_SILCR_USBL_1BIT 0x00000004 +#define TXx927_SILCR_USBL_2BIT 0x00000000 +#define TXx927_SILCR_UMODE_MASK 0x00000003 +#define TXx927_SILCR_UMODE_8BIT 0x00000000 +#define TXx927_SILCR_UMODE_7BIT 0x00000001 + +/* SIDICR : DMA/Int. Control */ +#define TXx927_SIDICR_TDE 0x00008000 +#define TXx927_SIDICR_RDE 0x00004000 +#define TXx927_SIDICR_TIE 0x00002000 +#define TXx927_SIDICR_RIE 0x00001000 +#define TXx927_SIDICR_SPIE 0x00000800 +#define TXx927_SIDICR_CTSAC 0x00000600 +#define TXx927_SIDICR_STIE_MASK 0x0000003f +#define TXx927_SIDICR_STIE_OERS 0x00000020 +#define TXx927_SIDICR_STIE_CTSS 0x00000010 +#define TXx927_SIDICR_STIE_RBRKD 0x00000008 +#define TXx927_SIDICR_STIE_TRDY 0x00000004 +#define TXx927_SIDICR_STIE_TXALS 0x00000002 +#define TXx927_SIDICR_STIE_UBRKD 0x00000001 + +/* SIDISR : DMA/Int. Status */ +#define TXx927_SIDISR_UBRK 0x00008000 +#define TXx927_SIDISR_UVALID 0x00004000 +#define TXx927_SIDISR_UFER 0x00002000 +#define TXx927_SIDISR_UPER 0x00001000 +#define TXx927_SIDISR_UOER 0x00000800 +#define TXx927_SIDISR_ERI 0x00000400 +#define TXx927_SIDISR_TOUT 0x00000200 +#define TXx927_SIDISR_TDIS 0x00000100 +#define TXx927_SIDISR_RDIS 0x00000080 +#define TXx927_SIDISR_STIS 0x00000040 +#define TXx927_SIDISR_RFDN_MASK 0x0000001f + +/* SICISR : Change Int. Status */ +#define TXx927_SICISR_OERS 0x00000020 +#define TXx927_SICISR_CTSS 0x00000010 +#define TXx927_SICISR_RBRKD 0x00000008 +#define TXx927_SICISR_TRDY 0x00000004 +#define TXx927_SICISR_TXALS 0x00000002 +#define TXx927_SICISR_UBRKD 0x00000001 + +/* SIFCR : FIFO Control */ +#define TXx927_SIFCR_SWRST 0x00008000 +#define TXx927_SIFCR_RDIL_MASK 0x00000180 +#define TXx927_SIFCR_RDIL_1 0x00000000 +#define TXx927_SIFCR_RDIL_4 0x00000080 +#define TXx927_SIFCR_RDIL_8 0x00000100 +#define TXx927_SIFCR_RDIL_12 0x00000180 +#define TXx927_SIFCR_RDIL_MAX 0x00000180 +#define TXx927_SIFCR_TDIL_MASK 0x00000018 +#define TXx927_SIFCR_TDIL_MASK 0x00000018 +#define TXx927_SIFCR_TDIL_1 0x00000000 +#define TXx927_SIFCR_TDIL_4 0x00000001 +#define TXx927_SIFCR_TDIL_8 0x00000010 +#define TXx927_SIFCR_TDIL_MAX 0x00000010 +#define TXx927_SIFCR_TFRST 0x00000004 +#define TXx927_SIFCR_RFRST 0x00000002 +#define TXx927_SIFCR_FRSTE 0x00000001 +#define TXx927_SIO_TX_FIFO 8 +#define TXx927_SIO_RX_FIFO 16 + +/* SIFLCR : Flow Control */ +#define TXx927_SIFLCR_RCS 0x00001000 +#define TXx927_SIFLCR_TES 0x00000800 +#define TXx927_SIFLCR_RTSSC 0x00000200 +#define TXx927_SIFLCR_RSDE 0x00000100 +#define TXx927_SIFLCR_TSDE 0x00000080 +#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e +#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e +#define TXx927_SIFLCR_TBRK 0x00000001 + +/* SIBGR : Baudrate Control */ +#define TXx927_SIBGR_BCLK_MASK 0x00000300 +#define TXx927_SIBGR_BCLK_T0 0x00000000 +#define TXx927_SIBGR_BCLK_T2 0x00000100 +#define TXx927_SIBGR_BCLK_T4 0x00000200 +#define TXx927_SIBGR_BCLK_T6 0x00000300 +#define TXx927_SIBGR_BRD_MASK 0x000000ff + +/* + * PIO + */ + +#endif /* __ASM_TXX9_TXX927_H */ -- cgit v1.2.3 From 89d63fe179520b11f54de1f26755b7444c79e73a Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 11 Jul 2008 00:33:08 +0900 Subject: [MIPS] TXx9: Reorganize PCI code Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 +- arch/mips/pci/Makefile | 8 +- arch/mips/pci/fixup-jmr3927.c | 25 +- arch/mips/pci/fixup-rbtx4927.c | 112 ++----- arch/mips/pci/fixup-rbtx4938.c | 52 +-- arch/mips/pci/ops-tx3927.c | 87 ++++- arch/mips/pci/ops-tx4927.c | 514 +++++++++++++++++++--------- arch/mips/pci/ops-tx4938.c | 214 ------------ arch/mips/pci/pci-jmr3927.c | 58 ---- arch/mips/pci/pci-tx4927.c | 83 +++++ arch/mips/pci/pci-tx4938.c | 134 ++++++++ arch/mips/txx9/Kconfig | 11 +- arch/mips/txx9/generic/Makefile | 2 + arch/mips/txx9/generic/pci.c | 377 +++++++++++++++++++++ arch/mips/txx9/generic/setup.c | 51 +++ arch/mips/txx9/jmr3927/irq.c | 2 + arch/mips/txx9/jmr3927/setup.c | 108 ++---- arch/mips/txx9/rbtx4927/irq.c | 20 +- arch/mips/txx9/rbtx4927/setup.c | 499 +++++++-------------------- arch/mips/txx9/rbtx4938/setup.c | 667 ++++++------------------------------- include/asm-mips/txx9/generic.h | 23 ++ include/asm-mips/txx9/pci.h | 36 ++ include/asm-mips/txx9/rbtx4927.h | 29 +- include/asm-mips/txx9/tx3927.h | 4 + include/asm-mips/txx9/tx4927.h | 318 ++++++++---------- include/asm-mips/txx9/tx4927pcic.h | 199 +++++++++++ include/asm-mips/txx9/tx4938.h | 226 ++----------- 27 files changed, 1851 insertions(+), 2011 deletions(-) delete mode 100644 arch/mips/pci/ops-tx4938.c delete mode 100644 arch/mips/pci/pci-jmr3927.c create mode 100644 arch/mips/pci/pci-tx4927.c create mode 100644 arch/mips/pci/pci-tx4938.c create mode 100644 arch/mips/txx9/generic/pci.c create mode 100644 arch/mips/txx9/generic/setup.c create mode 100644 include/asm-mips/txx9/generic.h create mode 100644 include/asm-mips/txx9/pci.h create mode 100644 include/asm-mips/txx9/tx4927pcic.h (limited to 'include/asm-mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3202960f7597..2ea6fff88811 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -575,7 +575,7 @@ config TOSHIBA_RBTX4927 select HW_HAS_PCI select IRQ_CPU select IRQ_TXX9 - select I8259 if TOSHIBA_FPCIB0 + select PCI_TX4927 select SWAP_IO_SPACE select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL @@ -598,6 +598,7 @@ config TOSHIBA_RBTX4938 select HW_HAS_PCI select IRQ_CPU select IRQ_TXX9 + select PCI_TX4927 select SWAP_IO_SPACE select SYS_HAS_CPU_TX49XX select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 4608e43de28c..908764878ac8 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -15,6 +15,8 @@ obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o +obj-$(CONFIG_PCI_TX3927) += ops-tx3927.o +obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o # # These are still pretty much in the old state, watch, go blind. @@ -41,9 +43,9 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o -obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o -obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ops-tx4938.o +obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o +obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o pci-tx4927.o pci-tx4938.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o pci-tx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index 41dcd6a3aae5..d5edaf21e088 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -28,36 +28,31 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include -#include - +#include #include int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; - /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ - if (dev->vendor == PCI_VENDOR_ID_EFAR && - dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1) - return irq; /* IRQ rotation (PICMG) */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) { + if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) { /* PCI CardSlot (IDSEL=A23, DevNu=12) */ /* PCIA => PCIC (IDSEL=A23) */ /* NOTE: JMR3927 JP1 must be set to OPEN */ irq = (irq + 2) % 4; - } else if (dev->bus->parent == NULL && - slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { + } else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { /* PCI CardSlot (IDSEL=A22, DevNu=11) */ /* PCIA => PCIA (IDSEL=A22) */ /* NOTE: JMR3927 JP1 must be set to OPEN */ irq = (irq + 0) % 4; } else { /* PCI Backplane */ - irq = (irq + 3 + slot) % 4; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } irq++; /* 1-4 */ @@ -66,15 +61,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) irq = JMR3927_IRQ_IOC_PCIA; break; case 2: - // wrong for backplane irq = JMR3927_IRQ_IOC_PCIB; - irq = JMR3927_IRQ_IOC_PCID; + irq = JMR3927_IRQ_IOC_PCIB; break; case 3: irq = JMR3927_IRQ_IOC_PCIC; break; case 4: - // wrong for backplane irq = JMR3927_IRQ_IOC_PCID; - irq = JMR3927_IRQ_IOC_PCIB; + irq = JMR3927_IRQ_IOC_PCID; break; } diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 26013badfe1f..abab4852d158 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -33,102 +33,42 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include -#include -#include +#include +#include -#include - -#undef DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/* look up table for backplane pci irq for slots 17-20 by pin # */ -static unsigned char backplane_pci_irq[4][4] = { - /* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA, - /* PJ6 SLOT: 17, PIN: 2 */ - TX4927_IRQ_IOC_PCIB, - /* PJ6 SLOT: 17, PIN: 3 */ - TX4927_IRQ_IOC_PCIC, - /* PJ6 SLOT: 17, PIN: 4 */ - TX4927_IRQ_IOC_PCID}, - /* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB, - /* SB SLOT: 18, PIN: 2 */ - TX4927_IRQ_IOC_PCIC, - /* SB SLOT: 18, PIN: 3 */ - TX4927_IRQ_IOC_PCID, - /* SB SLOT: 18, PIN: 4 */ - TX4927_IRQ_IOC_PCIA}, - /* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC, - /* PJ5 SLOT: 19, PIN: 2 */ - TX4927_IRQ_IOC_PCID, - /* PJ5 SLOT: 19, PIN: 3 */ - TX4927_IRQ_IOC_PCIA, - /* PJ5 SLOT: 19, PIN: 4 */ - TX4927_IRQ_IOC_PCIB}, - /* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID, - /* PJ4 SLOT: 20, PIN: 2 */ - TX4927_IRQ_IOC_PCIA, - /* PJ4 SLOT: 20, PIN: 3 */ - TX4927_IRQ_IOC_PCIB, - /* PJ4 SLOT: 20, PIN: 4 */ - TX4927_IRQ_IOC_PCIC} -}; - -static int pci_get_irq(const struct pci_dev *dev, int pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; - DBG("pci_get_irq: pin is %d\n", pin); /* IRQ rotation */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { - printk("Onboard PCI_SLOT(dev->devfn) is %d\n", - PCI_SLOT(dev->devfn)); - /* IDSEL=A23 is tx4927 onboard pci slot */ - irq = (irq + PCI_SLOT(dev->devfn)) % 4; - irq++; /* 1-4 */ - DBG("irq is now %d\n", irq); - - switch (irq) { - case 1: - irq = TX4927_IRQ_IOC_PCIA; - break; - case 2: - irq = TX4927_IRQ_IOC_PCIB; - break; - case 3: - irq = TX4927_IRQ_IOC_PCIC; - break; - case 4: - irq = TX4927_IRQ_IOC_PCID; - break; - } + if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { + /* PCI CardSlot (IDSEL=A23) */ + /* PCIA => PCIA */ + irq = (irq + 0 + slot) % 4; } else { /* PCI Backplane */ - DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n", - PCI_SLOT(dev->devfn)); - irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq]; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } - DBG("assigned irq %d\n", irq); - return irq; -} - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq; - - printk("PCI Setup for pin %d \n", pin); - - if (dev->device == 0x9130) /* IDE */ - irq = 14; - else - irq = pci_get_irq(dev, pin); + irq++; /* 1-4 */ + switch (irq) { + case 1: + irq = RBTX4927_IRQ_IOC_PCIA; + break; + case 2: + irq = RBTX4927_IRQ_IOC_PCIB; + break; + case 3: + irq = RBTX4927_IRQ_IOC_PCIC; + break; + case 4: + irq = RBTX4927_IRQ_IOC_PCID; + break; + } return irq; } diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c index 64d4510c0265..39c995830384 100644 --- a/arch/mips/pci/fixup-rbtx4938.c +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -10,45 +10,28 @@ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) */ #include -#include -#include -#include - +#include #include -extern struct pci_controller tx4938_pci_controller[]; - -static int pci_get_irq(const struct pci_dev *dev, int pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { - int irq = pin; - u8 slot = PCI_SLOT(dev->devfn); - struct pci_controller *controller = (struct pci_controller *)dev->sysdata; - - if (controller == &tx4938_pci_controller[1]) { - /* TX4938 PCIC1 */ - switch (slot) { - case TX4938_PCIC_IDSEL_AD_TO_SLOT(31): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH0; - break; - case TX4938_PCIC_IDSEL_AD_TO_SLOT(30): - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL) - return RBTX4938_IRQ_IRC + TX4938_IR_ETH1; - break; - } - return 0; - } + int irq = tx4938_pcic1_map_irq(dev, slot); + if (irq >= 0) + return irq; + irq = pin; /* IRQ rotation */ irq--; /* 0-3 */ - if (dev->bus->parent == NULL && - (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) { + if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { /* PCI CardSlot (IDSEL=A23) */ /* PCIA => PCIA (IDSEL=A23) */ irq = (irq + 0 + slot) % 4; } else { /* PCI Backplane */ - irq = (irq + 33 - slot) % 4; + if (txx9_pci_option & TXX9_PCI_OPT_PICMG) + irq = (irq + 33 - slot) % 4; + else + irq = (irq + 3 + slot) % 4; } irq++; /* 1-4 */ @@ -69,19 +52,6 @@ static int pci_get_irq(const struct pci_dev *dev, int pin) return irq; } -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char irq = 0; - - irq = pci_get_irq(dev, pin); - - printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", - dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), irq); - - return irq; -} - /* * Do platform specific device initialization at pci_enable_device() time */ diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c index 5d398f694682..8a17a39e5bf2 100644 --- a/arch/mips/pci/ops-tx3927.c +++ b/arch/mips/pci/ops-tx3927.c @@ -8,7 +8,7 @@ * * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c * - * Define the pci_ops for JMR3927. + * Define the pci_ops for TX3927. * * Much of the code is derived from the original DDB5074 port by * Geert Uytterhoeven @@ -39,7 +39,7 @@ #include #include -#include +#include static inline int mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where) @@ -68,7 +68,7 @@ static inline int check_abort(void) return PCIBIOS_SUCCESSFUL; } -static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, +static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) { int ret; @@ -94,7 +94,7 @@ static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, return check_abort(); } -static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, +static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { int ret; @@ -125,7 +125,80 @@ static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, return check_abort(); } -struct pci_ops jmr3927_pci_ops = { - jmr3927_pci_read_config, - jmr3927_pci_write_config, +static struct pci_ops tx3927_pci_ops = { + .read = tx3927_pci_read_config, + .write = tx3927_pci_write_config, }; + +void __init tx3927_pcic_setup(struct pci_controller *channel, + unsigned long sdram_size, int extarb) +{ + unsigned long flags; + unsigned long io_base = + channel->io_resource->start + mips_io_port_base - IO_BASE; + unsigned long io_size = + channel->io_resource->end - channel->io_resource->start; + unsigned long io_pciaddr = + channel->io_resource->start - channel->io_offset; + unsigned long mem_base = + channel->mem_resource->start; + unsigned long mem_size = + channel->mem_resource->end - channel->mem_resource->start; + unsigned long mem_pciaddr = + channel->mem_resource->start - channel->mem_offset; + + printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s", + tx3927_pcicptr->did, tx3927_pcicptr->vid, + tx3927_pcicptr->rid, + extarb ? "External" : "Internal"); + channel->pci_ops = &tx3927_pci_ops; + + local_irq_save(flags); + /* Disable External PCI Config. Access */ + tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; +#ifdef __BIG_ENDIAN + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | + TX3927_PCIC_LBC_TIBSE | + TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; +#endif + /* LB->PCI mappings */ + tx3927_pcicptr->iomas = ~(io_size - 1); + tx3927_pcicptr->ilbioma = io_base; + tx3927_pcicptr->ipbioma = io_pciaddr; + tx3927_pcicptr->mmas = ~(mem_size - 1); + tx3927_pcicptr->ilbmma = mem_base; + tx3927_pcicptr->ipbmma = mem_pciaddr; + /* PCI->LB mappings */ + tx3927_pcicptr->iobas = 0xffffffff; + tx3927_pcicptr->ioba = 0; + tx3927_pcicptr->tlbioma = 0; + tx3927_pcicptr->mbas = ~(sdram_size - 1); + tx3927_pcicptr->mba = 0; + tx3927_pcicptr->tlbmma = 0; + /* Enable Direct mapping Address Space Decoder */ + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; + + /* Clear All Local Bus Status */ + tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; + /* Enable All Local Bus Interrupts */ + tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; + /* Clear All PCI Status Error */ + tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; + /* Enable All PCI Status Error Interrupts */ + tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; + + /* PCIC Int => IRC IRQ10 */ + tx3927_pcicptr->il = TX3927_IR_PCI; + /* Target Control (per errata) */ + tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; + + /* Enable Bus Arbiter */ + if (!extarb) + tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; + + tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | + PCI_COMMAND_IO | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + local_irq_restore(flags); +} diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 54730eee451b..c6b49bccd274 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -1,206 +1,408 @@ /* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com + * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc. * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c - * - * Define the pci_ops for the Toshiba rbtx4927 - * - * Much of the code is derived from the original DDB5074 port by - * Geert Uytterhoeven - * - * Copyright 2004 MontaVista Software Inc. - * Author: Manish Lachwani (mlachwani@mvista.com) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * Based on linux/arch/mips/pci/ops-tx4938.c, + * linux/arch/mips/pci/fixup-rbtx4938.c, + * linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * 2003-2005 (c) MontaVista Software, Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. */ -#include -#include #include -#include -#include - -/* initialize in setup */ -struct resource pci_io_resource = { - .name = "TX4927 PCI IO SPACE", - .start = 0x1000, - .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1, - .flags = IORESOURCE_IO -}; +#include -/* initialize in setup */ -struct resource pci_mem_resource = { - .name = "TX4927 PCI MEM SPACE", - .start = TX4927_PCIMEM, - .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; +static struct { + struct pci_controller *channel; + struct tx4927_pcic_reg __iomem *pcicptr; +} pcicptrs[2]; /* TX4938 has 2 pcic */ + +static void __init set_tx4927_pcicptr(struct pci_controller *channel, + struct tx4927_pcic_reg __iomem *pcicptr) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].channel == channel) { + pcicptrs[i].pcicptr = pcicptr; + return; + } + } + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (!pcicptrs[i].channel) { + pcicptrs[i].channel = channel; + pcicptrs[i].pcicptr = pcicptr; + return; + } + } + BUG(); +} -static int mkaddr(int bus, int dev_fn, int where, int *flagsp) +struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( + struct pci_controller *channel) { - if (bus > 0) { - /* Type 1 configuration */ - tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; - } else { - if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) - return -1; + int i; - /* Type 0 configuration */ - tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc); + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].channel == channel) + return pcicptrs[i].pcicptr; } + return NULL; +} + +static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, + struct tx4927_pcic_reg __iomem *pcicptr) +{ + if (bus->parent == NULL && + devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) + return -1; + __raw_writel(((bus->number & 0xff) << 0x10) + | ((devfn & 0xff) << 0x08) | (where & 0xfc) + | (bus->parent ? 1 : 0), + &pcicptr->g2pcfgadrs); /* clear M_ABORT and Disable M_ABORT Int. */ - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr->pcistatus & 0x0000ffff) | - (PCI_STATUS_REC_MASTER_ABORT << 16); - tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (PCI_STATUS_REC_MASTER_ABORT << 16), + &pcicptr->pcistatus); return 0; } -static int check_abort(int flags) +static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) { int code = PCIBIOS_SUCCESSFUL; - if (tx4927_pcicptr-> - pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr-> - pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT - << 16); - tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; + + /* wait write cycle completion before checking error status */ + while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) + ; + if (__raw_readl(&pcicptr->pcistatus) + & (PCI_STATUS_REC_MASTER_ABORT << 16)) { + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (PCI_STATUS_REC_MASTER_ABORT << 16), + &pcicptr->pcistatus); code = PCIBIOS_DEVICE_NOT_FOUND; } return code; } -static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 * val) +static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 3; +#endif + return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 2; +#endif + return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr) +{ + return __raw_readl(&pcicptr->g2pcfgdata); +} +static void icd_writeb(u8 val, int offset, + struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 3; +#endif + __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static void icd_writew(u16 val, int offset, + struct tx4927_pcic_reg __iomem *pcicptr) +{ +#ifdef __BIG_ENDIAN + offset ^= 2; +#endif + __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); +} +static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr) { - int flags, retval, dev, busno, func; + __raw_writel(val, &pcicptr->g2pcfgdata); +} - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); +static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus) +{ + struct pci_controller *channel = bus->sysdata; + return get_tx4927_pcicptr(channel); +} - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } +static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); - if (mkaddr(busno, devfn, where, &flags)) + if (mkaddr(bus, devfn, where, pcicptr)) { + *val = 0xffffffff; return -1; - + } switch (size) { case 1: - *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)); -#else - ((where & 0x3) ^ 0x3)); -#endif + *val = icd_readb(where & 3, pcicptr); break; case 2: - *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)); -#else - ((where & 0x3) ^ 0x2)); -#endif - break; - case 4: - *val = tx4927_pcicptr->g2pcfgdata; + *val = icd_readw(where & 3, pcicptr); break; + default: + *val = icd_readl(pcicptr); } + return check_abort(pcicptr); +} - retval = check_abort(flags); - if (retval == PCIBIOS_DEVICE_NOT_FOUND) - *val = 0xffffffff; +static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); - return retval; + if (mkaddr(bus, devfn, where, pcicptr)) + return -1; + switch (size) { + case 1: + icd_writeb(val, where & 3, pcicptr); + break; + case 2: + icd_writew(val, where & 3, pcicptr); + break; + default: + icd_writel(val, pcicptr); + } + return check_abort(pcicptr); } -static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) +static struct pci_ops tx4927_pci_ops = { + .read = tx4927_pci_config_read, + .write = tx4927_pci_config_write, +}; + +static struct { + u8 trdyto; + u8 retryto; + u16 gbwc; +} tx4927_pci_opts __devinitdata = { + .trdyto = 0, + .retryto = 0, + .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ +}; + +void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, + struct pci_controller *channel, int extarb) { - int flags, dev, busno, func; - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); + int i; + unsigned long flags; - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } + set_tx4927_pcicptr(channel, pcicptr); - if (mkaddr(busno, devfn, where, &flags)) - return -1; + if (!channel->pci_ops) + printk(KERN_INFO + "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + __raw_readl(&pcicptr->pciid) >> 16, + __raw_readl(&pcicptr->pciid) & 0xffff, + __raw_readl(&pcicptr->pciccrev) & 0xff, + extarb ? "External" : "Internal"); + channel->pci_ops = &tx4927_pci_ops; - switch (size) { - case 1: - *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)) = val; + local_irq_save(flags); + + /* Disable All Initiator Space */ + __raw_writel(__raw_readl(&pcicptr->pciccfg) + & ~(TX4927_PCIC_PCICCFG_G2PMEN(0) + | TX4927_PCIC_PCICCFG_G2PMEN(1) + | TX4927_PCIC_PCICCFG_G2PMEN(2) + | TX4927_PCIC_PCICCFG_G2PIOEN), + &pcicptr->pciccfg); + + /* GB->PCI mappings */ + __raw_writel((channel->io_resource->end - channel->io_resource->start) + >> 4, + &pcicptr->g2piomask); + ____raw_writeq((channel->io_resource->start + + channel->io_map_base - IO_BASE) | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PIOGBASE_ECHG #else - ((where & 0x3) ^ 0x3)) = val; + TX4927_PCIC_G2PIOGBASE_BSDIS #endif - break; - - case 2: - *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> - g2pcfgdata | -#ifdef __LITTLE_ENDIAN - (where & 3)) = val; + , &pcicptr->g2piogbase); + ____raw_writeq(channel->io_resource->start - channel->io_offset, + &pcicptr->g2piopbase); + for (i = 0; i < 3; i++) { + __raw_writel(0, &pcicptr->g2pmmask[i]); + ____raw_writeq(0, &pcicptr->g2pmgbase[i]); + ____raw_writeq(0, &pcicptr->g2pmpbase[i]); + } + if (channel->mem_resource->end) { + __raw_writel((channel->mem_resource->end + - channel->mem_resource->start) >> 4, + &pcicptr->g2pmmask[0]); + ____raw_writeq(channel->mem_resource->start | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PMnGBASE_ECHG #else - ((where & 0x3) ^ 0x2)) = val; + TX4927_PCIC_G2PMnGBASE_BSDIS #endif - break; - case 4: - tx4927_pcicptr->g2pcfgdata = val; - break; + , &pcicptr->g2pmgbase[0]); + ____raw_writeq(channel->mem_resource->start - + channel->mem_offset, + &pcicptr->g2pmpbase[0]); + } + /* PCI->GB mappings (I/O 256B) */ + __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ + ____raw_writeq(0, &pcicptr->p2giogbase); + /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ + __raw_writel(0, &pcicptr->p2gm0plbase); + __raw_writel(0, &pcicptr->p2gm0pubase); + ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4927_PCIC_P2GMnGBASE_TECHG +#else + TX4927_PCIC_P2GMnGBASE_TBSDIS +#endif + , &pcicptr->p2gmgbase[0]); + /* PCI->GB mappings (MEM 16MB) */ + __raw_writel(0xffffffff, &pcicptr->p2gm1plbase); + __raw_writel(0xffffffff, &pcicptr->p2gm1pubase); + ____raw_writeq(0, &pcicptr->p2gmgbase[1]); + /* PCI->GB mappings (MEM 1MB) */ + __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */ + ____raw_writeq(0, &pcicptr->p2gmgbase[2]); + + /* Clear all (including IRBER) except for GBWC */ + __raw_writel((tx4927_pci_opts.gbwc << 16) + & TX4927_PCIC_PCICCFG_GBWC_MASK, + &pcicptr->pciccfg); + /* Enable Initiator Memory Space */ + if (channel->mem_resource->end) + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_G2PMEN(0), + &pcicptr->pciccfg); + /* Enable Initiator I/O Space */ + if (channel->io_resource->end) + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_G2PIOEN, + &pcicptr->pciccfg); + /* Enable Initiator Config */ + __raw_writel(__raw_readl(&pcicptr->pciccfg) + | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR, + &pcicptr->pciccfg); + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + __raw_writel(0, &pcicptr->pcicfg1); + + __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff) + | (tx4927_pci_opts.trdyto & 0xff) + | ((tx4927_pci_opts.retryto & 0xff) << 8), + &pcicptr->g2ptocnt); + + /* Clear All Local Bus Status */ + __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); + /* Enable All Local Bus Interrupts */ + __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask); + /* Clear All Initiator Status */ + __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); + /* Enable All Initiator Interrupts */ + __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask); + /* Clear All PCI Status Error */ + __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) + | (TX4927_PCIC_PCISTATUS_ALL << 16), + &pcicptr->pcistatus); + /* Enable All PCI Status Error Interrupts */ + __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask); + + if (!extarb) { + /* Reset Bus Arbiter */ + __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); + __raw_writel(0, &pcicptr->pbabm); + /* Enable Bus Arbiter */ + __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg); } - return check_abort(flags); + __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY + | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, + &pcicptr->pcistatus); + local_irq_restore(flags); + + printk(KERN_DEBUG + "PCI: COMMAND=%04x,PCIMASK=%04x," + "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n", + __raw_readl(&pcicptr->pcistatus) & 0xffff, + __raw_readl(&pcicptr->pcimask) & 0xffff, + __raw_readl(&pcicptr->g2ptocnt) & 0xff, + (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8, + (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff); } -struct pci_ops tx4927_pci_ops = { - tx4927_pcibios_read_config, - tx4927_pcibios_write_config -}; +static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr) +{ + __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16); + __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus); + __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus); + static struct { + __u32 flag; + const char *str; + } pcistat_tbl[] = { + { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, + { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, + { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, + { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, + { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, + { PCI_STATUS_PARITY, "MasterParityError" }, + }, g2pstat_tbl[] = { + { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" }, + { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" }, + }, pcicstat_tbl[] = { + { TX4927_PCIC_PCICSTATUS_PME, "PME" }, + { TX4927_PCIC_PCICSTATUS_TLB, "TLB" }, + { TX4927_PCIC_PCICSTATUS_NIB, "NIB" }, + { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" }, + { TX4927_PCIC_PCICSTATUS_PERR, "PERR" }, + { TX4927_PCIC_PCICSTATUS_SERR, "SERR" }, + { TX4927_PCIC_PCICSTATUS_GBE, "GBE" }, + { TX4927_PCIC_PCICSTATUS_IWB, "IWB" }, + }; + int i, cont; -/* - * h/w only supports devices 0x00 to 0x14 - */ -struct pci_controller tx4927_controller = { - .pci_ops = &tx4927_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, -}; + printk(KERN_ERR ""); + if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) { + printk(KERN_CONT "pcistat:%04x(", pcistatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++) + if (pcistatus & pcistat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", pcistat_tbl[i].str); + printk(KERN_CONT ") "); + } + if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) { + printk(KERN_CONT "g2pstatus:%08x(", g2pstatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) + if (g2pstatus & g2pstat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", g2pstat_tbl[i].str); + printk(KERN_CONT ") "); + } + if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) { + printk(KERN_CONT "pcicstatus:%08x(", pcicstatus); + for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) + if (pcicstatus & pcicstat_tbl[i].flag) + printk(KERN_CONT "%s%s", + cont++ ? " " : "", pcicstat_tbl[i].str); + printk(KERN_CONT ")"); + } + printk(KERN_CONT "\n"); +} + +void tx4927_report_pcic_status(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { + if (pcicptrs[i].pcicptr) + tx4927_report_pcic_status1(pcicptrs[i].pcicptr); + } +} diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c deleted file mode 100644 index 34494b82cb22..000000000000 --- a/arch/mips/pci/ops-tx4938.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Define the pci_ops for the Toshiba rbtx4938 - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include - -#include -#include - -/* initialize in setup */ -struct resource pci_io_resource = { - .name = "pci IO space", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO -}; - -/* initialize in setup */ -struct resource pci_mem_resource = { - .name = "pci memory space", - .start = 0, - .end = 0, - .flags = IORESOURCE_MEM -}; - -struct resource tx4938_pcic1_pci_io_resource = { - .name = "PCI1 IO", - .start = 0, - .end = 0, - .flags = IORESOURCE_IO -}; -struct resource tx4938_pcic1_pci_mem_resource = { - .name = "PCI1 mem", - .start = 0, - .end = 0, - .flags = IORESOURCE_MEM -}; - -static int mkaddr(int bus, int dev_fn, int where, - struct tx4938_pcic_reg *pcicptr) -{ - if (bus > 0) { - /* Type 1 configuration */ - pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; - } else { - if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0)) - return -1; - - /* Type 0 configuration */ - pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | - ((dev_fn & 0xff) << 0x08) | (where & 0xfc); - } - /* clear M_ABORT and Disable M_ABORT Int. */ - pcicptr->pcistatus = - (pcicptr->pcistatus & 0x0000ffff) | - (PCI_STATUS_REC_MASTER_ABORT << 16); - pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; - - return 0; -} - -static int check_abort(struct tx4938_pcic_reg *pcicptr) -{ - int code = PCIBIOS_SUCCESSFUL; - /* wait write cycle completion before checking error status */ - while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) - ; - if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { - pcicptr->pcistatus = - (pcicptr-> - pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT - << 16); - pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; - code = PCIBIOS_DEVICE_NOT_FOUND; - } - return code; -} - -extern struct pci_controller tx4938_pci_controller[]; -extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch); - -static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus) -{ - struct pci_controller *channel = bus->sysdata; - return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]); -} - -static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - int retval, dev, busno, func; - struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); - void __iomem *cfgdata = - (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; - - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); - - /* check if the bus is top-level */ - if (bus->parent != NULL) - busno = bus->number; - else { - busno = 0; - } - - if (mkaddr(busno, devfn, where, pcicptr)) - return -1; - - switch (size) { - case 1: -#ifdef __BIG_ENDIAN - cfgdata += (where & 3) ^ 3; -#else - cfgdata += where & 3; -#endif - *val = __raw_readb(cfgdata); - break; - case 2: -#ifdef __BIG_ENDIAN - cfgdata += (where & 2) ^ 2; -#else - cfgdata += where & 2; -#endif - *val = __raw_readw(cfgdata); - break; - case 4: - *val = __raw_readl(cfgdata); - break; - } - - retval = check_abort(pcicptr); - if (retval == PCIBIOS_DEVICE_NOT_FOUND) - *val = 0xffffffff; - - return retval; -} - -static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - int dev, busno, func; - struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); - void __iomem *cfgdata = - (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; - - busno = bus->number; - dev = PCI_SLOT(devfn); - func = PCI_FUNC(devfn); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busno = bus->number; - } else { - busno = 0; - } - - if (mkaddr(busno, devfn, where, pcicptr)) - return -1; - - switch (size) { - case 1: -#ifdef __BIG_ENDIAN - cfgdata += (where & 3) ^ 3; -#else - cfgdata += where & 3; -#endif - __raw_writeb(val, cfgdata); - break; - case 2: -#ifdef __BIG_ENDIAN - cfgdata += (where & 2) ^ 2; -#else - cfgdata += where & 2; -#endif - __raw_writew(val, cfgdata); - break; - case 4: - __raw_writel(val, cfgdata); - break; - } - - return check_abort(pcicptr); -} - -struct pci_ops tx4938_pci_ops = { - tx4938_pcibios_read_config, - tx4938_pcibios_write_config -}; - -struct pci_controller tx4938_pci_controller[] = { - /* h/w only supports devices 0x00 to 0x14 */ - { - .pci_ops = &tx4938_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, - }, - /* h/w only supports devices 0x00 to 0x14 */ - { - .pci_ops = &tx4938_pci_ops, - .io_resource = &tx4938_pcic1_pci_io_resource, - .mem_resource = &tx4938_pcic1_pci_mem_resource, - } -}; diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c deleted file mode 100644 index 7fb6bd71901a..000000000000 --- a/arch/mips/pci/pci-jmr3927.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * Copyright (C) 2000-2001 Toshiba Corporation - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include - -#include -#include - -struct resource pci_io_resource = { - .name = "IO MEM", - .start = 0x1000, /* reserve regacy I/O space */ - .end = 0x1000 + JMR3927_PCIIO_SIZE - 1, - .flags = IORESOURCE_IO -}; - -struct resource pci_mem_resource = { - .name = "PCI MEM", - .start = JMR3927_PCIMEM, - .end = JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops jmr3927_pci_ops; - -struct pci_controller jmr3927_controller = { - .pci_ops = &jmr3927_pci_ops, - .io_resource = &pci_io_resource, - .mem_resource = &pci_mem_resource, - .mem_offset = JMR3927_PCIMEM -}; diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c new file mode 100644 index 000000000000..27e86a09dd41 --- /dev/null +++ b/arch/mips/pci/pci-tx4927.c @@ -0,0 +1,83 @@ +/* + * linux/arch/mips/pci/pci-tx4927.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001, 2003-2005 MontaVista Software Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +int __init tx4927_report_pciclk(void) +{ + int pciclk = 0; + + printk(KERN_INFO "PCIC --%s PCICLK:", + (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ? + " PCI66" : ""); + if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) { + u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg); + switch ((unsigned long)ccfg & + TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + pciclk = txx9_cpu_clock * 2 / 5; break; + case TX4927_CCFG_PCIDIVMODE_3: + pciclk = txx9_cpu_clock / 3; break; + case TX4927_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4927_CCFG_PCIDIVMODE_6: + pciclk = txx9_cpu_clock / 6; break; + } + printk("Internal(%u.%uMHz)", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +int __init tx4927_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4927_ccfg_set(TX4927_CCFG_PCI66); + /* Double PCICLK (if possible) */ + if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = 0; + u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg); + pcidivmode = (unsigned long)ccfg & + TX4927_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4927_CCFG_PCIDIVMODE_5: + case TX4927_CCFG_PCIDIVMODE_2_5: + pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5; + pciclk = txx9_cpu_clock * 2 / 5; + break; + case TX4927_CCFG_PCIDIVMODE_6: + case TX4927_CCFG_PCIDIVMODE_3: + default: + pcidivmode = TX4927_CCFG_PCIDIVMODE_3; + pciclk = txx9_cpu_clock / 3; + } + tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK, + pcidivmode); + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg)); + } else + pciclk = -1; + return pciclk; +} diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c new file mode 100644 index 000000000000..e5375511c2b7 --- /dev/null +++ b/arch/mips/pci/pci-tx4938.c @@ -0,0 +1,134 @@ +/* + * linux/arch/mips/pci/pci-tx4938.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001, 2003-2005 MontaVista Software Inc. + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +int __init tx4938_report_pciclk(void) +{ + int pciclk = 0; + + printk(KERN_INFO "PCIC --%s PCICLK:", + (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ? + " PCI66" : ""); + if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) { + u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + switch ((unsigned long)ccfg & + TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_4: + pciclk = txx9_cpu_clock / 4; break; + case TX4938_CCFG_PCIDIVMODE_4_5: + pciclk = txx9_cpu_clock * 2 / 9; break; + case TX4938_CCFG_PCIDIVMODE_5: + pciclk = txx9_cpu_clock / 5; break; + case TX4938_CCFG_PCIDIVMODE_5_5: + pciclk = txx9_cpu_clock * 2 / 11; break; + case TX4938_CCFG_PCIDIVMODE_8: + pciclk = txx9_cpu_clock / 8; break; + case TX4938_CCFG_PCIDIVMODE_9: + pciclk = txx9_cpu_clock / 9; break; + case TX4938_CCFG_PCIDIVMODE_10: + pciclk = txx9_cpu_clock / 10; break; + case TX4938_CCFG_PCIDIVMODE_11: + pciclk = txx9_cpu_clock / 11; break; + } + printk("Internal(%u.%uMHz)", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); + } else { + printk("External"); + pciclk = -1; + } + printk("\n"); + return pciclk; +} + +void __init tx4938_report_pci1clk(void) +{ + __u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + unsigned int pciclk = + txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2); + + printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n", + (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "", + (pciclk + 50000) / 1000000, + ((pciclk + 50000) / 100000) % 10); +} + +int __init tx4938_pciclk66_setup(void) +{ + int pciclk; + + /* Assert M66EN */ + tx4938_ccfg_set(TX4938_CCFG_PCI66); + /* Double PCICLK (if possible) */ + if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = 0; + u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg); + pcidivmode = (unsigned long)ccfg & + TX4938_CCFG_PCIDIVMODE_MASK; + switch (pcidivmode) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4; + pciclk = txx9_cpu_clock / 4; + break; + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; + pciclk = txx9_cpu_clock * 2 / 9; + break; + case TX4938_CCFG_PCIDIVMODE_10: + case TX4938_CCFG_PCIDIVMODE_5: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5; + pciclk = txx9_cpu_clock / 5; + break; + case TX4938_CCFG_PCIDIVMODE_11: + case TX4938_CCFG_PCIDIVMODE_5_5: + default: + pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; + pciclk = txx9_cpu_clock * 2 / 11; + break; + } + tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK, + pcidivmode); + printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", + (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg)); + } else + pciclk = -1; + return pciclk; +} + +int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot) +{ + if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) { + switch (slot) { + case TX4927_PCIC_IDSEL_AD_TO_SLOT(31): + if (__raw_readq(&tx4938_ccfgptr->pcfg) & + TX4938_PCFG_ETH0_SEL) + return TXX9_IRQ_BASE + TX4938_IR_ETH0; + break; + case TX4927_PCIC_IDSEL_AD_TO_SLOT(30): + if (__raw_readq(&tx4938_ccfgptr->pcfg) & + TX4938_PCFG_ETH1_SEL) + return TXX9_IRQ_BASE + TX4938_IR_ETH1; + break; + } + return 0; + } + return -1; +} diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig index 98d103402b10..b8cdb192543a 100644 --- a/arch/mips/txx9/Kconfig +++ b/arch/mips/txx9/Kconfig @@ -1,6 +1,12 @@ config TOSHIBA_FPCIB0 bool "FPCIB0 Backplane Support" - depends on TOSHIBA_RBTX4927 + depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + select I8259 + +config PICMG_PCI_BACKPLANE_DEFAULT + bool "Support for PICMG PCI Backplane" + depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + default y if !TOSHIBA_FPCIB0 if TOSHIBA_RBTX4938 @@ -26,3 +32,6 @@ config TX4938_NAND_BOOT Select this option if you need to use NAND boot. endif + +config PCI_TX4927 + bool diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile index 8cb4a7e81473..b80b6e072284 100644 --- a/arch/mips/txx9/generic/Makefile +++ b/arch/mips/txx9/generic/Makefile @@ -2,6 +2,8 @@ # Makefile for common code for TXx9 based systems # +obj-y += setup.o +obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c new file mode 100644 index 000000000000..8173faab99bb --- /dev/null +++ b/arch/mips/txx9/generic/pci.c @@ -0,0 +1,377 @@ +/* + * linux/arch/mips/txx9/pci.c + * + * Based on linux/arch/mips/txx9/rbtx4927/setup.c, + * linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * Copyright 2001-2005 MontaVista Software Inc. + * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#include +#include +#endif + +static int __init +early_read_config_word(struct pci_controller *hose, + int top_bus, int bus, int devfn, int offset, u16 *value) +{ + struct pci_dev fake_dev; + struct pci_bus fake_bus; + + fake_dev.bus = &fake_bus; + fake_dev.sysdata = hose; + fake_dev.devfn = devfn; + fake_bus.number = bus; + fake_bus.sysdata = hose; + fake_bus.ops = hose->pci_ops; + + if (bus != top_bus) + /* Fake a parent bus structure. */ + fake_bus.parent = &fake_bus; + else + fake_bus.parent = NULL; + + return pci_read_config_word(&fake_dev, offset, value); +} + +int __init txx9_pci66_check(struct pci_controller *hose, int top_bus, + int current_bus) +{ + u32 pci_devfn; + unsigned short vid; + int cap66 = -1; + u16 stat; + + /* It seems SLC90E66 needs some time after PCI reset... */ + mdelay(80); + + printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); + + for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { + if (PCI_FUNC(pci_devfn)) + continue; + if (early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_VENDOR_ID, &vid) != + PCIBIOS_SUCCESSFUL) + continue; + if (vid == 0xffff) + continue; + + /* check 66MHz capability */ + if (cap66 < 0) + cap66 = 1; + if (cap66) { + early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_STATUS, &stat); + if (!(stat & PCI_STATUS_66MHZ)) { + printk(KERN_DEBUG + "PCI: %02x:%02x not 66MHz capable.\n", + current_bus, pci_devfn); + cap66 = 0; + break; + } + } + } + return cap66 > 0; +} + +static struct resource primary_pci_mem_res[2] = { + { .name = "PCI MEM" }, + { .name = "PCI MMIO" }, +}; +static struct resource primary_pci_io_res = { .name = "PCI IO" }; +struct pci_controller txx9_primary_pcic = { + .mem_resource = &primary_pci_mem_res[0], + .io_resource = &primary_pci_io_res, +}; + +#ifdef CONFIG_64BIT +int txx9_pci_mem_high __initdata = 1; +#else +int txx9_pci_mem_high __initdata; +#endif + +/* + * allocate pci_controller and resources. + * mem_base, io_base: physical addresss. 0 for auto assignment. + * mem_size and io_size means max size on auto assignment. + * pcic must be &txx9_primary_pcic or NULL. + */ +struct pci_controller *__init +txx9_alloc_pci_controller(struct pci_controller *pcic, + unsigned long mem_base, unsigned long mem_size, + unsigned long io_base, unsigned long io_size) +{ + struct pcic { + struct pci_controller c; + struct resource r_mem[2]; + struct resource r_io; + } *new = NULL; + int min_size = 0x10000; + + if (!pcic) { + new = kzalloc(sizeof(*new), GFP_KERNEL); + if (!new) + return NULL; + new->r_mem[0].name = "PCI mem"; + new->r_mem[1].name = "PCI mmio"; + new->r_io.name = "PCI io"; + new->c.mem_resource = new->r_mem; + new->c.io_resource = &new->r_io; + pcic = &new->c; + } else + BUG_ON(pcic != &txx9_primary_pcic); + pcic->io_resource->flags = IORESOURCE_IO; + + /* + * for auto assignment, first search a (big) region for PCI + * MEM, then search a region for PCI IO. + */ + if (mem_base) { + pcic->mem_resource[0].start = mem_base; + pcic->mem_resource[0].end = mem_base + mem_size - 1; + if (request_resource(&iomem_resource, &pcic->mem_resource[0])) + goto free_and_exit; + } else { + unsigned long min = 0, max = 0x20000000; /* low 512MB */ + if (!mem_size) { + /* default size for auto assignment */ + if (txx9_pci_mem_high) + mem_size = 0x20000000; /* mem:512M(max) */ + else + mem_size = 0x08000000; /* mem:128M(max) */ + } + if (txx9_pci_mem_high) { + min = 0x20000000; + max = 0xe0000000; + } + /* search free region for PCI MEM */ + for (; mem_size >= min_size; mem_size /= 2) { + if (allocate_resource(&iomem_resource, + &pcic->mem_resource[0], + mem_size, min, max, + mem_size, NULL, NULL) == 0) + break; + } + if (mem_size < min_size) + goto free_and_exit; + } + + pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY; + if (io_base) { + pcic->mem_resource[1].start = io_base; + pcic->mem_resource[1].end = io_base + io_size - 1; + if (request_resource(&iomem_resource, &pcic->mem_resource[1])) + goto release_and_exit; + } else { + if (!io_size) + /* default size for auto assignment */ + io_size = 0x01000000; /* io:16M(max) */ + /* search free region for PCI IO in low 512MB */ + for (; io_size >= min_size; io_size /= 2) { + if (allocate_resource(&iomem_resource, + &pcic->mem_resource[1], + io_size, 0, 0x20000000, + io_size, NULL, NULL) == 0) + break; + } + if (io_size < min_size) + goto release_and_exit; + io_base = pcic->mem_resource[1].start; + } + + pcic->mem_resource[0].flags = IORESOURCE_MEM; + if (pcic == &txx9_primary_pcic && + mips_io_port_base == (unsigned long)-1) { + /* map ioport 0 to PCI I/O space address 0 */ + set_io_port_base(IO_BASE + pcic->mem_resource[1].start); + pcic->io_resource->start = 0; + pcic->io_offset = 0; /* busaddr == ioaddr */ + pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start; + } else { + /* physaddr to ioaddr */ + pcic->io_resource->start = + io_base - (mips_io_port_base - IO_BASE); + pcic->io_offset = io_base - (mips_io_port_base - IO_BASE); + pcic->io_map_base = mips_io_port_base; + } + pcic->io_resource->end = pcic->io_resource->start + io_size - 1; + + pcic->mem_offset = 0; /* busaddr == physaddr */ + + printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n", + (unsigned long long)pcic->mem_resource[1].start, + (unsigned long long)pcic->mem_resource[1].end, + (unsigned long long)pcic->mem_resource[0].start, + (unsigned long long)pcic->mem_resource[0].end); + + /* register_pci_controller() will request MEM resource */ + release_resource(&pcic->mem_resource[0]); + return pcic; + release_and_exit: + release_resource(&pcic->mem_resource[0]); + free_and_exit: + kfree(new); + printk(KERN_ERR "PCI: Failed to allocate resources.\n"); + return NULL; +} + +static int __init +txx9_arch_pci_init(void) +{ + PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */ + return 0; +} +arch_initcall(txx9_arch_pci_init); + +/* IRQ/IDSEL mapping */ +int txx9_pci_option = +#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT + TXX9_PCI_OPT_PICMG | +#endif + TXX9_PCI_OPT_CLK_AUTO; + +enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT; + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static irqreturn_t i8259_interrupt(int irq, void *dev_id) +{ + int isairq; + + isairq = i8259_irq(); + if (unlikely(isairq <= I8259A_IRQ_BASE)) + return IRQ_NONE; + generic_handle_irq(isairq); + return IRQ_HANDLED; +} + +static int __init +txx9_i8259_irq_setup(int irq) +{ + int err; + + init_i8259_irqs(); + err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED, + "cascade(i8259)", (void *)(long)irq); + if (!err) + printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq); + return err; +} + +static void __init quirk_slc90e66_bridge(struct pci_dev *dev) +{ + int irq; /* PCI/ISA Bridge interrupt */ + u8 reg_64; + u32 reg_b0; + u8 reg_e1; + irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */ + if (!irq) + return; + txx9_i8259_irq_setup(irq); + pci_read_config_byte(dev, 0x64, ®_64); + pci_read_config_dword(dev, 0xb0, ®_b0); + pci_read_config_byte(dev, 0xe1, ®_e1); + /* serial irq control */ + reg_64 = 0xd0; + /* serial irq pin */ + reg_b0 |= 0x00010000; + /* ide irq on isa14 */ + reg_e1 &= 0xf0; + reg_e1 |= 0x0d; + pci_write_config_byte(dev, 0x64, reg_64); + pci_write_config_dword(dev, 0xb0, reg_b0); + pci_write_config_byte(dev, 0xe1, reg_e1); + + smsc_fdc37m81x_init(0x3f0); + smsc_fdc37m81x_config_beg(); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + smsc_fdc37m81x_config_end(); +} + +static void quirk_slc90e66_ide(struct pci_dev *dev) +{ + unsigned char dat; + int regs[2] = {0x41, 0x43}; + int i; + + /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14); + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat); + printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat); + /* enable SMSC SLC90E66 IDE */ + for (i = 0; i < ARRAY_SIZE(regs); i++) { + pci_read_config_byte(dev, regs[i], &dat); + pci_write_config_byte(dev, regs[i], dat | 0x80); + pci_read_config_byte(dev, regs[i], &dat); + printk(KERN_CONT " IDETIM%d %02x", i, dat); + } + pci_read_config_byte(dev, 0x5c, &dat); + /* + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + * + * This line of code is intended to provide the user with a work + * around solution to the anomalies cited in SMSC's anomaly sheet + * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". + * + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + */ + dat |= 0x01; + pci_write_config_byte(dev, regs[i], dat); + pci_read_config_byte(dev, 0x5c, &dat); + printk(KERN_CONT " REG5C %02x", dat); + printk(KERN_CONT "\n"); +} +#endif /* CONFIG_TOSHIBA_FPCIB0 */ + +static void final_fixup(struct pci_dev *dev) +{ + unsigned char bist; + + /* Do build-in self test */ + if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL && + (bist & PCI_BIST_CAPABLE)) { + unsigned long timeout; + pci_set_power_state(dev, PCI_D0); + printk(KERN_INFO "PCI: %s BIST...", pci_name(dev)); + pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START); + timeout = jiffies + HZ * 2; /* timeout after 2 sec */ + do { + pci_read_config_byte(dev, PCI_BIST, &bist); + if (time_after(jiffies, timeout)) + break; + } while (bist & PCI_BIST_START); + if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START)) + printk(KERN_CONT "failed. (0x%x)\n", bist); + else + printk(KERN_CONT "OK.\n"); + } +} + +#ifdef CONFIG_TOSHIBA_FPCIB0 +#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, + quirk_slc90e66_bridge); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, + quirk_slc90e66_ide); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, + quirk_slc90e66_ide); +#endif +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup); +DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup); diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c new file mode 100644 index 000000000000..46a631177757 --- /dev/null +++ b/arch/mips/txx9/generic/setup.c @@ -0,0 +1,51 @@ +/* + * linux/arch/mips/txx9/generic/setup.c + * + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * 2003-2005 (c) MontaVista Software, Inc. + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include + +/* EBUSC settings of TX4927, etc. */ +struct resource txx9_ce_res[8]; +static char txx9_ce_res_name[8][4]; /* "CEn" */ + +/* pcode, internal register */ +char txx9_pcode_str[8]; +static struct resource txx9_reg_res = { + .name = txx9_pcode_str, + .flags = IORESOURCE_MEM, +}; +void __init +txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) { + sprintf(txx9_ce_res_name[i], "CE%d", i); + txx9_ce_res[i].flags = IORESOURCE_MEM; + txx9_ce_res[i].name = txx9_ce_res_name[i]; + } + + sprintf(txx9_pcode_str, "TX%x", pcode); + if (base) { + txx9_reg_res.start = base & 0xfffffffffULL; + txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1); + request_resource(&iomem_resource, &txx9_reg_res); + } +} + +/* clocks */ +unsigned int txx9_master_clock; +unsigned int txx9_cpu_clock; +unsigned int txx9_gbus_clock; diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index 85e1daf15c7b..b97d22e15da6 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c @@ -109,6 +109,7 @@ static struct irqaction ioc_action = { .name = "IOC", }; +#ifdef CONFIG_PCI static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) { printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); @@ -122,6 +123,7 @@ static struct irqaction pcierr_action = { .mask = CPU_MASK_NONE, .name = "PCI error", }; +#endif static void __init jmr3927_irq_init(void); diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 41e0f3b3af2c..baa8c8db9a94 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -44,6 +43,7 @@ #include #include #include +#include #include #include @@ -96,8 +96,6 @@ void __init plat_time_init(void) extern char * __init prom_getcmdline(void); static void jmr3927_board_init(void); -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; void __init plat_mem_setup(void) { @@ -112,8 +110,8 @@ void __init plat_mem_setup(void) /* * IO/MEM resources. */ - ioport_resource.start = pci_io_resource.start; - ioport_resource.end = pci_io_resource.end; + ioport_resource.start = 0; + ioport_resource.end = 0xffffffff; iomem_resource.start = 0; iomem_resource.end = 0xffffffff; @@ -191,9 +189,33 @@ void __init plat_mem_setup(void) static void tx3927_setup(void); +static void __init jmr3927_pci_setup(void) +{ +#ifdef CONFIG_PCI + int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB); + struct pci_controller *c; + + c = txx9_alloc_pci_controller(&txx9_primary_pcic, + JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE, + JMR3927_PCIIO, JMR3927_PCIIO_SIZE); + register_pci_controller(c); + if (!extarb) { + /* Reset PCI Bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, + JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + } + tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb); +#endif /* CONFIG_PCI */ +} + static void __init jmr3927_board_init(void) { tx3927_setup(); + jmr3927_pci_setup(); /* SIO0 DTR on */ jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); @@ -210,14 +232,6 @@ static void __init jmr3927_board_init(void) static void __init tx3927_setup(void) { int i; -#ifdef CONFIG_PCI - unsigned long mips_pci_io_base = JMR3927_PCIIO; - unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; - unsigned long mips_pci_mem_base = JMR3927_PCIMEM; - unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; - /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ - unsigned long mips_pci_io_pciaddr = 0; -#endif /* SDRAMC are configured by PROM */ @@ -272,74 +286,6 @@ static void __init tx3927_setup(void) tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; #endif -#ifdef CONFIG_PCI - /* PCIC */ - printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", - tx3927_pcicptr->did, tx3927_pcicptr->vid, - tx3927_pcicptr->rid); - if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { - printk("External\n"); - /* XXX */ - } else { - printk("Internal\n"); - - /* Reset PCI Bus */ - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, - JMR3927_IOC_RESET_ADDR); - udelay(100); - jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); - - - /* Disable External PCI Config. Access */ - tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; -#ifdef __BIG_ENDIAN - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | - TX3927_PCIC_LBC_TIBSE | - TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; -#endif - /* LB->PCI mappings */ - tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); - tx3927_pcicptr->ilbioma = mips_pci_io_base; - tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; - tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->ilbmma = mips_pci_mem_base; - tx3927_pcicptr->ipbmma = mips_pci_mem_base; - /* PCI->LB mappings */ - tx3927_pcicptr->iobas = 0xffffffff; - tx3927_pcicptr->ioba = 0; - tx3927_pcicptr->tlbioma = 0; - tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); - tx3927_pcicptr->mba = 0; - tx3927_pcicptr->tlbmma = 0; - /* Enable Direct mapping Address Space Decoder */ - tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; - - /* Clear All Local Bus Status */ - tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; - /* Enable All Local Bus Interrupts */ - tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; - /* Clear All PCI Status Error */ - tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; - /* Enable All PCI Status Error Interrupts */ - tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; - - /* PCIC Int => IRC IRQ10 */ - tx3927_pcicptr->il = TX3927_IR_PCI; - /* Target Control (per errata) */ - tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; - - /* Enable Bus Arbiter */ - tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; - - tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - } -#endif /* CONFIG_PCI */ - /* PIO */ /* PIO[15:12] connected to LEDs */ __raw_writel(0x0000f000, &tx3927_pioptr->dir); diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c index 936e50e91d95..bef1447aeed2 100644 --- a/arch/mips/txx9/rbtx4927/irq.c +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -111,9 +111,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #include #include #include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif #include #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 @@ -125,8 +122,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) -extern int tx4927_using_backplane; - static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); @@ -146,17 +141,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq) u8 level3; level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; - if (level3) { + if (level3) sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC && - tx4927_using_backplane) { - int irq = i8259_irq(); - if (irq >= 0) - sw_irq = irq; - } -#endif - } return (sw_irq); } @@ -205,10 +191,6 @@ void __init arch_init_irq(void) tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) - init_i8259_irqs(); -#endif /* Onboard 10M Ether: High Active */ set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); } diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index df1b6e99b666..86b870abc319 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -47,10 +47,10 @@ #include #include #include -#include #include #include #include +#include #include #include @@ -58,10 +58,10 @@ #include #include #include -#ifdef CONFIG_TOSHIBA_FPCIB0 -#include -#endif +#include +#include #include +#include /* for TX4937 */ #ifdef CONFIG_SERIAL_TXX9 #include #endif @@ -70,356 +70,116 @@ extern void toshiba_rbtx4927_restart(char *command); extern void toshiba_rbtx4927_halt(void); extern void toshiba_rbtx4927_power_off(void); - -int tx4927_using_backplane = 0; - extern void toshiba_rbtx4927_irq_setup(void); char *prom_getcmdline(void); -#ifdef CONFIG_PCI -#undef TX4927_SUPPORT_COMMAND_IO -#undef TX4927_SUPPORT_PCI_66 -int tx4927_cpu_clock = 100000000; /* 100MHz */ -unsigned long mips_pci_io_base; -unsigned long mips_pci_io_size; -unsigned long mips_pci_mem_base; -unsigned long mips_pci_mem_size; -/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ -unsigned long mips_pci_io_pciaddr = 0; -unsigned long mips_memory_upper; static int tx4927_ccfg_toeon = 1; -static int tx4927_pcic_trdyto = 0; /* default: disabled */ -unsigned long tx4927_ce_base[8]; -int tx4927_pci66 = 0; /* 0:auto */ -#endif char *toshiba_name = ""; #ifdef CONFIG_PCI -extern struct pci_controller tx4927_controller; - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) +static void __init tx4927_pci_setup(void) { - static struct pci_dev dev; - static struct pci_bus bus; - - dev.sysdata = (void *)hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ + int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); + struct pci_controller *c = &txx9_primary_pcic; + + register_pci_controller(c); + + if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) + txx9_pci_option = + (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | + TXX9_PCI_OPT_CLK_66; /* already configured */ + + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_66) + tx4927_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + + tx4927_report_pciclk(); + tx4927_pcic_setup(tx4927_pcicptr, c, extarb); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_AUTO && + txx9_pci66_check(c, 0, 0)) { + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + tx4927_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + /* Reinitialize PCIC */ + tx4927_report_pciclk(); + tx4927_pcic_setup(tx4927_pcicptr, c, extarb); + } } -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, dword, u32) - -static int __init tx4927_pcibios_init(void) +static void __init tx4937_pci_setup(void) { - unsigned int id; - u32 pci_devfn; - int devfn_start = 0; - int devfn_stop = 0xff; - int busno = 0; /* One bus on the Toshiba */ - struct pci_controller *hose = &tx4927_controller; - - for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { - early_read_config_dword(hose, busno, busno, pci_devfn, - PCI_VENDOR_ID, &id); - - if (id == 0xffffffff) { - continue; - } - - if (id == 0x94601055) { - u8 v08_64; - u32 v32_b0; - u8 v08_e1; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x64, &v08_64); - early_read_config_dword(hose, busno, busno, - pci_devfn, 0xb0, &v32_b0); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0xe1, &v08_e1); - - /* serial irq control */ - v08_64 = 0xd0; - - /* serial irq pin */ - v32_b0 |= 0x00010000; - - /* ide irq on isa14 */ - v08_e1 &= 0xf0; - v08_e1 |= 0x0d; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x64, v08_64); - early_write_config_dword(hose, busno, busno, - pci_devfn, 0xb0, v32_b0); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0xe1, v08_e1); - } - - if (id == 0x91301055) { - u8 v08_04; - u8 v08_09; - u8 v08_41; - u8 v08_43; - u8 v08_5c; - - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x04, &v08_04); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x09, &v08_09); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x41, &v08_41); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x43, &v08_43); - early_read_config_byte(hose, busno, busno, - pci_devfn, 0x5c, &v08_5c); - - /* enable ide master/io */ - v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); - - /* enable ide native mode */ - v08_09 |= 0x05; - - /* enable primary ide */ - v08_41 |= 0x80; - - /* enable secondary ide */ - v08_43 |= 0x80; - - /* - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - * - * This line of code is intended to provide the user with a work - * around solution to the anomalies cited in SMSC's anomaly sheet - * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". - * - * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! - */ - v08_5c |= 0x01; - - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x5c, v08_5c); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x04, v08_04); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x09, v08_09); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x41, v08_41); - early_write_config_byte(hose, busno, busno, - pci_devfn, 0x43, v08_43); - } - + int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB); + struct pci_controller *c = &txx9_primary_pcic; + + register_pci_controller(c); + + if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) + txx9_pci_option = + (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | + TXX9_PCI_OPT_CLK_66; /* already configured */ + + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_66) + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + + tx4938_report_pciclk(); + tx4927_pcic_setup(tx4938_pcicptr, c, extarb); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_AUTO && + txx9_pci66_check(c, 0, 0)) { + /* Reset PCI Bus */ + writeb(1, rbtx4927_pcireset_addr); + /* Reset PCIC */ + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + tx4938_pciclk66_setup(); + mdelay(10); + /* clear PCIC reset */ + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + writeb(0, rbtx4927_pcireset_addr); + iob(); + /* Reinitialize PCIC */ + tx4938_report_pciclk(); + tx4927_pcic_setup(tx4938_pcicptr, c, extarb); } - - register_pci_controller(&tx4927_controller); - return 0; } -arch_initcall(tx4927_pcibios_init); - -extern struct resource pci_io_resource; -extern struct resource pci_mem_resource; - -void __init tx4927_pci_setup(void) +static int __init rbtx4927_arch_init(void) { - static int called = 0; - extern unsigned int tx4927_get_mem_size(void); - - mips_memory_upper = tx4927_get_mem_size() << 20; - mips_memory_upper += KSEG0; - mips_pci_io_base = TX4927_PCIIO; - mips_pci_io_size = TX4927_PCIIO_SIZE; - mips_pci_mem_base = TX4927_PCIMEM; - mips_pci_mem_size = TX4927_PCIMEM_SIZE; - - if (!called) { - printk - ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - toshiba_name, - (unsigned short) (tx4927_pcicptr->pciid >> 16), - (unsigned short) (tx4927_pcicptr->pciid & 0xffff), - (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), - (!(tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIXARB)) ? "External" : - "Internal"); - called = 1; - } - printk("%s PCIC --%s PCICLK:", toshiba_name, - (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); - if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { - int pciclk = 0; - if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_4: - pciclk = tx4927_cpu_clock / 4; - break; - case TX4937_CCFG_PCIDIVMODE_4_5: - pciclk = tx4927_cpu_clock * 2 / 9; - break; - case TX4937_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4937_CCFG_PCIDIVMODE_5_5: - pciclk = tx4927_cpu_clock * 2 / 11; - break; - case TX4937_CCFG_PCIDIVMODE_8: - pciclk = tx4927_cpu_clock / 8; - break; - case TX4937_CCFG_PCIDIVMODE_9: - pciclk = tx4927_cpu_clock / 9; - break; - case TX4937_CCFG_PCIDIVMODE_10: - pciclk = tx4927_cpu_clock / 10; - break; - case TX4937_CCFG_PCIDIVMODE_11: - pciclk = tx4927_cpu_clock / 11; - break; - } - - else - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - pciclk = tx4927_cpu_clock * 2 / 5; - break; - case TX4927_CCFG_PCIDIVMODE_3: - pciclk = tx4927_cpu_clock / 3; - break; - case TX4927_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4927_CCFG_PCIDIVMODE_6: - pciclk = tx4927_cpu_clock / 6; - break; - } - - printk("Internal(%dMHz)", pciclk / 1000000); - } else - printk("External"); - printk("\n"); - - /* GB->PCI mappings */ - tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; - tx4927_pcicptr->g2piogbase = mips_pci_io_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PIOGBASE_ECHG -#else - TX4927_PCIC_G2PIOGBASE_BSDIS -#endif - ; - - tx4927_pcicptr->g2piopbase = 0; - - tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; - tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | -#ifdef __BIG_ENDIAN - TX4927_PCIC_G2PMnGBASE_ECHG -#else - TX4927_PCIC_G2PMnGBASE_BSDIS -#endif - ; - tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; - - tx4927_pcicptr->g2pmmask[1] = 0; - tx4927_pcicptr->g2pmgbase[1] = 0; - tx4927_pcicptr->g2pmpbase[1] = 0; - tx4927_pcicptr->g2pmmask[2] = 0; - tx4927_pcicptr->g2pmgbase[2] = 0; - tx4927_pcicptr->g2pmpbase[2] = 0; - - - /* PCI->GB mappings (I/O 256B) */ - tx4927_pcicptr->p2giopbase = 0; /* 256B */ - - /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ - tx4927_pcicptr->p2gm0plbase = 0; - tx4927_pcicptr->p2gm0pubase = 0; - tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4927_PCIC_P2GMnGBASE_TECHG -#else - TX4927_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - - /* PCI->GB mappings (MEM 16MB) -not used */ - tx4927_pcicptr->p2gm1plbase = 0xffffffff; - tx4927_pcicptr->p2gm1pubase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[1] = 0; - - /* PCI->GB mappings (MEM 1MB) -not used */ - tx4927_pcicptr->p2gm2pbase = 0xffffffff; - tx4927_pcicptr->p2gmgbase[2] = 0; - - - /* Enable Initiator Memory 0 Space, I/O Space, Config */ - tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; - tx4927_pcicptr->pciccfg |= - TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | - TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; - - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - tx4927_pcicptr->pcicfg1 = 0; - - if (tx4927_pcic_trdyto >= 0) { - tx4927_pcicptr->g2ptocnt &= ~0xff; - tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); - } - - /* Clear All Local Bus Status */ - tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - tx4927_pcicptr->pcistatus = - (tx4927_pcicptr->pcistatus & 0x0000ffff) | - (TX4927_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; - - /* PCIC Int => IRC IRQ16 */ - tx4927_pcicptr->pcicfg2 = - (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; - - if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { - /* XXX */ - } else { - /* Reset Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; - /* Enable Bus Arbiter */ - tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; - } - - tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + tx4937_pci_setup(); + else + tx4927_pci_setup(); + return 0; } +arch_initcall(rbtx4927_arch_init); #endif /* CONFIG_PCI */ static void __noreturn wait_forever(void) @@ -479,8 +239,6 @@ void __init plat_mem_setup(void) cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); write_c0_config(cp0_config); - set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); - ioport_resource.end = 0xffffffff; iomem_resource.end = 0xffffffff; @@ -492,8 +250,13 @@ void __init plat_mem_setup(void) txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); #ifdef CONFIG_PCI + txx9_alloc_pci_controller(&txx9_primary_pcic, + RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, + RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); +#else + set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); +#endif - /* PCIC */ /* * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. * @@ -517,58 +280,38 @@ void __init plat_mem_setup(void) * */ if (mips_machtype == MACH_TOSHIBA_RBTX4937) - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { - case TX4937_CCFG_PCIDIVMODE_8: - case TX4937_CCFG_PCIDIVMODE_4: - tx4927_cpu_clock = 266666666; /* 266MHz */ + switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & + TX4938_CCFG_PCIDIVMODE_MASK) { + case TX4938_CCFG_PCIDIVMODE_8: + case TX4938_CCFG_PCIDIVMODE_4: + txx9_cpu_clock = 266666666; /* 266MHz */ break; - case TX4937_CCFG_PCIDIVMODE_9: - case TX4937_CCFG_PCIDIVMODE_4_5: - tx4927_cpu_clock = 300000000; /* 300MHz */ + case TX4938_CCFG_PCIDIVMODE_9: + case TX4938_CCFG_PCIDIVMODE_4_5: + txx9_cpu_clock = 300000000; /* 300MHz */ break; default: - tx4927_cpu_clock = 333333333; /* 333MHz */ + txx9_cpu_clock = 333333333; /* 333MHz */ } else - switch ((unsigned long)tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & + TX4927_CCFG_PCIDIVMODE_MASK) { case TX4927_CCFG_PCIDIVMODE_2_5: case TX4927_CCFG_PCIDIVMODE_5: - tx4927_cpu_clock = 166666666; /* 166MHz */ + txx9_cpu_clock = 166666666; /* 166MHz */ break; default: - tx4927_cpu_clock = 200000000; /* 200MHz */ + txx9_cpu_clock = 200000000; /* 200MHz */ } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; /* CCFG */ /* do reset on watchdog */ - tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; + tx4927_ccfg_set(TX4927_CCFG_WR); /* enable Timeout BusError */ if (tx4927_ccfg_toeon) - tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; - - tx4927_pci_setup(); - if (tx4927_using_backplane == 1) - printk("backplane board IS installed\n"); - else - printk("No Backplane \n"); - - /* this is on ISA bus behind PCI bus, so need PCI up first */ -#ifdef CONFIG_TOSHIBA_FPCIB0 - if (tx4927_using_backplane) { - smsc_fdc37m81x_init(0x3f0); - smsc_fdc37m81x_config_beg(); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, - SMSC_FDC37M81X_KBD); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); - smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, - 1); - smsc_fdc37m81x_config_end(); - } -#endif -#endif /* CONFIG_PCI */ + tx4927_ccfg_set(TX4927_CCFG_TOE); #ifdef CONFIG_SERIAL_TXX9 { @@ -611,8 +354,8 @@ void __init plat_mem_setup(void) void __init plat_time_init(void) { - mips_hpt_frequency = tx4927_cpu_clock / 2; - if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) + mips_hpt_frequency = txx9_cpu_clock / 2; + if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, TXX9_IRQ_BASE + 17, 50000000); diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index bbd572c9675b..144d2cada820 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -26,6 +25,8 @@ #include #include #include +#include +#include #include #ifdef CONFIG_SERIAL_TXX9 #include @@ -35,37 +36,13 @@ #include extern char * __init prom_getcmdline(void); -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); - /* These functions are used for rebooting or halting the machine*/ extern void rbtx4938_machine_restart(char *command); extern void rbtx4938_machine_halt(void); extern void rbtx4938_machine_power_off(void); -/* clocks */ -unsigned int txx9_master_clock; -unsigned int txx9_cpu_clock; -unsigned int txx9_gbus_clock; - -unsigned long rbtx4938_ce_base[8]; -unsigned long rbtx4938_ce_size[8]; -int txboard_pci66_mode; -static int tx4938_pcic_trdyto; /* default: disabled */ -static int tx4938_pcic_retryto; /* default: disabled */ static int tx4938_ccfg_toeon = 1; -struct tx4938_pcic_reg *pcicptrs[4] = { - tx4938_pcicptr /* default setting for TX4938 */ -}; - -static struct { - unsigned long base; - unsigned long size; -} phys_regions[16] __initdata; -static int num_phys_regions __initdata; - -#define PHYS_REGION_MINSIZE 0x10000 - void rbtx4938_machine_halt(void) { printk(KERN_NOTICE "System Halted\n"); @@ -95,473 +72,72 @@ void rbtx4938_machine_restart(char *command) ; } -void __init -txboard_add_phys_region(unsigned long base, unsigned long size) -{ - if (num_phys_regions >= ARRAY_SIZE(phys_regions)) { - printk("phys_region overflow\n"); - return; - } - phys_regions[num_phys_regions].base = base; - phys_regions[num_phys_regions].size = size; - num_phys_regions++; -} -unsigned long __init -txboard_find_free_phys_region(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - int i; - - for (base = begin / size * size; base < end; base += size) { - for (i = 0; i < num_phys_regions; i++) { - if (phys_regions[i].size && - base <= phys_regions[i].base + (phys_regions[i].size - 1) && - base + (size - 1) >= phys_regions[i].base) - break; - } - if (i == num_phys_regions) - return base; - } - return 0; -} -unsigned long __init -txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end, - unsigned long *size) -{ - unsigned long sz, base; - for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) { - base = txboard_find_free_phys_region(begin, end, sz); - if (base) { - *size = sz; - return base; - } - } - return 0; -} -unsigned long __init -txboard_request_phys_region_range(unsigned long begin, unsigned long end, - unsigned long size) -{ - unsigned long base; - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region(unsigned long size) +static void __init rbtx4938_pci_setup(void) { - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region(begin, end, size); - if (base) - txboard_add_phys_region(base, size); - return base; -} -unsigned long __init -txboard_request_phys_region_shrink(unsigned long *size) -{ - unsigned long base; - unsigned long begin = 0, end = 0x20000000; /* search low 512MB */ - base = txboard_find_free_phys_region_shrink(begin, end, size); - if (base) - txboard_add_phys_region(base, *size); - return base; -} - #ifdef CONFIG_PCI -void __init -tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, - struct pci_controller *channel, - unsigned long pci_io_base, - int extarb) -{ - int i; + int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB); + struct pci_controller *c = &txx9_primary_pcic; - /* Disable All Initiator Space */ - pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)| - TX4938_PCIC_PCICCFG_G2PMEN(1)| - TX4938_PCIC_PCICCFG_G2PMEN(2)| - TX4938_PCIC_PCICCFG_G2PIOEN); - - /* GB->PCI mappings */ - pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4; - pcicptr->g2piogbase = pci_io_base | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PIOGBASE_ECHG -#else - TX4938_PCIC_G2PIOGBASE_BSDIS -#endif - ; - pcicptr->g2piopbase = 0; - for (i = 0; i < 3; i++) { - pcicptr->g2pmmask[i] = 0; - pcicptr->g2pmgbase[i] = 0; - pcicptr->g2pmpbase[i] = 0; - } - if (channel->mem_resource->end) { - pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4; - pcicptr->g2pmgbase[0] = channel->mem_resource->start | -#ifdef __BIG_ENDIAN - TX4938_PCIC_G2PMnGBASE_ECHG -#else - TX4938_PCIC_G2PMnGBASE_BSDIS -#endif - ; - pcicptr->g2pmpbase[0] = channel->mem_resource->start; - } - /* PCI->GB mappings (I/O 256B) */ - pcicptr->p2giopbase = 0; /* 256B */ - pcicptr->p2giogbase = 0; - /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ - pcicptr->p2gm0plbase = 0; - pcicptr->p2gm0pubase = 0; - pcicptr->p2gmgbase[0] = 0 | - TX4938_PCIC_P2GMnGBASE_TMEMEN | -#ifdef __BIG_ENDIAN - TX4938_PCIC_P2GMnGBASE_TECHG -#else - TX4938_PCIC_P2GMnGBASE_TBSDIS -#endif - ; - /* PCI->GB mappings (MEM 16MB) */ - pcicptr->p2gm1plbase = 0xffffffff; - pcicptr->p2gm1pubase = 0xffffffff; - pcicptr->p2gmgbase[1] = 0; - /* PCI->GB mappings (MEM 1MB) */ - pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */ - pcicptr->p2gmgbase[2] = 0; - - pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK; - /* Enable Initiator Memory Space */ - if (channel->mem_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0); - /* Enable Initiator I/O Space */ - if (channel->io_resource->end) - pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN; - /* Enable Initiator Config */ - pcicptr->pciccfg |= - TX4938_PCIC_PCICCFG_ICAEN | - TX4938_PCIC_PCICCFG_TCAR; - - /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ - pcicptr->pcicfg1 = 0; - - pcicptr->g2ptocnt &= ~0xffff; - - if (tx4938_pcic_trdyto >= 0) { - pcicptr->g2ptocnt &= ~0xff; - pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff); - } - - if (tx4938_pcic_retryto >= 0) { - pcicptr->g2ptocnt &= ~0xff00; - pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00); - } - - /* Clear All Local Bus Status */ - pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL; - /* Enable All Local Bus Interrupts */ - pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL; - /* Clear All Initiator Status */ - pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL; - /* Enable All Initiator Interrupts */ - pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL; - /* Clear All PCI Status Error */ - pcicptr->pcistatus = - (pcicptr->pcistatus & 0x0000ffff) | - (TX4938_PCIC_PCISTATUS_ALL << 16); - /* Enable All PCI Status Error Interrupts */ - pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL; - - if (!extarb) { - /* Reset Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA; - pcicptr->pbabm = 0; - /* Enable Bus Arbiter */ - pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN; - } - - /* PCIC Int => IRC IRQ16 */ - pcicptr->pcicfg2 = - (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC; - - pcicptr->pcistatus = PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; -} - -int __init -tx4938_report_pciclk(void) -{ - unsigned long pcode = TX4938_REV_PCODE(); - int pciclk = 0; - printk("TX%lx PCIC --%s PCICLK:", - pcode, - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : ""); - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - - switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) { - case TX4938_CCFG_PCIDIVMODE_4: - pciclk = txx9_cpu_clock / 4; break; - case TX4938_CCFG_PCIDIVMODE_4_5: - pciclk = txx9_cpu_clock * 2 / 9; break; - case TX4938_CCFG_PCIDIVMODE_5: - pciclk = txx9_cpu_clock / 5; break; - case TX4938_CCFG_PCIDIVMODE_5_5: - pciclk = txx9_cpu_clock * 2 / 11; break; - case TX4938_CCFG_PCIDIVMODE_8: - pciclk = txx9_cpu_clock / 8; break; - case TX4938_CCFG_PCIDIVMODE_9: - pciclk = txx9_cpu_clock / 9; break; - case TX4938_CCFG_PCIDIVMODE_10: - pciclk = txx9_cpu_clock / 10; break; - case TX4938_CCFG_PCIDIVMODE_11: - pciclk = txx9_cpu_clock / 11; break; - } - printk("Internal(%dMHz)", pciclk / 1000000); - } else { - printk("External"); - pciclk = -1; - } - printk("\n"); - return pciclk; -} - -void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr) -{ - pcicptrs[ch] = pcicptr; -} - -struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch) -{ - return pcicptrs[ch]; -} - -static struct pci_dev *fake_pci_dev(struct pci_controller *hose, - int top_bus, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; + register_pci_controller(c); - dev.sysdata = bus.sysdata = hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - bus.parent = NULL; - dev.bus = &bus; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -static int early_##rw##_config_##size(struct pci_controller *hose, \ - int top_bus, int bus, int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size( \ - fake_pci_dev(hose, top_bus, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, word, u16 *) - -int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus) -{ - u32 pci_devfn; - unsigned short vid; - int devfn_start = 0; - int devfn_stop = 0xff; - int cap66 = -1; - u16 stat; - - printk("PCI: Checking 66MHz capabilities...\n"); - - for (pci_devfn=devfn_start; pci_devfn 0; -} - -int __init -tx4938_pciclk66_setup(void) -{ - int pciclk; - - /* Assert M66EN */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66; - /* Double PCICLK (if possible) */ - if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) { - unsigned int pcidivmode = - tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK; - switch (pcidivmode) { - case TX4938_CCFG_PCIDIVMODE_8: - case TX4938_CCFG_PCIDIVMODE_4: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4; - pciclk = txx9_cpu_clock / 4; - break; - case TX4938_CCFG_PCIDIVMODE_9: - case TX4938_CCFG_PCIDIVMODE_4_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5; - pciclk = txx9_cpu_clock * 2 / 9; - break; - case TX4938_CCFG_PCIDIVMODE_10: - case TX4938_CCFG_PCIDIVMODE_5: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5; - pciclk = txx9_cpu_clock / 5; - break; - case TX4938_CCFG_PCIDIVMODE_11: - case TX4938_CCFG_PCIDIVMODE_5_5: - default: - pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5; - pciclk = txx9_cpu_clock * 2 / 11; - break; - } - tx4938_ccfgptr->ccfg = - (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK) - | pcidivmode; - printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n", - (unsigned long)tx4938_ccfgptr->ccfg); - } else { - pciclk = -1; - } - return pciclk; -} - -extern struct pci_controller tx4938_pci_controller[]; -static int __init tx4938_pcibios_init(void) -{ - unsigned long mem_base[2]; - unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ - unsigned long io_base[2]; - unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ - /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ - int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); - - PCIBIOS_MIN_IO = 0x00001000UL; - - mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); - io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); - - printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", - (unsigned short)(tx4938_pcicptr->pciid >> 16), - (unsigned short)(tx4938_pcicptr->pciid & 0xffff), - (unsigned short)(tx4938_pcicptr->pciccrev & 0xff), - extarb ? "External" : "Internal"); - - /* setup PCI area */ - tx4938_pci_controller[0].io_resource->start = io_base[0]; - tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1; - tx4938_pci_controller[0].mem_resource->start = mem_base[0]; - tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1; - - set_tx4938_pcicptr(0, tx4938_pcicptr); - - register_pci_controller(&tx4938_pci_controller[0]); - - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) { - printk("TX4938_CCFG_PCI66 already configured\n"); - txboard_pci66_mode = -1; /* already configured */ - } + if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) + txx9_pci_option = + (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | + TXX9_PCI_OPT_CLK_66; /* already configured */ /* Reset PCI Bus */ writeb(0, rbtx4938_pcireset_addr); /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; - if (txboard_pci66_mode > 0) + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_66) tx4938_pciclk66_setup(); mdelay(10); /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); writeb(1, rbtx4938_pcireset_addr); - mmiowb(); - tx4938_report_pcic_status1(tx4938_pcicptr); + iob(); tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); - if (txboard_pci66_mode == 0 && - txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { + tx4927_pcic_setup(tx4938_pcicptr, c, extarb); + if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == + TXX9_PCI_OPT_CLK_AUTO && + txx9_pci66_check(c, 0, 0)) { /* Reset PCI Bus */ writeb(0, rbtx4938_pcireset_addr); /* Reset PCIC */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); tx4938_pciclk66_setup(); mdelay(10); /* clear PCIC reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); writeb(1, rbtx4938_pcireset_addr); - mmiowb(); + iob(); /* Reinitialize PCIC */ tx4938_report_pciclk(); - tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); + tx4927_pcic_setup(tx4938_pcicptr, c, extarb); } - mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); - io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); - /* Reset PCIC1 */ - tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; - /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; - else - tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; - mdelay(10); - /* clear PCIC1 reset */ - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; - tx4938_report_pcic_status1(tx4938_pcic1ptr); - - printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", - (unsigned short)(tx4938_pcic1ptr->pciid >> 16), - (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), - (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); - printk("%s PCICLK:%dMHz\n", - (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "", - txx9_gbus_clock / - ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) / - 1000000); - - /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */ - tx4938_pci_controller[1].io_resource->start = - io_base[1] - io_base[0]; - tx4938_pci_controller[1].io_resource->end = - io_base[1] - io_base[0] + io_size[1] - 1; - tx4938_pci_controller[1].mem_resource->start = mem_base[1]; - tx4938_pci_controller[1].mem_resource->end = - mem_base[1] + mem_size[1] - 1; - set_tx4938_pcicptr(1, tx4938_pcic1ptr); - - register_pci_controller(&tx4938_pci_controller[1]); - - tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb); - - /* map ioport 0 to PCI I/O space address 0 */ - set_io_port_base(KSEG1 + io_base[0]); - - return 0; -} - -arch_initcall(tx4938_pcibios_init); - + if (__raw_readq(&tx4938_ccfgptr->pcfg) & + (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) { + /* Reset PCIC1 */ + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); + /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ + if (!(__raw_readq(&tx4938_ccfgptr->ccfg) + & TX4938_CCFG_PCI1DMD)) + tx4938_ccfg_set(TX4938_CCFG_PCI1_66); + mdelay(10); + /* clear PCIC1 reset */ + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); + tx4938_report_pci1clk(); + + /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */ + c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000); + register_pci_controller(c); + tx4927_pcic_setup(tx4938_pcic1ptr, c, 0); + } #endif /* CONFIG_PCI */ +} /* SPI support */ @@ -594,7 +170,7 @@ static int __init rbtx4938_ethaddr_init(void) unsigned int id = TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); struct platform_device *pdev; - if (!(tx4938_ccfgptr->pcfg & + if (!(__raw_readq(&tx4938_ccfgptr->pcfg) & (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) continue; pdev = platform_device_alloc("tc35815-mac", id); @@ -611,18 +187,12 @@ device_initcall(rbtx4938_ethaddr_init); static void __init rbtx4938_spi_setup(void) { /* set SPI_SEL */ - tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; + txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL); } static struct resource rbtx4938_fpga_resource; - -static char pcode_str[8]; -static struct resource tx4938_reg_resource = { - .start = TX4938_REG_BASE, - .end = TX4938_REG_BASE + TX4938_REG_SIZE, - .name = pcode_str, - .flags = IORESOURCE_MEM -}; +static struct resource tx4938_sdram_resource[4]; +static struct resource tx4938_sram_resource; void __init tx4938_board_setup(void) { @@ -631,24 +201,28 @@ void __init tx4938_board_setup(void) int cpuclk = 0; unsigned long pcode = TX4938_REV_PCODE(); - ioport_resource.start = 0x1000; + ioport_resource.start = 0; ioport_resource.end = 0xffffffff; - iomem_resource.start = 0x1000; + iomem_resource.start = 0; iomem_resource.end = 0xffffffff; /* expand to 4GB */ - sprintf(pcode_str, "TX%lx", pcode); + txx9_reg_res_init(pcode, TX4938_REG_BASE, + TX4938_REG_SIZE); /* SDRAMC,EBUSC are configured by PROM */ for (i = 0; i < 8; i++) { - if (!(tx4938_ebuscptr->cr[i] & 0x8)) + if (!(TX4938_EBUSC_CR(i) & 0x8)) continue; /* disabled */ - rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); - txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); + txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i); + txx9_ce_res[i].end = + txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1; + request_resource(&iomem_resource, &txx9_ce_res[i]); } /* clocks */ if (txx9_master_clock) { + u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); /* calculate gbus_clock and cpu_clock_freq from master_clock */ - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; switch (divmode) { case TX4938_CCFG_DIVMODE_8: case TX4938_CCFG_DIVMODE_10: @@ -678,12 +252,13 @@ void __init tx4938_board_setup(void) } txx9_cpu_clock = cpuclk; } else { + u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); if (txx9_cpu_clock == 0) { txx9_cpu_clock = 300000000; /* 300MHz */ } /* calculate gbus_clock and master_clock from cpu_clock_freq */ cpuclk = txx9_cpu_clock; - divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; + divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; switch (divmode) { case TX4938_CCFG_DIVMODE_2: case TX4938_CCFG_DIVMODE_8: @@ -717,32 +292,32 @@ void __init tx4938_board_setup(void) /* CCFG */ /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; + tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW); /* do reset on watchdog */ - tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; + tx4938_ccfg_set(TX4938_CCFG_WR); /* clear PCIC1 reset */ - if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) - tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; + txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); /* enable Timeout BusError */ if (tx4938_ccfg_toeon) - tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; + tx4938_ccfg_set(TX4938_CCFG_TOE); /* DMA selection */ - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL); /* Use external clock for external arbiter */ - if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; - - printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", - pcode_str, - cpuclk / 1000000, txx9_master_clock / 1000000, - (unsigned long)tx4938_ccfgptr->crir, - tx4938_ccfgptr->ccfg, - tx4938_ccfgptr->pcfg); - - printk("%s SDRAMC --", pcode_str); + if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB)) + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL); + + printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", + txx9_pcode_str, + (cpuclk + 500000) / 1000000, + (txx9_master_clock + 500000) / 1000000, + (__u32)____raw_readq(&tx4938_ccfgptr->crir), + (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), + (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg)); + + printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); for (i = 0; i < 4; i++) { unsigned long long cr = tx4938_sdramcptr->cr[i]; unsigned long ram_base, ram_size; @@ -753,16 +328,24 @@ void __init tx4938_board_setup(void) if (ram_base >= 0x20000000) continue; /* high memory (ignore) */ printk(" CR%d:%016Lx", i, cr); - txboard_add_phys_region(ram_base, ram_size); + tx4938_sdram_resource[i].name = "SDRAM"; + tx4938_sdram_resource[i].start = ram_base; + tx4938_sdram_resource[i].end = ram_base + ram_size - 1; + tx4938_sdram_resource[i].flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &tx4938_sdram_resource[i]); } printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); /* SRAM */ - if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { + if (tx4938_sramcptr->cr & 1) { unsigned int size = 0x800; unsigned long base = (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); - txboard_add_phys_region(base, size); + tx4938_sram_resource.name = "SRAM"; + tx4938_sram_resource.start = base; + tx4938_sram_resource.end = base + size - 1; + tx4938_sram_resource.flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &tx4938_sram_resource); } /* TMR */ @@ -778,71 +361,15 @@ void __init tx4938_board_setup(void) __raw_writel(0, &tx4938_pioptr->maskcpu); __raw_writel(0, &tx4938_pioptr->maskext); - /* TX4938 internal registers */ - if (request_resource(&iomem_resource, &tx4938_reg_resource)) - printk("request resource for internal registers failed\n"); -} - #ifdef CONFIG_PCI -static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) -{ - unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16); - unsigned long g2pstatus = pcicptr->g2pstatus; - unsigned long pcicstatus = pcicptr->pcicstatus; - static struct { - unsigned long flag; - const char *str; - } pcistat_tbl[] = { - { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, - { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, - { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, - { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, - { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, - { PCI_STATUS_PARITY, "MasterParityError" }, - }, g2pstat_tbl[] = { - { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" }, - { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" }, - }, pcicstat_tbl[] = { - { TX4938_PCIC_PCICSTATUS_PME, "PME" }, - { TX4938_PCIC_PCICSTATUS_TLB, "TLB" }, - { TX4938_PCIC_PCICSTATUS_NIB, "NIB" }, - { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" }, - { TX4938_PCIC_PCICSTATUS_PERR, "PERR" }, - { TX4938_PCIC_PCICSTATUS_SERR, "SERR" }, - { TX4938_PCIC_PCICSTATUS_GBE, "GBE" }, - { TX4938_PCIC_PCICSTATUS_IWB, "IWB" }, - }; - int i; - - printk("pcistat:%04x(", pcistatus); - for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++) - if (pcistatus & pcistat_tbl[i].flag) - printk("%s ", pcistat_tbl[i].str); - printk("), g2pstatus:%08lx(", g2pstatus); - for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) - if (g2pstatus & g2pstat_tbl[i].flag) - printk("%s ", g2pstat_tbl[i].str); - printk("), pcicstatus:%08lx(", pcicstatus); - for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) - if (pcicstatus & pcicstat_tbl[i].flag) - printk("%s ", pcicstat_tbl[i].str); - printk(")\n"); -} - -void tx4938_report_pcic_status(void) -{ - int i; - struct tx4938_pcic_reg *pcicptr; - for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++) - tx4938_report_pcic_status1(pcicptr); + txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); +#endif } -#endif /* CONFIG_PCI */ - void __init plat_time_init(void) { mips_hpt_frequency = txx9_cpu_clock / 2; - if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) + if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, TXX9_IRQ_BASE + TX4938_IR_TMR(0), txx9_gbus_clock / 2); @@ -890,19 +417,20 @@ void __init plat_mem_setup(void) #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 printk("PIOSEL: disabling both ata and nand selection\n"); local_irq_disable(); - tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); + txx9_clear64(&tx4938_ccfgptr->pcfg, + TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND printk("PIOSEL: enabling nand selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; + txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA printk("PIOSEL: enabling ata selection\n"); - tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; - tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; + txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); #endif #ifdef CONFIG_IP_PNP @@ -920,7 +448,7 @@ void __init plat_mem_setup(void) #endif rbtx4938_spi_setup(); - pcfg = tx4938_ccfgptr->pcfg; /* updated */ + pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */ /* fixup piosel */ if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == TX4938_PCFG_ATA_SEL) @@ -1063,6 +591,7 @@ static int __init rbtx4938_arch_init(void) { txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); gpiochip_add(&rbtx4938_spi_gpio_chip); + rbtx4938_pci_setup(); return rbtx4938_spi_init(); } arch_initcall(rbtx4938_arch_init); diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h new file mode 100644 index 000000000000..2ff6c2002204 --- /dev/null +++ b/include/asm-mips/txx9/generic.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm-mips/txx9/generic.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9_GENERIC_H +#define __ASM_TXX9_GENERIC_H + +#include +#include /* for struct resource */ + +extern struct resource txx9_ce_res[]; +extern char txx9_pcode_str[8]; +void txx9_reg_res_init(unsigned int pcode, unsigned long base, + unsigned long size); + +extern unsigned int txx9_master_clock; +extern unsigned int txx9_cpu_clock; +extern unsigned int txx9_gbus_clock; + +#endif /* __ASM_TXX9_GENERIC_H */ diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h new file mode 100644 index 000000000000..d89a45091e24 --- /dev/null +++ b/include/asm-mips/txx9/pci.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9_PCI_H +#define __ASM_TXX9_PCI_H + +#include + +extern struct pci_controller txx9_primary_pcic; +struct pci_controller * +txx9_alloc_pci_controller(struct pci_controller *pcic, + unsigned long mem_base, unsigned long mem_size, + unsigned long io_base, unsigned long io_size); + +int txx9_pci66_check(struct pci_controller *hose, int top_bus, + int current_bus); +extern int txx9_pci_mem_high __initdata; + +extern int txx9_pci_option; +#define TXX9_PCI_OPT_PICMG 0x0002 +#define TXX9_PCI_OPT_CLK_33 0x0008 +#define TXX9_PCI_OPT_CLK_66 0x0010 +#define TXX9_PCI_OPT_CLK_MASK \ + (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66) +#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK + +enum txx9_pci_err_action { + TXX9_PCI_ERR_REPORT, + TXX9_PCI_ERR_IGNORE, + TXX9_PCI_ERR_PANIC, +}; +extern enum txx9_pci_err_action txx9_pci_err_action; + +#endif /* __ASM_TXX9_PCI_H */ diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h index 5531342bcc01..5b6f488b1b3c 100644 --- a/include/asm-mips/txx9/rbtx4927.h +++ b/include/asm-mips/txx9/rbtx4927.h @@ -29,10 +29,33 @@ #include +#define RBTX4927_PCIMEM 0x08000000 +#define RBTX4927_PCIMEM_SIZE 0x08000000 +#define RBTX4927_PCIIO 0x16000000 +#define RBTX4927_PCIIO_SIZE 0x01000000 + +#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL) + +/* bits for ISTAT/IMASK/IMSTAT */ +#define RBTX4927_INTB_PCID 0 +#define RBTX4927_INTB_PCIC 1 +#define RBTX4927_INTB_PCIB 2 +#define RBTX4927_INTB_PCIA 3 +#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID) +#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC) +#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB) +#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA) + +#define RBTX4927_IRQ_IOC (TX4927_IRQ_PIC_BEG + TX4927_NUM_IR) +#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID) +#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC) +#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB) +#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA) + #ifdef CONFIG_PCI -#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO +#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO #else -#define TBTX4927_ISA_IO_OFFSET 0 +#define RBTX4927_ISA_IO_OFFSET 0 #endif #define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL @@ -41,7 +64,7 @@ #define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL #define RBTX4927_SW_RESET_ENABLE_SET 0x01 -#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) +#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET) #define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) int toshiba_rbtx4927_irq_nested(int sw_irq); diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h index 63b62d6061f5..ca414c7624e1 100644 --- a/include/asm-mips/txx9/tx3927.h +++ b/include/asm-mips/txx9/tx3927.h @@ -316,4 +316,8 @@ struct tx3927_ccfg_reg { #define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) #define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) +struct pci_controller; +void __init tx3927_pcic_setup(struct pci_controller *channel, + unsigned long sdram_size, int extarb); + #endif /* __ASM_TXX9_TX3927_H */ diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h index f21a7b1831e5..c0382fd2ae7f 100644 --- a/include/asm-mips/txx9/tx4927.h +++ b/include/asm-mips/txx9/tx4927.h @@ -27,7 +27,10 @@ #ifndef __ASM_TXX9_TX4927_H #define __ASM_TXX9_TX4927_H +#include +#include #include +#include #define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE #define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) @@ -43,15 +46,6 @@ #define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) -#define TX4927_CCFG_TOE 0x00004000 -#define TX4927_CCFG_WR 0x00008000 -#define TX4927_CCFG_TINTDIS 0x01000000 - -#define TX4927_PCIMEM 0x08000000 -#define TX4927_PCIMEM_SIZE 0x08000000 -#define TX4927_PCIIO 0x16000000 -#define TX4927_PCIIO_SIZE 0x01000000 - #define TX4927_SDRAMC_REG 0xff1f8000 #define TX4927_EBUSC_REG 0xff1f9000 #define TX4927_PCIC_REG 0xff1fd000 @@ -60,36 +54,9 @@ #define TX4927_NR_TMR 3 #define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) -/* bits for ISTAT3/IMASK3/IMSTAT3 */ -#define TX4927_INT3B_PCID 0 -#define TX4927_INT3B_PCIC 1 -#define TX4927_INT3B_PCIB 2 -#define TX4927_INT3B_PCIA 3 -#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID) -#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC) -#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB) -#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA) - -#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG -#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ - #define TX4927_IR_PCIC 16 #define TX4927_IR_PCIERR 22 -#define TX4927_IR_PCIPMA 23 -#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC) -#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR) -#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC) -#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID) -#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC) -#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB) -#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA) - -#ifdef _LANGUAGE_ASSEMBLY -#define _CONST64(c) c -#else -#define _CONST64(c) c##ull - -#include +#define TX4927_NUM_IR 32 struct tx4927_sdramc_reg { volatile unsigned long long cr[4]; @@ -104,177 +71,158 @@ struct tx4927_ebusc_reg { }; struct tx4927_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; -}; - -struct tx4927_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmcut; - volatile unsigned long long pdmcnt; /* +220 */ - volatile unsigned long long pdmsts; - volatile unsigned long long unused8[2]; - volatile unsigned long long pdmdb[4]; /* +240 */ - volatile unsigned long long pdmtdh; /* +260 */ - volatile unsigned long long pdmdms; + u64 ccfg; + u64 crir; + u64 pcfg; + u64 toea; + u64 clkctr; + u64 unused0; + u64 garbc; + u64 unused1; + u64 unused2; + u64 ramp; }; -#endif /* _LANGUAGE_ASSEMBLY */ - -/* - * PCIC - */ - -/* bits for G2PSTATUS/G2PMASK */ -#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4927_PCIC_PBACFG_RPBA 0x00000004 -#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc - -/* bits for PCICCFG */ -#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000 -#define TX4927_PCIC_PCICCFG_HRST 0x00000800 -#define TX4927_PCIC_PCICCFG_SRST 0x00000400 -#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100 -#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080 -#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040 -#define TX4927_PCIC_PCICCFG_IISE 0x00000020 -#define TX4927_PCIC_PCICCFG_ATR 0x00000010 -#define TX4927_PCIC_PCICCFG_ICAE 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) - /* * CCFG */ /* CCFG : Chip Configuration */ +#define TX4927_CCFG_WDRST 0x0000020000000000ULL +#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL +#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL +#define TX4927_CCFG_TINTDIS 0x01000000 #define TX4927_CCFG_PCI66 0x00800000 -#define TX4927_CCFG_PCIMIDE 0x00400000 -#define TX4927_CCFG_PCIXARB 0x00002000 +#define TX4927_CCFG_PCIMODE 0x00400000 +#define TX4927_CCFG_DIVMODE_MASK 0x000e0000 +#define TX4927_CCFG_DIVMODE_8 (0x0 << 17) +#define TX4927_CCFG_DIVMODE_12 (0x1 << 17) +#define TX4927_CCFG_DIVMODE_16 (0x2 << 17) +#define TX4927_CCFG_DIVMODE_10 (0x3 << 17) +#define TX4927_CCFG_DIVMODE_2 (0x4 << 17) +#define TX4927_CCFG_DIVMODE_3 (0x5 << 17) +#define TX4927_CCFG_DIVMODE_4 (0x6 << 17) +#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17) +#define TX4927_CCFG_BEOW 0x00010000 +#define TX4927_CCFG_WR 0x00008000 +#define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_PCIARB 0x00002000 #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 #define TX4927_CCFG_PCIDIVMODE_3 0x00000800 #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 - -#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 -#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 -#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 -#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 -#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 -#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 -#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 -#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 -#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 +#define TX4927_CCFG_SYSSP_MASK 0x000000c0 +#define TX4927_CCFG_ENDIAN 0x00000004 +#define TX4927_CCFG_HALT 0x00000002 +#define TX4927_CCFG_ACEHOLD 0x00000001 +#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW) /* PCFG : Pin Configuration */ +#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000 +#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28) +#define TX4927_PCFG_SYSCLKEN 0x08000000 +#define TX4927_PCFG_SDCLKEN_ALL 0x07800000 +#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) +#define TX4927_PCFG_SEL2 0x00000200 +#define TX4927_PCFG_SEL1 0x00000100 +#define TX4927_PCFG_DMASEL_ALL 0x000000ff +#define TX4927_PCFG_DMASEL0_MASK 0x00000003 +#define TX4927_PCFG_DMASEL1_MASK 0x0000000c +#define TX4927_PCFG_DMASEL2_MASK 0x00000030 +#define TX4927_PCFG_DMASEL3_MASK 0x000000c0 +#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000 +#define TX4927_PCFG_DMASEL0_SIO1 0x00000001 +#define TX4927_PCFG_DMASEL0_ACL0 0x00000002 +#define TX4927_PCFG_DMASEL0_ACL2 0x00000003 +#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000 +#define TX4927_PCFG_DMASEL1_SIO1 0x00000004 +#define TX4927_PCFG_DMASEL1_ACL1 0x00000008 +#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c +#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */ +#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */ +#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */ +#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */ +#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */ +#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000 +#define TX4927_PCFG_DMASEL3_SIO0 0x00000040 +#define TX4927_PCFG_DMASEL3_ACL3 0x00000080 +#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0 /* CLKCTR : Clock Control */ +#define TX4927_CLKCTR_ACLCKD 0x02000000 +#define TX4927_CLKCTR_PIOCKD 0x01000000 +#define TX4927_CLKCTR_DMACKD 0x00800000 #define TX4927_CLKCTR_PCICKD 0x00400000 +#define TX4927_CLKCTR_TM0CKD 0x00100000 +#define TX4927_CLKCTR_TM1CKD 0x00080000 +#define TX4927_CLKCTR_TM2CKD 0x00040000 +#define TX4927_CLKCTR_SIO0CKD 0x00020000 +#define TX4927_CLKCTR_SIO1CKD 0x00010000 +#define TX4927_CLKCTR_ACLRST 0x00000200 +#define TX4927_CLKCTR_PIORST 0x00000100 +#define TX4927_CLKCTR_DMARST 0x00000080 #define TX4927_CLKCTR_PCIRST 0x00000040 - -#ifndef _LANGUAGE_ASSEMBLY +#define TX4927_CLKCTR_TM0RST 0x00000010 +#define TX4927_CLKCTR_TM1RST 0x00000008 +#define TX4927_CLKCTR_TM2RST 0x00000004 +#define TX4927_CLKCTR_SIO0RST 0x00000002 +#define TX4927_CLKCTR_SIO1RST 0x00000001 #define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) -#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) -#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) +#define tx4927_pcicptr \ + ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) +#define tx4927_ccfgptr \ + ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) #define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) -#endif /* _LANGUAGE_ASSEMBLY */ +/* utilities */ +static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) +{ +#ifdef CONFIG_32BIT + unsigned long flags; + local_irq_save(flags); +#endif + ____raw_writeq(____raw_readq(adr) & ~bits, adr); +#ifdef CONFIG_32BIT + local_irq_restore(flags); +#endif +} +static inline void txx9_set64(__u64 __iomem *adr, __u64 bits) +{ +#ifdef CONFIG_32BIT + unsigned long flags; + local_irq_save(flags); +#endif + ____raw_writeq(____raw_readq(adr) | bits, adr); +#ifdef CONFIG_32BIT + local_irq_restore(flags); +#endif +} + +/* These functions are not interrupt safe. */ +static inline void tx4927_ccfg_clear(__u64 bits) +{ + ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg) + & ~(TX4927_CCFG_W1CBITS | bits), + &tx4927_ccfgptr->ccfg); +} +static inline void tx4927_ccfg_set(__u64 bits) +{ + ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) + & ~TX4927_CCFG_W1CBITS) | bits, + &tx4927_ccfgptr->ccfg); +} +static inline void tx4927_ccfg_change(__u64 change, __u64 new) +{ + ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) + & ~(TX4927_CCFG_W1CBITS | change)) | + new, + &tx4927_ccfgptr->ccfg); +} + +int tx4927_report_pciclk(void); +int tx4927_pciclk66_setup(void); #endif /* __ASM_TXX9_TX4927_H */ diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h new file mode 100644 index 000000000000..d61c3d09c4a2 --- /dev/null +++ b/include/asm-mips/txx9/tx4927pcic.h @@ -0,0 +1,199 @@ +/* + * include/asm-mips/txx9/tx4927pcic.h + * TX4927 PCI controller definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9_TX4927PCIC_H +#define __ASM_TXX9_TX4927PCIC_H + +#include + +struct tx4927_pcic_reg { + u32 pciid; + u32 pcistatus; + u32 pciccrev; + u32 pcicfg1; + u32 p2gm0plbase; /* +10 */ + u32 p2gm0pubase; + u32 p2gm1plbase; + u32 p2gm1pubase; + u32 p2gm2pbase; /* +20 */ + u32 p2giopbase; + u32 unused0; + u32 pcisid; + u32 unused1; /* +30 */ + u32 pcicapptr; + u32 unused2; + u32 pcicfg2; + u32 g2ptocnt; /* +40 */ + u32 unused3[15]; + u32 g2pstatus; /* +80 */ + u32 g2pmask; + u32 pcisstatus; + u32 pcimask; + u32 p2gcfg; /* +90 */ + u32 p2gstatus; + u32 p2gmask; + u32 p2gccmd; + u32 unused4[24]; /* +a0 */ + u32 pbareqport; /* +100 */ + u32 pbacfg; + u32 pbastatus; + u32 pbamask; + u32 pbabm; /* +110 */ + u32 pbacreq; + u32 pbacgnt; + u32 pbacstate; + u64 g2pmgbase[3]; /* +120 */ + u64 g2piogbase; + u32 g2pmmask[3]; /* +140 */ + u32 g2piomask; + u64 g2pmpbase[3]; /* +150 */ + u64 g2piopbase; + u32 pciccfg; /* +170 */ + u32 pcicstatus; + u32 pcicmask; + u32 unused5; + u64 p2gmgbase[3]; /* +180 */ + u64 p2giogbase; + u32 g2pcfgadrs; /* +1a0 */ + u32 g2pcfgdata; + u32 unused6[8]; + u32 g2pintack; + u32 g2pspc; + u32 unused7[12]; /* +1d0 */ + u64 pdmca; /* +200 */ + u64 pdmga; + u64 pdmpa; + u64 pdmctr; + u64 pdmcfg; /* +220 */ + u64 pdmsts; +}; + +/* bits for PCICMD */ +/* see PCI_COMMAND_XXX in linux/pci_regs.h */ + +/* bits for PCISTAT */ +/* see PCI_STATUS_XXX in linux/pci_regs.h */ + +/* bits for IOBA/MBA */ +/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */ + +/* bits for G2PSTATUS/G2PMASK */ +#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 +#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 +#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 + +/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */ +#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 + +/* bits for PBACFG */ +#define TX4927_PCIC_PBACFG_FIXPA 0x00000008 +#define TX4927_PCIC_PBACFG_RPBA 0x00000004 +#define TX4927_PCIC_PBACFG_PBAEN 0x00000002 +#define TX4927_PCIC_PBACFG_BMCEN 0x00000001 + +/* bits for PBASTATUS/PBAMASK */ +#define TX4927_PCIC_PBASTATUS_ALL 0x00000001 +#define TX4927_PCIC_PBASTATUS_BM 0x00000001 + +/* bits for G2PMnGBASE */ +#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL +#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL + +/* bits for G2PIOGBASE */ +#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL +#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL + +/* bits for PCICSTATUS/PCICMASK */ +#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8 +#define TX4927_PCIC_PCICSTATUS_PME 0x00000400 +#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200 +#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100 +#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080 +#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020 +#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010 +#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008 +#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002 +#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001 + +/* bits for PCICCFG */ +#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 +#define TX4927_PCIC_PCICCFG_HRST 0x00000800 +#define TX4927_PCIC_PCICCFG_SRST 0x00000400 +#define TX4927_PCIC_PCICCFG_IRBER 0x00000200 +#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) +#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100 +#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080 +#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040 +#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020 +#define TX4927_PCIC_PCICCFG_TCAR 0x00000010 +#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008 + +/* bits for P2GMnGBASE */ +#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL +#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL +#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL + +/* bits for P2GIOGBASE */ +#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL +#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL +#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL + +#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) +#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) + +/* bits for PDMCFG */ +#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000 +#define TX4927_PCIC_PDMCFG_EXFER 0x00100000 +#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800 +#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11) +#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11) +#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400 +#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200 +#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100 +#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080 +#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040 +#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020 +#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c +#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 +#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 +#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 +#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002 +#define TX4927_PCIC_PDMCFG_CHRST 0x00000001 + +/* bits for PDMSTS */ +#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 +#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 +#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 +#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000 +#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800 +#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400 +#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200 +#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100 +#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080 +#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040 +#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020 +#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008 +#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004 +#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002 +#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001 +#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0 +#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f + +struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( + struct pci_controller *channel); +void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, + struct pci_controller *channel, int extarb); +void tx4927_report_pcic_status(void); + +#endif /* __ASM_TXX9_TX4927PCIC_H */ diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h index 7f9cfef1c6d2..0bb891993b08 100644 --- a/include/asm-mips/txx9/tx4938.h +++ b/include/asm-mips/txx9/tx4938.h @@ -12,6 +12,9 @@ #ifndef __ASM_TXX9_TX4938_H #define __ASM_TXX9_TX4938_H +/* some controllers are compatible with 4927 */ +#include + #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) #define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) @@ -51,9 +54,6 @@ #define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) #define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) -#ifdef __ASSEMBLY__ -#define _CONST64(c) c -#else #define _CONST64(c) c##ull #include @@ -113,68 +113,6 @@ struct tx4938_dma_reg { endian_def_l2(unused0, mcr); }; -struct tx4938_pcic_reg { - volatile unsigned long pciid; - volatile unsigned long pcistatus; - volatile unsigned long pciccrev; - volatile unsigned long pcicfg1; - volatile unsigned long p2gm0plbase; /* +10 */ - volatile unsigned long p2gm0pubase; - volatile unsigned long p2gm1plbase; - volatile unsigned long p2gm1pubase; - volatile unsigned long p2gm2pbase; /* +20 */ - volatile unsigned long p2giopbase; - volatile unsigned long unused0; - volatile unsigned long pcisid; - volatile unsigned long unused1; /* +30 */ - volatile unsigned long pcicapptr; - volatile unsigned long unused2; - volatile unsigned long pcicfg2; - volatile unsigned long g2ptocnt; /* +40 */ - volatile unsigned long unused3[15]; - volatile unsigned long g2pstatus; /* +80 */ - volatile unsigned long g2pmask; - volatile unsigned long pcisstatus; - volatile unsigned long pcimask; - volatile unsigned long p2gcfg; /* +90 */ - volatile unsigned long p2gstatus; - volatile unsigned long p2gmask; - volatile unsigned long p2gccmd; - volatile unsigned long unused4[24]; /* +a0 */ - volatile unsigned long pbareqport; /* +100 */ - volatile unsigned long pbacfg; - volatile unsigned long pbastatus; - volatile unsigned long pbamask; - volatile unsigned long pbabm; /* +110 */ - volatile unsigned long pbacreq; - volatile unsigned long pbacgnt; - volatile unsigned long pbacstate; - volatile unsigned long long g2pmgbase[3]; /* +120 */ - volatile unsigned long long g2piogbase; - volatile unsigned long g2pmmask[3]; /* +140 */ - volatile unsigned long g2piomask; - volatile unsigned long long g2pmpbase[3]; /* +150 */ - volatile unsigned long long g2piopbase; - volatile unsigned long pciccfg; /* +170 */ - volatile unsigned long pcicstatus; - volatile unsigned long pcicmask; - volatile unsigned long unused5; - volatile unsigned long long p2gmgbase[3]; /* +180 */ - volatile unsigned long long p2giogbase; - volatile unsigned long g2pcfgadrs; /* +1a0 */ - volatile unsigned long g2pcfgdata; - volatile unsigned long unused6[8]; - volatile unsigned long g2pintack; - volatile unsigned long g2pspc; - volatile unsigned long unused7[12]; /* +1d0 */ - volatile unsigned long long pdmca; /* +200 */ - volatile unsigned long long pdmga; - volatile unsigned long long pdmpa; - volatile unsigned long long pdmctr; - volatile unsigned long long pdmcfg; /* +220 */ - volatile unsigned long long pdmsts; -}; - struct tx4938_aclc_reg { volatile unsigned long acctlen; volatile unsigned long acctldis; @@ -262,18 +200,18 @@ struct tx4938_sramc_reg { }; struct tx4938_ccfg_reg { - volatile unsigned long long ccfg; - volatile unsigned long long crir; - volatile unsigned long long pcfg; - volatile unsigned long long tear; - volatile unsigned long long clkctr; - volatile unsigned long long unused0; - volatile unsigned long long garbc; - volatile unsigned long long unused1; - volatile unsigned long long unused2; - volatile unsigned long long ramp; - volatile unsigned long long unused3; - volatile unsigned long long jmpadr; + u64 ccfg; + u64 crir; + u64 pcfg; + u64 toea; + u64 clkctr; + u64 unused0; + u64 garbc; + u64 unused1; + u64 unused2; + u64 ramp; + u64 unused3; + u64 jmpadr; }; #undef endian_def_l2 @@ -282,8 +220,6 @@ struct tx4938_ccfg_reg { #undef endian_def_b2s #undef endian_def_b4 -#endif /* __ASSEMBLY__ */ - /* * NDFMC */ @@ -360,7 +296,7 @@ struct tx4938_ccfg_reg { #define TX4938_CCFG_BEOW 0x00010000 #define TX4938_CCFG_WR 0x00008000 #define TX4938_CCFG_TOE 0x00004000 -#define TX4938_CCFG_PCIXARB 0x00002000 +#define TX4938_CCFG_PCIARB 0x00002000 #define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 #define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) #define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) @@ -436,110 +372,6 @@ struct tx4938_ccfg_reg { #define TX4938_CLKCTR_SIO0RST 0x00000002 #define TX4938_CLKCTR_SIO1RST 0x00000001 -/* bits for G2PSTATUS/G2PMASK */ -#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003 -#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002 -#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001 - -/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900 - -/* bits for PBACFG */ -#define TX4938_PCIC_PBACFG_FIXPA 0x00000008 -#define TX4938_PCIC_PBACFG_RPBA 0x00000004 -#define TX4938_PCIC_PBACFG_PBAEN 0x00000002 -#define TX4938_PCIC_PBACFG_BMCEN 0x00000001 - -/* bits for G2PMnGBASE */ -#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for G2PIOGBASE */ -#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000) - -/* bits for PCICSTATUS/PCICMASK */ -#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8 -#define TX4938_PCIC_PCICSTATUS_PME 0x00000400 -#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200 -#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100 -#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080 -#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020 -#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010 -#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008 -#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002 -#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001 - -/* bits for PCICCFG */ -#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 -#define TX4938_PCIC_PCICCFG_HRST 0x00000800 -#define TX4938_PCIC_PCICCFG_SRST 0x00000400 -#define TX4938_PCIC_PCICCFG_IRBER 0x00000200 -#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) -#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100 -#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080 -#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040 -#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020 -#define TX4938_PCIC_PCICCFG_TCAR 0x00000010 -#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008 - -/* bits for P2GMnGBASE */ -#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000) - -/* bits for P2GIOGBASE */ -#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000) -#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000) -#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000) - -#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32) - -/* bits for PDMCFG */ -#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000 -#define TX4938_PCIC_PDMCFG_EXFER 0x00100000 -#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800 -#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11) -#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11) -#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400 -#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200 -#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100 -#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080 -#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040 -#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020 -#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c -#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 -#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 -#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 -#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002 -#define TX4938_PCIC_PDMCFG_CHRST 0x00000001 - -/* bits for PDMSTS */ -#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 -#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 -#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 -#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000 -#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800 -#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400 -#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200 -#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100 -#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080 -#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040 -#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020 -#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008 -#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004 -#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002 -#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001 -#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0 -#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f - /* * DMA */ @@ -595,15 +427,15 @@ struct tx4938_ccfg_reg { #define TX4938_DMA_CSR_DESERR 0x00000002 #define TX4938_DMA_CSR_SORERR 0x00000001 -#ifndef __ASSEMBLY__ - #define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) #define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) #define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) #define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) -#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) -#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) -#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) +#define tx4938_pcicptr tx4927_pcicptr +#define tx4938_pcic1ptr \ + ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG) +#define tx4938_ccfgptr \ + ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG) #define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) #define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) #define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) @@ -611,17 +443,25 @@ struct tx4938_ccfg_reg { #define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) -#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) -#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) +#define TX4938_REV_PCODE() \ + ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16) + +#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits) +#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) +#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) #define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) #define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) +#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)]) #define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) #define TX4938_EBUSC_SIZE(ch) \ (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) - -#endif /* !__ASSEMBLY__ */ +int tx4938_report_pciclk(void); +void tx4938_report_pci1clk(void); +int tx4938_pciclk66_setup(void); +struct pci_dev; +int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); #endif -- cgit v1.2.3 From edcaf1a6a77315562e9781245cc8e028c9a921dc Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 11 Jul 2008 23:27:54 +0900 Subject: [MIPS] TXx9: Make single kernel can support multiple boards Make single kernel can be used on RBTX4927/37/38. Also make some SoC-specific code independent from board-specific code. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 67 +------------- arch/mips/Makefile | 21 ++--- arch/mips/pci/Makefile | 9 +- arch/mips/pci/fixup-jmr3927.c | 8 +- arch/mips/pci/fixup-rbtx4927.c | 8 +- arch/mips/pci/fixup-rbtx4938.c | 11 +-- arch/mips/txx9/Kconfig | 82 ++++++++++++++++- arch/mips/txx9/generic/Makefile | 4 +- arch/mips/txx9/generic/irq_tx4927.c | 33 +------ arch/mips/txx9/generic/irq_tx4938.c | 31 +------ arch/mips/txx9/generic/pci.c | 11 +++ arch/mips/txx9/generic/setup.c | 169 ++++++++++++++++++++++++++++++++++++ arch/mips/txx9/jmr3927/Makefile | 2 +- arch/mips/txx9/jmr3927/init.c | 57 ------------ arch/mips/txx9/jmr3927/irq.c | 45 +++++----- arch/mips/txx9/jmr3927/prom.c | 46 +++------- arch/mips/txx9/jmr3927/setup.c | 54 +++++------- arch/mips/txx9/rbtx4927/irq.c | 57 ++++++------ arch/mips/txx9/rbtx4927/prom.c | 52 +---------- arch/mips/txx9/rbtx4927/setup.c | 78 ++++++++--------- arch/mips/txx9/rbtx4938/irq.c | 48 ++++++---- arch/mips/txx9/rbtx4938/prom.c | 49 +---------- arch/mips/txx9/rbtx4938/setup.c | 64 +++++--------- include/asm-mips/txx9/generic.h | 18 ++++ include/asm-mips/txx9/jmr3927.h | 5 ++ include/asm-mips/txx9/rbtx4927.h | 13 ++- include/asm-mips/txx9/rbtx4938.h | 36 ++------ include/asm-mips/txx9/tx4927.h | 19 ++-- include/asm-mips/txx9/tx4938.h | 8 +- 29 files changed, 520 insertions(+), 585 deletions(-) delete mode 100644 arch/mips/txx9/jmr3927/init.c (limited to 'include/asm-mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2ea6fff88811..72baa1a70fcb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -550,66 +550,11 @@ config SNI_RM Technology and now in turn merged with Fujitsu. Say Y here to support this machine type. -config TOSHIBA_JMR3927 - bool "Toshiba JMR-TX3927 board" - select CEVT_TXX9 - select DMA_NONCOHERENT - select HW_HAS_PCI - select MIPS_TX3927 - select IRQ_TXX9 - select SWAP_IO_SPACE - select SYS_HAS_CPU_TX39XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_BIG_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ - select GPIO_TXX9 +config MACH_TX39XX + bool "Toshiba TX39 series based machines" -config TOSHIBA_RBTX4927 - bool "Toshiba RBTX49[23]7 board" - select CEVT_R4K - select CSRC_R4K - select CEVT_TXX9 - select DMA_NONCOHERENT - select HAS_TXX9_SERIAL - select HW_HAS_PCI - select IRQ_CPU - select IRQ_TXX9 - select PCI_TX4927 - select SWAP_IO_SPACE - select SYS_HAS_CPU_TX49XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_KGDB - select GENERIC_HARDIRQS_NO__DO_IRQ - help - This Toshiba board is based on the TX4927 processor. Say Y here to - support this machine type - -config TOSHIBA_RBTX4938 - bool "Toshiba RBTX4938 board" - select CEVT_R4K - select CSRC_R4K - select CEVT_TXX9 - select DMA_NONCOHERENT - select HAS_TXX9_SERIAL - select HW_HAS_PCI - select IRQ_CPU - select IRQ_TXX9 - select PCI_TX4927 - select SWAP_IO_SPACE - select SYS_HAS_CPU_TX49XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_KGDB - select GENERIC_HARDIRQS_NO__DO_IRQ - select GPIO_TXX9 - help - This Toshiba board is based on the TX4938 processor. Say Y here to - support this machine type +config MACH_TX49XX + bool "Toshiba TX49 series based machines" config WR_PPMC bool "Wind River PPMC board" @@ -887,10 +832,6 @@ config PCI_GT64XXX_PCI0 config NO_EXCEPT_FILL bool -config MIPS_TX3927 - bool - select HAS_TXX9_SERIAL - config MIPS_RM9122 bool select SERIAL_RM9000 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 8e1e49c5186b..d319cd624135 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -550,30 +550,31 @@ load-$(CONFIG_SNI_RM) += 0xffffffff80030000 endif all-$(CONFIG_SNI_RM) := vmlinux.ecoff +# +# Common TXx9 +# +core-$(CONFIG_MACH_TX39XX) += arch/mips/txx9/generic/ +cflags-$(CONFIG_MACH_TX39XX) += -Iinclude/asm-mips/mach-jmr3927 +load-$(CONFIG_MACH_TX39XX) += 0xffffffff80050000 +core-$(CONFIG_MACH_TX49XX) += arch/mips/txx9/generic/ +cflags-$(CONFIG_MACH_TX49XX) += -Iinclude/asm-mips/mach-tx49xx +load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000 + # # Toshiba JMR-TX3927 board # -core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ \ - arch/mips/txx9/generic/ -cflags-$(CONFIG_TOSHIBA_JMR3927) += -Iinclude/asm-mips/mach-jmr3927 -load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 +core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ # # Toshiba RBTX4927 board or # Toshiba RBTX4937 board # core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ -core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/generic/ -cflags-$(CONFIG_TOSHIBA_RBTX4927) += -Iinclude/asm-mips/mach-tx49xx -load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 # # Toshiba RBTX4938 board # core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ -core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/generic/ -cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx -load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 cflags-y += -Iinclude/asm-mips/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 908764878ac8..875b643438c0 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -11,11 +11,10 @@ obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o -obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o +obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o -obj-$(CONFIG_PCI_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o # @@ -44,8 +43,10 @@ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o -obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o pci-tx4927.o pci-tx4938.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o pci-tx4938.o +obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o +obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o +obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o +obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index d5edaf21e088..0f1069527cba 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -31,7 +31,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; @@ -77,9 +77,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) irq = JMR3927_IRQ_ETHER0; return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index abab4852d158..321db265829c 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -36,7 +36,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; @@ -71,9 +71,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } return irq; } - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c index 39c995830384..a80579af609b 100644 --- a/arch/mips/pci/fixup-rbtx4938.c +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -13,7 +13,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { int irq = tx4938_pcic1_map_irq(dev, slot); @@ -51,12 +51,3 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } return irq; } - -/* - * Do platform specific device initialization at pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig index b8cdb192543a..b92a134ef124 100644 --- a/arch/mips/txx9/Kconfig +++ b/arch/mips/txx9/Kconfig @@ -1,11 +1,89 @@ +config TOSHIBA_JMR3927 + bool "Toshiba JMR-TX3927 board" + depends on MACH_TX39XX + select SOC_TX3927 + +config TOSHIBA_RBTX4927 + bool "Toshiba RBTX49[23]7 board" + depends on MACH_TX49XX + select SOC_TX4927 + help + This Toshiba board is based on the TX4927 processor. Say Y here to + support this machine type + +config TOSHIBA_RBTX4938 + bool "Toshiba RBTX4938 board" + depends on MACH_TX49XX + select SOC_TX4938 + help + This Toshiba board is based on the TX4938 processor. Say Y here to + support this machine type + +config SOC_TX3927 + bool + select CEVT_TXX9 + select DMA_NONCOHERENT + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select IRQ_TXX9 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX39XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + select GPIO_TXX9 + +config SOC_TX4927 + bool + select CEVT_R4K + select CSRC_R4K + select CEVT_TXX9 + select DMA_NONCOHERENT + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select IRQ_CPU + select IRQ_TXX9 + select PCI_TX4927 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX49XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB + select GENERIC_HARDIRQS_NO__DO_IRQ + select GPIO_TXX9 + +config SOC_TX4938 + bool + select CEVT_R4K + select CSRC_R4K + select CEVT_TXX9 + select DMA_NONCOHERENT + select HAS_TXX9_SERIAL + select HW_HAS_PCI + select IRQ_CPU + select IRQ_TXX9 + select PCI_TX4927 + select SWAP_IO_SPACE + select SYS_HAS_CPU_TX49XX + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_KGDB + select GENERIC_HARDIRQS_NO__DO_IRQ + select GPIO_TXX9 + config TOSHIBA_FPCIB0 bool "FPCIB0 Backplane Support" - depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + depends on PCI && (MACH_TX39XX || MACH_TX49XX) select I8259 config PICMG_PCI_BACKPLANE_DEFAULT bool "Support for PICMG PCI Backplane" - depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX) + depends on PCI && (MACH_TX39XX || MACH_TX49XX) default y if !TOSHIBA_FPCIB0 if TOSHIBA_RBTX4938 diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile index b80b6e072284..668fdaad6448 100644 --- a/arch/mips/txx9/generic/Makefile +++ b/arch/mips/txx9/generic/Makefile @@ -4,8 +4,8 @@ obj-y += setup.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o -obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o +obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o +obj-$(CONFIG_SOC_TX4938) += mem_tx4938.o irq_tx4938.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o obj-$(CONFIG_KGDB) += dbgio.o diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c index 685ecc2ed551..6377bd8a9050 100644 --- a/arch/mips/txx9/generic/irq_tx4927.c +++ b/arch/mips/txx9/generic/irq_tx4927.c @@ -26,39 +26,12 @@ #include #include #include -#include -#ifdef CONFIG_TOSHIBA_RBTX4927 -#include -#endif +#include void __init tx4927_irq_init(void) { mips_cpu_irq_init(); txx9_irq_init(TX4927_IRC_REG); - set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) /* cpu timer */ - do_IRQ(TX4927_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { /* tx4927 pic */ - int irq = txx9_irq(); -#ifdef CONFIG_TOSHIBA_RBTX4927 - if (irq == TX4927_IRQ_NEST_EXT_ON_PIC) - irq = toshiba_rbtx4927_irq_nested(irq); -#endif - if (unlikely(irq < 0)) { - spurious_interrupt(); - return; - } - do_IRQ(irq); - } else if (pending & STATUSF_IP0) /* user line 0 */ - do_IRQ(TX4927_IRQ_USER0); - else if (pending & STATUSF_IP1) /* user line 1 */ - do_IRQ(TX4927_IRQ_USER1); - else - spurious_interrupt(); + set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, + handle_simple_irq); } diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c index 0886d9138818..5fc86c9c9d2f 100644 --- a/arch/mips/txx9/generic/irq_tx4938.c +++ b/arch/mips/txx9/generic/irq_tx4938.c @@ -14,35 +14,12 @@ #include #include #include -#include -#include +#include -void __init -tx4938_irq_init(void) +void __init tx4938_irq_init(void) { mips_cpu_irq_init(); txx9_irq_init(TX4938_IRC_REG); - set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq); -} - -int toshiba_rbtx4938_irq_nested(int irq); - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status(); - - if (pending & STATUSF_IP7) - do_IRQ(TX4938_IRQ_CPU_TIMER); - else if (pending & STATUSF_IP2) { - int irq = txx9_irq(); - if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0)) - irq = toshiba_rbtx4938_irq_nested(irq); - if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); - } else if (pending & STATUSF_IP1) - do_IRQ(TX4938_IRQ_USER1); - else if (pending & STATUSF_IP0) - do_IRQ(TX4938_IRQ_USER0); + set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, + handle_simple_irq); } diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c index 8173faab99bb..0b92d8c13208 100644 --- a/arch/mips/txx9/generic/pci.c +++ b/arch/mips/txx9/generic/pci.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #ifdef CONFIG_TOSHIBA_FPCIB0 #include @@ -375,3 +376,13 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, #endif DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup); DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup); + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return txx9_board_vec->pci_map_irq(dev, slot, pin); +} diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 46a631177757..66ff74f80c6b 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -14,7 +14,16 @@ #include #include #include +#include +#include +#include +#include +#include +#include #include +#ifdef CONFIG_CPU_TX49XX +#include +#endif /* EBUSC settings of TX4927, etc. */ struct resource txx9_ce_res[8]; @@ -49,3 +58,163 @@ txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size) unsigned int txx9_master_clock; unsigned int txx9_cpu_clock; unsigned int txx9_gbus_clock; + + +/* Minimum CLK support */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "spi-baseclk")) + return (struct clk *)(txx9_gbus_clock / 2 / 4); + if (!strcmp(id, "imbus_clk")) + return (struct clk *)(txx9_gbus_clock / 2); + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return (unsigned long)clk; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +extern struct txx9_board_vec jmr3927_vec; +extern struct txx9_board_vec rbtx4927_vec; +extern struct txx9_board_vec rbtx4937_vec; +extern struct txx9_board_vec rbtx4938_vec; + +/* board definitions */ +static struct txx9_board_vec *board_vecs[] __initdata = { +#ifdef CONFIG_TOSHIBA_JMR3927 + &jmr3927_vec, +#endif +#ifdef CONFIG_TOSHIBA_RBTX4927 + &rbtx4927_vec, + &rbtx4937_vec, +#endif +#ifdef CONFIG_TOSHIBA_RBTX4938 + &rbtx4938_vec, +#endif +}; +struct txx9_board_vec *txx9_board_vec __initdata; +static char txx9_system_type[32]; + +void __init prom_init_cmdline(void) +{ + int argc = (int)fw_arg0; + char **argv = (char **)fw_arg1; + int i; /* Always ignore the "-c" at argv[0] */ + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) + *arcs_cmdline = '\0'; + + for (i = 1; i < argc; i++) { + if (i != 1) + strcat(arcs_cmdline, " "); + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(void) +{ + int i; + +#ifdef CONFIG_CPU_TX39XX + mips_machtype = MACH_TOSHIBA_JMR3927; +#endif +#ifdef CONFIG_CPU_TX49XX + switch (TX4938_REV_PCODE()) { + case 0x4927: + mips_machtype = MACH_TOSHIBA_RBTX4927; + break; + case 0x4937: + mips_machtype = MACH_TOSHIBA_RBTX4937; + break; + case 0x4938: + mips_machtype = MACH_TOSHIBA_RBTX4938; + break; + } +#endif + for (i = 0; i < ARRAY_SIZE(board_vecs); i++) { + if (board_vecs[i]->type == mips_machtype) { + txx9_board_vec = board_vecs[i]; + strcpy(txx9_system_type, txx9_board_vec->system); + return txx9_board_vec->prom_init(); + } + } +} + +void __init prom_free_prom_memory(void) +{ +} + +const char *get_system_type(void) +{ + return txx9_system_type; +} + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +/* wrappers */ +void __init plat_mem_setup(void) +{ + txx9_board_vec->mem_setup(); +} + +void __init arch_init_irq(void) +{ + txx9_board_vec->irq_setup(); +} + +void __init plat_time_init(void) +{ + txx9_board_vec->time_init(); +} + +static int __init _txx9_arch_init(void) +{ + if (txx9_board_vec->arch_init) + txx9_board_vec->arch_init(); + return 0; +} +arch_initcall(_txx9_arch_init); + +static int __init _txx9_device_init(void) +{ + if (txx9_board_vec->device_init) + txx9_board_vec->device_init(); + return 0; +} +device_initcall(_txx9_device_init); + +int (*txx9_irq_dispatch)(int pending); +asmlinkage void plat_irq_dispatch(void) +{ + int pending = read_c0_status() & read_c0_cause() & ST0_IM; + int irq = txx9_irq_dispatch(pending); + + if (likely(irq >= 0)) + do_IRQ(irq); + else + spurious_interrupt(); +} diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile index 5f83ea375225..ba292c945669 100644 --- a/arch/mips/txx9/jmr3927/Makefile +++ b/arch/mips/txx9/jmr3927/Makefile @@ -2,7 +2,7 @@ # Makefile for TOSHIBA JMR-TX3927 board # -obj-y += prom.o init.o irq.o setup.o +obj-y += prom.o irq.o setup.o obj-$(CONFIG_KGDB) += kgdb_io.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/txx9/jmr3927/init.c b/arch/mips/txx9/jmr3927/init.c deleted file mode 100644 index 1bbb5343baf4..000000000000 --- a/arch/mips/txx9/jmr3927/init.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * arch/mips/jmr3927/common/init.c - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include - -extern void __init prom_init_cmdline(void); - -const char *get_system_type(void) -{ - return "Toshiba" -#ifdef CONFIG_TOSHIBA_JMR3927 - " JMR_TX3927" -#endif - ; -} - -extern void puts(const char *cp); - -void __init prom_init(void) -{ -#ifdef CONFIG_TOSHIBA_JMR3927 - /* CCFG */ - if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) - puts("Warning: TX3927 TLB off\n"); -#endif - - prom_init_cmdline(); - add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); -} diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index b97d22e15da6..070c9a115e57 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c @@ -39,6 +39,7 @@ #include #include +#include #include #if JMR3927_IRQ_END > NR_IRQS @@ -77,37 +78,30 @@ static void unmask_irq_ioc(unsigned int irq) (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); } -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long cp0_cause = read_c0_cause(); - int irq; - - if ((cp0_cause & CAUSEF_IP7) == 0) - return; - irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; - - do_IRQ(irq + JMR3927_IRQ_IRC); -} - -static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) +static int jmr3927_ioc_irqroute(void) { unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); int i; for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { - if (istat & (1 << i)) { - irq = JMR3927_IRQ_IOC + i; - do_IRQ(irq); - } + if (istat & (1 << i)) + return JMR3927_IRQ_IOC + i; } - return IRQ_HANDLED; + return -1; } -static struct irqaction ioc_action = { - .handler = jmr3927_ioc_interrupt, - .mask = CPU_MASK_NONE, - .name = "IOC", -}; +static int jmr3927_irq_dispatch(int pending) +{ + int irq; + + if ((pending & CAUSEF_IP7) == 0) + return -1; + irq = (pending >> CAUSEB_IP2) & 0x0f; + irq += JMR3927_IRQ_IRC; + if (irq == JMR3927_IRQ_IOCINT) + irq = jmr3927_ioc_irqroute(); + return irq; +} #ifdef CONFIG_PCI static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) @@ -127,8 +121,9 @@ static struct irqaction pcierr_action = { static void __init jmr3927_irq_init(void); -void __init arch_init_irq(void) +void __init jmr3927_irq_setup(void) { + txx9_irq_dispatch = jmr3927_irq_dispatch; /* Now, interrupt control disabled, */ /* all IRC interrupts are masked, */ /* all IRC interrupt mode are Low Active. */ @@ -146,7 +141,7 @@ void __init arch_init_irq(void) jmr3927_irq_init(); /* setup IOC interrupt 1 (PCI, MODEM) */ - setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); + set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); #ifdef CONFIG_PCI setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c index 8bc1049b622e..2cadb423face 100644 --- a/arch/mips/txx9/jmr3927/prom.c +++ b/arch/mips/txx9/jmr3927/prom.c @@ -35,42 +35,10 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include #include -#include - #include -#include - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - int prom_argc = fw_arg0; - char **prom_argv = (char **) fw_arg1; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; -} - -void __init prom_free_prom_memory(void) -{ -} +#include +#include #define TIMEOUT 0xffffff @@ -96,3 +64,13 @@ puts(const char *cp) prom_putchar('\r'); prom_putchar('\n'); } + +void __init jmr3927_prom_init(void) +{ + /* CCFG */ + if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) + puts("Warning: TX3927 TLB off\n"); + + prom_init_cmdline(); + add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); +} diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index baa8c8db9a94..128a4ae3e72e 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -34,15 +34,16 @@ #include #include #include -#include #include #ifdef CONFIG_SERIAL_TXX9 #include #endif +#include #include #include #include +#include #include #include #include @@ -83,7 +84,7 @@ static void jmr3927_machine_power_off(void) while (1); } -void __init plat_time_init(void) +static void __init jmr3927_time_init(void) { txx9_clockevent_init(TX3927_TMR_REG(0), TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0), @@ -97,7 +98,7 @@ void __init plat_time_init(void) extern char * __init prom_getcmdline(void); static void jmr3927_board_init(void); -void __init plat_mem_setup(void) +static void __init jmr3927_mem_setup(void) { char *argptr; @@ -233,6 +234,8 @@ static void __init tx3927_setup(void) { int i; + txx9_cpu_clock = JMR3927_CORECLK; + txx9_gbus_clock = JMR3927_GBUSCLK; /* SDRAMC are configured by PROM */ /* ROMC */ @@ -336,7 +339,6 @@ static int __init jmr3927_rtc_init(void) dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1); return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -device_initcall(jmr3927_rtc_init); /* Watchdog support */ @@ -356,36 +358,22 @@ static int __init jmr3927_wdt_init(void) { return txx9_wdt_init(TX3927_TMR_REG(2)); } -device_initcall(jmr3927_wdt_init); -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)JMR3927_IMCLK; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) +static void __init jmr3927_device_init(void) { + jmr3927_rtc_init(); + jmr3927_wdt_init(); } -EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); +struct txx9_board_vec jmr3927_vec __initdata = { + .type = MACH_TOSHIBA_JMR3927, + .system = "Toshiba JMR_TX3927", + .prom_init = jmr3927_prom_init, + .mem_setup = jmr3927_mem_setup, + .irq_setup = jmr3927_irq_setup, + .time_init = jmr3927_time_init, + .device_init = jmr3927_device_init, +#ifdef CONFIG_PCI + .pci_map_irq = jmr3927_pci_map_irq, +#endif +}; diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c index bef1447aeed2..70f13211bc2a 100644 --- a/arch/mips/txx9/rbtx4927/irq.c +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -111,17 +111,10 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB #include #include #include +#include +#include #include -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ - -#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC -#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) - static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); @@ -136,34 +129,25 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { #define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL #define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL -int toshiba_rbtx4927_irq_nested(int sw_irq) +static int toshiba_rbtx4927_irq_nested(int sw_irq) { u8 level3; level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; if (level3) - sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; + sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; return (sw_irq); } -static struct irqaction toshiba_rbtx4927_irq_ioc_action = { - .handler = no_action, - .flags = IRQF_SHARED, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4927_IOC_NAME -}; - static void __init toshiba_rbtx4927_irq_ioc_init(void) { int i; - for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) + for (i = RBTX4927_IRQ_IOC; + i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, handle_level_irq); - - setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, - &toshiba_rbtx4927_irq_ioc_action); + set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); } static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) @@ -171,7 +155,7 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) unsigned char v; v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + v |= (1 << (irq - RBTX4927_IRQ_IOC)); writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); } @@ -180,15 +164,34 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) unsigned char v; v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); - v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + v &= ~(1 << (irq - RBTX4927_IRQ_IOC)); writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); mmiowb(); } -void __init arch_init_irq(void) + +static int rbtx4927_irq_dispatch(int pending) { - extern void tx4927_irq_init(void); + int irq; + + if (pending & STATUSF_IP7) /* cpu timer */ + irq = MIPS_CPU_IRQ_BASE + 7; + else if (pending & STATUSF_IP2) { /* tx4927 pic */ + irq = txx9_irq(); + if (irq == RBTX4927_IRQ_IOCINT) + irq = toshiba_rbtx4927_irq_nested(irq); + } else if (pending & STATUSF_IP0) /* user line 0 */ + irq = MIPS_CPU_IRQ_BASE + 0; + else if (pending & STATUSF_IP1) /* user line 1 */ + irq = MIPS_CPU_IRQ_BASE + 1; + else + irq = -1; + return irq; +} +void __init rbtx4927_irq_setup(void) +{ + txx9_irq_dispatch = rbtx4927_irq_dispatch; tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); /* Onboard 10M Ether: High Active */ diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c index 0020bbee838b..942e627d2dc1 100644 --- a/arch/mips/txx9/rbtx4927/prom.c +++ b/arch/mips/txx9/rbtx4927/prom.c @@ -30,62 +30,16 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include -#include #include -#include -#include -#include +#include +#include -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; /* Always ignore the "-c" at argv[0] */ - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} - -void __init prom_init(void) +void __init rbtx4927_prom_init(void) { extern int tx4927_get_mem_size(void); - extern char* toshiba_name; int msize; prom_init_cmdline(); - - if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { - mips_machtype = MACH_TOSHIBA_RBTX4927; - toshiba_name = "TX4927"; - } else { - mips_machtype = MACH_TOSHIBA_RBTX4937; - toshiba_name = "TX4937"; - } - msize = tx4927_get_mem_size(); add_memory_region(0, msize << 20, BOOT_MEM_RAM); } - -void __init prom_free_prom_memory(void) -{ -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4927/RBTX4937"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index 86b870abc319..c3566c39c26c 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -49,7 +49,6 @@ #include #include #include -#include #include #include @@ -76,8 +75,6 @@ char *prom_getcmdline(void); static int tx4927_ccfg_toeon = 1; -char *toshiba_name = ""; - #ifdef CONFIG_PCI static void __init tx4927_pci_setup(void) { @@ -171,15 +168,15 @@ static void __init tx4937_pci_setup(void) } } -static int __init rbtx4927_arch_init(void) +static void __init rbtx4927_arch_init(void) { if (mips_machtype == MACH_TOSHIBA_RBTX4937) tx4937_pci_setup(); else tx4927_pci_setup(); - return 0; } -arch_initcall(rbtx4927_arch_init); +#else +#define rbtx4927_arch_init NULL #endif /* CONFIG_PCI */ static void __noreturn wait_forever(void) @@ -223,14 +220,12 @@ void toshiba_rbtx4927_power_off(void) /* no return */ } -void __init plat_mem_setup(void) +static void __init rbtx4927_mem_setup(void) { int i; u32 cp0_config; char *argptr; - printk("CPU is %s\n", toshiba_name); - /* f/w leaves this on at startup */ clear_c0_status(ST0_ERL); @@ -323,7 +318,7 @@ void __init plat_mem_setup(void) req.iotype = UPIO_MEM; req.membase = (char *)(0xff1ff300 + i * 0x100); req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = TX4927_IRQ_PIC_BEG + 8 + i; + req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i); req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; req.uartclk = 50000000; early_serial_txx9_setup(&req); @@ -352,7 +347,7 @@ void __init plat_mem_setup(void) #endif } -void __init plat_time_init(void) +static void __init rbtx4927_time_init(void) { mips_hpt_frequency = txx9_cpu_clock / 2; if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) @@ -372,7 +367,6 @@ static int __init toshiba_rbtx4927_rtc_init(void) platform_device_register_simple("rtc-ds1742", -1, &res, 1); return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -device_initcall(toshiba_rbtx4927_rtc_init); static int __init rbtx4927_ne_init(void) { @@ -391,7 +385,6 @@ static int __init rbtx4927_ne_init(void) res, ARRAY_SIZE(res)); return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -device_initcall(rbtx4927_ne_init); /* Watchdog support */ @@ -411,36 +404,37 @@ static int __init rbtx4927_wdt_init(void) { return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); } -device_initcall(rbtx4927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)50000000; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); -void clk_disable(struct clk *clk) +static void __init rbtx4927_device_init(void) { + toshiba_rbtx4927_rtc_init(); + rbtx4927_ne_init(); + rbtx4927_wdt_init(); } -EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); +struct txx9_board_vec rbtx4927_vec __initdata = { + .type = MACH_TOSHIBA_RBTX4927, + .system = "Toshiba RBTX4927", + .prom_init = rbtx4927_prom_init, + .mem_setup = rbtx4927_mem_setup, + .irq_setup = rbtx4927_irq_setup, + .time_init = rbtx4927_time_init, + .device_init = rbtx4927_device_init, + .arch_init = rbtx4927_arch_init, +#ifdef CONFIG_PCI + .pci_map_irq = rbtx4927_pci_map_irq, +#endif +}; +struct txx9_board_vec rbtx4937_vec __initdata = { + .type = MACH_TOSHIBA_RBTX4937, + .system = "Toshiba RBTX4937", + .prom_init = rbtx4927_prom_init, + .mem_setup = rbtx4927_mem_setup, + .irq_setup = rbtx4927_irq_setup, + .time_init = rbtx4927_time_init, + .device_init = rbtx4927_device_init, + .arch_init = rbtx4927_arch_init, +#ifdef CONFIG_PCI + .pci_map_irq = rbtx4927_pci_map_irq, +#endif +}; diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c index f4984820251a..3971a061657a 100644 --- a/arch/mips/txx9/rbtx4938/irq.c +++ b/arch/mips/txx9/rbtx4938/irq.c @@ -66,6 +66,8 @@ IRQ Device */ #include #include +#include +#include #include static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); @@ -80,26 +82,17 @@ static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { .unmask = toshiba_rbtx4938_irq_ioc_enable, }; -int -toshiba_rbtx4938_irq_nested(int sw_irq) +static int toshiba_rbtx4938_irq_nested(int sw_irq) { u8 level3; level3 = readb(rbtx4938_imstat_addr); if (level3) /* must use fls so onboard ATA has priority */ - sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; - + sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1; return sw_irq; } -static struct irqaction toshiba_rbtx4938_irq_ioc_action = { - .handler = no_action, - .flags = 0, - .mask = CPU_MASK_NONE, - .name = TOSHIBA_RBTX4938_IOC_NAME, -}; - /**********************************************************************************/ /* Functions for ioc */ /**********************************************************************************/ @@ -108,13 +101,12 @@ toshiba_rbtx4938_irq_ioc_init(void) { int i; - for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; - i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) + for (i = RBTX4938_IRQ_IOC; + i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++) set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, handle_level_irq); - setup_irq(RBTX4938_IRQ_IOCINT, - &toshiba_rbtx4938_irq_ioc_action); + set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); } static void @@ -123,7 +115,7 @@ toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) unsigned char v; v = readb(rbtx4938_imask_addr); - v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + v |= (1 << (irq - RBTX4938_IRQ_IOC)); writeb(v, rbtx4938_imask_addr); mmiowb(); } @@ -134,15 +126,33 @@ toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) unsigned char v; v = readb(rbtx4938_imask_addr); - v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); + v &= ~(1 << (irq - RBTX4938_IRQ_IOC)); writeb(v, rbtx4938_imask_addr); mmiowb(); } -void __init arch_init_irq(void) +static int rbtx4938_irq_dispatch(int pending) { - extern void tx4938_irq_init(void); + int irq; + + if (pending & STATUSF_IP7) + irq = MIPS_CPU_IRQ_BASE + 7; + else if (pending & STATUSF_IP2) { + irq = txx9_irq(); + if (irq == RBTX4938_IRQ_IOCINT) + irq = toshiba_rbtx4938_irq_nested(irq); + } else if (pending & STATUSF_IP1) + irq = MIPS_CPU_IRQ_BASE + 0; + else if (pending & STATUSF_IP0) + irq = MIPS_CPU_IRQ_BASE + 1; + else + irq = -1; + return irq; +} +void __init rbtx4938_irq_setup(void) +{ + txx9_irq_dispatch = rbtx4938_irq_dispatch; /* Now, interrupt control disabled, */ /* all IRC interrupts are masked, */ /* all IRC interrupt mode are Low Active. */ diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c index 134fcc2dc7d2..fbb37458ddb2 100644 --- a/arch/mips/txx9/rbtx4938/prom.c +++ b/arch/mips/txx9/rbtx4938/prom.c @@ -11,34 +11,12 @@ */ #include -#include -#include #include - -#include #include -#include - -void __init prom_init_cmdline(void) -{ - int argc = (int) fw_arg0; - char **argv = (char **) fw_arg1; - int i; - - /* ignore all built-in args if any f/w args given */ - if (argc > 1) { - *arcs_cmdline = '\0'; - } - - for (i = 1; i < argc; i++) { - if (i != 1) { - strcat(arcs_cmdline, " "); - } - strcat(arcs_cmdline, argv[i]); - } -} +#include +#include -void __init prom_init(void) +void __init rbtx4938_prom_init(void) { extern int tx4938_get_mem_size(void); int msize; @@ -48,25 +26,4 @@ void __init prom_init(void) msize = tx4938_get_mem_size(); add_memory_region(0, msize << 20, BOOT_MEM_RAM); - - return; -} - -void __init prom_free_prom_memory(void) -{ -} - -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ - return; -} - -const char *get_system_type(void) -{ - return "Toshiba RBTX4938"; -} - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); } diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index 144d2cada820..8306ba333dda 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -147,9 +146,9 @@ static void __init rbtx4938_pci_setup(void) #define SEEPROM3_CS 1 /* IOC */ #define SRTC_CS 2 /* IOC */ -#ifdef CONFIG_PCI static int __init rbtx4938_ethaddr_init(void) { +#ifdef CONFIG_PCI unsigned char dat[17]; unsigned char sum; int i; @@ -179,10 +178,9 @@ static int __init rbtx4938_ethaddr_init(void) platform_device_add(pdev)) platform_device_put(pdev); } +#endif /* CONFIG_PCI */ return 0; } -device_initcall(rbtx4938_ethaddr_init); -#endif /* CONFIG_PCI */ static void __init rbtx4938_spi_setup(void) { @@ -366,7 +364,7 @@ void __init tx4938_board_setup(void) #endif } -void __init plat_time_init(void) +static void __init rbtx4938_time_init(void) { mips_hpt_frequency = txx9_cpu_clock / 2; if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) @@ -375,7 +373,7 @@ void __init plat_time_init(void) txx9_gbus_clock / 2); } -void __init plat_mem_setup(void) +static void __init rbtx4938_mem_setup(void) { unsigned long long pcfg; char *argptr; @@ -496,7 +494,6 @@ static int __init rbtx4938_ne_init(void) res, ARRAY_SIZE(res)); return IS_ERR(dev) ? PTR_ERR(dev) : 0; } -device_initcall(rbtx4938_ne_init); /* GPIO support */ @@ -587,14 +584,13 @@ static int __init rbtx4938_spi_init(void) return 0; } -static int __init rbtx4938_arch_init(void) +static void __init rbtx4938_arch_init(void) { txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); gpiochip_add(&rbtx4938_spi_gpio_chip); rbtx4938_pci_setup(); - return rbtx4938_spi_init(); + rbtx4938_spi_init(); } -arch_initcall(rbtx4938_arch_init); /* Watchdog support */ @@ -614,38 +610,24 @@ static int __init rbtx4938_wdt_init(void) { return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); } -device_initcall(rbtx4938_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "spi-baseclk")) - return (struct clk *)(txx9_gbus_clock / 2 / 4); - if (!strcmp(id, "imbus_clk")) - return (struct clk *)(txx9_gbus_clock / 2); - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) +static void __init rbtx4938_device_init(void) { - return (unsigned long)clk; + rbtx4938_ethaddr_init(); + rbtx4938_ne_init(); + rbtx4938_wdt_init(); } -EXPORT_SYMBOL(clk_get_rate); -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); +struct txx9_board_vec rbtx4938_vec __initdata = { + .type = MACH_TOSHIBA_RBTX4938, + .system = "Toshiba RBTX4938", + .prom_init = rbtx4938_prom_init, + .mem_setup = rbtx4938_mem_setup, + .irq_setup = rbtx4938_irq_setup, + .time_init = rbtx4938_time_init, + .device_init = rbtx4938_device_init, + .arch_init = rbtx4938_arch_init, +#ifdef CONFIG_PCI + .pci_map_irq = rbtx4938_pci_map_irq, +#endif +}; diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h index 2ff6c2002204..6cd147764f19 100644 --- a/include/asm-mips/txx9/generic.h +++ b/include/asm-mips/txx9/generic.h @@ -20,4 +20,22 @@ extern unsigned int txx9_master_clock; extern unsigned int txx9_cpu_clock; extern unsigned int txx9_gbus_clock; +struct pci_dev; +struct txx9_board_vec { + unsigned long type; + const char *system; + void (*prom_init)(void); + void (*mem_setup)(void); + void (*irq_setup)(void); + void (*time_init)(void); + void (*arch_init)(void); + void (*device_init)(void); +#ifdef CONFIG_PCI + int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); +#endif +}; +extern struct txx9_board_vec *txx9_board_vec; +extern int (*txx9_irq_dispatch)(int pending); +void prom_init_cmdline(void); + #endif /* __ASM_TXX9_GENERIC_H */ diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h index 29e54981a86e..d6eb1b6a54eb 100644 --- a/include/asm-mips/txx9/jmr3927.h +++ b/include/asm-mips/txx9/jmr3927.h @@ -174,4 +174,9 @@ * INT[3:0] */ +void jmr3927_prom_init(void); +void jmr3927_irq_setup(void); +struct pci_dev; +int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); + #endif /* __ASM_TXX9_JMR3927_H */ diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h index 5b6f488b1b3c..bf194589216f 100644 --- a/include/asm-mips/txx9/rbtx4927.h +++ b/include/asm-mips/txx9/rbtx4927.h @@ -46,12 +46,16 @@ #define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB) #define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA) -#define RBTX4927_IRQ_IOC (TX4927_IRQ_PIC_BEG + TX4927_NUM_IR) +#define RBTX4927_NR_IRQ_IOC 8 /* IOC */ + +#define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR) #define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID) #define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC) #define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB) #define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA) +#define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1)) + #ifdef CONFIG_PCI #define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO #else @@ -65,8 +69,11 @@ #define RBTX4927_SW_RESET_ENABLE_SET 0x01 #define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET) -#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) +#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) -int toshiba_rbtx4927_irq_nested(int sw_irq); +void rbtx4927_prom_init(void); +void rbtx4927_irq_setup(void); +struct pci_dev; +int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); #endif /* __ASM_TXX9_RBTX4927_H */ diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h index 8450f735d056..2f5d5e705a41 100644 --- a/include/asm-mips/txx9/rbtx4938.h +++ b/include/asm-mips/txx9/rbtx4938.h @@ -101,35 +101,12 @@ * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new * IRQ hardware is supported. */ -#define RBTX4938_NR_IRQ_LOCAL 8 -#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ #define RBTX4938_NR_IRQ_IOC 8 -#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) -#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) -#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) -#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) -#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1) -#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7) - -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0 -#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7 - -#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */ -#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */ -#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG -#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL) -#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC) +#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE +#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR) #define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) -#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0) -#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1) -#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT) -#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT) #define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) @@ -157,11 +134,16 @@ /* IOC (PCI, etc) */ -#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) +#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0)) /* Onboard 10M Ether */ -#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) +#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1)) #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) #define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) +void rbtx4938_prom_init(void); +void rbtx4938_irq_setup(void); +struct pci_dev; +int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); + #endif /* __ASM_TXX9_RBTX4938_H */ diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h index c0382fd2ae7f..46d60afc038b 100644 --- a/include/asm-mips/txx9/tx4927.h +++ b/include/asm-mips/txx9/tx4927.h @@ -32,20 +32,6 @@ #include #include -#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE -#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) - -#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE -#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) - - -#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) -#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) -#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) -#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) - -#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) - #define TX4927_SDRAMC_REG 0xff1f8000 #define TX4927_EBUSC_REG 0xff1f9000 #define TX4927_PCIC_REG 0xff1fd000 @@ -54,10 +40,14 @@ #define TX4927_NR_TMR 3 #define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) +#define TX4927_IR_INT(n) (2 + (n)) +#define TX4927_IR_SIO(n) (8 + (n)) #define TX4927_IR_PCIC 16 #define TX4927_IR_PCIERR 22 #define TX4927_NUM_IR 32 +#define TX4927_IRC_INT 2 /* IP[2] in Status register */ + struct tx4927_sdramc_reg { volatile unsigned long long cr[4]; volatile unsigned long long unused0[4]; @@ -224,5 +214,6 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new) int tx4927_report_pciclk(void); int tx4927_pciclk66_setup(void); +void tx4927_irq_init(void); #endif /* __ASM_TXX9_TX4927_H */ diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h index 0bb891993b08..12de68a4c10a 100644 --- a/include/asm-mips/txx9/tx4938.h +++ b/include/asm-mips/txx9/tx4938.h @@ -18,11 +18,6 @@ #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) #define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) -#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG - -#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC) -#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR) - #define TX4938_PCIIO_0 0x10000000 #define TX4938_PCIIO_1 0x01010000 #define TX4938_PCIMEM_0 0x08000000 @@ -271,6 +266,8 @@ struct tx4938_ccfg_reg { #define TX4938_IR_ETH0 TX4938_IR_INT(4) #define TX4938_IR_ETH1 TX4938_IR_INT(3) +#define TX4938_IRC_INT 2 /* IP[2] in Status register */ + /* * CCFG */ @@ -463,5 +460,6 @@ void tx4938_report_pci1clk(void); int tx4938_pciclk66_setup(void); struct pci_dev; int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); +void tx4938_irq_init(void); #endif -- cgit v1.2.3 From efff4ae259b8f750ea426d3084007f85c0a15a85 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Fri, 11 Jul 2008 22:45:21 +0900 Subject: [MIPS] cmbvr4133: Remove support It cannot be built for a long time and nobody maintains it. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 6 - arch/mips/pci/Makefile | 1 - arch/mips/pci/fixup-vr4133.c | 194 ---------------------- arch/mips/vr41xx/Kconfig | 17 -- arch/mips/vr41xx/nec-cmbvr4133/Makefile | 8 - arch/mips/vr41xx/nec-cmbvr4133/init.c | 65 -------- arch/mips/vr41xx/nec-cmbvr4133/irq.c | 46 ------ arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c | 249 ----------------------------- arch/mips/vr41xx/nec-cmbvr4133/setup.c | 89 ----------- include/asm-mips/mach-vr41xx/irq.h | 3 - include/asm-mips/vr41xx/cmbvr4133.h | 56 ------- 11 files changed, 734 deletions(-) delete mode 100644 arch/mips/pci/fixup-vr4133.c delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/Makefile delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/init.c delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/irq.c delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c delete mode 100644 arch/mips/vr41xx/nec-cmbvr4133/setup.c delete mode 100644 include/asm-mips/vr41xx/cmbvr4133.h (limited to 'include/asm-mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index d319cd624135..c4a3098a58c6 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -354,12 +354,6 @@ load-$(CONFIG_LASAT) += 0xffffffff80000000 core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ cflags-$(CONFIG_MACH_VR41XX) += -Iinclude/asm-mips/mach-vr41xx -# -# NEC VR4133 -# -core-$(CONFIG_NEC_CMBVR4133) += arch/mips/vr41xx/nec-cmbvr4133/ -load-$(CONFIG_NEC_CMBVR4133) += 0xffffffff80100000 - # # ZAO Networks Capcella (VR4131) # diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 875b643438c0..57e34cafa497 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_MIPS_MSC) += ops-msc.o obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o -obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c deleted file mode 100644 index 34e651bd2b5e..000000000000 --- a/arch/mips/pci/fixup-vr4133.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * arch/mips/pci/fixup-vr4133.c - * - * The NEC CMB-VR4133 Board specific PCI fixups. - * - * Author: Yoichi Yuasa and - * Alex Sapkov - * - * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Modified for support in 2.6 - * Author: Manish Lachwani (mlachwani@mvista.com) - * - */ -#include -#include -#include - -#include -#include -#include - -extern int vr4133_rockhopper; -extern void ali_m1535plus_init(struct pci_dev *dev); -extern void ali_m5229_init(struct pci_dev *dev); - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - /* - * We have to reset AMD PCnet adapter on Rockhopper since - * PMON leaves it enabled and generating interrupts. This leads - * to a lock if some PCI device driver later enables the IRQ line - * shared with PCnet and there is no AMD PCnet driver to catch its - * interrupts. - */ -#ifdef CONFIG_ROCKHOPPER - if (dev->vendor == PCI_VENDOR_ID_AMD && - dev->device == PCI_DEVICE_ID_AMD_LANCE) { - inl(pci_resource_start(dev, 0) + 0x18); - } -#endif - - /* - * we have to open the bridges' windows down to 0 because otherwise - * we cannot access ISA south bridge I/O registers that get mapped from - * 0. for example, 8259 PIC would be unaccessible without that - */ - if(dev->vendor == PCI_VENDOR_ID_INTEL && dev->device == PCI_DEVICE_ID_INTEL_S21152BB) { - pci_write_config_byte(dev, PCI_IO_BASE, 0); - if(dev->bus->number == 0) { - pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); - } else { - pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 1); - } - } - - return 0; -} - -/* - * M1535 IRQ mapping - * Feel free to change this, although it shouldn't be needed - */ -#define M1535_IRQ_INTA 7 -#define M1535_IRQ_INTB 9 -#define M1535_IRQ_INTC 10 -#define M1535_IRQ_INTD 11 - -#define M1535_IRQ_USB 9 -#define M1535_IRQ_IDE 14 -#define M1535_IRQ_IDE2 15 -#define M1535_IRQ_PS2 12 -#define M1535_IRQ_RTC 8 -#define M1535_IRQ_FDC 6 -#define M1535_IRQ_AUDIO 5 -#define M1535_IRQ_COM1 4 -#define M1535_IRQ_COM2 4 -#define M1535_IRQ_IRDA 3 -#define M1535_IRQ_KBD 1 -#define M1535_IRQ_TMR 0 - -/* Rockhopper "slots" assignment; this is hard-coded ... */ -#define ROCKHOPPER_M5451_SLOT 1 -#define ROCKHOPPER_M1535_SLOT 2 -#define ROCKHOPPER_M5229_SLOT 11 -#define ROCKHOPPER_M5237_SLOT 15 -#define ROCKHOPPER_PMU_SLOT 12 -/* ... and hard-wired. */ -#define ROCKHOPPER_PCI1_SLOT 3 -#define ROCKHOPPER_PCI2_SLOT 4 -#define ROCKHOPPER_PCI3_SLOT 5 -#define ROCKHOPPER_PCI4_SLOT 6 -#define ROCKHOPPER_PCNET_SLOT 1 - -#define M1535_IRQ_MASK(n) (1 << (n)) - -#define M1535_IRQ_EDGE (M1535_IRQ_MASK(M1535_IRQ_TMR) | \ - M1535_IRQ_MASK(M1535_IRQ_KBD) | \ - M1535_IRQ_MASK(M1535_IRQ_COM1) | \ - M1535_IRQ_MASK(M1535_IRQ_COM2) | \ - M1535_IRQ_MASK(M1535_IRQ_IRDA) | \ - M1535_IRQ_MASK(M1535_IRQ_RTC) | \ - M1535_IRQ_MASK(M1535_IRQ_FDC) | \ - M1535_IRQ_MASK(M1535_IRQ_PS2)) - -#define M1535_IRQ_LEVEL (M1535_IRQ_MASK(M1535_IRQ_IDE) | \ - M1535_IRQ_MASK(M1535_IRQ_USB) | \ - M1535_IRQ_MASK(M1535_IRQ_INTA) | \ - M1535_IRQ_MASK(M1535_IRQ_INTB) | \ - M1535_IRQ_MASK(M1535_IRQ_INTC) | \ - M1535_IRQ_MASK(M1535_IRQ_INTD)) - -struct irq_map_entry { - u16 bus; - u8 slot; - u8 irq; -}; -static struct irq_map_entry int_map[] = { - {1, ROCKHOPPER_M5451_SLOT, M1535_IRQ_AUDIO}, /* Audio controller */ - {1, ROCKHOPPER_PCI1_SLOT, M1535_IRQ_INTD}, /* PCI slot #1 */ - {1, ROCKHOPPER_PCI2_SLOT, M1535_IRQ_INTC}, /* PCI slot #2 */ - {1, ROCKHOPPER_M5237_SLOT, M1535_IRQ_USB}, /* USB host controller */ - {1, ROCKHOPPER_M5229_SLOT, IDE_PRIMARY_IRQ}, /* IDE controller */ - {2, ROCKHOPPER_PCNET_SLOT, M1535_IRQ_INTD}, /* AMD Am79c973 on-board - ethernet */ - {2, ROCKHOPPER_PCI3_SLOT, M1535_IRQ_INTB}, /* PCI slot #3 */ - {2, ROCKHOPPER_PCI4_SLOT, M1535_IRQ_INTC} /* PCI slot #4 */ -}; - -static int pci_intlines[] = - { M1535_IRQ_INTA, M1535_IRQ_INTB, M1535_IRQ_INTC, M1535_IRQ_INTD }; - -/* Determine the Rockhopper IRQ line number for the PCI device */ -int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot) -{ - struct pci_bus *bus; - int i; - - bus = dev->bus; - if (bus == NULL) - return -1; - - for (i = 0; i < ARRAY_SIZE(int_map); i++) { - if (int_map[i].bus == bus->number && int_map[i].slot == slot) { - int line; - for (line = 0; line < 4; line++) - if (pci_intlines[line] == int_map[i].irq) - break; - if (line < 4) - return pci_intlines[(line + (pin - 1)) % 4]; - else - return int_map[i].irq; - } - } - return -1; -} - -#ifdef CONFIG_ROCKHOPPER -void i8259_init(void) -{ - init_i8259_irqs(); - - outb(0x00, 0x4d0); - outb(0x02, 0x4d1); /* USB IRQ9 is level */ -} -#endif - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - pci_probe_only = 1; - -#ifdef CONFIG_ROCKHOPPER - if( dev->bus->number == 1 && vr4133_rockhopper ) { - if(slot == ROCKHOPPER_PCI1_SLOT || slot == ROCKHOPPER_PCI2_SLOT) - dev->irq = CMBVR41XX_INTA_IRQ; - else - dev->irq = rockhopper_get_irq(dev, pin, slot); - } else - dev->irq = CMBVR41XX_INTA_IRQ; -#else - dev->irq = CMBVR41XX_INTA_IRQ; -#endif - - return dev->irq; -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, ali_m1535plus_init); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, ali_m5229_init); - - diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig index 559acc09c819..c1be6b37fb2a 100644 --- a/arch/mips/vr41xx/Kconfig +++ b/arch/mips/vr41xx/Kconfig @@ -23,16 +23,6 @@ config IBM_WORKPAD select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN -config NEC_CMBVR4133 - bool "NEC CMB-VR4133" - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select IRQ_CPU - select HW_HAS_PCI - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - config TANBAC_TB022X bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM" select CEVT_R4K @@ -73,13 +63,6 @@ config ZAO_CAPCELLA endchoice -config ROCKHOPPER - bool "Support for Rockhopper base board" - depends on NEC_CMBVR4133 - select PCI_VR41XX - select I8259 - select HAVE_STD_PC_SERIAL_PORT - choice prompt "Base board type" depends on TANBAC_TB022X diff --git a/arch/mips/vr41xx/nec-cmbvr4133/Makefile b/arch/mips/vr41xx/nec-cmbvr4133/Makefile deleted file mode 100644 index 5835cae54aca..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the NEC-CMBVR4133 -# - -obj-y := init.o setup.o - -obj-$(CONFIG_PCI) += m1535plus.o -obj-$(CONFIG_ROCKHOPPER) += irq.o diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c deleted file mode 100644 index 7c5e18ee2231..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/init.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * arch/mips/vr41xx/nec-cmbvr4133/init.c - * - * PROM library initialisation code for NEC CMB-VR4133 board. - * - * Author: Yoichi Yuasa and - * Jun Sun and - * Alex Sapkov - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for NEC-CMBVR4133 in 2.6 - * Manish Lachwani (mlachwani@mvista.com) - */ - -#ifdef CONFIG_ROCKHOPPER -#include -#include - -#define PCICONFDREG 0xaf000c14 -#define PCICONFAREG 0xaf000c18 - -void disable_pcnet(void) -{ - u32 data; - - /* - * Workaround for the bug in PMON on VR4133. PMON leaves - * AMD PCNet controller (on Rockhopper) initialized and running in - * bus master mode. We have do disable it before doing any - * further initialization. Or we get problems with PCI bus 2 - * and random lockups and crashes. - */ - - writel((2 << 16) | - (PCI_DEVFN(1, 0) << 8) | - (0 & 0xfc) | - 1UL, - PCICONFAREG); - - data = readl(PCICONFDREG); - - writel((2 << 16) | - (PCI_DEVFN(1, 0) << 8) | - (4 & 0xfc) | - 1UL, - PCICONFAREG); - - data = readl(PCICONFDREG); - - writel((2 << 16) | - (PCI_DEVFN(1, 0) << 8) | - (4 & 0xfc) | - 1UL, - PCICONFAREG); - - data &= ~4; - - writel(data, PCICONFDREG); -} -#endif - diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c deleted file mode 100644 index 7d2d076b0f54..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/mips/vr41xx/nec-cmbvr4133/irq.c - * - * Interrupt routines for the NEC CMB-VR4133 board. - * - * Author: Yoichi Yuasa and - * Alex Sapkov - * - * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for NEC-CMBVR4133 in 2.6 - * Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -extern int vr4133_rockhopper; - -static int i8259_get_irq_number(int irq) -{ - return i8259_irq(); -} - -void __init rockhopper_init_irq(void) -{ - int i; - - if(!vr4133_rockhopper) { - printk(KERN_ERR "Not a Rockhopper Board \n"); - return; - } - - vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH); - vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH); - vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number); -} diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c deleted file mode 100644 index 1341f3287d04..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c - * - * Initialize for ALi M1535+(included M5229 and M5237). - * - * Author: Yoichi Yuasa and - * Alex Sapkov - * - * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for NEC-CMBVR4133 in 2.6 - * Author: Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include - -#include -#include -#include - -#define CONFIG_PORT(port) ((port) ? 0x3f0 : 0x370) -#define DATA_PORT(port) ((port) ? 0x3f1 : 0x371) -#define INDEX_PORT(port) CONFIG_PORT(port) - -#define ENTER_CONFIG_MODE(port) \ - do { \ - outb_p(0x51, CONFIG_PORT(port)); \ - outb_p(0x23, CONFIG_PORT(port)); \ - } while(0) - -#define SELECT_LOGICAL_DEVICE(port, dev_no) \ - do { \ - outb_p(0x07, INDEX_PORT(port)); \ - outb_p((dev_no), DATA_PORT(port)); \ - } while(0) - -#define WRITE_CONFIG_DATA(port, index, data) \ - do { \ - outb_p((index), INDEX_PORT(port)); \ - outb_p((data), DATA_PORT(port)); \ - } while(0) - -#define EXIT_CONFIG_MODE(port) outb(0xbb, CONFIG_PORT(port)) - -#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18) -#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14) - -#ifdef CONFIG_BLK_DEV_FD - -void __devinit ali_m1535plus_fdc_init(int port) -{ - ENTER_CONFIG_MODE(port); - SELECT_LOGICAL_DEVICE(port, 0); /* FDC */ - WRITE_CONFIG_DATA(port, 0x30, 0x01); /* FDC: enable */ - WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x3f0 */ - WRITE_CONFIG_DATA(port, 0x61, 0xf0); - WRITE_CONFIG_DATA(port, 0x70, 0x06); /* IRQ: 6 */ - WRITE_CONFIG_DATA(port, 0x74, 0x02); /* DMA: channel 2 */ - WRITE_CONFIG_DATA(port, 0xf0, 0x08); - WRITE_CONFIG_DATA(port, 0xf1, 0x00); - WRITE_CONFIG_DATA(port, 0xf2, 0xff); - WRITE_CONFIG_DATA(port, 0xf4, 0x00); - EXIT_CONFIG_MODE(port); -} - -#endif - -void __devinit ali_m1535plus_parport_init(int port) -{ - ENTER_CONFIG_MODE(port); - SELECT_LOGICAL_DEVICE(port, 3); /* Parallel Port */ - WRITE_CONFIG_DATA(port, 0x30, 0x01); - WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x378 */ - WRITE_CONFIG_DATA(port, 0x61, 0x78); - WRITE_CONFIG_DATA(port, 0x70, 0x07); /* IRQ: 7 */ - WRITE_CONFIG_DATA(port, 0x74, 0x04); /* DMA: None */ - WRITE_CONFIG_DATA(port, 0xf0, 0x8c); /* IRQ polarity: Active Low */ - WRITE_CONFIG_DATA(port, 0xf1, 0xc5); - EXIT_CONFIG_MODE(port); -} - -void __devinit ali_m1535plus_keyboard_init(int port) -{ - ENTER_CONFIG_MODE(port); - SELECT_LOGICAL_DEVICE(port, 7); /* KEYBOARD */ - WRITE_CONFIG_DATA(port, 0x30, 0x01); /* KEYBOARD: eable */ - WRITE_CONFIG_DATA(port, 0x70, 0x01); /* IRQ: 1 */ - WRITE_CONFIG_DATA(port, 0x72, 0x0c); /* PS/2 Mouse IRQ: 12 */ - WRITE_CONFIG_DATA(port, 0xf0, 0x00); - EXIT_CONFIG_MODE(port); -} - -void __devinit ali_m1535plus_hotkey_init(int port) -{ - ENTER_CONFIG_MODE(port); - SELECT_LOGICAL_DEVICE(port, 0xc); /* HOTKEY */ - WRITE_CONFIG_DATA(port, 0x30, 0x00); - WRITE_CONFIG_DATA(port, 0xf0, 0x35); - WRITE_CONFIG_DATA(port, 0xf1, 0x14); - WRITE_CONFIG_DATA(port, 0xf2, 0x11); - WRITE_CONFIG_DATA(port, 0xf3, 0x71); - WRITE_CONFIG_DATA(port, 0xf5, 0x05); - EXIT_CONFIG_MODE(port); -} - -void ali_m1535plus_init(struct pci_dev *dev) -{ - pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */ - pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */ - pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */ - pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */ - pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */ - pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */ - pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */ - - /* IRQ routing */ - pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */ - pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */ - pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */ - pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */ - - pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */ - pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */ - pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */ - pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */ - - pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */ - pci_write_config_byte(dev, 0x5a, 0x00); - pci_write_config_byte(dev, 0x5b, 0x00); - pci_write_config_word(dev, 0x5c, 0x0000); - pci_write_config_byte(dev, 0x5e, 0x00); - pci_write_config_byte(dev, 0x5f, 0x00); - pci_write_config_word(dev, 0x60, 0x0000); - - pci_write_config_byte(dev, 0x6c, 0x00); - pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */ - pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */ - - pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */ - pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */ - pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */ - pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */ - - /* - * IRQ setup ALi M5237 USB Host Controller - * IRQ: 9 - */ - pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */ - - pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15 */ - pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */ - pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */ - pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */ - pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */ - pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */ - pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */ - pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */ - -#ifdef CONFIG_BLK_DEV_FD - ali_m1535plus_fdc_init(1); -#endif - - ali_m1535plus_keyboard_init(1); - ali_m1535plus_hotkey_init(1); -} - -static inline void ali_config_writeb(u8 reg, u8 val, int devfn) -{ - u32 data; - int shift; - - writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); - data = readl(PCI_CONFIG_DATA); - - shift = (reg & 3) << 3; - data &= ~(0xff << shift); - data |= (((u32)val) << shift); - - writel(data, PCI_CONFIG_DATA); -} - -static inline u8 ali_config_readb(u8 reg, int devfn) -{ - u32 data; - - writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); - data = readl(PCI_CONFIG_DATA); - - return (u8)(data >> ((reg & 3) << 3)); -} - -static inline u16 ali_config_readw(u8 reg, int devfn) -{ - u32 data; - - writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR); - data = readl(PCI_CONFIG_DATA); - - return (u16)(data >> ((reg & 2) << 3)); -} - -int vr4133_rockhopper = 0; -void __init ali_m5229_preinit(void) -{ - if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL && - ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) { - printk(KERN_INFO "Found an NEC Rockhopper \n"); - vr4133_rockhopper = 1; - /* - * Enable ALi M5229 IDE Controller (both channels) - * IDSEL: A27 - */ - ali_config_writeb(0x58, 0x4c, 16); - } -} - -void __init ali_m5229_init(struct pci_dev *dev) -{ - /* - * Enable Primary/Secondary Channel Cable Detect 40-Pin - */ - pci_write_config_word(dev, 0x4a, 0xc023); - - /* - * Set only the 3rd byteis for the master IDE's cycle and - * enable Internal IDE Function - */ - pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */ - - pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */ - pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */ - pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */ - pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */ - pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */ - pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */ - pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */ - pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */ - pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */ - pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */ - pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); - pci_write_config_word(dev, PCI_COMMAND, - PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | - PCI_COMMAND_IO); -} - diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c deleted file mode 100644 index 7723d2011b08..000000000000 --- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * arch/mips/vr41xx/nec-cmbvr4133/setup.c - * - * Setup for the NEC CMB-VR4133. - * - * Author: Yoichi Yuasa and - * Alex Sapkov - * - * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for CMBVR4133 board in 2.6 - * Author: Manish Lachwani (mlachwani@mvista.com) - */ -#include -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_MTD -#include -#include -#include -#include - -static struct mtd_partition cmbvr4133_mtd_parts[] = { - { - .name = "User FS", - .size = 0x1be0000, - .offset = 0, - .mask_flags = 0, - }, - { - .name = "PMON", - .size = 0x140000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "User FS2", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - .mask_flags = 0, - } -}; - -#define number_partitions ARRAY_SIZE(cmbvr4133_mtd_parts) -#endif - -extern void i8259_init(void); - -static void __init nec_cmbvr4133_setup(void) -{ -#ifdef CONFIG_ROCKHOPPER - extern void disable_pcnet(void); - - disable_pcnet(); -#endif - set_io_port_base(KSEG1ADDR(0x16000000)); - -#ifdef CONFIG_PCI -#ifdef CONFIG_ROCKHOPPER - ali_m5229_preinit(); -#endif -#endif - -#ifdef CONFIG_ROCKHOPPER - rockhopper_init_irq(); -#endif - -#ifdef CONFIG_MTD - /* we use generic physmap mapping driver and we use partitions */ - physmap_configure(0x1C000000, 0x02000000, 4, NULL); - physmap_set_partitions(cmbvr4133_mtd_parts, number_partitions); -#endif - - /* 128 MB memory support */ - add_memory_region(0, 0x08000000, BOOT_MEM_RAM); - -#ifdef CONFIG_ROCKHOPPER - i8259_init(); -#endif -} diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h index 848812296052..862058d3f81b 100644 --- a/include/asm-mips/mach-vr41xx/irq.h +++ b/include/asm-mips/mach-vr41xx/irq.h @@ -2,9 +2,6 @@ #define __ASM_MACH_VR41XX_IRQ_H #include /* for MIPS_CPU_IRQ_BASE */ -#ifdef CONFIG_NEC_CMBVR4133 -#include /* for I8259A_IRQ_BASE */ -#endif #include_next diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h deleted file mode 100644 index 42300037d593..000000000000 --- a/include/asm-mips/vr41xx/cmbvr4133.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * include/asm-mips/vr41xx/cmbvr4133.h - * - * Include file for NEC CMB-VR4133. - * - * Author: Yoichi Yuasa and - * Jun Sun and - * Alex Sapkov - * - * 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __NEC_CMBVR4133_H -#define __NEC_CMBVR4133_H - -#include - -/* - * General-Purpose I/O Pin Number - */ -#define CMBVR41XX_INTA_PIN 1 -#define CMBVR41XX_INTB_PIN 1 -#define CMBVR41XX_INTC_PIN 3 -#define CMBVR41XX_INTD_PIN 1 -#define CMBVR41XX_INTE_PIN 1 - -/* - * Interrupt Number - */ -#define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN) -#define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN) -#define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN) -#define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) -#define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) - -#define I8259A_IRQ_BASE 72 -#define I8259_IRQ(x) (I8259A_IRQ_BASE + (x)) -#define TIMER_IRQ I8259_IRQ(0) -#define KEYBOARD_IRQ I8259_IRQ(1) -#define I8259_SLAVE_IRQ I8259_IRQ(2) -#define UART3_IRQ I8259_IRQ(3) -#define UART1_IRQ I8259_IRQ(4) -#define UART2_IRQ I8259_IRQ(5) -#define FDC_IRQ I8259_IRQ(6) -#define PARPORT_IRQ I8259_IRQ(7) -#define RTC_IRQ I8259_IRQ(8) -#define USB_IRQ I8259_IRQ(9) -#define I8259_INTA_IRQ I8259_IRQ(10) -#define AUDIO_IRQ I8259_IRQ(11) -#define AUX_IRQ I8259_IRQ(12) -#define IDE_PRIMARY_IRQ I8259_IRQ(14) -#define IDE_SECONDARY_IRQ I8259_IRQ(15) - -#endif /* __NEC_CMBVR4133_H */ -- cgit v1.2.3 From 6e68665e51b9937b132a990b9ae7f04118e64688 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sun, 13 Jul 2008 20:04:18 +0900 Subject: [MIPS] remove machtype for group Toshiba Signed-off-by: Yoichi Yuasa Acked-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/jmr3927/setup.c | 1 - arch/mips/txx9/rbtx4927/setup.c | 2 -- arch/mips/txx9/rbtx4938/setup.c | 1 - include/asm-mips/bootinfo.h | 11 ----------- include/asm-mips/txx9/generic.h | 1 - 5 files changed, 16 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 128a4ae3e72e..43a8dad22ef7 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -366,7 +366,6 @@ static void __init jmr3927_device_init(void) } struct txx9_board_vec jmr3927_vec __initdata = { - .type = MACH_TOSHIBA_JMR3927, .system = "Toshiba JMR_TX3927", .prom_init = jmr3927_prom_init, .mem_setup = jmr3927_mem_setup, diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index adc91c0bbb95..aba11f376a51 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -428,7 +428,6 @@ static void __init rbtx4927_device_init(void) } struct txx9_board_vec rbtx4927_vec __initdata = { - .type = MACH_TOSHIBA_RBTX4927, .system = "Toshiba RBTX4927", .prom_init = rbtx4927_prom_init, .mem_setup = rbtx4927_mem_setup, @@ -441,7 +440,6 @@ struct txx9_board_vec rbtx4927_vec __initdata = { #endif }; struct txx9_board_vec rbtx4937_vec __initdata = { - .type = MACH_TOSHIBA_RBTX4937, .system = "Toshiba RBTX4937", .prom_init = rbtx4927_prom_init, .mem_setup = rbtx4927_mem_setup, diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index 8306ba333dda..2ef71adea827 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -619,7 +619,6 @@ static void __init rbtx4938_device_init(void) } struct txx9_board_vec rbtx4938_vec __initdata = { - .type = MACH_TOSHIBA_RBTX4938, .system = "Toshiba RBTX4938", .prom_init = rbtx4938_prom_init, .mem_setup = rbtx4938_mem_setup, diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index e031bdff9920..c70848d4f632 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -61,17 +61,6 @@ #define MACH_SGI_IP32 3 /* O2 */ #define MACH_SGI_IP30 4 /* Octane, Octane2 */ -/* - * Valid machtypes for group Toshiba - */ -#define MACH_PALLAS 0 -#define MACH_TOPAS 1 -#define MACH_JMR 2 -#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ -#define MACH_TOSHIBA_RBTX4927 4 -#define MACH_TOSHIBA_RBTX4937 5 -#define MACH_TOSHIBA_RBTX4938 6 - /* * Valid machtype for group LASAT */ diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h index 6cd147764f19..715d7c8ade5c 100644 --- a/include/asm-mips/txx9/generic.h +++ b/include/asm-mips/txx9/generic.h @@ -22,7 +22,6 @@ extern unsigned int txx9_gbus_clock; struct pci_dev; struct txx9_board_vec { - unsigned long type; const char *system; void (*prom_init)(void); void (*mem_setup)(void); -- cgit v1.2.3 From 4c642f3f5e9f3f1a2fcce2c3fa1a94bf80142202 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sun, 13 Jul 2008 23:37:56 +0900 Subject: [MIPS] TXx9: rename asm-mips/mach-jmr3927 to asm-mips/mach-tx39xx Rename mach-jmr3927 directory to more proper name to make adding other platforms easier. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Makefile | 2 +- arch/mips/txx9/generic/setup.c | 10 ++++++++ arch/mips/txx9/jmr3927/setup.c | 4 +-- include/asm-mips/mach-jmr3927/ioremap.h | 38 ----------------------------- include/asm-mips/mach-jmr3927/mangle-port.h | 18 -------------- include/asm-mips/mach-jmr3927/war.h | 25 ------------------- include/asm-mips/mach-tx39xx/ioremap.h | 38 +++++++++++++++++++++++++++++ include/asm-mips/mach-tx39xx/mangle-port.h | 23 +++++++++++++++++ include/asm-mips/mach-tx39xx/war.h | 25 +++++++++++++++++++ 9 files changed, 99 insertions(+), 84 deletions(-) delete mode 100644 include/asm-mips/mach-jmr3927/ioremap.h delete mode 100644 include/asm-mips/mach-jmr3927/mangle-port.h delete mode 100644 include/asm-mips/mach-jmr3927/war.h create mode 100644 include/asm-mips/mach-tx39xx/ioremap.h create mode 100644 include/asm-mips/mach-tx39xx/mangle-port.h create mode 100644 include/asm-mips/mach-tx39xx/war.h (limited to 'include/asm-mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index c4a3098a58c6..356453322b49 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -548,7 +548,7 @@ all-$(CONFIG_SNI_RM) := vmlinux.ecoff # Common TXx9 # core-$(CONFIG_MACH_TX39XX) += arch/mips/txx9/generic/ -cflags-$(CONFIG_MACH_TX39XX) += -Iinclude/asm-mips/mach-jmr3927 +cflags-$(CONFIG_MACH_TX39XX) += -Iinclude/asm-mips/mach-tx39xx load-$(CONFIG_MACH_TX39XX) += 0xffffffff80050000 core-$(CONFIG_MACH_TX49XX) += arch/mips/txx9/generic/ cflags-$(CONFIG_MACH_TX49XX) += -Iinclude/asm-mips/mach-tx49xx diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 517828e1ec92..452cb9ea12c0 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -200,3 +200,13 @@ asmlinkage void plat_irq_dispatch(void) else spurious_interrupt(); } + +/* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */ +#ifdef NEEDS_TXX9_SWIZZLE_ADDR_B +static unsigned long __swizzle_addr_none(unsigned long port) +{ + return port; +} +unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none; +EXPORT_SYMBOL(__swizzle_addr_b); +#endif diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 43a8dad22ef7..61edc4ac1dbc 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -315,7 +315,7 @@ static void __init tx3927_setup(void) } /* This trick makes rtc-ds1742 driver usable as is. */ -unsigned long __swizzle_addr_b(unsigned long port) +static unsigned long jmr3927_swizzle_addr_b(unsigned long port) { if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR) return port; @@ -326,7 +326,6 @@ unsigned long __swizzle_addr_b(unsigned long port) return port | 1; #endif } -EXPORT_SYMBOL(__swizzle_addr_b); static int __init jmr3927_rtc_init(void) { @@ -361,6 +360,7 @@ static int __init jmr3927_wdt_init(void) static void __init jmr3927_device_init(void) { + __swizzle_addr_b = jmr3927_swizzle_addr_b; jmr3927_rtc_init(); jmr3927_wdt_init(); } diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-jmr3927/ioremap.h deleted file mode 100644 index 29989ff10d66..000000000000 --- a/include/asm-mips/mach-jmr3927/ioremap.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-mips/mach-jmr3927/ioremap.h - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MACH_JMR3927_IOREMAP_H -#define __ASM_MACH_JMR3927_IOREMAP_H - -#include - -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, - unsigned long flags) -{ -#define TXX9_DIRECTMAP_BASE 0xff000000ul - if (offset >= TXX9_DIRECTMAP_BASE && - offset < TXX9_DIRECTMAP_BASE + 0xff0000) - return (void __iomem *)offset; - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return (unsigned long)addr >= TXX9_DIRECTMAP_BASE; -} - -#endif /* __ASM_MACH_JMR3927_IOREMAP_H */ diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-jmr3927/mangle-port.h deleted file mode 100644 index 11bffcd1043b..000000000000 --- a/include/asm-mips/mach-jmr3927/mangle-port.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __ASM_MACH_JMR3927_MANGLE_PORT_H -#define __ASM_MACH_JMR3927_MANGLE_PORT_H - -extern unsigned long __swizzle_addr_b(unsigned long port); -#define __swizzle_addr_w(port) (port) -#define __swizzle_addr_l(port) (port) -#define __swizzle_addr_q(port) (port) - -#define ioswabb(a, x) (x) -#define __mem_ioswabb(a, x) (x) -#define ioswabw(a, x) le16_to_cpu(x) -#define __mem_ioswabw(a, x) (x) -#define ioswabl(a, x) le32_to_cpu(x) -#define __mem_ioswabl(a, x) (x) -#define ioswabq(a, x) le64_to_cpu(x) -#define __mem_ioswabq(a, x) (x) - -#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-jmr3927/war.h deleted file mode 100644 index 1ff55fb3fbcb..000000000000 --- a/include/asm-mips/mach-jmr3927/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H -#define __ASM_MIPS_MACH_JMR3927_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ diff --git a/include/asm-mips/mach-tx39xx/ioremap.h b/include/asm-mips/mach-tx39xx/ioremap.h new file mode 100644 index 000000000000..93c6c04ffda3 --- /dev/null +++ b/include/asm-mips/mach-tx39xx/ioremap.h @@ -0,0 +1,38 @@ +/* + * include/asm-mips/mach-tx39xx/ioremap.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MACH_TX39XX_IOREMAP_H +#define __ASM_MACH_TX39XX_IOREMAP_H + +#include + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ +#define TXX9_DIRECTMAP_BASE 0xff000000ul + if (offset >= TXX9_DIRECTMAP_BASE && + offset < TXX9_DIRECTMAP_BASE + 0xff0000) + return (void __iomem *)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return (unsigned long)addr >= TXX9_DIRECTMAP_BASE; +} + +#endif /* __ASM_MACH_TX39XX_IOREMAP_H */ diff --git a/include/asm-mips/mach-tx39xx/mangle-port.h b/include/asm-mips/mach-tx39xx/mangle-port.h new file mode 100644 index 000000000000..ef0b502fd8b7 --- /dev/null +++ b/include/asm-mips/mach-tx39xx/mangle-port.h @@ -0,0 +1,23 @@ +#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H +#define __ASM_MACH_TX39XX_MANGLE_PORT_H + +#if defined(CONFIG_TOSHIBA_JMR3927) +extern unsigned long (*__swizzle_addr_b)(unsigned long port); +#define NEEDS_TXX9_SWIZZLE_ADDR_B +#else +#define __swizzle_addr_b(port) (port) +#endif +#define __swizzle_addr_w(port) (port) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +#define ioswabb(a, x) (x) +#define __mem_ioswabb(a, x) (x) +#define ioswabw(a, x) le16_to_cpu(x) +#define __mem_ioswabw(a, x) (x) +#define ioswabl(a, x) le32_to_cpu(x) +#define __mem_ioswabl(a, x) (x) +#define ioswabq(a, x) le64_to_cpu(x) +#define __mem_ioswabq(a, x) (x) + +#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-tx39xx/war.h b/include/asm-mips/mach-tx39xx/war.h new file mode 100644 index 000000000000..433814616359 --- /dev/null +++ b/include/asm-mips/mach-tx39xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H +#define __ASM_MIPS_MACH_TX39XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */ -- cgit v1.2.3 From 7b22609442a32050e37cec5f6735376af61e68a1 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 14 Jul 2008 00:15:04 +0900 Subject: [MIPS] TXx9: cleanup and fix some sparse warnings * Do not return void value * Make some functions static * Do not include unnecessary bootinfo.h Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/generic/setup.c | 2 +- arch/mips/txx9/jmr3927/setup.c | 3 --- arch/mips/txx9/rbtx4927/setup.c | 16 +++------------- arch/mips/txx9/rbtx4938/setup.c | 13 +++---------- include/asm-mips/txx9/generic.h | 1 + 5 files changed, 8 insertions(+), 27 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 452cb9ea12c0..5afc5d5cab03 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -140,7 +140,7 @@ void __init prom_init(void) strcpy(txx9_system_type, txx9_board_vec->system); - return txx9_board_vec->prom_init(); + txx9_board_vec->prom_init(); } void __init prom_free_prom_memory(void) diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 61edc4ac1dbc..5e35ef73c5a5 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -38,8 +38,6 @@ #ifdef CONFIG_SERIAL_TXX9 #include #endif - -#include #include #include #include @@ -95,7 +93,6 @@ static void __init jmr3927_time_init(void) #define DO_WRITE_THROUGH #define DO_ENABLE_CACHE -extern char * __init prom_getcmdline(void); static void jmr3927_board_init(void); static void __init jmr3927_mem_setup(void) diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index aba11f376a51..1657fd935da8 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -50,8 +50,6 @@ #include #include #include - -#include #include #include #include @@ -65,14 +63,6 @@ #include #endif -/* These functions are used for rebooting or halting the machine*/ -extern void toshiba_rbtx4927_restart(char *command); -extern void toshiba_rbtx4927_halt(void); -extern void toshiba_rbtx4927_power_off(void); -extern void toshiba_rbtx4927_irq_setup(void); - -char *prom_getcmdline(void); - static int tx4927_ccfg_toeon = 1; #ifdef CONFIG_PCI @@ -189,7 +179,7 @@ static void __noreturn wait_forever(void) (*cpu_wait)(); } -void toshiba_rbtx4927_restart(char *command) +static void toshiba_rbtx4927_restart(char *command) { printk(KERN_NOTICE "System Rebooting...\n"); @@ -209,7 +199,7 @@ void toshiba_rbtx4927_restart(char *command) /* no return */ } -void toshiba_rbtx4927_halt(void) +static void toshiba_rbtx4927_halt(void) { printk(KERN_NOTICE "System Halted\n"); local_irq_disable(); @@ -217,7 +207,7 @@ void toshiba_rbtx4927_halt(void) /* no return */ } -void toshiba_rbtx4927_power_off(void) +static void toshiba_rbtx4927_power_off(void) { toshiba_rbtx4927_halt(); /* no return */ diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index 2ef71adea827..aaa987ae0f83 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -34,15 +33,9 @@ #include #include -extern char * __init prom_getcmdline(void); -/* These functions are used for rebooting or halting the machine*/ -extern void rbtx4938_machine_restart(char *command); -extern void rbtx4938_machine_halt(void); -extern void rbtx4938_machine_power_off(void); - static int tx4938_ccfg_toeon = 1; -void rbtx4938_machine_halt(void) +static void rbtx4938_machine_halt(void) { printk(KERN_NOTICE "System Halted\n"); local_irq_disable(); @@ -53,13 +46,13 @@ void rbtx4938_machine_halt(void) ".set\tmips0"); } -void rbtx4938_machine_power_off(void) +static void rbtx4938_machine_power_off(void) { rbtx4938_machine_halt(); /* no return */ } -void rbtx4938_machine_restart(char *command) +static void rbtx4938_machine_restart(char *command) { local_irq_disable(); diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h index 715d7c8ade5c..d8756660523d 100644 --- a/include/asm-mips/txx9/generic.h +++ b/include/asm-mips/txx9/generic.h @@ -36,5 +36,6 @@ struct txx9_board_vec { extern struct txx9_board_vec *txx9_board_vec; extern int (*txx9_irq_dispatch)(int pending); void prom_init_cmdline(void); +char *prom_getcmdline(void); #endif /* __ASM_TXX9_GENERIC_H */ -- cgit v1.2.3 From c660729501894e0b88054ad4b66a5f98a1a2a37e Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 14 Jul 2008 15:11:40 +0200 Subject: [MIPS] Remove mips_machtype from ARC based machines This is the ARC part of the mips_machtype removal. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/fw/arc/identify.c | 11 ----------- arch/mips/jazz/setup.c | 3 +-- include/asm-mips/bootinfo.h | 21 --------------------- 3 files changed, 1 insertion(+), 34 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/fw/arc/identify.c b/arch/mips/fw/arc/identify.c index 23066985a734..0ce9acf10c39 100644 --- a/arch/mips/fw/arc/identify.c +++ b/arch/mips/fw/arc/identify.c @@ -22,7 +22,6 @@ struct smatch { char *arcname; char *liname; - int type; int flags; }; @@ -30,47 +29,38 @@ static struct smatch mach_table[] = { { .arcname = "SGI-IP22", .liname = "SGI Indy", - .type = MACH_SGI_IP22, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP27", .liname = "SGI Origin", - .type = MACH_SGI_IP27, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP28", .liname = "SGI IP28", - .type = MACH_SGI_IP28, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP30", .liname = "SGI Octane", - .type = MACH_SGI_IP30, .flags = PROM_FLAG_ARCS, }, { .arcname = "SGI-IP32", .liname = "SGI O2", - .type = MACH_SGI_IP32, .flags = PROM_FLAG_ARCS, }, { .arcname = "Microsoft-Jazz", .liname = "Jazz MIPS_Magnum_4000", - .type = MACH_MIPS_MAGNUM_4000, .flags = 0, }, { .arcname = "PICA-61", .liname = "Jazz Acer_PICA_61", - .type = MACH_ACER_PICA_61, .flags = 0, }, { .arcname = "RM200PCI", .liname = "SNI RM200_PCI", - .type = MACH_SNI_RM200_PCI, .flags = PROM_FLAG_DONT_FREE_TEMP, }, { .arcname = "RM200PCI-R5K", .liname = "SNI RM200_PCI-R5K", - .type = MACH_SNI_RM200_PCI, .flags = PROM_FLAG_DONT_FREE_TEMP, } }; @@ -121,6 +111,5 @@ void __init prom_identify_arch(void) mach = string_to_mach(iname); system_type = mach->liname; - mips_machtype = mach->type; prom_flags = mach->flags; } diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index f136c8a8591c..f60524e8bc44 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -76,8 +76,7 @@ void __init plat_mem_setup(void) set_io_port_base(JAZZ_PORT_BASE); #ifdef CONFIG_EISA - if (mips_machtype == MACH_MIPS_MAGNUM_4000) - EISA_bus = 1; + EISA_bus = 1; #endif /* request I/O space for devices used on all i[345]86 PCs */ diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index c70848d4f632..653096a69d16 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -25,13 +25,6 @@ */ #define MACH_UNKNOWN 0 /* whatever... */ -/* - * Valid machtype values for group JAZZ - */ -#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ -#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ -#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ - /* * Valid machtype for group DEC */ @@ -47,20 +40,6 @@ #define MACH_DS5800 9 /* DECsystem 5800 */ #define MACH_DS5900 10 /* DECsystem 5900 */ -/* - * Valid machtype for group SNI_RM - */ -#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ - -/* - * Valid machtype for group SGI - */ -#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ -#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ -#define MACH_SGI_IP28 2 /* Indigo2 Impact */ -#define MACH_SGI_IP32 3 /* O2 */ -#define MACH_SGI_IP30 4 /* Octane, Octane2 */ - /* * Valid machtype for group LASAT */ -- cgit v1.2.3 From 0b56fd8c7abbf85baeecb77be25c54d3c7d11587 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 14 Jul 2008 15:54:30 +0200 Subject: [MIPS] Remove mips_machtype from EMMA2RH machines This is the EMMA2RH part of the mips_machtype removal. [Ralf: Fixed to the #error statements] Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/emma2rh/common/prom.c | 15 +++++++-------- include/asm-mips/bootinfo.h | 5 ----- 2 files changed, 7 insertions(+), 13 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c index 0f791eb6bb66..5e92b3a9c5b8 100644 --- a/arch/mips/emma2rh/common/prom.c +++ b/arch/mips/emma2rh/common/prom.c @@ -34,12 +34,11 @@ const char *get_system_type(void) { - switch (mips_machtype) { - case MACH_NEC_MARKEINS: - return "NEC EMMA2RH Mark-eins"; - default: - return "Unknown NEC board"; - } +#if defined(CONFIG_MARKEINS) + return "NEC EMMA2RH Mark-eins"; +#else +#error Unknown NEC board +#endif } /* [jsun@junsun.net] PMON passes arguments in C main() style */ @@ -63,10 +62,10 @@ void __init prom_init(void) } #if defined(CONFIG_MARKEINS) - mips_machtype = MACH_NEC_MARKEINS; add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); +#else +#error Unknown NEC board #endif - } void __init prom_free_prom_memory(void) diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 653096a69d16..51dbec9dabfd 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -46,11 +46,6 @@ #define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ #define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ -/* - * Valid machtype for group NEC EMMA2RH - */ -#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ - /* * Valid machtype for group PMC-MSP */ -- cgit v1.2.3 From b27418aa551a153e8bf1bd16cf93e5786f9590a9 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 14 Jul 2008 16:58:47 +0200 Subject: [MIPS] Remove mips_machtype for LASAT machines This is the LASAT part of the mips_machtype removal. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/lasat/interrupt.c | 21 ++++++++------------- arch/mips/lasat/lasat_board.c | 3 +-- arch/mips/lasat/prom.c | 8 +++----- arch/mips/lasat/serial.c | 3 +-- arch/mips/lasat/setup.c | 8 +++++--- arch/mips/pci/pci-lasat.c | 14 ++++---------- include/asm-mips/bootinfo.h | 6 ------ include/asm-mips/lasat/lasat.h | 2 ++ 8 files changed, 24 insertions(+), 41 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index a56c15026965..d1ac7a25c856 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -22,8 +22,8 @@ #include #include -#include #include +#include #include #include @@ -112,23 +112,18 @@ void __init arch_init_irq(void) { int i; - switch (mips_machtype) { - case MACH_LASAT_100: - lasat_int_status = (void *)LASAT_INT_STATUS_REG_100; - lasat_int_mask = (void *)LASAT_INT_MASK_REG_100; - lasat_int_mask_shift = LASATINT_MASK_SHIFT_100; - get_int_status = get_int_status_100; - *lasat_int_mask = 0; - break; - case MACH_LASAT_200: + if (IS_LASAT_200()) { lasat_int_status = (void *)LASAT_INT_STATUS_REG_200; lasat_int_mask = (void *)LASAT_INT_MASK_REG_200; lasat_int_mask_shift = LASATINT_MASK_SHIFT_200; get_int_status = get_int_status_200; *lasat_int_mask &= 0xffff; - break; - default: - panic("arch_init_irq: mips_machtype incorrect"); + } else { + lasat_int_status = (void *)LASAT_INT_STATUS_REG_100; + lasat_int_mask = (void *)LASAT_INT_MASK_REG_100; + lasat_int_mask_shift = LASATINT_MASK_SHIFT_100; + get_int_status = get_int_status_100; + *lasat_int_mask = 0; } mips_cpu_irq_init(); diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c index 31e328b3814d..577bb463a871 100644 --- a/arch/mips/lasat/lasat_board.c +++ b/arch/mips/lasat/lasat_board.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "at93c.h" /* New model description table */ @@ -66,7 +65,7 @@ static void init_flash_sizes(void) ls[LASAT_MTD_SERVICE] = 0xC0000; ls[LASAT_MTD_NORMAL] = 0x100000; - if (mips_machtype == MACH_LASAT_100) { + if (!IS_LASAT_200()) { lasat_board_info.li_flash_base = 0x1e000000; lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index 209edcc26f07..6acc6cb85f0a 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -86,18 +86,16 @@ void __init prom_init(void) setup_prom_vectors(); - if (current_cpu_data.cputype == CPU_R5000) { + if (IS_LASAT_200()) { printk(KERN_INFO "LASAT 200 board\n"); - mips_machtype = MACH_LASAT_200; lasat_ndelay_divider = LASAT_200_DIVIDER; + at93c = &at93c_defs[1]; } else { printk(KERN_INFO "LASAT 100 board\n"); - mips_machtype = MACH_LASAT_100; lasat_ndelay_divider = LASAT_100_DIVIDER; + at93c = &at93c_defs[0]; } - at93c = &at93c_defs[mips_machtype]; - lasat_init_board_info(); /* Read info from EEPROM */ /* Get the command line */ diff --git a/arch/mips/lasat/serial.c b/arch/mips/lasat/serial.c index 205bd397d75b..5bcb6e89ab78 100644 --- a/arch/mips/lasat/serial.c +++ b/arch/mips/lasat/serial.c @@ -23,7 +23,6 @@ #include #include -#include #include #include @@ -47,7 +46,7 @@ static __init int lasat_uart_add(void) if (!pdev) return -ENOMEM; - if (mips_machtype == MACH_LASAT_100) { + if (!IS_LASAT_200()) { lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_100); lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_100 * 8 - 1; lasat_serial_res[0].flags = IORESOURCE_MEM; diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index e072da4ff3b3..dbd3163a85c2 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -127,9 +127,11 @@ void __init plat_time_init(void) void __init plat_mem_setup(void) { int i; - lasat_misc = &lasat_misc_info[mips_machtype]; + int lasat_type = IS_LASAT_200() ? 1 : 0; + + lasat_misc = &lasat_misc_info[lasat_type]; #ifdef CONFIG_PICVUE - picvue = &pvc_defs[mips_machtype]; + picvue = &pvc_defs[lasat_type]; #endif /* Set up panic notifier */ @@ -140,7 +142,7 @@ void __init plat_mem_setup(void) lasat_reboot_setup(); #ifdef CONFIG_DS1603 - ds1603 = &ds_defs[mips_machtype]; + ds1603 = &ds_defs[lasat_type]; #endif #ifdef DYNAMIC_SERIAL_INIT diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c index e70ae3236e0b..a98e543a514a 100644 --- a/arch/mips/pci/pci-lasat.c +++ b/arch/mips/pci/pci-lasat.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include @@ -39,16 +39,10 @@ static int __init lasat_pci_setup(void) { printk(KERN_DEBUG "PCI: starting\n"); - switch (mips_machtype) { - case MACH_LASAT_100: - lasat_pci_controller.pci_ops = >64xxx_pci0_ops; - break; - case MACH_LASAT_200: + if (IS_LASAT_200()) lasat_pci_controller.pci_ops = &nile4_pci_ops; - break; - default: - panic("pcibios_init: mips_machtype incorrect"); - } + else + lasat_pci_controller.pci_ops = >64xxx_pci0_ops; register_pci_controller(&lasat_pci_controller); diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 51dbec9dabfd..d39e143b4a3c 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -40,12 +40,6 @@ #define MACH_DS5800 9 /* DECsystem 5800 */ #define MACH_DS5900 10 /* DECsystem 5900 */ -/* - * Valid machtype for group LASAT - */ -#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ -#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ - /* * Valid machtype for group PMC-MSP */ diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h index ea04d9262edc..caeba1e302a2 100644 --- a/include/asm-mips/lasat/lasat.h +++ b/include/asm-mips/lasat/lasat.h @@ -240,6 +240,8 @@ static inline void lasat_ndelay(unsigned int ns) __delay(ns / lasat_ndelay_divider); } +#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000) + #endif /* !defined (_LANGUAGE_ASSEMBLY) */ #define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef -- cgit v1.2.3 From 3450004a8cec8bab246372a1cabb9c2483b1e6c3 Mon Sep 17 00:00:00 2001 From: Dmitri Vorobiev Date: Tue, 15 Jul 2008 19:57:30 +0300 Subject: [MIPS] PCI: Make the pcibios_max_latency variable static The pcibios_max_latency variable is needlessly defined global, and this patch makes it static. Build-tested using malta_defconfig. Signed-off-by: Dmitri Vorobiev Signed-off-by: Ralf Baechle --- arch/mips/pci/pci.c | 2 +- include/asm-mips/pci.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index d7d6cb063d26..77bd5b68dc43 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -204,7 +204,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) * If we set up a device for bus mastering, we need to check the latency * timer as certain crappy BIOSes forget to set it properly. */ -unsigned int pcibios_max_latency = 255; +static unsigned int pcibios_max_latency = 255; void pcibios_set_master(struct pci_dev *dev) { diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index d3be83436070..c205875d7f31 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -173,6 +173,5 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) } extern int pci_probe_only; -extern unsigned int pcibios_max_latency; #endif /* _ASM_PCI_H */ -- cgit v1.2.3 From f028b8605613ade67fda554e30d367911d6c7222 Mon Sep 17 00:00:00 2001 From: Dmitri Vorobiev Date: Tue, 15 Jul 2008 19:57:31 +0300 Subject: [MIPS] Fix missing prototypes in asm/fpu.h While building the Malta defconfig, sparse spat the following warnings: >>>>>>>>>>>>>>>>>> arch/mips/math-emu/kernel_linkage.c:31:6: warning: symbol 'fpu_emulator_init_fpu' was not declared. Should it be static? arch/mips/math-emu/kernel_linkage.c:54:5: warning: symbol 'fpu_emulator_save_context' was not declared. Should it be static? arch/mips/math-emu/kernel_linkage.c:68:5: warning: symbol 'fpu_emulator_restore_context' was not declared. Should it be static? >>>>>>>>>>>>>>>>>> This patch fixes these errors by adding the proper prototypes to the include/asm-mips/fpu.h header, and actually using this header in the sparse-spotted source file. Build-tested with Malta defconfig. Signed-off-by: Dmitri Vorobiev Signed-off-by: Ralf Baechle --- arch/mips/math-emu/kernel_linkage.c | 1 + include/asm-mips/fpu.h | 2 ++ 2 files changed, 3 insertions(+) (limited to 'include/asm-mips') diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c index ed49ef01ac53..52e6c58c8de1 100644 --- a/arch/mips/math-emu/kernel_linkage.c +++ b/arch/mips/math-emu/kernel_linkage.c @@ -24,6 +24,7 @@ #include #include +#include #include #define SIGNALLING_NAN 0x7ff800007ff80000LL diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index e59d4c039661..8a3ef247659a 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -35,6 +35,8 @@ extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); extern void fpu_emulator_init_fpu(void); +extern int fpu_emulator_save_context(struct sigcontext __user *sc); +extern int fpu_emulator_restore_context(struct sigcontext __user *sc); extern void _init_fpu(void); extern void _save_fp(struct task_struct *); extern void _restore_fp(struct task_struct *); -- cgit v1.2.3 From c29d150305f7f655b7002cc31754c605e5c0d1a0 Mon Sep 17 00:00:00 2001 From: Dmitri Vorobiev Date: Tue, 15 Jul 2008 19:57:32 +0300 Subject: [MIPS] Add missing prototypes to asm/page.h This patch fixes the following sparse warnings: >>>>>>>>>>>>>>>>>> arch/mips/mm/page.c:284:16: warning: symbol 'build_clear_page' was not declared. Should it be static? arch/mips/mm/page.c:426:16: warning: symbol 'build_copy_page' was not declared. Should it be static? >>>>>>>>>>>>>>>>>> The fix is to add appropriate prototypes to the header include/asm-mips/page.h. Build-tested against Malta defconfig. Signed-off-by: Dmitri Vorobiev Signed-off-by: Ralf Baechle --- include/asm-mips/page.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/asm-mips') diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 8735aa0b8963..494f00ba9541 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -34,6 +34,9 @@ #include #include +extern void build_clear_page(void); +extern void build_copy_page(void); + /* * It's normally defined only for FLATMEM config but it's * used in our early mem init code for all memory models. -- cgit v1.2.3 From d6d8a4635a8451ca3c6fa2aaf9bbf934d8e2097b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 16 Jul 2008 12:07:05 +0100 Subject: [MIPS] Tinker with constraints in to fix build error. [...] CC init/main.o include/asm/bitops.h: In function `start_kernel': include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: error: impossible constraint in `asm' include/asm/bitops.h:76: error: impossible constraint in `asm' include/asm/bitops.h:76: error: impossible constraint in `asm' make[1]: *** [init/main.o] Error 1 [...] The build error is caused by the ages old gcc bug where gcc at the time of analyzing the constraints is unable to figure out that an "i" constraint actually can be satisfied and thus will abort unless an "r" is added to the constraint. For the actual code generation gcc will only ever use the "i" constraint. Signed-off-by: Ralf Baechle --- include/asm-mips/bitops.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 9a7274ba6a0b..49df8c4c9d25 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) - : "i" (bit), "m" (*m), "r" (~0)); + : "ir" (bit), "m" (*m), "r" (~0)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( @@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) - : "i" (bit), "m" (*m)); + : "ir" (bit), "m" (*m)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( @@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr, "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m), "=&r" (res) - : "i" (bit), "m" (*m) + : "ir" (bit), "m" (*m) : "memory"); #endif } else if (cpu_has_llsc) { -- cgit v1.2.3 From 73b4390fb23456964201abda79f1210fe337d01a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 16 Jul 2008 16:12:25 +0100 Subject: [MIPS] Routerboard 532: Support for base system Signed-off-by: Phil Sutter Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 20 +- arch/mips/Makefile | 7 + arch/mips/configs/rb532_defconfig | 1314 ++++++++++++++++++++ arch/mips/pci/Makefile | 1 + arch/mips/pci/fixup-rc32434.c | 69 + arch/mips/pci/ops-rc32434.c | 207 +++ arch/mips/pci/pci-rc32434.c | 221 ++++ arch/mips/rb532/Makefile | 7 + arch/mips/rb532/devices.c | 331 +++++ arch/mips/rb532/gpio.c | 220 ++++ arch/mips/rb532/irq.c | 209 ++++ arch/mips/rb532/prom.c | 158 +++ arch/mips/rb532/serial.c | 53 + arch/mips/rb532/setup.c | 79 ++ arch/mips/rb532/time.c | 67 + include/asm-mips/bootinfo.h | 6 + .../asm-mips/mach-rc32434/cpu-feature-overrides.h | 81 ++ include/asm-mips/mach-rc32434/ddr.h | 141 +++ include/asm-mips/mach-rc32434/dma.h | 103 ++ include/asm-mips/mach-rc32434/dma_v.h | 52 + include/asm-mips/mach-rc32434/eth.h | 220 ++++ include/asm-mips/mach-rc32434/gpio.h | 126 ++ include/asm-mips/mach-rc32434/integ.h | 59 + include/asm-mips/mach-rc32434/irq.h | 8 + include/asm-mips/mach-rc32434/pci.h | 481 +++++++ include/asm-mips/mach-rc32434/prom.h | 44 + include/asm-mips/mach-rc32434/rb.h | 81 ++ include/asm-mips/mach-rc32434/rc32434.h | 61 + include/asm-mips/mach-rc32434/timer.h | 65 + include/asm-mips/mach-rc32434/war.h | 25 + 30 files changed, 4515 insertions(+), 1 deletion(-) create mode 100644 arch/mips/configs/rb532_defconfig create mode 100644 arch/mips/pci/fixup-rc32434.c create mode 100644 arch/mips/pci/ops-rc32434.c create mode 100644 arch/mips/pci/pci-rc32434.c create mode 100644 arch/mips/rb532/Makefile create mode 100644 arch/mips/rb532/devices.c create mode 100644 arch/mips/rb532/gpio.c create mode 100644 arch/mips/rb532/irq.c create mode 100644 arch/mips/rb532/prom.c create mode 100644 arch/mips/rb532/serial.c create mode 100644 arch/mips/rb532/setup.c create mode 100644 arch/mips/rb532/time.c create mode 100644 include/asm-mips/mach-rc32434/cpu-feature-overrides.h create mode 100644 include/asm-mips/mach-rc32434/ddr.h create mode 100644 include/asm-mips/mach-rc32434/dma.h create mode 100644 include/asm-mips/mach-rc32434/dma_v.h create mode 100644 include/asm-mips/mach-rc32434/eth.h create mode 100644 include/asm-mips/mach-rc32434/gpio.h create mode 100644 include/asm-mips/mach-rc32434/integ.h create mode 100644 include/asm-mips/mach-rc32434/irq.h create mode 100644 include/asm-mips/mach-rc32434/pci.h create mode 100644 include/asm-mips/mach-rc32434/prom.h create mode 100644 include/asm-mips/mach-rc32434/rb.h create mode 100644 include/asm-mips/mach-rc32434/rc32434.h create mode 100644 include/asm-mips/mach-rc32434/timer.h create mode 100644 include/asm-mips/mach-rc32434/war.h (limited to 'include/asm-mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 30edc395dce7..b9c754f4070c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -558,6 +558,24 @@ config MACH_TX39XX config MACH_TX49XX bool "Toshiba TX49 series based machines" +config MIKROTIK_RB532 + bool "Mikrotik RB532 boards" + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select GENERIC_HARDIRQS_NO__DO_IRQ + select HW_HAS_PCI + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SWAP_IO_SPACE + select BOOT_RAW + select GENERIC_GPIO + help + Support the Mikrotik(tm) RouterBoard 532 series, + based on the IDT RC32434 SoC. + config WR_PPMC bool "Wind River PPMC board" select CEVT_R4K @@ -899,7 +917,7 @@ config BOOT_ELF32 config MIPS_L1_CACHE_SHIFT int - default "4" if MACH_DECSTATION + default "4" if MACH_DECSTATION || MIKROTIK_RB532 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM default "4" if PMC_MSP4200_EVAL default "5" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 356453322b49..9aab51caf16a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -559,6 +559,13 @@ load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000 # core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ +# +# Routerboard 532 board +# +core-$(CONFIG_MIKROTIK_RB532) += arch/mips/rb532/ +cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434 +load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000 + # # Toshiba RBTX4927 board or # Toshiba RBTX4937 board diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig new file mode 100644 index 000000000000..f28dc32974e5 --- /dev/null +++ b/arch/mips/configs/rb532_defconfig @@ -0,0 +1,1314 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.25 +# Mon Apr 28 12:24:17 2008 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_TOSHIBA_JMR3927 is not set +CONFIG_MIKROTIK_RB532=y +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_WR_PPMC is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_BOOT_RAW=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_MIPS_L1_CACHE_SHIFT=4 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_CLASSIC_RCU=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=y +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +# CONFIG_DEFAULT_BIC is not set +# CONFIG_DEFAULT_CUBIC is not set +# CONFIG_DEFAULT_HTCP is not set +CONFIG_DEFAULT_VEGAS=y +# CONFIG_DEFAULT_WESTWOOD is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="vegas" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CT_ACCT=y +CONFIG_NF_CONNTRACK_MARK=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=m +# CONFIG_NF_CONNTRACK_H323 is not set +CONFIG_NF_CONNTRACK_IRC=m +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +CONFIG_NF_CONNTRACK_TFTP=m +# CONFIG_NF_CT_NETLINK is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_TRACE=m +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=m +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATE=y +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_RECENT is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_REDIRECT is not set +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_SIP is not set +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +# CONFIG_DECNET is not set +CONFIG_LLC=y +CONFIG_LLC2=m +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RR=m +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_INGRESS is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +# CONFIG_NET_ACT_NAT is not set +CONFIG_NET_ACT_PEDIT=m +# CONFIG_NET_ACT_SIMP is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +# CONFIG_AX25 is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_BLOCK2MTD=y + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_SATA_PMP is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +CONFIG_PATA_RB532=y +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +CONFIG_IFB=m +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_KORINA=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_DM9000 is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_TC35815 is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +CONFIG_VIA_RHINE=y +# CONFIG_VIA_RHINE_MMIO is not set +CONFIG_VIA_RHINE_NAPI=y +# CONFIG_SC92031 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +CONFIG_ATMEL=m +# CONFIG_PCI_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_HOSTAP is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +# CONFIG_PPP_MPPE is not set +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# + +# +# Video decoders +# + +# +# Video and audio decoders +# + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# + +# +# Video improvement chips +# +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_STRADIS is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +# CONFIG_HID is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_GPIO is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SAMPLES is not set +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_BLKCIPHER=m +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 57e34cafa497..15e01aec37fd 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -49,3 +49,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o +obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c new file mode 100644 index 000000000000..75b90dcb7a09 --- /dev/null +++ b/arch/mips/pci/fixup-rc32434.c @@ -0,0 +1,69 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#include + +static int __devinitdata irq_map[2][12] = { + {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1}, + {0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3} +}; + +int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq = 0; + + if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) + irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)]; + + return irq + GROUP4_IRQ_BASE + 4; +} + +static void rc32434_pci_early_fixup(struct pci_dev *dev) +{ + if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) { + /* disable prefetched memory range */ + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0); + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10); + + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4); + } +} + +/* + * The fixup applies to both the IDT and VIA devices present on the board + */ +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, rc32434_pci_early_fixup); + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c new file mode 100644 index 000000000000..d1f8fa210ca1 --- /dev/null +++ b/arch/mips/pci/ops-rc32434.c @@ -0,0 +1,207 @@ +/* + * BRIEF MODULE DESCRIPTION + * pci_ops for IDT EB434 board + * + * Copyright 2004 IDT Inc. (rischelp@idt.com) + * Copyright 2006 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + + +#define PCI_CFG_SET(bus, slot, func, off) \ + (rc32434_pci->pcicfga = (0x80000000 | \ + ((bus) << 16) | ((slot)<<11) | \ + ((func)<<8) | (off))) + +static inline int config_access(unsigned char access_type, + struct pci_bus *bus, unsigned int devfn, + unsigned char where, u32 *data) +{ + unsigned int slot = PCI_SLOT(devfn); + u8 func = PCI_FUNC(devfn); + + /* Setup address */ + PCI_CFG_SET(bus->number, slot, func, where); + rc32434_sync(); + + if (access_type == PCI_ACCESS_WRITE) + rc32434_pci->pcicfgd = *data; + else + *data = rc32434_pci->pcicfgd; + + rc32434_sync(); + + return 0; +} + + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int read_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 *val) +{ + u32 data; + int ret; + + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + *val = (data >> ((where & 3) << 3)) & 0xff; + return ret; +} + +static int read_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 *val) +{ + u32 data; + int ret; + + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + *val = (data >> ((where & 3) << 3)) & 0xffff; + return ret; +} + +static int read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 *val) +{ + int ret; + int delay = 1; + + /* + * Don't scan too far, else there will be errors with plugged in + * daughterboard (rb564). + */ + if (bus->number == 0 && PCI_SLOT(devfn) > 21) + return 0; + +retry: + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); + + /* + * Certain devices react delayed at device scan time, this + * gives them time to settle + */ + if (where == PCI_VENDOR_ID) { + if (ret == 0xffffffff || ret == 0x00000000 || + ret == 0x0000ffff || ret == 0xffff0000) { + if (delay > 4) + return 0; + delay *= 2; + msleep(delay); + goto retry; + } + } + + return ret; +} + +static int +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, + u8 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + + +static int +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, + u16 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + + return PCIBIOS_SUCCESSFUL; +} + + +static int +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, + u32 val) +{ + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + switch (size) { + case 1: + return read_config_byte(bus, devfn, where, (u8 *) val); + case 2: + return read_config_word(bus, devfn, where, (u16 *) val); + default: + return read_config_dword(bus, devfn, where, val); + } +} + +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + switch (size) { + case 1: + return write_config_byte(bus, devfn, where, (u8) val); + case 2: + return write_config_word(bus, devfn, where, (u16) val); + default: + return write_config_dword(bus, devfn, where, val); + } +} + +struct pci_ops rc32434_pci_ops = { + .read = pci_config_read, + .write = pci_config_write, +}; diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c new file mode 100644 index 000000000000..1c2821e2f494 --- /dev/null +++ b/arch/mips/pci/pci-rc32434.c @@ -0,0 +1,221 @@ +/* + * BRIEF MODULE DESCRIPTION + * PCI initialization for IDT EB434 board + * + * Copyright 2004 IDT Inc. (rischelp@idt.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +/* define an unsigned array for the PCI registers */ +static unsigned int korina_cnfg_regs[25] = { + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4, + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8, + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12, + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16, + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20, + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24 +}; +static struct resource rc32434_res_pci_mem1; +static struct resource rc32434_res_pci_mem2; + +static struct resource rc32434_res_pci_mem1 = { + .name = "PCI MEM1", + .start = 0x50000000, + .end = 0x5FFFFFFF, + .flags = IORESOURCE_MEM, + .parent = &rc32434_res_pci_mem1, + .sibling = NULL, + .child = &rc32434_res_pci_mem2 +}; + +static struct resource rc32434_res_pci_mem2 = { + .name = "PCI Mem2", + .start = 0x60000000, + .end = 0x6FFFFFFF, + .flags = IORESOURCE_MEM, + .parent = &rc32434_res_pci_mem1, + .sibling = NULL, + .child = NULL +}; + +static struct resource rc32434_res_pci_io1 = { + .name = "PCI I/O1", + .start = 0x18800000, + .end = 0x188FFFFF, + .flags = IORESOURCE_IO, +}; + +extern struct pci_ops rc32434_pci_ops; + +#define PCI_MEM1_START PCI_ADDR_START +#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1) +#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN) +#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1) +#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)) +#define PCI_IO1_END \ + (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1) +#define PCI_IO2_START \ + (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN) +#define PCI_IO2_END \ + (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1) + +struct pci_controller rc32434_controller2; + +struct pci_controller rc32434_controller = { + .pci_ops = &rc32434_pci_ops, + .mem_resource = &rc32434_res_pci_mem1, + .io_resource = &rc32434_res_pci_io1, + .mem_offset = 0, + .io_offset = 0, + +}; + +#ifdef __MIPSEB__ +#define PCI_ENDIAN_FLAG PCILBAC_sb_m +#else +#define PCI_ENDIAN_FLAG 0 +#endif + +static int __init rc32434_pcibridge_init(void) +{ + unsigned int pcicvalue, pcicdata = 0; + unsigned int dummyread, pcicntlval; + int loopCount; + unsigned int pci_config_addr; + + pcicvalue = rc32434_pci->pcic; + pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN; + if (!((pcicvalue == PCIM_H_EA) || + (pcicvalue == PCIM_H_IA_FIX) || + (pcicvalue == PCIM_H_IA_RR))) { + pr_err(KERN_ERR "PCI init error!!!\n"); + /* Not in Host Mode, return ERROR */ + return -1; + } + /* Enables the Idle Grant mode, Arbiter Parking */ + pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN); + rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */ + /* Zero out the PCI status & PCI Status Mask */ + for (;;) { + pcicdata = rc32434_pci->pcis; + if (!(pcicdata & PCI_STAT_RIP)) + break; + } + + rc32434_pci->pcis = 0; + rc32434_pci->pcism = 0xFFFFFFFF; + /* Zero out the PCI decoupled registers */ + rc32434_pci->pcidac = 0; /* + * disable PCI decoupled accesses at + * initialization + */ + rc32434_pci->pcidas = 0; /* clear the status */ + rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */ + /* Mask PCI Messaging Interrupts */ + rc32434_pci_msg->pciiic = 0; + rc32434_pci_msg->pciiim = 0xFFFFFFFF; + rc32434_pci_msg->pciioic = 0; + rc32434_pci_msg->pciioim = 0; + + + /* Setup PCILB0 as Memory Window */ + rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START); + + /* setup the PCI map address as same as the local address */ + + rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START); + + + /* Setup PCILBA1 as MEM */ + rc32434_pci->pcilba[0].control = + (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); + dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */ + rc32434_pci->pcilba[1].address = 0x60000000; + rc32434_pci->pcilba[1].mapping = 0x60000000; + + /* setup PCILBA2 as IO Window */ + rc32434_pci->pcilba[1].control = + (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); + dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */ + rc32434_pci->pcilba[2].address = 0x18C00000; + rc32434_pci->pcilba[2].mapping = 0x18FFFFFF; + + /* setup PCILBA2 as IO Window */ + rc32434_pci->pcilba[2].control = + (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); + dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */ + + /* Setup PCILBA3 as IO Window */ + rc32434_pci->pcilba[3].address = 0x18800000; + rc32434_pci->pcilba[3].mapping = 0x18800000; + rc32434_pci->pcilba[3].control = + ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) | + PCI_ENDIAN_FLAG); + dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */ + + pci_config_addr = (unsigned int) (0x80000004); + for (loopCount = 0; loopCount < 24; loopCount++) { + rc32434_pci->pcicfga = pci_config_addr; + dummyread = rc32434_pci->pcicfga; + rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount]; + dummyread = rc32434_pci->pcicfgd; + pci_config_addr += 4; + } + rc32434_pci->pcitc = + (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) | + ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT); + + pcicntlval = rc32434_pci->pcic; + pcicntlval &= ~PCI_CTL_TNR; + rc32434_pci->pcic = pcicntlval; + pcicntlval = rc32434_pci->pcic; + + return 0; +} + +static int __init rc32434_pci_init(void) +{ + pr_info("PCI: Initializing PCI\n"); + + ioport_resource.start = rc32434_res_pci_io1.start; + ioport_resource.end = rc32434_res_pci_io1.end; + + rc32434_pcibridge_init(); + + register_pci_controller(&rc32434_controller); + rc32434_sync(); + + return 0; +} + +arch_initcall(rc32434_pci_init); diff --git a/arch/mips/rb532/Makefile b/arch/mips/rb532/Makefile new file mode 100644 index 000000000000..8f0b6b6a1625 --- /dev/null +++ b/arch/mips/rb532/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the RB532 board specific parts of the kernel +# + +obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c new file mode 100644 index 000000000000..44fb0a62877f --- /dev/null +++ b/arch/mips/rb532/devices.c @@ -0,0 +1,331 @@ +/* + * RouterBoard 500 Platform devices + * + * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2007 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) +#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) +#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) +#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) + +#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET) +#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET) + +/* NAND definitions */ +#define GPIO_RDY (1 << 0x08) +#define GPIO_WPX (1 << 0x09) +#define GPIO_ALE (1 << 0x0a) +#define GPIO_CLE (1 << 0x0b) + +extern char *board_type; + +static struct resource korina_dev0_res[] = { + { + .name = "korina_regs", + .start = ETH0_BASE_ADDR, + .end = ETH0_BASE_ADDR + sizeof(struct eth_regs), + .flags = IORESOURCE_MEM, + }, { + .name = "korina_rx", + .start = ETH0_DMA_RX_IRQ, + .end = ETH0_DMA_RX_IRQ, + .flags = IORESOURCE_IRQ + }, { + .name = "korina_tx", + .start = ETH0_DMA_TX_IRQ, + .end = ETH0_DMA_TX_IRQ, + .flags = IORESOURCE_IRQ + }, { + .name = "korina_ovr", + .start = ETH0_RX_OVR_IRQ, + .end = ETH0_RX_OVR_IRQ, + .flags = IORESOURCE_IRQ + }, { + .name = "korina_und", + .start = ETH0_TX_UND_IRQ, + .end = ETH0_TX_UND_IRQ, + .flags = IORESOURCE_IRQ + }, { + .name = "korina_dma_rx", + .start = ETH0_RX_DMA_ADDR, + .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "korina_dma_tx", + .start = ETH0_TX_DMA_ADDR, + .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct korina_device korina_dev0_data = { + .name = "korina0", + .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee} +}; + +static struct platform_device korina_dev0 = { + .id = 0, + .name = "korina", + .dev.platform_data = &korina_dev0_data, + .resource = korina_dev0_res, + .num_resources = ARRAY_SIZE(korina_dev0_res), +}; + +#define CF_GPIO_NUM 13 + +static struct resource cf_slot0_res[] = { + { + .name = "cf_membase", + .flags = IORESOURCE_MEM + }, { + .name = "cf_irq", + .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */ + .end = (8 + 4 * 32 + CF_GPIO_NUM), + .flags = IORESOURCE_IRQ + } +}; + +static struct cf_device cf_slot0_data = { + .gpio_pin = 13 +}; + +static struct platform_device cf_slot0 = { + .id = 0, + .name = "pata-rb532-cf", + .dev.platform_data = &cf_slot0_data, + .resource = cf_slot0_res, + .num_resources = ARRAY_SIZE(cf_slot0_res), +}; + +/* Resources and device for NAND */ +static int rb532_dev_ready(struct mtd_info *mtd) +{ + return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; +} + +static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *chip = mtd->priv; + unsigned char orbits, nandbits; + + if (ctrl & NAND_CTRL_CHANGE) { + orbits = (ctrl & NAND_CLE) << 1; + orbits |= (ctrl & NAND_ALE) >> 1; + + nandbits = (~ctrl & NAND_CLE) << 1; + nandbits |= (~ctrl & NAND_ALE) >> 1; + + set_latch_u5(orbits, nandbits); + } + if (cmd != NAND_CMD_NONE) + writeb(cmd, chip->IO_ADDR_W); +} + +static struct resource nand_slot0_res[] = { + [0] = { + .name = "nand_membase", + .flags = IORESOURCE_MEM + } +}; + +static struct platform_nand_data rb532_nand_data = { + .ctrl.dev_ready = rb532_dev_ready, + .ctrl.cmd_ctrl = rb532_cmd_ctrl, +}; + +static struct platform_device nand_slot0 = { + .name = "gen_nand", + .id = -1, + .resource = nand_slot0_res, + .num_resources = ARRAY_SIZE(nand_slot0_res), + .dev.platform_data = &rb532_nand_data, +}; + +static struct mtd_partition rb532_partition_info[] = { + { + .name = "Routerboard NAND boot", + .offset = 0, + .size = 4 * 1024 * 1024, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct platform_device rb532_led = { + .name = "rb532-led", + .id = 0, +}; + +static struct gpio_keys_button rb532_gpio_btn[] = { + { + .gpio = 1, + .code = BTN_0, + .desc = "S1", + .active_low = 1, + } +}; + +static struct gpio_keys_platform_data rb532_gpio_btn_data = { + .buttons = rb532_gpio_btn, + .nbuttons = ARRAY_SIZE(rb532_gpio_btn), +}; + +static struct platform_device rb532_button = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &rb532_gpio_btn_data, + } +}; + +static struct resource rb532_wdt_res[] = { + { + .name = "rb532_wdt_res", + .start = INTEG0_BASE_ADDR, + .end = INTEG0_BASE_ADDR + sizeof(struct integ), + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device rb532_wdt = { + .name = "rc32434_wdt", + .id = -1, + .resource = rb532_wdt_res, + .num_resources = ARRAY_SIZE(rb532_wdt_res), +}; + +static struct platform_device *rb532_devs[] = { + &korina_dev0, + &nand_slot0, + &cf_slot0, + &rb532_led, + &rb532_button, + &rb532_wdt +}; + +static void __init parse_mac_addr(char *macstr) +{ + int i, j; + unsigned char result, value; + + for (i = 0; i < 6; i++) { + result = 0; + + if (i != 5 && *(macstr + 2) != ':') + return; + + for (j = 0; j < 2; j++) { + if (isxdigit(*macstr) + && (value = + isdigit(*macstr) ? *macstr - + '0' : toupper(*macstr) - 'A' + 10) < 16) { + result = result * 16 + value; + macstr++; + } else + return; + } + + macstr++; + korina_dev0_data.mac[i] = result; + } +} + + +/* DEVICE CONTROLLER 1 */ +#define CFG_DC_DEV1 ((void *)0xb8010010) +#define CFG_DC_DEV2 ((void *)0xb8010020) +#define CFG_DC_DEVBASE 0x0 +#define CFG_DC_DEVMASK 0x4 +#define CFG_DC_DEVC 0x8 +#define CFG_DC_DEVTC 0xC + +/* NAND definitions */ +#define NAND_CHIP_DELAY 25 + +static void __init rb532_nand_setup(void) +{ + switch (mips_machtype) { + case MACH_MIKROTIK_RB532A: + set_latch_u5(LO_FOFF | LO_CEX, + LO_ULED | LO_ALE | LO_CLE | LO_WPX); + break; + default: + set_latch_u5(LO_WPX | LO_FOFF | LO_CEX, + LO_ULED | LO_ALE | LO_CLE); + break; + } + + /* Setup NAND specific settings */ + rb532_nand_data.chip.nr_chips = 1; + rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info); + rb532_nand_data.chip.partitions = rb532_partition_info; + rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY; + rb532_nand_data.chip.options = NAND_NO_AUTOINCR; +} + + +static int __init plat_setup_devices(void) +{ + /* Look for the CF card reader */ + if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK)) + rb532_devs[1] = NULL; + else { + cf_slot0_res[0].start = + readl(CFG_DC_DEV1 + CFG_DC_DEVBASE); + cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; + } + + /* Read the NAND resources from the device controller */ + nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE); + nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; + + /* Initialise the NAND device */ + rb532_nand_setup(); + + return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs)); +} + +static int __init setup_kmac(char *s) +{ + printk(KERN_INFO "korina mac = %s\n", s); + parse_mac_addr(s); + return 0; +} + +__setup("kmac=", setup_kmac); + +arch_initcall(plat_setup_devices); diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c new file mode 100644 index 000000000000..b2fe82dba0a5 --- /dev/null +++ b/arch/mips/rb532/gpio.c @@ -0,0 +1,220 @@ +/* + * Miscellaneous functions for IDT EB434 board + * + * Copyright 2004 IDT Inc. (rischelp@idt.com) + * Copyright 2006 Phil Sutter + * Copyright 2007 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +struct rb532_gpio_reg __iomem *rb532_gpio_reg0; +EXPORT_SYMBOL(rb532_gpio_reg0); + +struct mpmc_device dev3; + +static struct resource rb532_gpio_reg0_res[] = { + { + .name = "gpio_reg0", + .start = (u32)(IDT434_REG_BASE + GPIOBASE), + .end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)), + .flags = IORESOURCE_MEM, + } +}; + +static struct resource rb532_dev3_ctl_res[] = { + { + .name = "dev3_ctl", + .start = (u32)(IDT434_REG_BASE + DEV3BASE), + .end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)), + .flags = IORESOURCE_MEM, + } +}; + +void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val) +{ + unsigned flags, data; + unsigned i = 0; + + spin_lock_irqsave(&dev3.lock, flags); + + data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs); + for (i = 0; i != len; ++i) { + if (val & (1 << i)) + data |= (1 << (i + bit)); + else + data &= ~(1 << (i + bit)); + } + writel(data, (IDT434_REG_BASE + reg_offs)); + + spin_unlock_irqrestore(&dev3.lock, flags); +} +EXPORT_SYMBOL(set_434_reg); + +unsigned get_434_reg(unsigned reg_offs) +{ + return readl(IDT434_REG_BASE + reg_offs); +} +EXPORT_SYMBOL(get_434_reg); + +void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) +{ + unsigned flags; + + spin_lock_irqsave(&dev3.lock, flags); + + dev3.state = (dev3.state | or_mask) & ~nand_mask; + writel(dev3.state, &dev3.base); + + spin_unlock_irqrestore(&dev3.lock, flags); +} +EXPORT_SYMBOL(set_latch_u5); + +unsigned char get_latch_u5(void) +{ + return dev3.state; +} +EXPORT_SYMBOL(get_latch_u5); + +int rb532_gpio_get_value(unsigned gpio) +{ + return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio); +} +EXPORT_SYMBOL(rb532_gpio_get_value); + +void rb532_gpio_set_value(unsigned gpio, int value) +{ + unsigned tmp; + + tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio); + if (value) + tmp |= 1 << gpio; + + writel(tmp, (void *)&rb532_gpio_reg0->gpiod); +} +EXPORT_SYMBOL(rb532_gpio_set_value); + +int rb532_gpio_direction_input(unsigned gpio) +{ + writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio), + (void *)&rb532_gpio_reg0->gpiocfg); + + return 0; +} +EXPORT_SYMBOL(rb532_gpio_direction_input); + +int rb532_gpio_direction_output(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); + writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio), + (void *)&rb532_gpio_reg0->gpiocfg); + + return 0; +} +EXPORT_SYMBOL(rb532_gpio_direction_output); + +void rb532_gpio_set_int_level(unsigned gpio, int value) +{ + unsigned tmp; + + tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio); + if (value) + tmp |= 1 << gpio; + writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel); +} +EXPORT_SYMBOL(rb532_gpio_set_int_level); + +int rb532_gpio_get_int_level(unsigned gpio) +{ + return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio); +} +EXPORT_SYMBOL(rb532_gpio_get_int_level); + +void rb532_gpio_set_int_status(unsigned gpio, int value) +{ + unsigned tmp; + + tmp = readl(&rb532_gpio_reg0->gpioistat); + if (value) + tmp |= 1 << gpio; + writel(tmp, (void *)&rb532_gpio_reg0->gpioistat); +} +EXPORT_SYMBOL(rb532_gpio_set_int_status); + +int rb532_gpio_get_int_status(unsigned gpio) +{ + return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio); +} +EXPORT_SYMBOL(rb532_gpio_get_int_status); + +void rb532_gpio_set_func(unsigned gpio, int value) +{ + unsigned tmp; + + tmp = readl(&rb532_gpio_reg0->gpiofunc); + if (value) + tmp |= 1 << gpio; + writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc); +} +EXPORT_SYMBOL(rb532_gpio_set_func); + +int rb532_gpio_get_func(unsigned gpio) +{ + return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio); +} +EXPORT_SYMBOL(rb532_gpio_get_func); + +int __init rb532_gpio_init(void) +{ + rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start, + rb532_gpio_reg0_res[0].end - + rb532_gpio_reg0_res[0].start); + + if (!rb532_gpio_reg0) { + printk(KERN_ERR "rb532: cannot remap GPIO register 0\n"); + return -ENXIO; + } + + dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, + rb532_dev3_ctl_res[0].end - + rb532_dev3_ctl_res[0].start); + + if (!dev3.base) { + printk(KERN_ERR "rb532: cannot remap device controller 3\n"); + return -ENXIO; + } + + return 0; +} +arch_initcall(rb532_gpio_init); diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c new file mode 100644 index 000000000000..c0d0f950caf2 --- /dev/null +++ b/arch/mips/rb532/irq.c @@ -0,0 +1,209 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright 2002 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or source@mvista.com + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +struct intr_group { + u32 mask; /* mask of valid bits in pending/mask registers */ + volatile u32 *base_addr; +}; + +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32) + +#if (NR_IRQS < RC32434_NR_IRQS) +#error Too little irqs defined. Did you override ? +#endif + +static const struct intr_group intr_group[NUM_INTR_GROUPS] = { + { + .mask = 0x0000efff, + .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)}, + { + .mask = 0x00001fff, + .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)}, + { + .mask = 0x00000007, + .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)}, + { + .mask = 0x0003ffff, + .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)}, + { + .mask = 0xffffffff, + .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)} +}; + +#define READ_PEND(base) (*(base)) +#define READ_MASK(base) (*(base + 2)) +#define WRITE_MASK(base, val) (*(base + 2) = (val)) + +static inline int irq_to_group(unsigned int irq_nr) +{ + return (irq_nr - GROUP0_IRQ_BASE) >> 5; +} + +static inline int group_to_ip(unsigned int group) +{ + return group + 2; +} + +static inline void enable_local_irq(unsigned int ip) +{ + int ipnum = 0x100 << ip; + + set_c0_status(ipnum); +} + +static inline void disable_local_irq(unsigned int ip) +{ + int ipnum = 0x100 << ip; + + clear_c0_status(ipnum); +} + +static inline void ack_local_irq(unsigned int ip) +{ + int ipnum = 0x100 << ip; + + clear_c0_cause(ipnum); +} + +static void rb532_enable_irq(unsigned int irq_nr) +{ + int ip = irq_nr - GROUP0_IRQ_BASE; + unsigned int group, intr_bit; + volatile unsigned int *addr; + + if (ip < 0) + enable_local_irq(irq_nr); + else { + group = ip >> 5; + + ip &= (1 << 5) - 1; + intr_bit = 1 << ip; + + enable_local_irq(group_to_ip(group)); + + addr = intr_group[group].base_addr; + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit); + } +} + +static void rb532_disable_irq(unsigned int irq_nr) +{ + int ip = irq_nr - GROUP0_IRQ_BASE; + unsigned int group, intr_bit, mask; + volatile unsigned int *addr; + + if (ip < 0) { + disable_local_irq(irq_nr); + } else { + group = ip >> 5; + + ip &= (1 << 5) - 1; + intr_bit = 1 << ip; + addr = intr_group[group].base_addr; + mask = READ_MASK(addr); + mask |= intr_bit; + WRITE_MASK(addr, mask); + + /* + * if there are no more interrupts enabled in this + * group, disable corresponding IP + */ + if (mask == intr_group[group].mask) + disable_local_irq(group_to_ip(group)); + } +} + +static void rb532_mask_and_ack_irq(unsigned int irq_nr) +{ + rb532_disable_irq(irq_nr); + ack_local_irq(group_to_ip(irq_to_group(irq_nr))); +} + +static struct irq_chip rc32434_irq_type = { + .name = "RB532", + .ack = rb532_disable_irq, + .mask = rb532_disable_irq, + .mask_ack = rb532_mask_and_ack_irq, + .unmask = rb532_enable_irq, +}; + +void __init arch_init_irq(void) +{ + int i; + + pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS); + + for (i = 0; i < RC32434_NR_IRQS; i++) + set_irq_chip_and_handler(i, &rc32434_irq_type, + handle_level_irq); +} + +/* Main Interrupt dispatcher */ +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int ip, pend, group; + volatile unsigned int *addr; + unsigned int cp0_cause = read_c0_cause() & read_c0_status(); + + if (cp0_cause & CAUSEF_IP7) { + do_IRQ(7); + } else { + ip = (cp0_cause & 0x7c00); + if (ip) { + group = 21 + (fls(ip) - 32); + + addr = intr_group[group].base_addr; + + pend = READ_PEND(addr); + pend &= ~READ_MASK(addr); /* only unmasked interrupts */ + pend = 39 + (fls(pend) - 32); + do_IRQ((group << 5) + pend); + } + } +} diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c new file mode 100644 index 000000000000..1bc0af8febf4 --- /dev/null +++ b/arch/mips/rb532/prom.c @@ -0,0 +1,158 @@ +/* + * RouterBoard 500 specific prom routines + * + * Copyright (C) 2003, Peter Sadik + * Copyright (C) 2005-2006, P.Christeas + * Copyright (C) 2007, Gabor Juhos + * Felix Fietkau + * Florian Fainelli + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +extern void __init setup_serial_port(void); + +unsigned int idt_cpu_freq = 132000000; +EXPORT_SYMBOL(idt_cpu_freq); +unsigned int gpio_bootup_state; +EXPORT_SYMBOL(gpio_bootup_state); + +static struct resource ddr_reg[] = { + { + .name = "ddr-reg", + .start = DDR0_PHYS_ADDR, + .end = DDR0_PHYS_ADDR + sizeof(struct ddr_ram), + .flags = IORESOURCE_MEM, + } +}; + +void __init prom_free_prom_memory(void) +{ + /* No prom memory to free */ +} + +static inline int match_tag(char *arg, const char *tag) +{ + return strncmp(arg, tag, strlen(tag)) == 0; +} + +static inline unsigned long tag2ul(char *arg, const char *tag) +{ + char *num; + + num = arg + strlen(tag); + return simple_strtoul(num, 0, 10); +} + +void __init prom_setup_cmdline(void) +{ + char cmd_line[CL_SIZE]; + char *cp, *board; + int prom_argc; + char **prom_argv, **prom_envp; + int i; + + prom_argc = fw_arg0; + prom_argv = (char **) fw_arg1; + prom_envp = (char **) fw_arg2; + + cp = cmd_line; + /* Note: it is common that parameters start + * at argv[1] and not argv[0], + * however, our elf loader starts at [0] */ + for (i = 0; i < prom_argc; i++) { + if (match_tag(prom_argv[i], FREQ_TAG)) { + idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG); + continue; + } +#ifdef IGNORE_CMDLINE_MEM + /* parses out the "mem=xx" arg */ + if (match_tag(prom_argv[i], MEM_TAG)) + continue; +#endif + if (i > 0) + *(cp++) = ' '; + if (match_tag(prom_argv[i], BOARD_TAG)) { + board = prom_argv[i] + strlen(BOARD_TAG); + + if (match_tag(board, BOARD_RB532A)) + mips_machtype = MACH_MIKROTIK_RB532A; + else + mips_machtype = MACH_MIKROTIK_RB532; + } + + if (match_tag(prom_argv[i], GPIO_TAG)) + gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG); + + strcpy(cp, prom_argv[i]); + cp += strlen(prom_argv[i]); + } + *(cp++) = ' '; + + i = strlen(arcs_cmdline); + if (i > 0) { + *(cp++) = ' '; + strcpy(cp, arcs_cmdline); + cp += strlen(arcs_cmdline); + } + if (gpio_bootup_state & 0x02) + strcpy(cp, GPIO_INIT_NOBUTTON); + else + strcpy(cp, GPIO_INIT_BUTTON); + + cmd_line[CL_SIZE-1] = '\0'; + + strcpy(arcs_cmdline, cmd_line); +} + +void __init prom_init(void) +{ + struct ddr_ram __iomem *ddr; + phys_t memsize; + phys_t ddrbase; + + ddr = ioremap_nocache(ddr_reg[0].start, + ddr_reg[0].end - ddr_reg[0].start); + + if (!ddr) { + printk(KERN_ERR "Unable to remap DDR register\n"); + return; + } + + ddrbase = (phys_t)&ddr->ddrbase; + memsize = (phys_t)&ddr->ddrmask; + memsize = 0 - memsize; + + prom_setup_cmdline(); + + /* give all RAM to boot allocator, + * except for the first 0x400 and the last 0x200 bytes */ + add_memory_region(ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM); +} diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c new file mode 100644 index 000000000000..1a05b5ddee09 --- /dev/null +++ b/arch/mips/rb532/serial.c @@ -0,0 +1,53 @@ +/* + * BRIEF MODULE DESCRIPTION + * Serial port initialisation. + * + * Copyright 2004 IDT Inc. (rischelp@idt.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#include +#include + +extern unsigned int idt_cpu_freq; + +static struct uart_port rb532_uart = { + .type = PORT_16550A, + .line = 0, + .irq = RC32434_UART0_IRQ, + .iotype = UPIO_MEM, + .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE), + .regshift = 2 +}; + +int __init setup_serial_port(void) +{ + rb532_uart.uartclk = idt_cpu_freq; + + return early_serial_setup(&rb532_uart); +} +arch_initcall(setup_serial_port); diff --git a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c new file mode 100644 index 000000000000..7aafa95ac20b --- /dev/null +++ b/arch/mips/rb532/setup.c @@ -0,0 +1,79 @@ +/* + * setup.c - boot time setup code + */ + +#include + +#include +#include +#include +#include + +#include +#include + +struct pci_reg __iomem *pci_reg; +EXPORT_SYMBOL(pci_reg); + +static struct resource pci0_res[] = { + { + .name = "pci_reg0", + .start = PCI0_BASE_ADDR, + .end = PCI0_BASE_ADDR + sizeof(struct pci_reg), + .flags = IORESOURCE_MEM, + } +}; + +static void rb_machine_restart(char *command) +{ + /* just jump to the reset vector */ + writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST)); + ((void (*)(void)) KSEG1ADDR(0x1FC00000u))(); +} + +static void rb_machine_halt(void) +{ + for (;;) + continue; +} + +void __init plat_mem_setup(void) +{ + u32 val; + + _machine_restart = rb_machine_restart; + _machine_halt = rb_machine_halt; + pm_power_off = rb_machine_halt; + + set_io_port_base(KSEG1); + + pci_reg = ioremap_nocache(pci0_res[0].start, + pci0_res[0].end - pci0_res[0].start); + if (!pci_reg) { + printk(KERN_ERR "Could not remap PCI registers\n"); + return; + } + + val = __raw_readl(&pci_reg->pcic); + val &= 0xFFFFFF7; + __raw_writel(val, (void *)&pci_reg->pcic); + +#ifdef CONFIG_PCI + /* Enable PCI interrupts in EPLD Mask register */ + *epld_mask = 0x0; + *(epld_mask + 1) = 0x0; +#endif + write_c0_wired(0); +} + +const char *get_system_type(void) +{ + switch (mips_machtype) { + case MACH_MIKROTIK_RB532A: + return "Mikrotik RB532A"; + break; + default: + return "Mikrotik RB532"; + break; + } +} diff --git a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c new file mode 100644 index 000000000000..db74edf8cefb --- /dev/null +++ b/arch/mips/rb532/time.c @@ -0,0 +1,67 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Setting up the clock on the MIPS boards. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +extern unsigned int idt_cpu_freq; + +/* + * Figure out the r4k offset, the amount to increment the compare + * register for each time tick. There is no RTC available. + * + * The RC32434 counts at half the CPU *core* speed. + */ +static unsigned long __init cal_r4koff(void) +{ + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2; + + return mips_hpt_frequency / HZ; +} + +void __init plat_time_init(void) +{ + unsigned int est_freq, flags; + unsigned long r4k_offset; + + local_irq_save(flags); + + printk(KERN_INFO "calculating r4koff... "); + r4k_offset = cal_r4koff(); + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); + + est_freq = 2 * r4k_offset * HZ; + est_freq += 5000; /* round */ + est_freq -= est_freq % 10000; + printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, + (est_freq % 1000000) * 100 / 1000000); + local_irq_restore(flags); +} diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index d39e143b4a3c..610fe3af7a03 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -51,6 +51,12 @@ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ +/* + * Valid machtype for group Mikrotik + */ +#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ +#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ + #define CL_SIZE COMMAND_LINE_SIZE extern char *system_type; diff --git a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h new file mode 100644 index 000000000000..f3bc7efa2608 --- /dev/null +++ b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h @@ -0,0 +1,81 @@ +/* + * IDT RC32434 specific CPU feature overrides + * + * Copyright (C) 2008 Florian Fainelli + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ +#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H + +/* + * The IDT RC32434 SOC has a built-in MIPS 4Kc core. + */ +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_vtag_icache 0 +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +/* #define cpu_has_pindexed_dcache ? */ + +/* #define cpu_icache_snoops_remote_store ? */ + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +/* #define cpu_has_nofpuex ? */ +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 16 +#define cpu_icache_line_size() 16 + +#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-rc32434/ddr.h b/include/asm-mips/mach-rc32434/ddr.h new file mode 100644 index 000000000000..291e2cf9dde0 --- /dev/null +++ b/include/asm-mips/mach-rc32434/ddr.h @@ -0,0 +1,141 @@ +/* + * Definitions for the DDR registers + * + * Copyright 2002 Ryan Holm + * Copyright 2008 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef _ASM_RC32434_DDR_H_ +#define _ASM_RC32434_DDR_H_ + +#include + +/* DDR register structure */ +struct ddr_ram { + u32 ddrbase; + u32 ddrmask; + u32 res1; + u32 res2; + u32 ddrc; + u32 ddrabase; + u32 ddramask; + u32 ddramap; + u32 ddrcust; + u32 ddrrdc; + u32 ddrspare; +}; + +#define DDR0_PHYS_ADDR 0x18018000 + +/* DDR banks masks */ +#define DDR_MASK 0xffff0000 +#define DDR0_BASE_MSK DDR_MASK +#define DDR1_BASE_MSK DDR_MASK + +/* DDR bank0 registers */ +#define RC32434_DDR0_ATA_BIT 5 +#define RC32434_DDR0_ATA_MSK 0x000000E0 +#define RC32434_DDR0_DBW_BIT 8 +#define RC32434_DDR0_DBW_MSK 0x00000100 +#define RC32434_DDR0_WR_BIT 9 +#define RC32434_DDR0_WR_MSK 0x00000600 +#define RC32434_DDR0_PS_BIT 11 +#define RC32434_DDR0_PS_MSK 0x00001800 +#define RC32434_DDR0_DTYPE_BIT 13 +#define RC32434_DDR0_DTYPE_MSK 0x0000e000 +#define RC32434_DDR0_RFC_BIT 16 +#define RC32434_DDR0_RFC_MSK 0x000f0000 +#define RC32434_DDR0_RP_BIT 20 +#define RC32434_DDR0_RP_MSK 0x00300000 +#define RC32434_DDR0_AP_BIT 22 +#define RC32434_DDR0_AP_MSK 0x00400000 +#define RC32434_DDR0_RCD_BIT 23 +#define RC32434_DDR0_RCD_MSK 0x01800000 +#define RC32434_DDR0_CL_BIT 25 +#define RC32434_DDR0_CL_MSK 0x06000000 +#define RC32434_DDR0_DBM_BIT 27 +#define RC32434_DDR0_DBM_MSK 0x08000000 +#define RC32434_DDR0_SDS_BIT 28 +#define RC32434_DDR0_SDS_MSK 0x10000000 +#define RC32434_DDR0_ATP_BIT 29 +#define RC32434_DDR0_ATP_MSK 0x60000000 +#define RC32434_DDR0_RE_BIT 31 +#define RC32434_DDR0_RE_MSK 0x80000000 + +/* DDR bank C registers */ +#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x) +#define RC32434_DDRC_CES_BIT 0 +#define RC32434_DDRC_ACE_BIT 1 + +/* Custom DDR bank registers */ +#define RC32434_DCST_MSK(x) BIT_TO_MASK(x) +#define RC32434_DCST_CS_BIT 0 +#define RC32434_DCST_CS_MSK 0x00000003 +#define RC32434_DCST_WE_BIT 2 +#define RC32434_DCST_RAS_BIT 3 +#define RC32434_DCST_CAS_BIT 4 +#define RC32434_DSCT_CKE_BIT 5 +#define RC32434_DSCT_BA_BIT 6 +#define RC32434_DSCT_BA_MSK 0x000000c0 + +/* DDR QSC registers */ +#define RC32434_QSC_DM_BIT 0 +#define RC32434_QSC_DM_MSK 0x00000003 +#define RC32434_QSC_DQSBS_BIT 2 +#define RC32434_QSC_DQSBS_MSK 0x000000fc +#define RC32434_QSC_DB_BIT 8 +#define RC32434_QSC_DB_MSK 0x00000100 +#define RC32434_QSC_DBSP_BIT 9 +#define RC32434_QSC_DBSP_MSK 0x01fffe00 +#define RC32434_QSC_BDP_BIT 25 +#define RC32434_QSC_BDP_MSK 0x7e000000 + +/* DDR LLC registers */ +#define RC32434_LLC_EAO_BIT 0 +#define RC32434_LLC_EAO_MSK 0x00000001 +#define RC32434_LLC_EO_BIT 1 +#define RC32434_LLC_EO_MSK 0x0000003e +#define RC32434_LLC_FS_BIT 6 +#define RC32434_LLC_FS_MSK 0x000000c0 +#define RC32434_LLC_AS_BIT 8 +#define RC32434_LLC_AS_MSK 0x00000700 +#define RC32434_LLC_SP_BIT 11 +#define RC32434_LLC_SP_MSK 0x001ff800 + +/* DDR LLFC registers */ +#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x) +#define RC32434_LLFC_MEN_BIT 0 +#define RC32434_LLFC_EAN_BIT 1 +#define RC32434_LLFC_FF_BIT 2 + +/* DDR DLLTA registers */ +#define RC32434_DLLTA_ADDR_BIT 2 +#define RC32434_DLLTA_ADDR_MSK 0xfffffffc + +/* DDR DLLED registers */ +#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x) +#define RC32434_DLLED_DBE_BIT 0 +#define RC32434_DLLED_DTE_BIT 1 + +#endif /* _ASM_RC32434_DDR_H_ */ diff --git a/include/asm-mips/mach-rc32434/dma.h b/include/asm-mips/mach-rc32434/dma.h new file mode 100644 index 000000000000..5f898b5873f7 --- /dev/null +++ b/include/asm-mips/mach-rc32434/dma.h @@ -0,0 +1,103 @@ +/* + * Copyright 2002 Integrated Device Technology, Inc. + * All rights reserved. + * + * DMA register definition. + * + * Author : ryan.holmQVist@idt.com + * Date : 20011005 + */ + +#ifndef __ASM_RC32434_DMA_H +#define __ASM_RC32434_DMA_H + +#include + +#define DMA0_BASE_ADDR 0x18040000 + +/* + * DMA descriptor (in physical memory). + */ + +struct dma_desc { + u32 control; /* Control. use DMAD_* */ + u32 ca; /* Current Address. */ + u32 devcs; /* Device control and status. */ + u32 link; /* Next descriptor in chain. */ +}; + +#define DMA_DESC_SIZ sizeof(struct dma_desc) +#define DMA_DESC_COUNT_BIT 0 +#define DMA_DESC_COUNT_MSK 0x0003ffff +#define DMA_DESC_DS_BIT 20 +#define DMA_DESC_DS_MSK 0x00300000 + +#define DMA_DESC_DEV_CMD_BIT 22 +#define DMA_DESC_DEV_CMD_MSK 0x01c00000 + +/* DMA command sizes */ +#define DMA_DESC_DEV_CMD_BYTE 0 +#define DMA_DESC_DEV_CMD_HLF_WD 1 +#define DMA_DESC_DEV_CMD_WORD 2 +#define DMA_DESC_DEV_CMD_2WORDS 3 +#define DMA_DESC_DEV_CMD_4WORDS 4 +#define DMA_DESC_DEV_CMD_6WORDS 5 +#define DMA_DESC_DEV_CMD_8WORDS 6 +#define DMA_DESC_DEV_CMD_16WORDS 7 + +/* DMA descriptors interrupts */ +#define DMA_DESC_COF (1 << 25) /* Chain on finished */ +#define DMA_DESC_COD (1 << 26) /* Chain on done */ +#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */ +#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */ +#define DMA_DESC_TERM (1 << 29) /* Terminated */ +#define DMA_DESC_DONE (1 << 30) /* Done */ +#define DMA_DESC_FINI (1 << 31) /* Finished */ + +/* + * DMA register (within Internal Register Map). + */ + +struct dma_reg { + u32 dmac; /* Control. */ + u32 dmas; /* Status. */ + u32 dmasm; /* Mask. */ + u32 dmadptr; /* Descriptor pointer. */ + u32 dmandptr; /* Next descriptor pointer. */ +}; + +/* DMA channels specific registers */ +#define DMA_CHAN_RUN_BIT (1 << 0) +#define DMA_CHAN_DONE_BIT (1 << 1) +#define DMA_CHAN_MODE_BIT (1 << 2) +#define DMA_CHAN_MODE_MSK 0x0000000c +#define DMA_CHAN_MODE_AUTO 0 +#define DMA_CHAN_MODE_BURST 1 +#define DMA_CHAN_MODE_XFRT 2 +#define DMA_CHAN_MODE_RSVD 3 +#define DMA_CHAN_ACT_BIT (1 << 4) + +/* DMA status registers */ +#define DMA_STAT_FINI (1 << 0) +#define DMA_STAT_DONE (1 << 1) +#define DMA_STAT_CHAIN (1 << 2) +#define DMA_STAT_ERR (1 << 3) +#define DMA_STAT_HALT (1 << 4) + +/* + * DMA channel definitions + */ + +#define DMA_CHAN_ETH_RCV 0 +#define DMA_CHAN_ETH_XMT 1 +#define DMA_CHAN_MEM_TO_FIFO 2 +#define DMA_CHAN_FIFO_TO_MEM 3 +#define DMA_CHAN_PCI_TO_MEM 4 +#define DMA_CHAN_MEM_TO_PCI 5 +#define DMA_CHAN_COUNT 6 + +struct dma_channel { + struct dma_reg ch[DMA_CHAN_COUNT]; +}; + +#endif /* __ASM_RC32434_DMA_H */ diff --git a/include/asm-mips/mach-rc32434/dma_v.h b/include/asm-mips/mach-rc32434/dma_v.h new file mode 100644 index 000000000000..173a9f9146cd --- /dev/null +++ b/include/asm-mips/mach-rc32434/dma_v.h @@ -0,0 +1,52 @@ +/* + * Copyright 2002 Integrated Device Technology, Inc. + * All rights reserved. + * + * DMA register definition. + * + * Author : ryan.holmQVist@idt.com + * Date : 20011005 + */ + +#ifndef _ASM_RC32434_DMA_V_H_ +#define _ASM_RC32434_DMA_V_H_ + +#include +#include + +#define DMA_CHAN_OFFSET 0x14 +#define IS_DMA_USED(X) (((X) & \ + (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \ + != 0) +#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK) + +#define DMA_HALT_TIMEOUT 500 + +static inline int rc32434_halt_dma(struct dma_reg *ch) +{ + int timeout = 1; + if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { + __raw_writel(0, &ch->dmac); + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) { + if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) { + __raw_writel(0, &ch->dmas); + break; + } + } + } + + return timeout ? 0 : 1; +} + +static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr) +{ + __raw_writel(0, &ch->dmandptr); + __raw_writel(dma_addr, &ch->dmadptr); +} + +static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr) +{ + __raw_writel(dma_addr, &ch->dmandptr); +} + +#endif /* _ASM_RC32434_DMA_V_H_ */ diff --git a/include/asm-mips/mach-rc32434/eth.h b/include/asm-mips/mach-rc32434/eth.h new file mode 100644 index 000000000000..a25cbc56173d --- /dev/null +++ b/include/asm-mips/mach-rc32434/eth.h @@ -0,0 +1,220 @@ +/* + * Definitions for the Ethernet registers + * + * Copyright 2002 Allend Stichter + * Copyright 2008 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __ASM_RC32434_ETH_H +#define __ASM_RC32434_ETH_H + + +#define ETH0_BASE_ADDR 0x18060000 + +struct eth_regs { + u32 ethintfc; + u32 ethfifott; + u32 etharc; + u32 ethhash0; + u32 ethhash1; + u32 ethu0[4]; /* Reserved. */ + u32 ethpfs; + u32 ethmcp; + u32 eth_u1[10]; /* Reserved. */ + u32 ethspare; + u32 eth_u2[42]; /* Reserved. */ + u32 ethsal0; + u32 ethsah0; + u32 ethsal1; + u32 ethsah1; + u32 ethsal2; + u32 ethsah2; + u32 ethsal3; + u32 ethsah3; + u32 ethrbc; + u32 ethrpc; + u32 ethrupc; + u32 ethrfc; + u32 ethtbc; + u32 ethgpf; + u32 eth_u9[50]; /* Reserved. */ + u32 ethmac1; + u32 ethmac2; + u32 ethipgt; + u32 ethipgr; + u32 ethclrt; + u32 ethmaxf; + u32 eth_u10; /* Reserved. */ + u32 ethmtest; + u32 miimcfg; + u32 miimcmd; + u32 miimaddr; + u32 miimwtd; + u32 miimrdd; + u32 miimind; + u32 eth_u11; /* Reserved. */ + u32 eth_u12; /* Reserved. */ + u32 ethcfsa0; + u32 ethcfsa1; + u32 ethcfsa2; +}; + +/* Ethernet interrupt registers */ +#define ETH_INT_FC_EN (1 << 0) +#define ETH_INT_FC_ITS (1 << 1) +#define ETH_INT_FC_RIP (1 << 2) +#define ETH_INT_FC_JAM (1 << 3) +#define ETH_INT_FC_OVR (1 << 4) +#define ETH_INT_FC_UND (1 << 5) +#define ETH_INT_FC_IOC 0x000000c0 + +/* Ethernet FIFO registers */ +#define ETH_FIFI_TT_TTH_BIT 0 +#define ETH_FIFO_TT_TTH 0x0000007f + +/* Ethernet ARC/multicast registers */ +#define ETH_ARC_PRO (1 << 0) +#define ETH_ARC_AM (1 << 1) +#define ETH_ARC_AFM (1 << 2) +#define ETH_ARC_AB (1 << 3) + +/* Ethernet SAL registers */ +#define ETH_SAL_BYTE_5 0x000000ff +#define ETH_SAL_BYTE_4 0x0000ff00 +#define ETH_SAL_BYTE_3 0x00ff0000 +#define ETH_SAL_BYTE_2 0xff000000 + +/* Ethernet SAH registers */ +#define ETH_SAH_BYTE1 0x000000ff +#define ETH_SAH_BYTE0 0x0000ff00 + +/* Ethernet GPF register */ +#define ETH_GPF_PTV 0x0000ffff + +/* Ethernet PFG register */ +#define ETH_PFS_PFD (1 << 0) + +/* Ethernet CFSA[0-3] registers */ +#define ETH_CFSA0_CFSA4 0x000000ff +#define ETH_CFSA0_CFSA5 0x0000ff00 +#define ETH_CFSA1_CFSA2 0x000000ff +#define ETH_CFSA1_CFSA3 0x0000ff00 +#define ETH_CFSA1_CFSA0 0x000000ff +#define ETH_CFSA1_CFSA1 0x0000ff00 + +/* Ethernet MAC1 registers */ +#define ETH_MAC1_RE (1 << 0) +#define ETH_MAC1_PAF (1 << 1) +#define ETH_MAC1_RFC (1 << 2) +#define ETH_MAC1_TFC (1 << 3) +#define ETH_MAC1_LB (1 << 4) +#define ETH_MAC1_MR (1 << 31) + +/* Ethernet MAC2 registers */ +#define ETH_MAC2_FD (1 << 0) +#define ETH_MAC2_FLC (1 << 1) +#define ETH_MAC2_HFE (1 << 2) +#define ETH_MAC2_DC (1 << 3) +#define ETH_MAC2_CEN (1 << 4) +#define ETH_MAC2_PE (1 << 5) +#define ETH_MAC2_VPE (1 << 6) +#define ETH_MAC2_APE (1 << 7) +#define ETH_MAC2_PPE (1 << 8) +#define ETH_MAC2_LPE (1 << 9) +#define ETH_MAC2_NB (1 << 12) +#define ETH_MAC2_BP (1 << 13) +#define ETH_MAC2_ED (1 << 14) + +/* Ethernet IPGT register */ +#define ETH_IPGT 0x0000007f + +/* Ethernet IPGR registers */ +#define ETH_IPGR_IPGR2 0x0000007f +#define ETH_IPGR_IPGR1 0x00007f00 + +/* Ethernet CLRT registers */ +#define ETH_CLRT_MAX_RET 0x0000000f +#define ETH_CLRT_COL_WIN 0x00003f00 + +/* Ethernet MAXF register */ +#define ETH_MAXF 0x0000ffff + +/* Ethernet test registers */ +#define ETH_TEST_REG (1 << 2) +#define ETH_MCP_DIV 0x000000ff + +/* MII registers */ +#define ETH_MII_CFG_RSVD 0x0000000c +#define ETH_MII_CMD_RD (1 << 0) +#define ETH_MII_CMD_SCN (1 << 1) +#define ETH_MII_REG_ADDR 0x0000001f +#define ETH_MII_PHY_ADDR 0x00001f00 +#define ETH_MII_WTD_DATA 0x0000ffff +#define ETH_MII_RDD_DATA 0x0000ffff +#define ETH_MII_IND_BSY (1 << 0) +#define ETH_MII_IND_SCN (1 << 1) +#define ETH_MII_IND_NV (1 << 2) + +/* + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors. + */ + +#define ETH_RX_FD (1 << 0) +#define ETH_RX_LD (1 << 1) +#define ETH_RX_ROK (1 << 2) +#define ETH_RX_FM (1 << 3) +#define ETH_RX_MP (1 << 4) +#define ETH_RX_BP (1 << 5) +#define ETH_RX_VLT (1 << 6) +#define ETH_RX_CF (1 << 7) +#define ETH_RX_OVR (1 << 8) +#define ETH_RX_CRC (1 << 9) +#define ETH_RX_CV (1 << 10) +#define ETH_RX_DB (1 << 11) +#define ETH_RX_LE (1 << 12) +#define ETH_RX_LOR (1 << 13) +#define ETH_RX_CES (1 << 14) +#define ETH_RX_LEN_BIT 16 +#define ETH_RX_LEN 0xffff0000 + +#define ETH_TX_FD (1 << 0) +#define ETH_TX_LD (1 << 1) +#define ETH_TX_OEN (1 << 2) +#define ETH_TX_PEN (1 << 3) +#define ETH_TX_CEN (1 << 4) +#define ETH_TX_HEN (1 << 5) +#define ETH_TX_TOK (1 << 6) +#define ETH_TX_MP (1 << 7) +#define ETH_TX_BP (1 << 8) +#define ETH_TX_UND (1 << 9) +#define ETH_TX_OF (1 << 10) +#define ETH_TX_ED (1 << 11) +#define ETH_TX_EC (1 << 12) +#define ETH_TX_LC (1 << 13) +#define ETH_TX_TD (1 << 14) +#define ETH_TX_CRC (1 << 15) +#define ETH_TX_LE (1 << 16) +#define ETH_TX_CC 0x001E0000 + +#endif /* __ASM_RC32434_ETH_H */ diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h new file mode 100644 index 000000000000..f946f5f45bbb --- /dev/null +++ b/include/asm-mips/mach-rc32434/gpio.h @@ -0,0 +1,126 @@ +/* + * Copyright 2002 Integrated Device Technology, Inc. + * All rights reserved. + * + * GPIO register definition. + * + * Author : ryan.holmQVist@idt.com + * Date : 20011005 + * Copyright (C) 2001, 2002 Ryan Holm + * Copyright (C) 2008 Florian Fainelli + */ + +#ifndef _RC32434_GPIO_H_ +#define _RC32434_GPIO_H_ + +#include + +struct rb532_gpio_reg { + u32 gpiofunc; /* GPIO Function Register + * gpiofunc[x]==0 bit = gpio + * func[x]==1 bit = altfunc + */ + u32 gpiocfg; /* GPIO Configuration Register + * gpiocfg[x]==0 bit = input + * gpiocfg[x]==1 bit = output + */ + u32 gpiod; /* GPIO Data Register + * gpiod[x] read/write gpio pinX status + */ + u32 gpioilevel; /* GPIO Interrupt Status Register + * interrupt level (see gpioistat) + */ + u32 gpioistat; /* Gpio Interrupt Status Register + * istat[x] = (gpiod[x] == level[x]) + * cleared in ISR (STICKY bits) + */ + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */ +}; + +/* UART GPIO signals */ +#define RC32434_UART0_SOUT (1 << 0) +#define RC32434_UART0_SIN (1 << 1) +#define RC32434_UART0_RTS (1 << 2) +#define RC32434_UART0_CTS (1 << 3) + +/* M & P bus GPIO signals */ +#define RC32434_MP_BIT_22 (1 << 4) +#define RC32434_MP_BIT_23 (1 << 5) +#define RC32434_MP_BIT_24 (1 << 6) +#define RC32434_MP_BIT_25 (1 << 7) + +/* CPU GPIO signals */ +#define RC32434_CPU_GPIO (1 << 8) + +/* Reserved GPIO signals */ +#define RC32434_AF_SPARE_6 (1 << 9) +#define RC32434_AF_SPARE_4 (1 << 10) +#define RC32434_AF_SPARE_3 (1 << 11) +#define RC32434_AF_SPARE_2 (1 << 12) + +/* PCI messaging unit */ +#define RC32434_PCI_MSU_GPIO (1 << 13) + + +extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val); +extern unsigned get_434_reg(unsigned reg_offs); +extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); +extern unsigned char get_latch_u5(void); + +extern int rb532_gpio_get_value(unsigned gpio); +extern void rb532_gpio_set_value(unsigned gpio, int value); +extern int rb532_gpio_direction_input(unsigned gpio); +extern int rb532_gpio_direction_output(unsigned gpio, int value); +extern void rb532_gpio_set_int_level(unsigned gpio, int value); +extern int rb532_gpio_get_int_level(unsigned gpio); +extern void rb532_gpio_set_int_status(unsigned gpio, int value); +extern int rb532_gpio_get_int_status(unsigned gpio); + + +/* Wrappers for the arch-neutral GPIO API */ + +static inline int gpio_request(unsigned gpio, const char *label) +{ + /* Not yet implemented */ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ + /* Not yet implemented */ +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return rb532_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return rb532_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return rb532_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + rb532_gpio_set_value(gpio, value); +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return gpio; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return irq; +} + +/* For cansleep */ +#include + +#endif /* _RC32434_GPIO_H_ */ diff --git a/include/asm-mips/mach-rc32434/integ.h b/include/asm-mips/mach-rc32434/integ.h new file mode 100644 index 000000000000..fa65bc3d8807 --- /dev/null +++ b/include/asm-mips/mach-rc32434/integ.h @@ -0,0 +1,59 @@ +/* + * Definitions for the Watchdog registers + * + * Copyright 2002 Ryan Holm + * Copyright 2008 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __RC32434_INTEG_H__ +#define __RC32434_INTEG_H__ + +#include + +#define INTEG0_BASE_ADDR 0x18030030 + +struct integ { + u32 errcs; /* sticky use ERRCS_ */ + u32 wtcount; /* Watchdog timer count reg. */ + u32 wtcompare; /* Watchdog timer timeout value. */ + u32 wtc; /* Watchdog timer control. use WTC_ */ +}; + +/* Error counters */ +#define RC32434_ERR_WTO 0 +#define RC32434_ERR_WNE 1 +#define RC32434_ERR_UCW 2 +#define RC32434_ERR_UCR 3 +#define RC32434_ERR_UPW 4 +#define RC32434_ERR_UPR 5 +#define RC32434_ERR_UDW 6 +#define RC32434_ERR_UDR 7 +#define RC32434_ERR_SAE 8 +#define RC32434_ERR_WRE 9 + +/* Watchdog control bits */ +#define RC32434_WTC_EN 0 +#define RC32434_WTC_TO 1 + +#endif /* __RC32434_INTEG_H__ */ diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h new file mode 100644 index 000000000000..cb9e4725f5dc --- /dev/null +++ b/include/asm-mips/mach-rc32434/irq.h @@ -0,0 +1,8 @@ +#ifndef __ASM_RC32434_IRQ_H +#define __ASM_RC32434_IRQ_H + +#define NR_IRQS 256 + +#include + +#endif /* __ASM_RC32434_IRQ_H */ diff --git a/include/asm-mips/mach-rc32434/pci.h b/include/asm-mips/mach-rc32434/pci.h new file mode 100644 index 000000000000..410638f2af74 --- /dev/null +++ b/include/asm-mips/mach-rc32434/pci.h @@ -0,0 +1,481 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright 2004 IDT Inc. (rischelp@idt.com) + * + * Initial Release + */ + +#ifndef _ASM_RC32434_PCI_H_ +#define _ASM_RC32434_PCI_H_ + +#define epld_mask ((volatile unsigned char *)0xB900000d) + +#define PCI0_BASE_ADDR 0x18080000 +#define PCI_LBA_COUNT 4 + +struct pci_map { + u32 address; /* Address. */ + u32 control; /* Control. */ + u32 mapping; /* mapping. */ +}; + +struct pci_reg { + u32 pcic; + u32 pcis; + u32 pcism; + u32 pcicfga; + u32 pcicfgd; + volatile struct pci_map pcilba[PCI_LBA_COUNT]; + u32 pcidac; + u32 pcidas; + u32 pcidasm; + u32 pcidad; + u32 pcidma8c; + u32 pcidma9c; + u32 pcitc; +}; + +#define PCI_MSU_COUNT 2 + +struct pci_msu { + u32 pciim[PCI_MSU_COUNT]; + u32 pciom[PCI_MSU_COUNT]; + u32 pciid; + u32 pciiic; + u32 pciiim; + u32 pciiod; + u32 pciioic; + u32 pciioim; +}; + +/* + * PCI Control Register + */ + +#define PCI_CTL_EN (1 << 0) +#define PCI_CTL_TNR (1 << 1) +#define PCI_CTL_SCE (1 << 2) +#define PCI_CTL_IEN (1 << 3) +#define PCI_CTL_AAA (1 << 4) +#define PCI_CTL_EAP (1 << 5) +#define PCI_CTL_PCIM_BIT 6 +#define PCI_CTL_PCIM 0x000001c0 + +#define PCI_CTL_PCIM_DIS 0 +#define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */ +#define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */ +#define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */ +#define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */ +#define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */ +#define PCI_CTL_PCIM_RSVD6 6 +#define PCI_CTL_PCIM_RSVD7 7 + +#define PCI_CTL_IGM (1 << 9) + +/* + * PCI Status Register + */ + +#define PCI_STAT_EED (1 << 0) +#define PCI_STAT_WR (1 << 1) +#define PCI_STAT_NMI (1 << 2) +#define PCI_STAT_II (1 << 3) +#define PCI_STAT_CWE (1 << 4) +#define PCI_STAT_CRE (1 << 5) +#define PCI_STAT_MDPE (1 << 6) +#define PCI_STAT_STA (1 << 7) +#define PCI_STAT_RTA (1 << 8) +#define PCI_STAT_RMA (1 << 9) +#define PCI_STAT_SSE (1 << 10) +#define PCI_STAT_OSE (1 << 11) +#define PCI_STAT_PE (1 << 12) +#define PCI_STAT_TAE (1 << 13) +#define PCI_STAT_RLE (1 << 14) +#define PCI_STAT_BME (1 << 15) +#define PCI_STAT_PRD (1 << 16) +#define PCI_STAT_RIP (1 << 17) + +/* + * PCI Status Mask Register + */ + +#define PCI_STATM_EED PCI_STAT_EED +#define PCI_STATM_WR PCI_STAT_WR +#define PCI_STATM_NMI PCI_STAT_NMI +#define PCI_STATM_II PCI_STAT_II +#define PCI_STATM_CWE PCI_STAT_CWE +#define PCI_STATM_CRE PCI_STAT_CRE +#define PCI_STATM_MDPE PCI_STAT_MDPE +#define PCI_STATM_STA PCI_STAT_STA +#define PCI_STATM_RTA PCI_STAT_RTA +#define PCI_STATM_RMA PCI_STAT_RMA +#define PCI_STATM_SSE PCI_STAT_SSE +#define PCI_STATM_OSE PCI_STAT_OSE +#define PCI_STATM_PE PCI_STAT_PE +#define PCI_STATM_TAE PCI_STAT_TAE +#define PCI_STATM_RLE PCI_STAT_RLE +#define PCI_STATM_BME PCI_STAT_BME +#define PCI_STATM_PRD PCI_STAT_PRD +#define PCI_STATM_RIP PCI_STAT_RIP + +/* + * PCI Configuration Address Register + */ +#define PCI_CFGA_REG_BIT 2 +#define PCI_CFGA_REG 0x000000fc +#define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */ +#define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */ +#define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */ +#define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */ +#define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */ +#define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */ +#define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */ +#define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */ +#define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */ +#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */ +#define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */ +#define PCI_CFGA_REG_PBA0M (0x48 >> 2) +#define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */ +#define PCI_CFGA_REG_PBA1M (0x50 >> 2) +#define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */ +#define PCI_CFGA_REG_PBA2M (0x58 >> 2) +#define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */ +#define PCI_CFGA_REG_PBA3M (0x60 >> 2) +#define PCI_CFGA_REG_PMGT (0x64 >> 2) +#define PCI_CFGA_FUNC_BIT 8 +#define PCI_CFGA_FUNC 0x00000700 +#define PCI_CFGA_DEV_BIT 11 +#define PCI_CFGA_DEV 0x0000f800 +#define PCI_CFGA_DEV_INTERN 0 +#define PCI_CFGA_BUS_BIT 16 +#define PCI CFGA_BUS 0x00ff0000 +#define PCI_CFGA_BUS_TYPE0 0 +#define PCI_CFGA_EN (1 << 31) + +/* PCI CFG04 commands */ +#define PCI_CFG04_CMD_IO_ENA (1 << 0) +#define PCI_CFG04_CMD_MEM_ENA (1 << 1) +#define PCI_CFG04_CMD_BM_ENA (1 << 2) +#define PCI_CFG04_CMD_MW_INV (1 << 4) +#define PCI_CFG04_CMD_PAR_ENA (1 << 6) +#define PCI_CFG04_CMD_SER_ENA (1 << 8) +#define PCI_CFG04_CMD_FAST_ENA (1 << 9) + +/* PCI CFG04 status fields */ +#define PCI_CFG04_STAT_BIT 16 +#define PCI_CFG04_STAT 0xffff0000 +#define PCI_CFG04_STAT_66_MHZ (1 << 21) +#define PCI_CFG04_STAT_FBB (1 << 23) +#define PCI_CFG04_STAT_MDPE (1 << 24) +#define PCI_CFG04_STAT_DST (1 << 25) +#define PCI_CFG04_STAT_STA (1 << 27) +#define PCI_CFG04_STAT_RTA (1 << 28) +#define PCI_CFG04_STAT_RMA (1 << 29) +#define PCI_CFG04_STAT_SSE (1 << 30) +#define PCI_CFG04_STAT_PE (1 << 31) + +#define PCI_PBA_MSI (1 << 0) +#define PCI_PBA_P (1 << 2) + +/* PCI PBAC registers */ +#define PCI_PBAC_MSI (1 << 0) +#define PCI_PBAC_P (1 << 1) +#define PCI_PBAC_SIZE_BIT 2 +#define PCI_PBAC_SIZE 0x0000007c +#define PCI_PBAC_SB (1 << 7) +#define PCI_PBAC_PP (1 << 8) +#define PCI_PBAC_MR_BIT 9 +#define PCI_PBAC_MR 0x00000600 +#define PCI_PBAC_MR_RD 0 +#define PCI_PBAC_MR_RD_LINE 1 +#define PCI_PBAC_MR_RD_MULT 2 +#define PCI_PBAC_MRL (1 << 11) +#define PCI_PBAC_MRM (1 << 12) +#define PCI_PBAC_TRP (1 << 13) + +#define PCI_CFG40_TRDY_TIM 0x000000ff +#define PCI_CFG40_RET_LIM 0x0000ff00 + +/* + * PCI Local Base Address [0|1|2|3] Register + */ + +#define PCI_LBA_BADDR_BIT 0 +#define PCI_LBA_BADDR 0xffffff00 + +/* + * PCI Local Base Address Control Register + */ + +#define PCI_LBAC_MSI (1 << 0) +#define PCI_LBAC_MSI_MEM 0 +#define PCI_LBAC_MSI_IO 1 +#define PCI_LBAC_SIZE_BIT 2 +#define PCI_LBAC_SIZE 0x0000007c +#define PCI_LBAC_SB (1 << 7) +#define PCI_LBAC_RT (1 << 8) +#define PCI_LBAC_RT_NO_PREF 0 +#define PCI_LBAC_RT_PREF 1 + +/* + * PCI Local Base Address [0|1|2|3] Mapping Register + */ +#define PCI_LBAM_MADDR_BIT 8 +#define PCI_LBAM_MADDR 0xffffff00 + +/* + * PCI Decoupled Access Control Register + */ +#define PCI_DAC_DEN (1 << 0) + +/* + * PCI Decoupled Access Status Register + */ +#define PCI_DAS_D (1 << 0) +#define PCI_DAS_B (1 << 1) +#define PCI_DAS_E (1 << 2) +#define PCI_DAS_OFE (1 << 3) +#define PCI_DAS_OFF (1 << 4) +#define PCI_DAS_IFE (1 << 5) +#define PCI_DAS_IFF (1 << 6) + +/* + * PCI DMA Channel 8 Configuration Register + */ +#define PCI_DMA8C_MBS_BIT 0 +#define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */ +#define PCI_DMA8C_OUR (1 << 12) + +/* + * PCI DMA Channel 9 Configuration Register + */ +#define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */ +#define PCI_DMA9C_MBS 0x00000fff + +/* + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors + */ + +#define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */ +#define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */ +/* These are for reads (DMA channel 8) */ +#define PCI_DMAD_DEVCMD_MR 0 /* memory read */ +#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */ +#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */ +#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */ +/* These are for writes (DMA channel 9) */ +#define PCI_DMAD_DEVCMD_MW 0 /* memory write */ +#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */ +#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */ + +/* Swap byte field applies to both DMA channel 8 and 9 */ +#define PCI_DMAD_SB (1 << 24) /* swap byte field */ + + +/* + * PCI Target Control Register + */ + +#define PCI_TC_RTIMER_BIT 0 +#define PCI_TC_RTIMER 0x000000ff +#define PCI_TC_DTIMER_BIT 8 +#define PCI_TC_DTIMER 0x0000ff00 +#define PCI_TC_RDR (1 << 18) +#define PCI_TC_DDT (1 << 19) + +/* + * PCI messaging unit [applies to both inbound and outbound registers ] + */ +#define PCI_MSU_M0 (1 << 0) +#define PCI_MSU_M1 (1 << 1) +#define PCI_MSU_DB (1 << 2) + +#define PCI_MSG_ADDR 0xB8088010 +#define PCI0_ADDR 0xB8080000 +#define rc32434_pci ((struct pci_reg *) PCI0_ADDR) +#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR) + +#define PCIM_SHFT 0x6 +#define PCIM_BIT_LEN 0x7 +#define PCIM_H_EA 0x3 +#define PCIM_H_IA_FIX 0x4 +#define PCIM_H_IA_RR 0x5 +#if 0 +#define PCI_ADDR_START 0x13000000 +#endif + +#define PCI_ADDR_START 0x50000000 + +#define CPUTOPCI_MEM_WIN 0x02000000 +#define CPUTOPCI_IO_WIN 0x00100000 +#define PCILBA_SIZE_SHFT 2 +#define PCILBA_SIZE_MASK 0x1F +#define SIZE_256MB 0x1C +#define SIZE_128MB 0x1B +#define SIZE_64MB 0x1A +#define SIZE_32MB 0x19 +#define SIZE_16MB 0x18 +#define SIZE_4MB 0x16 +#define SIZE_2MB 0x15 +#define SIZE_1MB 0x14 +#define KORINA_CONFIG0_ADDR 0x80000000 +#define KORINA_CONFIG1_ADDR 0x80000004 +#define KORINA_CONFIG2_ADDR 0x80000008 +#define KORINA_CONFIG3_ADDR 0x8000000C +#define KORINA_CONFIG4_ADDR 0x80000010 +#define KORINA_CONFIG5_ADDR 0x80000014 +#define KORINA_CONFIG6_ADDR 0x80000018 +#define KORINA_CONFIG7_ADDR 0x8000001C +#define KORINA_CONFIG8_ADDR 0x80000020 +#define KORINA_CONFIG9_ADDR 0x80000024 +#define KORINA_CONFIG10_ADDR 0x80000028 +#define KORINA_CONFIG11_ADDR 0x8000002C +#define KORINA_CONFIG12_ADDR 0x80000030 +#define KORINA_CONFIG13_ADDR 0x80000034 +#define KORINA_CONFIG14_ADDR 0x80000038 +#define KORINA_CONFIG15_ADDR 0x8000003C +#define KORINA_CONFIG16_ADDR 0x80000040 +#define KORINA_CONFIG17_ADDR 0x80000044 +#define KORINA_CONFIG18_ADDR 0x80000048 +#define KORINA_CONFIG19_ADDR 0x8000004C +#define KORINA_CONFIG20_ADDR 0x80000050 +#define KORINA_CONFIG21_ADDR 0x80000054 +#define KORINA_CONFIG22_ADDR 0x80000058 +#define KORINA_CONFIG23_ADDR 0x8000005C +#define KORINA_CONFIG24_ADDR 0x80000060 +#define KORINA_CONFIG25_ADDR 0x80000064 +#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \ + PCI_CFG04_CMD_MEM_ENA | \ + PCI_CFG04_CMD_BM_ENA | \ + PCI_CFG04_CMD_MW_INV | \ + PCI_CFG04_CMD_PAR_ENA | \ + PCI_CFG04_CMD_SER_ENA) + +#define KORINA_STAT (PCI_CFG04_STAT_MDPE | \ + PCI_CFG04_STAT_STA | \ + PCI_CFG04_STAT_RTA | \ + PCI_CFG04_STAT_RMA | \ + PCI_CFG04_STAT_SSE | \ + PCI_CFG04_STAT_PE) + +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD) + +#define KORINA_REVID 0 +#define KORINA_CLASS_CODE 0 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \ + KORINA_REVID) + +#define KORINA_CACHE_LINE_SIZE 4 +#define KORINA_MASTER_LAT 0x3c +#define KORINA_HEADER_TYPE 0 +#define KORINA_BIST 0 + +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \ + (KORINA_HEADER_TYPE<<16) | \ + (KORINA_MASTER_LAT<<8) | \ + KORINA_CACHE_LINE_SIZE) + +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */ +#define KORINA_BAR1 0x18800001 /* 1 MB IO */ +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina + internal Registers */ +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */ + +#define KORINA_CNFG4 KORINA_BAR0 +#define KORINA_CNFG5 KORINA_BAR1 +#define KORINA_CNFG6 KORINA_BAR2 +#define KORINA_CNFG7 KORINA_BAR3 + +#define KORINA_SUBSYS_VENDOR_ID 0x011d +#define KORINA_SUBSYSTEM_ID 0x0214 +#define KORINA_CNFG8 0 +#define KORINA_CNFG9 0 +#define KORINA_CNFG10 0 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ + KORINA_SUBSYSTEM_ID) +#define KORINA_INT_LINE 1 +#define KORINA_INT_PIN 1 +#define KORINA_MIN_GNT 8 +#define KORINA_MAX_LAT 0x38 +#define KORINA_CNFG12 0 +#define KORINA_CNFG13 0 +#define KORINA_CNFG14 0 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \ + (KORINA_MIN_GNT<<16) | \ + (KORINA_INT_PIN<<8) | \ + KORINA_INT_LINE) +#define KORINA_RETRY_LIMIT 0x80 +#define KORINA_TRDY_LIMIT 0x80 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \ + KORINA_TRDY_LIMIT) +#define PCI_PBAxC_R 0x0 +#define PCI_PBAxC_RL 0x1 +#define PCI_PBAxC_RM 0x2 +#define SIZE_SHFT 2 + +#if defined(__MIPSEB__) +#define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \ + ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \ + PCI_PBAC_PP | \ + (SIZE_128MB< + * Copyright 2008 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8)) + +#define GPIO_INIT_NOBUTTON "" +#define GPIO_INIT_BUTTON " 2" + +#define SR_NMI 0x00180000 +#define SERIAL_SPEED_ENTRY 0x00000001 + +#define FREQ_TAG "HZ=" +#define GPIO_TAG "gpio=" +#define KMAC_TAG "kmac=" +#define MEM_TAG "mem=" +#define BOARD_TAG "board=" + +#define BOARD_RB532 "500" +#define BOARD_RB532A "500r5" diff --git a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h new file mode 100644 index 000000000000..e0a76e3ffea8 --- /dev/null +++ b/include/asm-mips/mach-rc32434/rb.h @@ -0,0 +1,81 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2004 IDT Inc. + * Copyright (C) 2006 Felix Fietkau + */ +#ifndef __ASM_RC32434_RB_H +#define __ASM_RC32434_RB_H + +#include + +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000)) +#define DEV0BASE 0x010000 +#define DEV0MASK 0x010004 +#define DEV0C 0x010008 +#define DEV0T 0x01000C +#define DEV1BASE 0x010010 +#define DEV1MASK 0x010014 +#define DEV1C 0x010018 +#define DEV1TC 0x01001C +#define DEV2BASE 0x010020 +#define DEV2MASK 0x010024 +#define DEV2C 0x010028 +#define DEV2TC 0x01002C +#define DEV3BASE 0x010030 +#define DEV3MASK 0x010034 +#define DEV3C 0x010038 +#define DEV3TC 0x01003C +#define BTCS 0x010040 +#define BTCOMPARE 0x010044 +#define GPIOBASE 0x050000 +#define GPIOCFG 0x050004 +#define GPIOD 0x050008 +#define GPIOILEVEL 0x05000C +#define GPIOISTAT 0x050010 +#define GPIONMIEN 0x050014 +#define IMASK6 0x038038 +#define LO_WPX (1 << 0) +#define LO_ALE (1 << 1) +#define LO_CLE (1 << 2) +#define LO_CEX (1 << 3) +#define LO_FOFF (1 << 5) +#define LO_SPICS (1 << 6) +#define LO_ULED (1 << 7) + +#define BIT_TO_MASK(x) (1 << x) + +struct dev_reg { + u32 base; + u32 mask; + u32 ctl; + u32 timing; +}; + +struct korina_device { + char *name; + unsigned char mac[6]; + struct net_device *dev; +}; + +struct cf_device { + int gpio_pin; + void *dev; + struct gendisk *gd; +}; + +struct mpmc_device { + unsigned char state; + spinlock_t lock; + void __iomem *base; +}; + +#endif /* __ASM_RC32434_RB_H */ diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h new file mode 100644 index 000000000000..c4a02145104e --- /dev/null +++ b/include/asm-mips/mach-rc32434/rc32434.h @@ -0,0 +1,61 @@ +/* + * Definitions for IDT RC323434 CPU. + */ + +#ifndef _ASM_RC32434_RC32434_H_ +#define _ASM_RC32434_RC32434_H_ + +#include +#include + +#define RC32434_REG_BASE 0x18000000 +#define RC32434_RST (1 << 15) + +#define IDT_CLOCK_MULT 2 +#define MIPS_CPU_TIMER_IRQ 7 + +/* Interrupt Controller */ +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000) +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008) +#define IC_GROUP_OFFSET 0x0C + +#define NUM_INTR_GROUPS 5 + +/* 16550 UARTs */ +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */ + /* GRP3 IRQ numbers start here */ +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) + /* GRP4 IRQ numbers start here */ +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) + /* GRP5 IRQ numbers start here */ +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) + + +#ifdef __MIPSEB__ +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003) +#else +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000) +#endif + +#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0) + +/* cpu pipeline flush */ +static inline void rc32434_sync(void) +{ + __asm__ volatile ("sync"); +} + +static inline void rc32434_sync_udelay(int us) +{ + __asm__ volatile ("sync"); + udelay(us); +} + +static inline void rc32434_sync_delay(int ms) +{ + __asm__ volatile ("sync"); + mdelay(ms); +} + +#endif /* _ASM_RC32434_RC32434_H_ */ diff --git a/include/asm-mips/mach-rc32434/timer.h b/include/asm-mips/mach-rc32434/timer.h new file mode 100644 index 000000000000..e49b1d57a017 --- /dev/null +++ b/include/asm-mips/mach-rc32434/timer.h @@ -0,0 +1,65 @@ +/* + * Definitions for timer registers + * + * Copyright 2004 Philip Rischel + * Copyright 2008 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __ASM_RC32434_TIMER_H +#define __ASM_RC32434_TIMER_H + +#include + +#define TIMER0_BASE_ADDR 0x18028000 +#define TIMER_COUNT 3 + +struct timer_counter { + u32 count; + u32 compare; + u32 ctc; /*use CTC_ */ +}; + +struct timer { + struct timer_counter tim[TIMER_COUNT]; + u32 rcount; /* use RCOUNT_ */ + u32 rcompare; /* use RCOMPARE_ */ + u32 rtc; /* use RTC_ */ +}; + +#define RC32434_CTC_EN_BIT 0 +#define RC32434_CTC_TO_BIT 1 + +/* Real time clock registers */ +#define RC32434_RTC_MSK(x) BIT_TO_MASK(x) +#define RC32434_RTC_CE_BIT 0 +#define RC32434_RTC_TO_BIT 1 +#define RC32434_RTC_RQE_BIT 2 + +/* Counter registers */ +#define RC32434_RCOUNT_BIT 0 +#define RC32434_RCOUNT_MSK 0x0000ffff +#define RC32434_RCOMP_BIT 0 +#define RC32434_RCOMP_MSK 0x0000ffff + +#endif /* __ASM_RC32434_TIMER_H */ diff --git a/include/asm-mips/mach-rc32434/war.h b/include/asm-mips/mach-rc32434/war.h new file mode 100644 index 000000000000..3ddf187e98a6 --- /dev/null +++ b/include/asm-mips/mach-rc32434/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ -- cgit v1.2.3 From e76812eddcebe06403934c868f3a707fd5bc167d Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Wed, 16 Jul 2008 19:25:44 +0300 Subject: [MIPS] Remove asm-mips/mips-boards/atlas{,int}.h asm-mips/mips-boards/atlas{,int}.h are now obsolete. Signed-off-by: Adrian Bunk Signed-off-by: Ralf Baechle --- include/asm-mips/mips-boards/atlas.h | 80 ----------------------- include/asm-mips/mips-boards/atlasint.h | 109 -------------------------------- 2 files changed, 189 deletions(-) delete mode 100644 include/asm-mips/mips-boards/atlas.h delete mode 100644 include/asm-mips/mips-boards/atlasint.h (limited to 'include/asm-mips') diff --git a/include/asm-mips/mips-boards/atlas.h b/include/asm-mips/mips-boards/atlas.h deleted file mode 100644 index a8ae12d120ee..000000000000 --- a/include/asm-mips/mips-boards/atlas.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines of the Atlas board specific address-MAP, registers, etc. - * - */ -#ifndef _MIPS_ATLAS_H -#define _MIPS_ATLAS_H - -#include - -/* - * Atlas RTC-device indirect register access. - */ -#define ATLAS_RTC_ADR_REG 0x1f000800 -#define ATLAS_RTC_DAT_REG 0x1f000808 - -/* - * Atlas interrupt controller register base. - */ -#define ATLAS_ICTRL_REGS_BASE 0x1f000000 - -/* - * Atlas registers are memory mapped on 64-bit aligned boundaries and - * only word access are allowed. - */ -struct atlas_ictrl_regs { - volatile unsigned int intraw; - int dummy1; - volatile unsigned int intseten; - int dummy2; - volatile unsigned int intrsten; - int dummy3; - volatile unsigned int intenable; - int dummy4; - volatile unsigned int intstatus; - int dummy5; -}; - -/* - * Atlas UART register base. - */ -#define ATLAS_UART_REGS_BASE 0x1f000900 -#define ATLAS_BASE_BAUD ( 3686400 / 16 ) - -/* - * Atlas PSU standby register. - */ -#define ATLAS_PSUSTBY_REG 0x1f000600 -#define ATLAS_GOSTBY 0x4d - -/* - * We make a universal assumption about the way the bootloader (YAMON) - * have located the Philips SAA9730 chip. - * This is not ideal, but is needed for setting up remote debugging as - * soon as possible. - */ -#define ATLAS_SAA9730_REG 0x10800000 - -#define ATLAS_SAA9730_BAUDCLOCK 3692300 - -#endif /* !(_MIPS_ATLAS_H) */ diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h deleted file mode 100644 index 93ba1c1b2a4f..000000000000 --- a/include/asm-mips/mips-boards/atlasint.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines for the Atlas interrupt controller. - * - */ -#ifndef _MIPS_ATLASINT_H -#define _MIPS_ATLASINT_H - -#include - -/* CPU interrupt offsets */ -#define MIPSCPU_INT_SW0 0 -#define MIPSCPU_INT_SW1 1 -#define MIPSCPU_INT_MB0 2 -#define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0 -#define MIPSCPU_INT_MB1 3 -#define MIPSCPU_INT_MB2 4 -#define MIPSCPU_INT_MB3 5 -#define MIPSCPU_INT_MB4 6 - -/* - * Interrupts 8..39 are used for Atlas interrupt controller interrupts - */ -#define ATLAS_INT_BASE 8 -#define ATLAS_INT_UART (ATLAS_INT_BASE + 0) -#define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1) -#define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2) -#define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3) -#define ATLAS_INT_RTC (ATLAS_INT_BASE + 4) -#define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5) -#define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6) -#define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7) -#define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8) -#define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9) -#define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10) -#define ATLAS_INT_PCID (ATLAS_INT_BASE + 11) -#define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12) -#define ATLAS_INT_DEG (ATLAS_INT_BASE + 13) -#define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14) -#define ATLAS_INT_INTA (ATLAS_INT_BASE + 15) -#define ATLAS_INT_INTB (ATLAS_INT_BASE + 16) -#define ATLAS_INT_ETH ATLAS_INT_INTB -#define ATLAS_INT_INTC (ATLAS_INT_BASE + 17) -#define ATLAS_INT_SCSI ATLAS_INT_INTC -#define ATLAS_INT_INTD (ATLAS_INT_BASE + 18) -#define ATLAS_INT_SERR (ATLAS_INT_BASE + 19) -#define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20) -#define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21) -#define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22) -#define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23) -#define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24) -#define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25) -#define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26) -#define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27) -#define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28) -#define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29) -#define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30) -#define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31) -#define ATLAS_INT_END (ATLAS_INT_BASE + 31) - -/* - * Interrupts 64..127 are used for Soc-it Classic interrupts - */ -#define MSC01C_INT_BASE 64 - -/* SOC-it Classic interrupt offsets */ -#define MSC01C_INT_TMR 0 -#define MSC01C_INT_PCI 1 - -/* - * Interrupts 64..127 are used for Soc-it EIC interrupts - */ -#define MSC01E_INT_BASE 64 - -/* SOC-it EIC interrupt offsets */ -#define MSC01E_INT_SW0 1 -#define MSC01E_INT_SW1 2 -#define MSC01E_INT_MB0 3 -#define MSC01E_INT_ATLAS MSC01E_INT_MB0 -#define MSC01E_INT_MB1 4 -#define MSC01E_INT_MB2 5 -#define MSC01E_INT_MB3 6 -#define MSC01E_INT_MB4 7 -#define MSC01E_INT_TMR 8 -#define MSC01E_INT_PCI 9 -#define MSC01E_INT_PERFCTR 10 -#define MSC01E_INT_CPUCTR 11 - -#endif /* !(_MIPS_ATLASINT_H) */ -- cgit v1.2.3 From f113c5eda22c349a163ea17ba11bc64727a0f799 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Wed, 16 Jul 2008 19:25:50 +0300 Subject: [MIPS] Remove include/asm-mips/mips-boards/sead{,int}.h include/asm-mips/mips-boards/sead{,int}.h are now obsolete. Signed-off-by: Adrian Bunk Signed-off-by: Ralf Baechle --- include/asm-mips/mips-boards/sead.h | 36 ---------------------------------- include/asm-mips/mips-boards/seadint.h | 28 -------------------------- 2 files changed, 64 deletions(-) delete mode 100644 include/asm-mips/mips-boards/sead.h delete mode 100644 include/asm-mips/mips-boards/seadint.h (limited to 'include/asm-mips') diff --git a/include/asm-mips/mips-boards/sead.h b/include/asm-mips/mips-boards/sead.h deleted file mode 100644 index 68c69de0b66f..000000000000 --- a/include/asm-mips/mips-boards/sead.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Defines of the SEAD board specific address-MAP, registers, etc. - * - */ -#ifndef _MIPS_SEAD_H -#define _MIPS_SEAD_H - -#include - -/* - * SEAD UART register base. - */ -#define SEAD_UART0_REGS_BASE (0x1f000800) -#define SEAD_BASE_BAUD ( 3686400 / 16 ) - -#endif /* !(_MIPS_SEAD_H) */ diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h deleted file mode 100644 index e710bae07340..000000000000 --- a/include/asm-mips/mips-boards/seadint.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Defines for the SEAD interrupt controller. - */ -#ifndef _MIPS_SEADINT_H -#define _MIPS_SEADINT_H - -#include - -#define MIPSCPU_INT_UART0 2 -#define MIPSCPU_INT_UART1 3 - -#endif /* !(_MIPS_SEADINT_H) */ -- cgit v1.2.3 From 5f15d378763e88c361364c0d0ad256d523f2d72f Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Wed, 16 Jul 2008 19:26:15 +0300 Subject: [MIPS] don't leak setup_early_printk() in userspace header Our userspace headers shouldn't contain prototypes of in-kernel functions. Signed-off-by: Adrian Bunk Signed-off-by: Ralf Baechle --- include/asm-mips/setup.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-mips') diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h index 883f59bfa097..e600cedda976 100644 --- a/include/asm-mips/setup.h +++ b/include/asm-mips/setup.h @@ -3,6 +3,8 @@ #define COMMAND_LINE_SIZE 256 +#ifdef __KERNEL__ extern void setup_early_printk(void); +#endif /* __KERNEL__ */ #endif /* __SETUP_H */ -- cgit v1.2.3 From 255033a9bb900a06c9a7798908ce12557d24fb66 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 19 Jul 2008 01:51:41 +0900 Subject: [MIPS] TXx9: Cleanups for 64-bit support * Unify (and fix) mem_tx4938.c and mem_tx4927.c * Simplify prom_init * Kill volatiles and unused definitions for tx4927.h and tx4938.h Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/generic/Makefile | 2 +- arch/mips/txx9/generic/mem_tx4927.c | 94 +++----------- arch/mips/txx9/generic/mem_tx4938.c | 124 ------------------- arch/mips/txx9/rbtx4927/prom.c | 6 +- arch/mips/txx9/rbtx4938/prom.c | 6 +- arch/mips/txx9/rbtx4938/setup.c | 11 +- include/asm-mips/txx9/tx4927.h | 48 +++++--- include/asm-mips/txx9/tx4938.h | 237 +++++------------------------------- 8 files changed, 86 insertions(+), 442 deletions(-) delete mode 100644 arch/mips/txx9/generic/mem_tx4938.c (limited to 'include/asm-mips') diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile index 668fdaad6448..ab274ede9a70 100644 --- a/arch/mips/txx9/generic/Makefile +++ b/arch/mips/txx9/generic/Makefile @@ -5,7 +5,7 @@ obj-y += setup.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o -obj-$(CONFIG_SOC_TX4938) += mem_tx4938.o irq_tx4938.o +obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o irq_tx4938.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o obj-$(CONFIG_KGDB) += dbgio.o diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c index 12dfc377bf2f..ef6ea6e97873 100644 --- a/arch/mips/txx9/generic/mem_tx4927.c +++ b/arch/mips/txx9/generic/mem_tx4927.c @@ -1,5 +1,5 @@ /* - * linux/arch/mips/tx4927/common/tx4927_prom.c + * linux/arch/mips/txx9/generic/mem_tx4927.c * * common tx4927 memory interface * @@ -32,8 +32,9 @@ #include #include #include +#include -static unsigned int __init tx4927_process_sdccr(unsigned long addr) +static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr) { u64 val; unsigned int sdccr_ce; @@ -45,97 +46,32 @@ static unsigned int __init tx4927_process_sdccr(unsigned long addr) unsigned int rs = 0; unsigned int cs = 0; unsigned int mw = 0; - unsigned int msize = 0; - val = __raw_readq((void __iomem *)addr); + val = __raw_readq(addr); /* MVMCP -- need #defs for these bits masks */ sdccr_ce = ((val & (1 << 10)) >> 10); sdccr_bs = ((val & (1 << 8)) >> 8); sdccr_rs = ((val & (3 << 5)) >> 5); - sdccr_cs = ((val & (3 << 2)) >> 2); + sdccr_cs = ((val & (7 << 2)) >> 2); sdccr_mw = ((val & (1 << 0)) >> 0); if (sdccr_ce) { - switch (sdccr_bs) { - case 0:{ - bs = 2; - break; - } - case 1:{ - bs = 4; - break; - } - } - switch (sdccr_rs) { - case 0:{ - rs = 2048; - break; - } - case 1:{ - rs = 4096; - break; - } - case 2:{ - rs = 8192; - break; - } - case 3:{ - rs = 0; - break; - } - } - switch (sdccr_cs) { - case 0:{ - cs = 256; - break; - } - case 1:{ - cs = 512; - break; - } - case 2:{ - cs = 1024; - break; - } - case 3:{ - cs = 2048; - break; - } - } - switch (sdccr_mw) { - case 0:{ - mw = 8; - break; - } /* 8 bytes = 64 bits */ - case 1:{ - mw = 4; - break; - } /* 4 bytes = 32 bits */ - } + bs = 2 << sdccr_bs; + rs = 2048 << sdccr_rs; + cs = 256 << sdccr_cs; + mw = 8 >> sdccr_mw; } - /* bytes per chip MB per chip num chips */ - msize = (((rs * cs * mw) / (1024 * 1024)) * bs); - - return (msize); + return rs * cs * mw * bs; } - unsigned int __init tx4927_get_mem_size(void) { - unsigned int c0; - unsigned int c1; - unsigned int c2; - unsigned int c3; - unsigned int total; - - /* MVMCP -- need #defs for these registers */ - c0 = tx4927_process_sdccr(0xff1f8000); - c1 = tx4927_process_sdccr(0xff1f8008); - c2 = tx4927_process_sdccr(0xff1f8010); - c3 = tx4927_process_sdccr(0xff1f8018); - total = c0 + c1 + c2 + c3; + unsigned int total = 0; + int i; - return (total); + for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++) + total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]); + return total; } diff --git a/arch/mips/txx9/generic/mem_tx4938.c b/arch/mips/txx9/generic/mem_tx4938.c deleted file mode 100644 index 20baeaeba4cd..000000000000 --- a/arch/mips/txx9/generic/mem_tx4938.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * linux/arch/mips/tx4938/common/prom.c - * - * common tx4938 memory interface - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ - -#include -#include -#include - -static unsigned int __init -tx4938_process_sdccr(u64 * addr) -{ - u64 val; - unsigned int sdccr_ce; - unsigned int sdccr_rs; - unsigned int sdccr_cs; - unsigned int sdccr_mw; - unsigned int rs = 0; - unsigned int cs = 0; - unsigned int mw = 0; - unsigned int bc = 4; - unsigned int msize = 0; - - val = ____raw_readq((void __iomem *)addr); - - /* MVMCP -- need #defs for these bits masks */ - sdccr_ce = ((val & (1 << 10)) >> 10); - sdccr_rs = ((val & (3 << 5)) >> 5); - sdccr_cs = ((val & (7 << 2)) >> 2); - sdccr_mw = ((val & (1 << 0)) >> 0); - - if (sdccr_ce) { - switch (sdccr_rs) { - case 0:{ - rs = 2048; - break; - } - case 1:{ - rs = 4096; - break; - } - case 2:{ - rs = 8192; - break; - } - default:{ - rs = 0; - break; - } - } - switch (sdccr_cs) { - case 0:{ - cs = 256; - break; - } - case 1:{ - cs = 512; - break; - } - case 2:{ - cs = 1024; - break; - } - case 3:{ - cs = 2048; - break; - } - case 4:{ - cs = 4096; - break; - } - default:{ - cs = 0; - break; - } - } - switch (sdccr_mw) { - case 0:{ - mw = 8; - break; - } /* 8 bytes = 64 bits */ - case 1:{ - mw = 4; - break; - } /* 4 bytes = 32 bits */ - } - } - - /* bytes per chip MB per chip bank count */ - msize = (((rs * cs * mw) / (1024 * 1024)) * (bc)); - - /* MVMCP -- bc hard coded to 4 from table 9.3.1 */ - /* boad supports bc=2 but no way to detect */ - - return (msize); -} - -unsigned int __init -tx4938_get_mem_size(void) -{ - unsigned int c0; - unsigned int c1; - unsigned int c2; - unsigned int c3; - unsigned int total; - - /* MVMCP -- need #defs for these registers */ - c0 = tx4938_process_sdccr((u64 *) 0xff1f8000); - c1 = tx4938_process_sdccr((u64 *) 0xff1f8008); - c2 = tx4938_process_sdccr((u64 *) 0xff1f8010); - c3 = tx4938_process_sdccr((u64 *) 0xff1f8018); - total = c0 + c1 + c2 + c3; - - return (total); -} diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c index 942e627d2dc1..5c0de54ebdd2 100644 --- a/arch/mips/txx9/rbtx4927/prom.c +++ b/arch/mips/txx9/rbtx4927/prom.c @@ -36,10 +36,6 @@ void __init rbtx4927_prom_init(void) { - extern int tx4927_get_mem_size(void); - int msize; - prom_init_cmdline(); - msize = tx4927_get_mem_size(); - add_memory_region(0, msize << 20, BOOT_MEM_RAM); + add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM); } diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c index fbb37458ddb2..ee189519ce5a 100644 --- a/arch/mips/txx9/rbtx4938/prom.c +++ b/arch/mips/txx9/rbtx4938/prom.c @@ -18,12 +18,8 @@ void __init rbtx4938_prom_init(void) { - extern int tx4938_get_mem_size(void); - int msize; #ifndef CONFIG_TX4938_NAND_BOOT prom_init_cmdline(); #endif - - msize = tx4938_get_mem_size(); - add_memory_region(0, msize << 20, BOOT_MEM_RAM); + add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM); } diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index c2da92396b7a..c1e076c7b2d2 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -310,7 +310,7 @@ void __init tx4938_board_setup(void) printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); for (i = 0; i < 4; i++) { - unsigned long long cr = tx4938_sdramcptr->cr[i]; + u64 cr = TX4938_SDRAMC_CR(i); unsigned long ram_base, ram_size; if (!((unsigned long)cr & 0x00000400)) continue; /* disabled */ @@ -318,20 +318,21 @@ void __init tx4938_board_setup(void) ram_size = ((unsigned long)(cr >> 33) + 1) << 21; if (ram_base >= 0x20000000) continue; /* high memory (ignore) */ - printk(" CR%d:%016Lx", i, cr); + printk(KERN_CONT " CR%d:%016llx", i, cr); tx4938_sdram_resource[i].name = "SDRAM"; tx4938_sdram_resource[i].start = ram_base; tx4938_sdram_resource[i].end = ram_base + ram_size - 1; tx4938_sdram_resource[i].flags = IORESOURCE_MEM; request_resource(&iomem_resource, &tx4938_sdram_resource[i]); } - printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); + printk(KERN_CONT " TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr)); /* SRAM */ - if (tx4938_sramcptr->cr & 1) { + if (____raw_readq(&tx4938_sramcptr->cr) & 1) { unsigned int size = 0x800; unsigned long base = - (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); + (____raw_readq(&tx4938_sramcptr->cr) >> (39-11)) + & ~(size - 1); tx4938_sram_resource.name = "SRAM"; tx4938_sram_resource.start = base; tx4938_sram_resource.end = base + size - 1; diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h index 46d60afc038b..c9212155f686 100644 --- a/include/asm-mips/txx9/tx4927.h +++ b/include/asm-mips/txx9/tx4927.h @@ -32,13 +32,20 @@ #include #include -#define TX4927_SDRAMC_REG 0xff1f8000 -#define TX4927_EBUSC_REG 0xff1f9000 -#define TX4927_PCIC_REG 0xff1fd000 -#define TX4927_CCFG_REG 0xff1fe000 -#define TX4927_IRC_REG 0xff1ff600 +#ifdef CONFIG_64BIT +#define TX4927_REG_BASE 0xffffffffff1f0000UL +#else +#define TX4927_REG_BASE 0xff1f0000UL +#endif +#define TX4927_REG_SIZE 0x00010000 + +#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000) +#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000) +#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000) +#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000) +#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) #define TX4927_NR_TMR 3 -#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) +#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) #define TX4927_IR_INT(n) (2 + (n)) #define TX4927_IR_SIO(n) (8 + (n)) @@ -49,15 +56,15 @@ #define TX4927_IRC_INT 2 /* IP[2] in Status register */ struct tx4927_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; + u64 cr[4]; + u64 unused0[4]; + u64 tr; + u64 unused1[2]; + u64 cmd; }; struct tx4927_ebusc_reg { - volatile unsigned long long cr[8]; + u64 cr[8]; }; struct tx4927_ccfg_reg { @@ -160,12 +167,24 @@ struct tx4927_ccfg_reg { #define TX4927_CLKCTR_SIO0RST 0x00000002 #define TX4927_CLKCTR_SIO1RST 0x00000001 -#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG) +#define tx4927_sdramcptr \ + ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG) #define tx4927_pcicptr \ ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) #define tx4927_ccfgptr \ ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) -#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) +#define tx4927_ebuscptr \ + ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG) + +#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) +#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) +#define TX4927_SDRAMC_SIZE(ch) \ + ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21) + +#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)]) +#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20) +#define TX4927_EBUSC_SIZE(ch) \ + (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf)) /* utilities */ static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) @@ -212,6 +231,7 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new) &tx4927_ccfgptr->ccfg); } +unsigned int tx4927_get_mem_size(void); int tx4927_report_pciclk(void); int tx4927_pciclk66_setup(void); void tx4927_irq_init(void); diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h index 12de68a4c10a..6690246a1149 100644 --- a/include/asm-mips/txx9/tx4938.h +++ b/include/asm-mips/txx9/tx4938.h @@ -15,20 +15,11 @@ /* some controllers are compatible with 4927 */ #include -#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) -#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) - -#define TX4938_PCIIO_0 0x10000000 -#define TX4938_PCIIO_1 0x01010000 -#define TX4938_PCIMEM_0 0x08000000 -#define TX4938_PCIMEM_1 0x11000000 - -#define TX4938_PCIIO_SIZE_0 0x01000000 -#define TX4938_PCIIO_SIZE_1 0x00010000 -#define TX4938_PCIMEM_SIZE_0 0x08000000 -#define TX4938_PCIMEM_SIZE_1 0x00010000 - -#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */ +#ifdef CONFIG_64BIT +#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */ +#else +#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */ +#endif #define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ @@ -49,149 +40,8 @@ #define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) #define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) -#define _CONST64(c) c##ull - -#include - -#ifdef __BIG_ENDIAN -#define endian_def_l2(e1, e2) \ - volatile unsigned long e1, e2 -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_l2(e1, e2) \ - volatile unsigned long e2, e1 -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - - -struct tx4938_sdramc_reg { - volatile unsigned long long cr[4]; - volatile unsigned long long unused0[4]; - volatile unsigned long long tr; - volatile unsigned long long unused1[2]; - volatile unsigned long long cmd; - volatile unsigned long long sfcmd; -}; - -struct tx4938_ebusc_reg { - volatile unsigned long long cr[8]; -}; - -struct tx4938_dma_reg { - struct tx4938_dma_ch_reg { - volatile unsigned long long cha; - volatile unsigned long long sar; - volatile unsigned long long dar; - endian_def_l2(unused0, cntr); - endian_def_l2(unused1, sair); - endian_def_l2(unused2, dair); - endian_def_l2(unused3, ccr); - endian_def_l2(unused4, csr); - } ch[4]; - volatile unsigned long long dbr[8]; - volatile unsigned long long tdhr; - volatile unsigned long long midr; - endian_def_l2(unused0, mcr); -}; - -struct tx4938_aclc_reg { - volatile unsigned long acctlen; - volatile unsigned long acctldis; - volatile unsigned long acregacc; - volatile unsigned long unused0; - volatile unsigned long acintsts; - volatile unsigned long acintmsts; - volatile unsigned long acinten; - volatile unsigned long acintdis; - volatile unsigned long acsemaph; - volatile unsigned long unused1[7]; - volatile unsigned long acgpidat; - volatile unsigned long acgpodat; - volatile unsigned long acslten; - volatile unsigned long acsltdis; - volatile unsigned long acfifosts; - volatile unsigned long unused2[11]; - volatile unsigned long acdmasts; - volatile unsigned long acdmasel; - volatile unsigned long unused3[6]; - volatile unsigned long acaudodat; - volatile unsigned long acsurrdat; - volatile unsigned long accentdat; - volatile unsigned long aclfedat; - volatile unsigned long acaudiat; - volatile unsigned long unused4; - volatile unsigned long acmodoat; - volatile unsigned long acmodidat; - volatile unsigned long unused5[15]; - volatile unsigned long acrevid; -}; - - -struct tx4938_tmr_reg { - volatile unsigned long tcr; - volatile unsigned long tisr; - volatile unsigned long cpra; - volatile unsigned long cprb; - volatile unsigned long itmr; - volatile unsigned long unused0[3]; - volatile unsigned long ccdr; - volatile unsigned long unused1[3]; - volatile unsigned long pgmr; - volatile unsigned long unused2[3]; - volatile unsigned long wtmr; - volatile unsigned long unused3[43]; - volatile unsigned long trr; -}; - -struct tx4938_sio_reg { - volatile unsigned long lcr; - volatile unsigned long dicr; - volatile unsigned long disr; - volatile unsigned long cisr; - volatile unsigned long fcr; - volatile unsigned long flcr; - volatile unsigned long bgr; - volatile unsigned long tfifo; - volatile unsigned long rfifo; -}; - -struct tx4938_ndfmc_reg { - endian_def_l2(unused0, dtr); - endian_def_l2(unused1, mcr); - endian_def_l2(unused2, sr); - endian_def_l2(unused3, isr); - endian_def_l2(unused4, imr); - endian_def_l2(unused5, spr); - endian_def_l2(unused6, rstr); -}; - -struct tx4938_spi_reg { - volatile unsigned long mcr; - volatile unsigned long cr0; - volatile unsigned long cr1; - volatile unsigned long fs; - volatile unsigned long unused1; - volatile unsigned long sr; - volatile unsigned long dr; - volatile unsigned long unused2; -}; - struct tx4938_sramc_reg { - volatile unsigned long long cr; + u64 cr; }; struct tx4938_ccfg_reg { @@ -209,34 +59,6 @@ struct tx4938_ccfg_reg { u64 jmpadr; }; -#undef endian_def_l2 -#undef endian_def_s2 -#undef endian_def_sb2 -#undef endian_def_b2s -#undef endian_def_b4 - -/* - * NDFMC - */ - -/* NDFMCR : NDFMC Mode Control */ -#define TX4938_NDFMCR_WE 0x80 -#define TX4938_NDFMCR_ECC_ALL 0x60 -#define TX4938_NDFMCR_ECC_RESET 0x60 -#define TX4938_NDFMCR_ECC_READ 0x40 -#define TX4938_NDFMCR_ECC_ON 0x20 -#define TX4938_NDFMCR_ECC_OFF 0x00 -#define TX4938_NDFMCR_CE 0x10 -#define TX4938_NDFMCR_BSPRT 0x04 -#define TX4938_NDFMCR_ALE 0x02 -#define TX4938_NDFMCR_CLE 0x01 - -/* NDFMCR : NDFMC Status */ -#define TX4938_NDFSR_BUSY 0x80 - -/* NDFMCR : NDFMC Reset */ -#define TX4938_NDFRSTR_RST 0x01 - /* * IRC */ @@ -272,9 +94,9 @@ struct tx4938_ccfg_reg { * CCFG */ /* CCFG : Chip Configuration */ -#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) -#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) -#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) +#define TX4938_CCFG_WDRST 0x0000020000000000ULL +#define TX4938_CCFG_WDREXEN 0x0000010000000000ULL +#define TX4938_CCFG_BCFG_MASK 0x000000ff00000000ULL #define TX4938_CCFG_TINTDIS 0x01000000 #define TX4938_CCFG_PCI66 0x00800000 #define TX4938_CCFG_PCIMODE 0x00400000 @@ -310,12 +132,12 @@ struct tx4938_ccfg_reg { #define TX4938_CCFG_ACEHOLD 0x00000001 /* PCFG : Pin Configuration */ -#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) -#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) -#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) -#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) -#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) -#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) +#define TX4938_PCFG_ETH0_SEL 0x8000000000000000ULL +#define TX4938_PCFG_ETH1_SEL 0x4000000000000000ULL +#define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL +#define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL +#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL +#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL #define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 #define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) #define TX4938_PCFG_SYSCLKEN 0x08000000 @@ -336,8 +158,8 @@ struct tx4938_ccfg_reg { #define TX4938_PCFG_DMASEL3_SIO0 0x00000008 /* CLKCTR : Clock Control */ -#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) -#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) +#define TX4938_CLKCTR_NDFCKD 0x0001000000000000ULL +#define TX4938_CLKCTR_NDFRST 0x0000000100000000ULL #define TX4938_CLKCTR_ETH1CKD 0x80000000 #define TX4938_CLKCTR_ETH0CKD 0x40000000 #define TX4938_CLKCTR_SPICKD 0x20000000 @@ -424,20 +246,16 @@ struct tx4938_ccfg_reg { #define TX4938_DMA_CSR_DESERR 0x00000002 #define TX4938_DMA_CSR_SORERR 0x00000001 -#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) -#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) -#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) -#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) +#define tx4938_sdramcptr tx4927_sdramcptr +#define tx4938_ebuscptr tx4927_ebuscptr #define tx4938_pcicptr tx4927_pcicptr #define tx4938_pcic1ptr \ ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG) #define tx4938_ccfgptr \ ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG) -#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) #define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) -#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) -#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) -#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) +#define tx4938_sramcptr \ + ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG) #define TX4938_REV_PCODE() \ @@ -447,14 +265,15 @@ struct tx4938_ccfg_reg { #define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) #define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) -#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) -#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) +#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch) +#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch) +#define TX4938_SDRAMC_SIZE(ch) TX4927_SDRAMC_SIZE(ch) -#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)]) -#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) -#define TX4938_EBUSC_SIZE(ch) \ - (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) +#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch) +#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch) +#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) +#define tx4938_get_mem_size() tx4927_get_mem_size() int tx4938_report_pciclk(void); void tx4938_report_pci1clk(void); int tx4938_pciclk66_setup(void); -- cgit v1.2.3 From 94a4c32939dede9328c6e4face335eb8441fc18d Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 19 Jul 2008 01:51:47 +0900 Subject: [MIPS] TXx9: Add 64-bit support SYS_SUPPORTS_64BIT_KERNEL is enabled for RBTX4927/RBTX4938, but actually it was broken for long time (or from the beginning). Now it should work. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/generic/Makefile | 4 +- arch/mips/txx9/generic/irq_tx4927.c | 2 +- arch/mips/txx9/generic/irq_tx4938.c | 2 +- arch/mips/txx9/generic/setup.c | 16 ++- arch/mips/txx9/generic/setup_tx4927.c | 194 +++++++++++++++++++++++++ arch/mips/txx9/generic/setup_tx4938.c | 259 ++++++++++++++++++++++++++++++++++ arch/mips/txx9/jmr3927/setup.c | 8 -- arch/mips/txx9/rbtx4927/irq.c | 12 +- arch/mips/txx9/rbtx4927/setup.c | 89 ++++-------- arch/mips/txx9/rbtx4938/setup.c | 218 ++-------------------------- include/asm-mips/txx9/generic.h | 7 + include/asm-mips/txx9/rbtx4927.h | 26 ++-- include/asm-mips/txx9/rbtx4938.h | 52 ++++--- include/asm-mips/txx9/tx4927.h | 15 ++ include/asm-mips/txx9/tx4938.h | 6 + 15 files changed, 580 insertions(+), 330 deletions(-) create mode 100644 arch/mips/txx9/generic/setup_tx4927.c create mode 100644 arch/mips/txx9/generic/setup_tx4938.c (limited to 'include/asm-mips') diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile index ab274ede9a70..9c120771e65f 100644 --- a/arch/mips/txx9/generic/Makefile +++ b/arch/mips/txx9/generic/Makefile @@ -4,8 +4,8 @@ obj-y += setup.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o -obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o irq_tx4938.o +obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o +obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o obj-$(CONFIG_KGDB) += dbgio.o diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c index 6377bd8a9050..cbea1fdde82b 100644 --- a/arch/mips/txx9/generic/irq_tx4927.c +++ b/arch/mips/txx9/generic/irq_tx4927.c @@ -31,7 +31,7 @@ void __init tx4927_irq_init(void) { mips_cpu_irq_init(); - txx9_irq_init(TX4927_IRC_REG); + txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, handle_simple_irq); } diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c index 5fc86c9c9d2f..6eac684bf190 100644 --- a/arch/mips/txx9/generic/irq_tx4938.c +++ b/arch/mips/txx9/generic/irq_tx4938.c @@ -19,7 +19,7 @@ void __init tx4938_irq_init(void) { mips_cpu_irq_init(); - txx9_irq_init(TX4938_IRC_REG); + txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, handle_simple_irq); } diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 8caef07701bb..3715a8f5ea44 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -30,6 +30,7 @@ struct resource txx9_ce_res[8]; static char txx9_ce_res_name[8][4]; /* "CEn" */ /* pcode, internal register */ +unsigned int txx9_pcode; char txx9_pcode_str[8]; static struct resource txx9_reg_res = { .name = txx9_pcode_str, @@ -59,15 +60,16 @@ unsigned int txx9_master_clock; unsigned int txx9_cpu_clock; unsigned int txx9_gbus_clock; +int txx9_ccfg_toeon __initdata = 1; /* Minimum CLK support */ struct clk *clk_get(struct device *dev, const char *id) { if (!strcmp(id, "spi-baseclk")) - return (struct clk *)(txx9_gbus_clock / 2 / 4); + return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4); if (!strcmp(id, "imbus_clk")) - return (struct clk *)(txx9_gbus_clock / 2); + return (struct clk *)((unsigned long)txx9_gbus_clock / 2); return ERR_PTR(-ENOENT); } EXPORT_SYMBOL(clk_get); @@ -123,6 +125,12 @@ void __init prom_init_cmdline(void) int argc = (int)fw_arg0; char **argv = (char **)fw_arg1; int i; /* Always ignore the "-c" at argv[0] */ +#ifdef CONFIG_64BIT + char *fixed_argv[32]; + for (i = 0; i < argc; i++) + fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i)); + argv = fixed_argv; +#endif /* ignore all built-in args if any f/w args given */ if (argc > 1) @@ -180,6 +188,10 @@ char * __init prom_getcmdline(void) /* wrappers */ void __init plat_mem_setup(void) { + ioport_resource.start = 0; + ioport_resource.end = ~0UL; /* no limit */ + iomem_resource.start = 0; + iomem_resource.end = ~0UL; /* no limit */ txx9_board_vec->mem_setup(); } diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c new file mode 100644 index 000000000000..89d6e28add93 --- /dev/null +++ b/arch/mips/txx9/generic/setup_tx4927.c @@ -0,0 +1,194 @@ +/* + * TX4927 setup routines + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * 2003-2005 (c) MontaVista Software, Inc. + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __init tx4927_wdr_init(void) +{ + /* clear WatchDogReset (W1C) */ + tx4927_ccfg_set(TX4927_CCFG_WDRST); + /* do reset on watchdog */ + tx4927_ccfg_set(TX4927_CCFG_WR); +} + +static struct resource tx4927_sdram_resource[4]; + +void __init tx4927_setup(void) +{ + int i; + __u32 divmode; + int cpuclk = 0; + u64 ccfg; + + txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE, + TX4927_REG_SIZE); + + /* SDRAMC,EBUSC are configured by PROM */ + for (i = 0; i < 8; i++) { + if (!(TX4927_EBUSC_CR(i) & 0x8)) + continue; /* disabled */ + txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i); + txx9_ce_res[i].end = + txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1; + request_resource(&iomem_resource, &txx9_ce_res[i]); + } + + /* clocks */ + ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg); + if (txx9_master_clock) { + /* calculate gbus_clock and cpu_clock from master_clock */ + divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4927_CCFG_DIVMODE_8: + case TX4927_CCFG_DIVMODE_10: + case TX4927_CCFG_DIVMODE_12: + case TX4927_CCFG_DIVMODE_16: + txx9_gbus_clock = txx9_master_clock * 4; break; + default: + txx9_gbus_clock = txx9_master_clock; + } + switch (divmode) { + case TX4927_CCFG_DIVMODE_2: + case TX4927_CCFG_DIVMODE_8: + cpuclk = txx9_gbus_clock * 2; break; + case TX4927_CCFG_DIVMODE_2_5: + case TX4927_CCFG_DIVMODE_10: + cpuclk = txx9_gbus_clock * 5 / 2; break; + case TX4927_CCFG_DIVMODE_3: + case TX4927_CCFG_DIVMODE_12: + cpuclk = txx9_gbus_clock * 3; break; + case TX4927_CCFG_DIVMODE_4: + case TX4927_CCFG_DIVMODE_16: + cpuclk = txx9_gbus_clock * 4; break; + } + txx9_cpu_clock = cpuclk; + } else { + if (txx9_cpu_clock == 0) + txx9_cpu_clock = 200000000; /* 200MHz */ + /* calculate gbus_clock and master_clock from cpu_clock */ + cpuclk = txx9_cpu_clock; + divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4927_CCFG_DIVMODE_2: + case TX4927_CCFG_DIVMODE_8: + txx9_gbus_clock = cpuclk / 2; break; + case TX4927_CCFG_DIVMODE_2_5: + case TX4927_CCFG_DIVMODE_10: + txx9_gbus_clock = cpuclk * 2 / 5; break; + case TX4927_CCFG_DIVMODE_3: + case TX4927_CCFG_DIVMODE_12: + txx9_gbus_clock = cpuclk / 3; break; + case TX4927_CCFG_DIVMODE_4: + case TX4927_CCFG_DIVMODE_16: + txx9_gbus_clock = cpuclk / 4; break; + } + switch (divmode) { + case TX4927_CCFG_DIVMODE_8: + case TX4927_CCFG_DIVMODE_10: + case TX4927_CCFG_DIVMODE_12: + case TX4927_CCFG_DIVMODE_16: + txx9_master_clock = txx9_gbus_clock / 4; break; + default: + txx9_master_clock = txx9_gbus_clock; + } + } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; + + /* CCFG */ + tx4927_wdr_init(); + /* clear BusErrorOnWrite flag (W1C) */ + tx4927_ccfg_set(TX4927_CCFG_BEOW); + /* enable Timeout BusError */ + if (txx9_ccfg_toeon) + tx4927_ccfg_set(TX4927_CCFG_TOE); + + /* DMA selection */ + txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL); + + /* Use external clock for external arbiter */ + if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB)) + txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL); + + printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", + txx9_pcode_str, + (cpuclk + 500000) / 1000000, + (txx9_master_clock + 500000) / 1000000, + (__u32)____raw_readq(&tx4927_ccfgptr->crir), + (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg), + (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg)); + + printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); + for (i = 0; i < 4; i++) { + __u64 cr = TX4927_SDRAMC_CR(i); + unsigned long base, size; + if (!((__u32)cr & 0x00000400)) + continue; /* disabled */ + base = (unsigned long)(cr >> 49) << 21; + size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; + printk(" CR%d:%016llx", i, (unsigned long long)cr); + tx4927_sdram_resource[i].name = "SDRAM"; + tx4927_sdram_resource[i].start = base; + tx4927_sdram_resource[i].end = base + size - 1; + tx4927_sdram_resource[i].flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &tx4927_sdram_resource[i]); + } + printk(" TR:%09llx\n", + (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr)); + + /* TMR */ + /* disable all timers */ + for (i = 0; i < TX4927_NR_TMR; i++) + txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL); + + /* PIO */ + txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO); + __raw_writel(0, &tx4927_pioptr->maskcpu); + __raw_writel(0, &tx4927_pioptr->maskext); +} + +void __init tx4927_time_init(unsigned int tmrnr) +{ + if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) + txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL, + TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr), + TXX9_IMCLK); +} + +void __init tx4927_setup_serial(void) +{ +#ifdef CONFIG_SERIAL_TXX9 + int i; + struct uart_port req; + + for (i = 0; i < 2; i++) { + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i); + req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL; + req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i); + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = TXX9_IMCLK; + early_serial_txx9_setup(&req); + } +#endif /* CONFIG_SERIAL_TXX9 */ +} diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c new file mode 100644 index 000000000000..317378d8579d --- /dev/null +++ b/arch/mips/txx9/generic/setup_tx4938.c @@ -0,0 +1,259 @@ +/* + * TX4938/4937 setup routines + * Based on linux/arch/mips/txx9/rbtx4938/setup.c, + * and RBTX49xx patch from CELF patch archive. + * + * 2003-2005 (c) MontaVista Software, Inc. + * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __init tx4938_wdr_init(void) +{ + /* clear WatchDogReset (W1C) */ + tx4938_ccfg_set(TX4938_CCFG_WDRST); + /* do reset on watchdog */ + tx4938_ccfg_set(TX4938_CCFG_WR); +} + +static struct resource tx4938_sdram_resource[4]; +static struct resource tx4938_sram_resource; + +#define TX4938_SRAM_SIZE 0x800 + +void __init tx4938_setup(void) +{ + int i; + __u32 divmode; + int cpuclk = 0; + u64 ccfg; + + txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE, + TX4938_REG_SIZE); + + /* SDRAMC,EBUSC are configured by PROM */ + for (i = 0; i < 8; i++) { + if (!(TX4938_EBUSC_CR(i) & 0x8)) + continue; /* disabled */ + txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i); + txx9_ce_res[i].end = + txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1; + request_resource(&iomem_resource, &txx9_ce_res[i]); + } + + /* clocks */ + ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); + if (txx9_master_clock) { + /* calculate gbus_clock and cpu_clock from master_clock */ + divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = txx9_master_clock * 4; break; + default: + txx9_gbus_clock = txx9_master_clock; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + cpuclk = txx9_gbus_clock * 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + cpuclk = txx9_gbus_clock * 5 / 2; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + cpuclk = txx9_gbus_clock * 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + cpuclk = txx9_gbus_clock * 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + cpuclk = txx9_gbus_clock * 9 / 2; break; + } + txx9_cpu_clock = cpuclk; + } else { + if (txx9_cpu_clock == 0) + txx9_cpu_clock = 300000000; /* 300MHz */ + /* calculate gbus_clock and master_clock from cpu_clock */ + cpuclk = txx9_cpu_clock; + divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; + switch (divmode) { + case TX4938_CCFG_DIVMODE_2: + case TX4938_CCFG_DIVMODE_8: + txx9_gbus_clock = cpuclk / 2; break; + case TX4938_CCFG_DIVMODE_2_5: + case TX4938_CCFG_DIVMODE_10: + txx9_gbus_clock = cpuclk * 2 / 5; break; + case TX4938_CCFG_DIVMODE_3: + case TX4938_CCFG_DIVMODE_12: + txx9_gbus_clock = cpuclk / 3; break; + case TX4938_CCFG_DIVMODE_4: + case TX4938_CCFG_DIVMODE_16: + txx9_gbus_clock = cpuclk / 4; break; + case TX4938_CCFG_DIVMODE_4_5: + case TX4938_CCFG_DIVMODE_18: + txx9_gbus_clock = cpuclk * 2 / 9; break; + } + switch (divmode) { + case TX4938_CCFG_DIVMODE_8: + case TX4938_CCFG_DIVMODE_10: + case TX4938_CCFG_DIVMODE_12: + case TX4938_CCFG_DIVMODE_16: + case TX4938_CCFG_DIVMODE_18: + txx9_master_clock = txx9_gbus_clock / 4; break; + default: + txx9_master_clock = txx9_gbus_clock; + } + } + /* change default value to udelay/mdelay take reasonable time */ + loops_per_jiffy = txx9_cpu_clock / HZ / 2; + + /* CCFG */ + tx4938_wdr_init(); + /* clear BusErrorOnWrite flag (W1C) */ + tx4938_ccfg_set(TX4938_CCFG_BEOW); + /* enable Timeout BusError */ + if (txx9_ccfg_toeon) + tx4938_ccfg_set(TX4938_CCFG_TOE); + + /* DMA selection */ + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL); + + /* Use external clock for external arbiter */ + if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB)) + txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL); + + printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", + txx9_pcode_str, + (cpuclk + 500000) / 1000000, + (txx9_master_clock + 500000) / 1000000, + (__u32)____raw_readq(&tx4938_ccfgptr->crir), + (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), + (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg)); + + printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); + for (i = 0; i < 4; i++) { + __u64 cr = TX4938_SDRAMC_CR(i); + unsigned long base, size; + if (!((__u32)cr & 0x00000400)) + continue; /* disabled */ + base = (unsigned long)(cr >> 49) << 21; + size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; + printk(" CR%d:%016llx", i, (unsigned long long)cr); + tx4938_sdram_resource[i].name = "SDRAM"; + tx4938_sdram_resource[i].start = base; + tx4938_sdram_resource[i].end = base + size - 1; + tx4938_sdram_resource[i].flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &tx4938_sdram_resource[i]); + } + printk(" TR:%09llx\n", + (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr)); + + /* SRAM */ + if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) { + unsigned int size = TX4938_SRAM_SIZE; + tx4938_sram_resource.name = "SRAM"; + tx4938_sram_resource.start = + (____raw_readq(&tx4938_sramcptr->cr) >> (39-11)) + & ~(size - 1); + tx4938_sram_resource.end = + tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1; + tx4938_sram_resource.flags = IORESOURCE_MEM; + request_resource(&iomem_resource, &tx4938_sram_resource); + } + + /* TMR */ + /* disable all timers */ + for (i = 0; i < TX4938_NR_TMR; i++) + txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); + + /* DMA */ + for (i = 0; i < 2; i++) + ____raw_writeq(TX4938_DMA_MCR_MSTEN, + (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); + + /* PIO */ + txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO); + __raw_writel(0, &tx4938_pioptr->maskcpu); + __raw_writel(0, &tx4938_pioptr->maskext); + + if (txx9_pcode == 0x4938) { + __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); + /* set PCIC1 reset */ + txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); + if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) { + mdelay(1); /* at least 128 cpu clock */ + /* clear PCIC1 reset */ + txx9_clear64(&tx4938_ccfgptr->clkctr, + TX4938_CLKCTR_PCIC1RST); + } else { + printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str); + /* stop PCIC1 */ + txx9_set64(&tx4938_ccfgptr->clkctr, + TX4938_CLKCTR_PCIC1CKD); + } + if (!(pcfg & TX4938_PCFG_ETH0_SEL)) { + printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str); + txx9_set64(&tx4938_ccfgptr->clkctr, + TX4938_CLKCTR_ETH0RST); + txx9_set64(&tx4938_ccfgptr->clkctr, + TX4938_CLKCTR_ETH0CKD); + } + if (!(pcfg & TX4938_PCFG_ETH1_SEL)) { + printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str); + txx9_set64(&tx4938_ccfgptr->clkctr, + TX4938_CLKCTR_ETH1RST); + txx9_set64(&tx4938_ccfgptr->clkctr, + TX4938_CLKCTR_ETH1CKD); + } + } +} + +void __init tx4938_time_init(unsigned int tmrnr) +{ + if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) + txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL, + TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr), + TXX9_IMCLK); +} + +void __init tx4938_setup_serial(void) +{ +#ifdef CONFIG_SERIAL_TXX9 + int i; + struct uart_port req; + unsigned int ch_mask = 0; + + if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL) + ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */ + for (i = 0; i < 2; i++) { + if ((1 << i) & ch_mask) + continue; + memset(&req, 0, sizeof(req)); + req.line = i; + req.iotype = UPIO_MEM; + req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i); + req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL; + req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i); + req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; + req.uartclk = TXX9_IMCLK; + early_serial_txx9_setup(&req); + } +#endif /* CONFIG_SERIAL_TXX9 */ +} diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 5e35ef73c5a5..03647ebe4130 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -105,14 +105,6 @@ static void __init jmr3927_mem_setup(void) _machine_halt = jmr3927_machine_halt; pm_power_off = jmr3927_machine_power_off; - /* - * IO/MEM resources. - */ - ioport_resource.start = 0; - ioport_resource.end = 0xffffffff; - iomem_resource.start = 0; - iomem_resource.end = 0xffffffff; - /* Reboot on panic */ panic_timeout = 180; diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c index 70f13211bc2a..cd748a930328 100644 --- a/arch/mips/txx9/rbtx4927/irq.c +++ b/arch/mips/txx9/rbtx4927/irq.c @@ -126,14 +126,12 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { .mask_ack = toshiba_rbtx4927_irq_ioc_disable, .unmask = toshiba_rbtx4927_irq_ioc_enable, }; -#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL -#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL static int toshiba_rbtx4927_irq_nested(int sw_irq) { u8 level3; - level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + level3 = readb(rbtx4927_imstat_addr) & 0x1f; if (level3) sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; return (sw_irq); @@ -154,18 +152,18 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) { unsigned char v; - v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v = readb(rbtx4927_imask_addr); v |= (1 << (irq - RBTX4927_IRQ_IOC)); - writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); + writeb(v, rbtx4927_imask_addr); } static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) { unsigned char v; - v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v = readb(rbtx4927_imask_addr); v &= ~(1 << (irq - RBTX4927_IRQ_IOC)); - writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); + writeb(v, rbtx4927_imask_addr); mmiowb(); } diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index 1657fd935da8..3da20ea3e55c 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -53,17 +53,10 @@ #include #include #include -#include -#include #include #include #include #include /* for TX4937 */ -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif - -static int tx4927_ccfg_toeon = 1; #ifdef CONFIG_PCI static void __init tx4927_pci_setup(void) @@ -184,14 +177,14 @@ static void toshiba_rbtx4927_restart(char *command) printk(KERN_NOTICE "System Rebooting...\n"); /* enable the s/w reset register */ - writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); + writeb(1, rbtx4927_softresetlock_addr); /* wait for enable to be seen */ - while ((readb(RBTX4927_SW_RESET_ENABLE) & - RBTX4927_SW_RESET_ENABLE_SET) == 0x00); + while (!(readb(rbtx4927_softresetlock_addr) & 1)) + ; /* do a s/w reset */ - writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); + writeb(1, rbtx4927_softreset_addr); /* do something passive while waiting for reset */ local_irq_disable(); @@ -213,9 +206,11 @@ static void toshiba_rbtx4927_power_off(void) /* no return */ } +static void __init rbtx4927_clock_init(void); +static void __init rbtx4937_clock_init(void); + static void __init rbtx4927_mem_setup(void) { - int i; u32 cp0_config; char *argptr; @@ -227,16 +222,18 @@ static void __init rbtx4927_mem_setup(void) cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); write_c0_config(cp0_config); - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; + if (TX4927_REV_PCODE() == 0x4927) { + rbtx4927_clock_init(); + tx4927_setup(); + } else { + rbtx4937_clock_init(); + tx4938_setup(); + } _machine_restart = toshiba_rbtx4927_restart; _machine_halt = toshiba_rbtx4927_halt; pm_power_off = toshiba_rbtx4927_power_off; - for (i = 0; i < TX4927_NR_TMR; i++) - txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); - #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, @@ -245,36 +242,13 @@ static void __init rbtx4927_mem_setup(void) set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); #endif - /* CCFG */ - /* do reset on watchdog */ - tx4927_ccfg_set(TX4927_CCFG_WR); - /* enable Timeout BusError */ - if (tx4927_ccfg_toeon) - tx4927_ccfg_set(TX4927_CCFG_TOE); - -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (char *)(0xff1ff300 + i * 0x100); - req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i); - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = 50000000; - early_serial_txx9_setup(&req); - } - } + tx4927_setup_serial(); #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if (strstr(argptr, "console=") == NULL) { strcat(argptr, " console=ttyS0,38400"); } #endif -#endif #ifdef CONFIG_ROOT_NFS argptr = prom_getcmdline(); @@ -291,19 +265,7 @@ static void __init rbtx4927_mem_setup(void) #endif } -static void __init rbtx49x7_common_time_init(void) -{ - /* change default value to udelay/mdelay take reasonable time */ - loops_per_jiffy = txx9_cpu_clock / HZ / 2; - - mips_hpt_frequency = txx9_cpu_clock / 2; - if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) - txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, - TXX9_IRQ_BASE + 17, - 50000000); -} - -static void __init rbtx4927_time_init(void) +static void __init rbtx4927_clock_init(void) { /* * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. @@ -325,11 +287,9 @@ static void __init rbtx4927_time_init(void) default: txx9_cpu_clock = 200000000; /* 200MHz */ } - - rbtx49x7_common_time_init(); } -static void __init rbtx4937_time_init(void) +static void __init rbtx4937_clock_init(void) { /* * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. @@ -357,15 +317,18 @@ static void __init rbtx4937_time_init(void) default: txx9_cpu_clock = 333333333; /* 333MHz */ } +} - rbtx49x7_common_time_init(); +static void __init rbtx4927_time_init(void) +{ + tx4927_time_init(0); } static int __init toshiba_rbtx4927_rtc_init(void) { - static struct resource __initdata res = { - .start = 0x1c010000, - .end = 0x1c010000 + 0x800 - 1, + struct resource res = { + .start = RBTX4927_BRAMRTC_BASE - IO_BASE, + .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, .flags = IORESOURCE_MEM, }; struct platform_device *dev = @@ -375,7 +338,7 @@ static int __init toshiba_rbtx4927_rtc_init(void) static int __init rbtx4927_ne_init(void) { - static struct resource __initdata res[] = { + struct resource res[] = { { .start = RBTX4927_RTL_8019_BASE, .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, @@ -434,7 +397,7 @@ struct txx9_board_vec rbtx4937_vec __initdata = { .prom_init = rbtx4927_prom_init, .mem_setup = rbtx4927_mem_setup, .irq_setup = rbtx4927_irq_setup, - .time_init = rbtx4937_time_init, + .time_init = rbtx4927_time_init, .device_init = rbtx4927_device_init, .arch_init = rbtx4937_arch_init, #ifdef CONFIG_PCI diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index c1e076c7b2d2..6c2b99bb8af6 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -20,21 +20,14 @@ #include #include -#include -#include #include #include #include #include -#ifdef CONFIG_SERIAL_TXX9 -#include -#endif #include #include #include -static int tx4938_ccfg_toeon = 1; - static void rbtx4938_machine_halt(void) { printk(KERN_NOTICE "System Halted\n"); @@ -182,189 +175,10 @@ static void __init rbtx4938_spi_setup(void) } static struct resource rbtx4938_fpga_resource; -static struct resource tx4938_sdram_resource[4]; -static struct resource tx4938_sram_resource; - -void __init tx4938_board_setup(void) -{ - int i; - unsigned long divmode; - int cpuclk = 0; - unsigned long pcode = TX4938_REV_PCODE(); - - ioport_resource.start = 0; - ioport_resource.end = 0xffffffff; - iomem_resource.start = 0; - iomem_resource.end = 0xffffffff; /* expand to 4GB */ - - txx9_reg_res_init(pcode, TX4938_REG_BASE, - TX4938_REG_SIZE); - /* SDRAMC,EBUSC are configured by PROM */ - for (i = 0; i < 8; i++) { - if (!(TX4938_EBUSC_CR(i) & 0x8)) - continue; /* disabled */ - txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i); - txx9_ce_res[i].end = - txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1; - request_resource(&iomem_resource, &txx9_ce_res[i]); - } - - /* clocks */ - if (txx9_master_clock) { - u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); - /* calculate gbus_clock and cpu_clock_freq from master_clock */ - divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; - switch (divmode) { - case TX4938_CCFG_DIVMODE_8: - case TX4938_CCFG_DIVMODE_10: - case TX4938_CCFG_DIVMODE_12: - case TX4938_CCFG_DIVMODE_16: - case TX4938_CCFG_DIVMODE_18: - txx9_gbus_clock = txx9_master_clock * 4; break; - default: - txx9_gbus_clock = txx9_master_clock; - } - switch (divmode) { - case TX4938_CCFG_DIVMODE_2: - case TX4938_CCFG_DIVMODE_8: - cpuclk = txx9_gbus_clock * 2; break; - case TX4938_CCFG_DIVMODE_2_5: - case TX4938_CCFG_DIVMODE_10: - cpuclk = txx9_gbus_clock * 5 / 2; break; - case TX4938_CCFG_DIVMODE_3: - case TX4938_CCFG_DIVMODE_12: - cpuclk = txx9_gbus_clock * 3; break; - case TX4938_CCFG_DIVMODE_4: - case TX4938_CCFG_DIVMODE_16: - cpuclk = txx9_gbus_clock * 4; break; - case TX4938_CCFG_DIVMODE_4_5: - case TX4938_CCFG_DIVMODE_18: - cpuclk = txx9_gbus_clock * 9 / 2; break; - } - txx9_cpu_clock = cpuclk; - } else { - u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); - if (txx9_cpu_clock == 0) { - txx9_cpu_clock = 300000000; /* 300MHz */ - } - /* calculate gbus_clock and master_clock from cpu_clock_freq */ - cpuclk = txx9_cpu_clock; - divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; - switch (divmode) { - case TX4938_CCFG_DIVMODE_2: - case TX4938_CCFG_DIVMODE_8: - txx9_gbus_clock = cpuclk / 2; break; - case TX4938_CCFG_DIVMODE_2_5: - case TX4938_CCFG_DIVMODE_10: - txx9_gbus_clock = cpuclk * 2 / 5; break; - case TX4938_CCFG_DIVMODE_3: - case TX4938_CCFG_DIVMODE_12: - txx9_gbus_clock = cpuclk / 3; break; - case TX4938_CCFG_DIVMODE_4: - case TX4938_CCFG_DIVMODE_16: - txx9_gbus_clock = cpuclk / 4; break; - case TX4938_CCFG_DIVMODE_4_5: - case TX4938_CCFG_DIVMODE_18: - txx9_gbus_clock = cpuclk * 2 / 9; break; - } - switch (divmode) { - case TX4938_CCFG_DIVMODE_8: - case TX4938_CCFG_DIVMODE_10: - case TX4938_CCFG_DIVMODE_12: - case TX4938_CCFG_DIVMODE_16: - case TX4938_CCFG_DIVMODE_18: - txx9_master_clock = txx9_gbus_clock / 4; break; - default: - txx9_master_clock = txx9_gbus_clock; - } - } - /* change default value to udelay/mdelay take reasonable time */ - loops_per_jiffy = txx9_cpu_clock / HZ / 2; - - /* CCFG */ - /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ - tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW); - /* do reset on watchdog */ - tx4938_ccfg_set(TX4938_CCFG_WR); - /* clear PCIC1 reset */ - txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); - - /* enable Timeout BusError */ - if (tx4938_ccfg_toeon) - tx4938_ccfg_set(TX4938_CCFG_TOE); - - /* DMA selection */ - txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL); - - /* Use external clock for external arbiter */ - if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB)) - txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL); - - printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", - txx9_pcode_str, - (cpuclk + 500000) / 1000000, - (txx9_master_clock + 500000) / 1000000, - (__u32)____raw_readq(&tx4938_ccfgptr->crir), - (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), - (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg)); - - printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); - for (i = 0; i < 4; i++) { - u64 cr = TX4938_SDRAMC_CR(i); - unsigned long ram_base, ram_size; - if (!((unsigned long)cr & 0x00000400)) - continue; /* disabled */ - ram_base = (unsigned long)(cr >> 49) << 21; - ram_size = ((unsigned long)(cr >> 33) + 1) << 21; - if (ram_base >= 0x20000000) - continue; /* high memory (ignore) */ - printk(KERN_CONT " CR%d:%016llx", i, cr); - tx4938_sdram_resource[i].name = "SDRAM"; - tx4938_sdram_resource[i].start = ram_base; - tx4938_sdram_resource[i].end = ram_base + ram_size - 1; - tx4938_sdram_resource[i].flags = IORESOURCE_MEM; - request_resource(&iomem_resource, &tx4938_sdram_resource[i]); - } - printk(KERN_CONT " TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr)); - - /* SRAM */ - if (____raw_readq(&tx4938_sramcptr->cr) & 1) { - unsigned int size = 0x800; - unsigned long base = - (____raw_readq(&tx4938_sramcptr->cr) >> (39-11)) - & ~(size - 1); - tx4938_sram_resource.name = "SRAM"; - tx4938_sram_resource.start = base; - tx4938_sram_resource.end = base + size - 1; - tx4938_sram_resource.flags = IORESOURCE_MEM; - request_resource(&iomem_resource, &tx4938_sram_resource); - } - - /* TMR */ - for (i = 0; i < TX4938_NR_TMR; i++) - txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); - - /* enable DMA */ - for (i = 0; i < 2; i++) - ____raw_writeq(TX4938_DMA_MCR_MSTEN, - (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); - - /* PIO */ - __raw_writel(0, &tx4938_pioptr->maskcpu); - __raw_writel(0, &tx4938_pioptr->maskext); - -#ifdef CONFIG_PCI - txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); -#endif -} static void __init rbtx4938_time_init(void) { - mips_hpt_frequency = txx9_cpu_clock / 2; - if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) - txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, - TXX9_IRQ_BASE + TX4938_IR_TMR(0), - txx9_gbus_clock / 2); + tx4938_time_init(0); } static void __init rbtx4938_mem_setup(void) @@ -372,39 +186,24 @@ static void __init rbtx4938_mem_setup(void) unsigned long long pcfg; char *argptr; - iomem_resource.end = 0xffffffff; /* 4GB */ - if (txx9_master_clock == 0) txx9_master_clock = 25000000; /* 25MHz */ - tx4938_board_setup(); -#ifndef CONFIG_PCI + + tx4938_setup(); + +#ifdef CONFIG_PCI + txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); +#else set_io_port_base(RBTX4938_ETHER_BASE); #endif -#ifdef CONFIG_SERIAL_TXX9 - { - extern int early_serial_txx9_setup(struct uart_port *port); - int i; - struct uart_port req; - for(i = 0; i < 2; i++) { - memset(&req, 0, sizeof(req)); - req.line = i; - req.iotype = UPIO_MEM; - req.membase = (char *)(0xff1ff300 + i * 0x100); - req.mapbase = 0xff1ff300 + i * 0x100; - req.irq = RBTX4938_IRQ_IRC_SIO(i); - req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; - req.uartclk = 50000000; - early_serial_txx9_setup(&req); - } - } + tx4938_setup_serial(); #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if (strstr(argptr, "console=") == NULL) { strcat(argptr, " console=ttyS0,38400"); } #endif -#endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 printk("PIOSEL: disabling both ata and nand selection\n"); @@ -568,7 +367,6 @@ static int __init rbtx4938_spi_init(void) static void __init rbtx4938_arch_init(void) { - txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); gpiochip_add(&rbtx4938_spi_gpio_chip); rbtx4938_pci_setup(); rbtx4938_spi_init(); diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h index d8756660523d..cbae37ec3d88 100644 --- a/include/asm-mips/txx9/generic.h +++ b/include/asm-mips/txx9/generic.h @@ -12,6 +12,8 @@ #include /* for struct resource */ extern struct resource txx9_ce_res[]; +#define TXX9_CE(n) (unsigned long)(txx9_ce_res[(n)].start) +extern unsigned int txx9_pcode; extern char txx9_pcode_str[8]; void txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size); @@ -19,6 +21,11 @@ void txx9_reg_res_init(unsigned int pcode, unsigned long base, extern unsigned int txx9_master_clock; extern unsigned int txx9_cpu_clock; extern unsigned int txx9_gbus_clock; +#define TXX9_IMCLK (txx9_gbus_clock / 2) + +extern int txx9_ccfg_toeon; +struct uart_port; +int early_serial_txx9_setup(struct uart_port *port); struct pci_dev; struct txx9_board_vec { diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h index bf194589216f..6fcec912c143 100644 --- a/include/asm-mips/txx9/rbtx4927.h +++ b/include/asm-mips/txx9/rbtx4927.h @@ -34,7 +34,23 @@ #define RBTX4927_PCIIO 0x16000000 #define RBTX4927_PCIIO_SIZE 0x01000000 -#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL) +#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) +#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) +#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) +#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) +#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) +#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000) +#define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) + +/* Ethernet port address */ +#define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280) + +#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) +#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) +#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) +#define rbtx4927_softresetlock_addr \ + ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) +#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR) /* bits for ISTAT/IMASK/IMSTAT */ #define RBTX4927_INTB_PCID 0 @@ -62,13 +78,7 @@ #define RBTX4927_ISA_IO_OFFSET 0 #endif -#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL -#define RBTX4927_SW_RESET_DO_SET 0x01 - -#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL -#define RBTX4927_SW_RESET_ENABLE_SET 0x01 - -#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET) +#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base) #define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) void rbtx4927_prom_init(void); diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h index 2f5d5e705a41..9f0441a28126 100644 --- a/include/asm-mips/txx9/rbtx4938.h +++ b/include/asm-mips/txx9/rbtx4938.h @@ -15,35 +15,31 @@ #include #include -/* CS */ -#define RBTX4938_CE0 0x1c000000 /* 64M */ -#define RBTX4938_CE2 0x17f00000 /* 1M */ - /* Address map */ -#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000) -#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002) -#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004) -#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006) -#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008) -#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000) -#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002) -#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004) -#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000) -#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002) -#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004) -#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006) -#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008) -#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a) -#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c) -#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000) -#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000) -#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002) -#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008) -#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a) -#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000) -#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002) -#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004) -#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000) +#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000) +#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002) +#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004) +#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006) +#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008) +#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000) +#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002) +#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004) +#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) +#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002) +#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004) +#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) +#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008) +#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a) +#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c) +#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) +#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000) +#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002) +#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008) +#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a) +#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000) +#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002) +#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004) +#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) /* Ethernet port address (Jumperless Mode (W12:Open)) */ #define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h index c9212155f686..ceb4b79ff4e3 100644 --- a/include/asm-mips/txx9/tx4927.h +++ b/include/asm-mips/txx9/tx4927.h @@ -46,15 +46,22 @@ #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) #define TX4927_NR_TMR 3 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) +#define TX4927_NR_SIO 2 +#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) +#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) #define TX4927_IR_INT(n) (2 + (n)) #define TX4927_IR_SIO(n) (8 + (n)) #define TX4927_IR_PCIC 16 +#define TX4927_NUM_IR_TMR 3 +#define TX4927_IR_TMR(n) (17 + (n)) #define TX4927_IR_PCIERR 22 #define TX4927_NUM_IR 32 #define TX4927_IRC_INT 2 /* IP[2] in Status register */ +#define TX4927_NUM_PIO 16 + struct tx4927_sdramc_reg { u64 cr[4]; u64 unused0[4]; @@ -175,6 +182,10 @@ struct tx4927_ccfg_reg { ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) #define tx4927_ebuscptr \ ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG) +#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG) + +#define TX4927_REV_PCODE() \ + ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16) #define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) #define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) @@ -232,6 +243,10 @@ static inline void tx4927_ccfg_change(__u64 change, __u64 new) } unsigned int tx4927_get_mem_size(void); +void tx4927_wdr_init(void); +void tx4927_setup(void); +void tx4927_time_init(unsigned int tmrnr); +void tx4927_setup_serial(void); int tx4927_report_pciclk(void); int tx4927_pciclk66_setup(void); void tx4927_irq_init(void); diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h index 6690246a1149..1ed969d381d6 100644 --- a/include/asm-mips/txx9/tx4938.h +++ b/include/asm-mips/txx9/tx4938.h @@ -90,6 +90,8 @@ struct tx4938_ccfg_reg { #define TX4938_IRC_INT 2 /* IP[2] in Status register */ +#define TX4938_NUM_PIO 16 + /* * CCFG */ @@ -274,6 +276,10 @@ struct tx4938_ccfg_reg { #define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) #define tx4938_get_mem_size() tx4927_get_mem_size() +void tx4938_wdr_init(void); +void tx4938_setup(void); +void tx4938_time_init(unsigned int tmrnr); +void tx4938_setup_serial(void); int tx4938_report_pciclk(void); void tx4938_report_pci1clk(void); int tx4938_pciclk66_setup(void); -- cgit v1.2.3 From e0eb730757665d7e8ec0e79d9042a9311f3edb7e Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Sat, 19 Jul 2008 01:51:52 +0900 Subject: [MIPS] TXx9: Fix some sparse warnings Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/generic/setup.c | 2 ++ include/asm-mips/txx9/tx3927.h | 19 ++++++++++--------- 2 files changed, 12 insertions(+), 9 deletions(-) (limited to 'include/asm-mips') diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 3715a8f5ea44..8c60c78b9a9e 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -19,7 +19,9 @@ #include #include #include +#include #include +#include #include #ifdef CONFIG_CPU_TX49XX #include diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h index ca414c7624e1..ea79e1b16e71 100644 --- a/include/asm-mips/txx9/tx3927.h +++ b/include/asm-mips/txx9/tx3927.h @@ -10,17 +10,18 @@ #include -#define TX3927_SDRAMC_REG 0xfffe8000 -#define TX3927_ROMC_REG 0xfffe9000 -#define TX3927_DMA_REG 0xfffeb000 -#define TX3927_IRC_REG 0xfffec000 -#define TX3927_PCIC_REG 0xfffed000 -#define TX3927_CCFG_REG 0xfffee000 +#define TX3927_REG_BASE 0xfffe0000UL +#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000) +#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000) +#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000) +#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000) +#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000) +#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000) #define TX3927_NR_TMR 3 -#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100) +#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100) #define TX3927_NR_SIO 2 -#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100) -#define TX3927_PIO_REG 0xfffef500 +#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100) +#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500) struct tx3927_sdramc_reg { volatile unsigned long cr[8]; -- cgit v1.2.3 From 3d739f2daaed442f5bee9da2164757401ae4a417 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sun, 20 Jul 2008 22:01:06 +0900 Subject: [MIPS] Remove unused saa9730_uart.h. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- include/asm-mips/mips-boards/saa9730_uart.h | 69 ----------------------------- 1 file changed, 69 deletions(-) delete mode 100644 include/asm-mips/mips-boards/saa9730_uart.h (limited to 'include/asm-mips') diff --git a/include/asm-mips/mips-boards/saa9730_uart.h b/include/asm-mips/mips-boards/saa9730_uart.h deleted file mode 100644 index c913143d58ec..000000000000 --- a/include/asm-mips/mips-boards/saa9730_uart.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Register definitions for the UART part of the Philips SAA9730 chip. - * - */ - -#ifndef SAA9730_UART_H -#define SAA9730_UART_H - -/* The SAA9730 UART register map, as seen via the PCI bus */ - -#define SAA9730_UART_REGS_ADDR 0x21800 - -struct uart_saa9730_regmap { - volatile unsigned char Thr_Rbr; - volatile unsigned char Ier; - volatile unsigned char Iir_Fcr; - volatile unsigned char Lcr; - volatile unsigned char Mcr; - volatile unsigned char Lsr; - volatile unsigned char Msr; - volatile unsigned char Scr; - volatile unsigned char BaudDivLsb; - volatile unsigned char BaudDivMsb; - volatile unsigned char Junk0; - volatile unsigned char Junk1; - volatile unsigned int Config; /* 0x2180c */ - volatile unsigned int TxStart; /* 0x21810 */ - volatile unsigned int TxLength; /* 0x21814 */ - volatile unsigned int TxCounter; /* 0x21818 */ - volatile unsigned int RxStart; /* 0x2181c */ - volatile unsigned int RxLength; /* 0x21820 */ - volatile unsigned int RxCounter; /* 0x21824 */ -}; -typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap; - -/* - * Only a subset of the UART control bits are defined here, - * enough to make the serial debug port work. - */ - -#define SAA9730_LCR_DATA8 0x03 - -#define SAA9730_MCR_DTR 0x01 -#define SAA9730_MCR_RTS 0x02 - -#define SAA9730_LSR_DR 0x01 -#define SAA9730_LSR_THRE 0x20 - -#endif /* !(SAA9730_UART_H) */ -- cgit v1.2.3 From cb7f39d2bc5a20615d016dd86fca0fd233c13b5d Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Sun, 20 Jul 2008 22:03:32 +0900 Subject: [MIPS] Remove unused maltasmp.h. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- include/asm-mips/mips-boards/maltasmp.h | 36 --------------------------------- 1 file changed, 36 deletions(-) delete mode 100644 include/asm-mips/mips-boards/maltasmp.h (limited to 'include/asm-mips') diff --git a/include/asm-mips/mips-boards/maltasmp.h b/include/asm-mips/mips-boards/maltasmp.h deleted file mode 100644 index 8d7e955d506e..000000000000 --- a/include/asm-mips/mips-boards/maltasmp.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * There are several SMP models supported - * SMTC is mutually exclusive to other options (atm) - */ -#if defined(CONFIG_MIPS_MT_SMTC) -#define malta_smtc 1 -#define malta_cmp 0 -#define malta_smvp 0 -#else -#define malta_smtc 0 -#if defined(CONFIG_MIPS_CMP) -extern int gcmp_present; -#define malta_cmp gcmp_present -#else -#define malta_cmp 0 -#endif -/* FIXME: should become COMFIG_MIPS_MT_SMVP */ -#if defined(CONFIG_MIPS_MT_SMP) -#define malta_smvp 1 -#else -#define malta_smvp 0 -#endif -#endif - -#include -#include - -/* malta_smtc */ -#include -#include - -/* malta_cmp */ -#include - -/* malta_smvp */ -#include -- cgit v1.2.3