diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-25 15:17:05 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:51:46 +0200 |
| commit | 0475a478d0a88c7ec31763697eb01b25957bece3 (patch) | |
| tree | fff8ab964c58106e547dd3a799524094fca22fc1 | |
| parent | clk: renesas: r9a09g077: Add PLL2 and SDHI clock support (diff) | |
| download | linux-0475a478d0a88c7ec31763697eb01b25957bece3.tar.gz linux-0475a478d0a88c7ec31763697eb01b25957bece3.zip | |
clk: renesas: r9a09g077: Add RIIC module clocks
Add RIIC module clocks for: iic0, iic1, and iic2.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r9a09g077-cpg.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c index 93862d84f95f..c920d6a9707f 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -154,6 +154,9 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC), + DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL), + DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL), + DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL), DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM), DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM), }; |