diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2025-05-22 22:03:29 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> | 2025-07-04 16:35:16 +0300 |
| commit | 2287f32e32a083f07e593f550bf304220912dc2e (patch) | |
| tree | a6fb8622c0a850f900807ddd550107706ce209e8 | |
| parent | ef31cf538b987efd5ade8e5e4fdcdd3242fb172a (diff) | |
| download | linux-2287f32e32a083f07e593f550bf304220912dc2e.tar.gz linux-2287f32e32a083f07e593f550bf304220912dc2e.zip | |
drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655379/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-10-3b2085a07884@oss.qualcomm.com
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 |
3 files changed, 2 insertions, 5 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 0863e5cfb328..6fed2cce082c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -105,8 +105,7 @@ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_FETCH_ACTIVE) | \ - BIT(DPU_CTL_VM_CFG) | \ + (BIT(DPU_CTL_VM_CFG) | \ BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) #define INTF_SC7180_MASK \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 9981d090b689..82f04de6300e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -132,14 +132,12 @@ enum { /** * CTL sub-blocks * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display - * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ enum { DPU_CTL_SPLIT_DISPLAY = 0x1, - DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 2dfb7db371a3..772df53bfc4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -809,7 +809,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, else c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; - if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE)) + if (mdss_ver->core_major_ver >= 7) c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes; c->idx = cfg->id; |