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| author | Mihai Sain <mihai.sain@microchip.com> | 2025-06-19 10:06:36 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2025-07-05 10:43:31 +0300 |
| commit | 314862edb13d52c481ecc330c9d3fec0507cd9bb (patch) | |
| tree | 6a1d918e88f1a7b038612d3d062e034d4f6a2114 | |
| parent | ARM: dts: microchip: sama7d65: Add cache configuration for cpu node (diff) | |
| download | linux-314862edb13d52c481ecc330c9d3fec0507cd9bb.tar.gz linux-314862edb13d52c481ecc330c9d3fec0507cd9bb.zip | |
ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
Describe the cache memories according with datasheet chapter 15.2:
- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.
Before this patch the kernel reported the warning:
[ 0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250619070636.8844-3-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| -rw-r--r-- | arch/arm/boot/dts/microchip/sama7g5.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index e128074137e0..381cbcfcb34a 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -38,6 +38,16 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB + next-level-cache = <&L2>; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; // L2, 256 KB + cache-unified; + }; }; }; |