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| author | ShihChen Chen <ShihChen.Chen@amd.com> | 2017-09-12 11:10:12 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-10-21 16:41:27 -0400 |
| commit | 4b7e7e2b1bb2c7308ee3ccbef3f67cb9ce52e954 (patch) | |
| tree | 8601a63168f23f08f9e3c2db1ab7108891ae411c | |
| parent | bc6828e0e6b6c5bcafbb093f9fe475f63dbe47e5 (diff) | |
| download | linux-4b7e7e2b1bb2c7308ee3ccbef3f67cb9ce52e954.tar.gz linux-4b7e7e2b1bb2c7308ee3ccbef3f67cb9ce52e954.zip | |
drm/amd/display: make tile changing run at ISR
Signed-off-by: ShihChen Chen <ShihChen.Chen@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 1ec6df9870da..2cea8de9c9be 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1031,7 +1031,6 @@ static enum surface_update_type get_plane_info_update_type( temp_plane_info.plane_size = u->surface->plane_size; temp_plane_info.rotation = u->surface->rotation; temp_plane_info.stereo_format = u->surface->stereo_format; - temp_plane_info.tiling_info = u->surface->tiling_info; if (surface_index == 0) temp_plane_info.visible = u->plane_info->visible; @@ -1044,10 +1043,26 @@ static enum surface_update_type get_plane_info_update_type( if (pixel_format_to_bpp(u->plane_info->format) != pixel_format_to_bpp(u->surface->format)) { + /* different bytes per element will require full bandwidth + * and DML calculation + */ return UPDATE_TYPE_FULL; - } else { - return UPDATE_TYPE_MED; } + + if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, + sizeof(union dc_tiling_info)) != 0) { + /* todo: below are HW dependent, we should add a hook to + * DCE/N resource and validated there. + */ + if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { + /* swizzled mode requires RQ to be setup properly, + * thus need to run DML to calculate RQ settings + */ + return UPDATE_TYPE_FULL; + } + } + + return UPDATE_TYPE_MED; } static enum surface_update_type get_scaling_info_update_type( |