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| author | Gustavo Sousa <gustavo.sousa@intel.com> | 2025-02-03 17:58:58 -0300 |
|---|---|---|
| committer | Gustavo Sousa <gustavo.sousa@intel.com> | 2025-02-04 08:43:12 -0300 |
| commit | 71be802005074a4cc2297e4a1da1ca268d9c6b49 (patch) | |
| tree | 6297f589b4a775bf7cdf830bfbbac807d50c7d0f | |
| parent | drm/i915/mst: Convert intel_dp_mtp_tu_compute_config() to .4 format (diff) | |
| download | linux-71be802005074a4cc2297e4a1da1ca268d9c6b49.tar.gz linux-71be802005074a4cc2297e4a1da1ca268d9c6b49.zip | |
drm/i915/dmc_wl: Track INITIATE_PM_DMD_REQ for DC5
The Bspec has been updated to include INITIATE_PM_DMD_REQ in the set of
register offsets that require the DMC wakelock for access during DC5.
Update our table accordingly.
Bspec: 71583
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250203205941.251754-1-gustavo.sousa@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 43884740f8ea..86ba159b683c 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -102,6 +102,7 @@ static const struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = { { .start = 0x42088 }, /* CHICKEN_MISC_3 */ { .start = 0x46160 }, /* CMTG_CLK_SEL */ { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ + { .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */ {}, }; |