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| author | Irving-CH Lin <irving-ch.lin@mediatek.com> | 2026-02-02 14:48:13 +0800 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2026-02-23 11:55:42 +0100 |
| commit | 82d58440cd72dd4bf719e50eddfb9c4ef50f2deb (patch) | |
| tree | 160a79426cb3bf95d03e3808f23e5ec4016f5de8 | |
| parent | 3cdac25e80a23ca107189b55deaadf0a49bab44b (diff) | |
| download | linux-82d58440cd72dd4bf719e50eddfb9c4ef50f2deb.tar.gz linux-82d58440cd72dd4bf719e50eddfb9c4ef50f2deb.zip | |
dt-bindings: power: Add MediaTek MT8189 power domain
Add dt schema and IDs for the power domain of MediaTek MT8189 SoC.
The MT8189 power domain IP provide power domains control function
for subsys (eg. MFG, audio, venc/vdec ...).
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/power/mediatek,power-controller.yaml | 1 | ||||
| -rw-r--r-- | include/dt-bindings/power/mediatek,mt8189-power.h | 38 |
2 files changed, 39 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 9507b342a7ee..07f046277f8a 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8183-power-controller - mediatek,mt8186-power-controller - mediatek,mt8188-power-controller + - mediatek,mt8189-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller - mediatek,mt8196-hwv-hfrp-power-controller diff --git a/include/dt-bindings/power/mediatek,mt8189-power.h b/include/dt-bindings/power/mediatek,mt8189-power.h new file mode 100644 index 000000000000..70a8c2113457 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8189-power.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang <qiqi.wang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H +#define _DT_BINDINGS_POWER_MT8189_POWER_H + +/* SPM */ +#define MT8189_POWER_DOMAIN_CONN 0 +#define MT8189_POWER_DOMAIN_AUDIO 1 +#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2 +#define MT8189_POWER_DOMAIN_ADSP_INFRA 3 +#define MT8189_POWER_DOMAIN_ADSP_AO 4 +#define MT8189_POWER_DOMAIN_MM_INFRA 5 +#define MT8189_POWER_DOMAIN_ISP_IMG1 6 +#define MT8189_POWER_DOMAIN_ISP_IMG2 7 +#define MT8189_POWER_DOMAIN_ISP_IPE 8 +#define MT8189_POWER_DOMAIN_VDE0 9 +#define MT8189_POWER_DOMAIN_VEN0 10 +#define MT8189_POWER_DOMAIN_CAM_MAIN 11 +#define MT8189_POWER_DOMAIN_CAM_SUBA 12 +#define MT8189_POWER_DOMAIN_CAM_SUBB 13 +#define MT8189_POWER_DOMAIN_MDP0 14 +#define MT8189_POWER_DOMAIN_DISP 15 +#define MT8189_POWER_DOMAIN_DP_TX 16 +#define MT8189_POWER_DOMAIN_CSI_RX 17 +#define MT8189_POWER_DOMAIN_SSUSB 18 +#define MT8189_POWER_DOMAIN_MFG0 19 +#define MT8189_POWER_DOMAIN_MFG1 20 +#define MT8189_POWER_DOMAIN_MFG2 21 +#define MT8189_POWER_DOMAIN_MFG3 22 +#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23 +#define MT8189_POWER_DOMAIN_PCIE 24 +#define MT8189_POWER_DOMAIN_PCIE_PHY 25 + +#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */ |