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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-11-25 22:14:19 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-12-15 11:49:10 +0100 |
| commit | 94cdeca6a17a3e2ba617c8a03e17d989de005a20 (patch) | |
| tree | 394364057aa36021d89e67b97b938cd3abd084ae | |
| parent | 75faf216112a69cdbf415fa057abbe7ed2ae6da6 (diff) | |
| download | linux-94cdeca6a17a3e2ba617c8a03e17d989de005a20.tar.gz linux-94cdeca6a17a3e2ba617c8a03e17d989de005a20.zip | |
clk: renesas: r9a09g056: Add entries for ICU
Add clock and reset entries for the ICU IP block.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251125221420.288809-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r9a09g056-cpg.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c index 19b712685a31..1c6228b0544e 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -245,6 +245,8 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { BUS_MSTOP(10, BIT(11))), DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4, BUS_MSTOP(10, BIT(12))), + DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, + BUS_MSTOP_NONE), DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, BUS_MSTOP(3, BIT(5))), DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, @@ -420,6 +422,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */ DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */ DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */ + DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ |