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| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2024-12-11 01:06:16 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-02-11 10:20:31 +0100 |
| commit | bed6964e779b5853de042da14320edf9f79506fe (patch) | |
| tree | 1adc8132fffc1f3e622f7e41ac705bfe5c08720b | |
| parent | arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588 (diff) | |
| download | linux-bed6964e779b5853de042da14320edf9f79506fe.tar.gz linux-bed6964e779b5853de042da14320edf9f79506fe.zip | |
arm64: dts: rockchip: Add HDMI1 node on RK3588
Add support for the second HDMI TX port found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-3-02cdca22ff68@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index f5ffe593a182..8b2edf362ce8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -170,6 +170,47 @@ status = "disabled"; }; + hdmi1: hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfdea0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX1>, + <&cru CLK_HDMITX1_EARC>, + <&cru CLK_HDMITX1_REF>, + <&cru MCLK_I2S6_8CH_TX>, + <&cru CLK_HDMIHDP1>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in: port@0 { + reg = <0>; + }; + + hdmi1_out: port@1 { + reg = <1>; + }; + }; + }; + pcie3x4: pcie@fe150000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; |