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| author | Jonathan Kim <jonathan.kim@amd.com> | 2019-07-11 12:19:44 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:18:07 -0500 |
| commit | c52e7ebce72bc9d269c6025da5a4d41601e5f6ca (patch) | |
| tree | 20fac844cdfd5e72753046b643457c45e040210d | |
| parent | drm/amd/powerplay: input check for unsupported message/clock index (diff) | |
| download | linux-c52e7ebce72bc9d269c6025da5a4d41601e5f6ca.tar.gz linux-c52e7ebce72bc9d269c6025da5a4d41601e5f6ca.zip | |
drm/amdgpu: exposing fica registers to df offsets
exposing fica registers to poll df pie data for xgmi error counters for
vega20.
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h index 6efcaa93e17b..c2bd25589e84 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h @@ -48,4 +48,8 @@ #define smnPerfMonCtrLo3 0x01d478UL #define smnPerfMonCtrHi3 0x01d47cUL +#define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3 0x1d05cUL +#define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3 0x1d098UL +#define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3 0x1d09cUL + #endif |