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| author | Alex Deucher <alexander.deucher@amd.com> | 2019-07-26 11:04:39 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-30 23:48:32 -0500 |
| commit | d3b9f39d8417ee2f2cd87b5e5410015ce6f78491 (patch) | |
| tree | 2270f6229cc17d3dbfd52c328de59d5223e5508c | |
| parent | drm/amdgpu: Fix amdgpu_display_supported_domains logic. (diff) | |
| download | linux-d3b9f39d8417ee2f2cd87b5e5410015ce6f78491.tar.gz linux-d3b9f39d8417ee2f2cd87b5e5410015ce6f78491.zip | |
drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT
Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 69e4d0d96c7f..38b3c89b2a59 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -630,9 +630,11 @@ static void dcn20_init_hw(struct dc *dc) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Power gate DSCs */ for (i = 0; i < res_pool->res_cap->num_dsc; i++) dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false); +#endif /* Blank pixel data with OPP DPG */ for (i = 0; i < dc->res_pool->timing_generator_count; i++) { |