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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-06-22 18:54:50 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-10-07 20:10:02 +0300 |
| commit | eadbd867177e1d72b2ff71b7ba0dffcae4dabc64 (patch) | |
| tree | b5690e3b9fd1f9de9f064c1cc19d6e20ac824989 | |
| parent | drm/i915: Fix g4x/vlv/chv CxSR vs. format/tiling/rotation changes (diff) | |
| download | linux-eadbd867177e1d72b2ff71b7ba0dffcae4dabc64.tar.gz linux-eadbd867177e1d72b2ff71b7ba0dffcae4dabc64.zip | |
drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platforms
Like most other plane control register bits, the pipe gamma
enable bit is also blocked by CxSR. So make sure we kick the
machine out of CxSR before trying to change that bit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220622155452.32587-8-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_color.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index fc23d5d8f7fd..123c57ceeb73 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1287,6 +1287,10 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) return PTR_ERR(plane_state); new_crtc_state->update_planes |= BIT(plane->id); + + /* plane control register changes blocked by CxSR */ + if (HAS_GMCH(dev_priv)) + new_crtc_state->disable_cxsr = true; } return 0; |