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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2025-01-20 15:09:35 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-21 16:23:00 +0100 |
| commit | ec32d57b4bbf27d91c55c7a258bdb87690993ea6 (patch) | |
| tree | 722ce36b474ed6f93c53688646efbbf02fb01d49 | |
| parent | arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different... (diff) | |
| download | linux-ec32d57b4bbf27d91c55c7a258bdb87690993ea6.tar.gz linux-ec32d57b4bbf27d91c55c7a258bdb87690993ea6.zip | |
arm64: dts: renesas: rzg3s-smarc: Enable SCIF3
Enable SCIF3. It is routed to the SER1_UART interface on the RZ SMARC
Carrier II board.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 81b4ffd1417d..0851e0b7ed40 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,6 +12,7 @@ / { aliases { i2c0 = &i2c0; + serial1 = &scif3; serial3 = &scif0; mmc1 = &sdhi1; }; @@ -162,6 +163,11 @@ <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */ }; + scif3_pins: scif3 { + pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */ + <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */ + }; + sdhi1_pins: sd1 { data { pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; @@ -208,6 +214,12 @@ status = "okay"; }; +&scif3 { + pinctrl-names = "default"; + pinctrl-0 = <&scif3_pins>; + status = "okay"; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>; |