diff options
| author | Alexandre Ghiti <alexghiti@rivosinc.com> | 2025-06-20 20:21:58 +0000 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2025-09-16 16:28:30 -0600 |
| commit | 833bbb0d91d21694ec0d8909b6c71f5df448c575 (patch) | |
| tree | b27acf6b65a77ca0ec2f63b1fa11520807934ac7 /arch/riscv/kernel | |
| parent | riscv: Fix typo EXRACT -> EXTRACT (diff) | |
| download | linux-833bbb0d91d21694ec0d8909b6c71f5df448c575.tar.gz linux-833bbb0d91d21694ec0d8909b6c71f5df448c575.zip | |
riscv: Strengthen duplicate and inconsistent definition of RV_X()
RV_X() macro is defined in two different ways which is error prone.
So harmonize its first definition and add another macro RV_X_MASK() for
the second one.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250620-dev-alex-insn_duplicate_v5_manual-v5-2-d865dc9ad180@rivosinc.com
[pjw@kernel.org: upcase the macro name to conform with previous practice]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'arch/riscv/kernel')
| -rw-r--r-- | arch/riscv/kernel/machine_kexec_file.c | 2 | ||||
| -rw-r--r-- | arch/riscv/kernel/traps_misaligned.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c index b9eb41b0a975..dd9d92a96517 100644 --- a/arch/riscv/kernel/machine_kexec_file.c +++ b/arch/riscv/kernel/machine_kexec_file.c @@ -15,6 +15,7 @@ #include <linux/memblock.h> #include <linux/vmalloc.h> #include <asm/setup.h> +#include <asm/insn.h> const struct kexec_file_ops * const kexec_file_loaders[] = { &elf_kexec_ops, @@ -109,7 +110,6 @@ static char *setup_kdump_cmdline(struct kimage *image, char *cmdline, } #endif -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RISCV_IMM_BITS 12 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) #define RISCV_CONST_HIGH_PART(x) \ diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index f760e4fcc052..18a1fb240e25 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -18,6 +18,7 @@ #include <asm/cpufeature.h> #include <asm/sbi.h> #include <asm/vector.h> +#include <asm/insn.h> #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f @@ -113,7 +114,6 @@ #define SH_RS2 20 #define SH_RS2C 2 -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \ (RV_X(x, 10, 3) << 3) | \ (RV_X(x, 5, 1) << 6)) |