diff options
| author | Tony Luck <tony.luck@intel.com> | 2022-01-31 15:01:08 -0800 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-02-01 16:15:19 +0100 |
| commit | 00a2f23eef7d1fa6c2dfdc613857b84fbf5e2b3b (patch) | |
| tree | ab88738de6a22311e9bf260341b856e2845009bf /arch/x86/kernel/cpu/common.c | |
| parent | 0dcab41d3487acadf64d0667398e032341bd9918 (diff) | |
| download | linux-00a2f23eef7d1fa6c2dfdc613857b84fbf5e2b3b.tar.gz linux-00a2f23eef7d1fa6c2dfdc613857b84fbf5e2b3b.zip | |
x86/cpu: X86_FEATURE_INTEL_PPIN finally has a CPUID bit
After nine generations of adding to model specific list of CPUs that
support PPIN (Protected Processor Inventory Number) Intel allocated
a CPUID bit to enumerate the MSRs.
CPUID(EAX=7, ECX=1).EBX bit 0 enumerates presence of MSR_PPIN_CTL and
MSR_PPIN. Add it to the "scattered" CPUID bits and add an entry to the
ppin_cpuids[] x86_match_cpu() array to catch Intel CPUs that implement
it.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220131230111.2004669-3-tony.luck@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/common.c')
| -rw-r--r-- | arch/x86/kernel/cpu/common.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index b0bd8a6b5beb..0681c69a1f09 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -104,6 +104,7 @@ static struct ppin_info { static const struct x86_cpu_id ppin_cpuids[] = { X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), + X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), /* Legacy models without CPUID enumeration */ X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), |