diff options
| author | Maíra Canal <mairacanal@riseup.net> | 2022-07-14 13:44:56 -0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-07-20 16:03:59 -0400 |
| commit | 40835624efcde7f984cb859035b95b5a526d1a9f (patch) | |
| tree | 79f64a11d012c2b461e3492a9a1bde4ab66e1ef9 /drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | |
| parent | drm/amdgpu: fix scratch register access method in SRIOV (diff) | |
| download | linux-40835624efcde7f984cb859035b95b5a526d1a9f.tar.gz linux-40835624efcde7f984cb859035b95b5a526d1a9f.zip | |
drm/amdgpu: Write masked value to control register
On the dce_v6_0 and dce_v8_0 hpd tear down callback, the tmp variable
should be written into the control register instead of 0.
Reviewed-by: André Almeida <andrealmeid@igalia.com>
Signed-off-by: Maíra Canal <mairacanal@riseup.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v6_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 3caf6f386042..77f5e998a120 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -339,7 +339,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; - WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } |