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| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2023-08-08 16:25:59 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-08-30 14:58:44 -0400 |
| commit | 96182df99dadd4b59b7338b29bf45a90ad722625 (patch) | |
| tree | 279ff406c8c32e774931c61a4be3ece478484e22 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |
| parent | drm/amd/display: Refactor edp power control (diff) | |
| download | linux-96182df99dadd4b59b7338b29bf45a90ad722625.tar.gz linux-96182df99dadd4b59b7338b29bf45a90ad722625.zip | |
drm/amd/display: Enable runtime register offset init for DCN32 DMUB
[Why&How]
DMUB subsystem was continuing to use compile time offset calculation for
register access. Switch this to runtime calculation to stay consistent
with rest of DC code.
To enable this, an additional interface init_reg_offsets() are added to
DMUB's hw_funcs struct. Asics with runtime register offset calculation
enabled shall populate this hook with a fn pointer that will invoke the
necessary macros to calculate the offset.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f2b4f1720abd..3ce63e98e9ce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1069,6 +1069,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) const struct firmware *dmub_fw = adev->dm.dmub_fw; struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; struct abm *abm = adev->dm.dc->res_pool->abm; + struct dc_context *ctx = adev->dm.dc->ctx; struct dmub_srv_hw_params hw_params; enum dmub_status status; const unsigned char *fw_inst_const, *fw_bss_data; @@ -1090,6 +1091,10 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) return -EINVAL; } + /* initialize register offsets for ASICs with runtime initialization available */ + if (dmub_srv->hw_funcs.init_reg_offsets) + dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); + status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); if (status != DMUB_STATUS_OK) { DRM_ERROR("Error checking HW support for DMUB: %d\n", status); |